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? freescale semiconductor, inc., 2011. all rights reserved. freescale semiconductor technical data the powerpc? 603e microprocessor is an implementation of the powerpc family of reduced instruction set computing (risc) microprocessors. in this document, the term ?603e? is used as an abbreviation for the powerpc 603e microprocessor. the powerpc 603e microprocessors are available from freescale as mpc603e. the 603e is implemented in several semiconductor fabrication processes. diff erent processes may require different supply voltages and may have other electrical differences but will have th e same functionality. as a technical designator to distinguish between 603e implementations in various proc esses, a prefix composed of the processor version register (pvr) value and a process identifier (pid) is assigned to the various implementations as shown in table 1 . this document describes the pertinent physical characteristics of the pid7 t-603e from freescale. for functional characteristics of the 603e, refer to the powerpc 603e risc microprocessor user?s manual . to locate any published errata or updates for this document, refer to the website at www.freescale.com. document number: mpc603e7tec rev. 5, 09/2011 powerpc 603e risc microprocessor family: pid7t-603e hardware specifications contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. general parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4. electrical and thermal characteristics . . . . . . . . . . . . 4 5. pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. pinout listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. package descriptions . . . . . . . . . . . . . . . . . . . . . . . . 17 8. system design information . . . . . . . . . . . . . . . . . . . . 20 9. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 29 10. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
pid7t-603e hardware specifications, rev. 5 2 freescale semiconductor overview 1 overview the 603e is a low-power implem entation of the powerpc microprocessor family of risc microprocessors. the 603e implements the 32-bit portion of the powerpc architecture specification that provides 32-bit effective addresses, integer data types of 8, 16, and 32 bi ts, and floating-point data types of 32 and 64 bits. for 64-bit powerp c microprocessors, the powerpc architecture pr ovides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. the 603e provides four software cont rollable power-saving modes. three of the modes (the nap, doze, and sleep) are static in nature, and pr ogressively reduce the amount of power dissipated by the processor. the fourth is a dynamic power management mode that causes the functional units in the 603e to automatically enter a low-power mode when the functional units ar e idle without affecting operational performance, software execution, or any external hardware. the 603e is a superscalar pr ocessor capable of issuing and retiring as many as thre e instructions per clock. instructions can execute out of order for increas ed performance; however, the 603e makes completion appear sequential. the 603e integrates five execution units?an integer unit (iu), a floating-point unit (fpu), a branch processing unit (bpu), a load/store unit (lsu), and a system register unit (sru). the ability to execute five instructions in parallel and the use of simp le instructions with rapid execution times yield high efficiency and throughput for 603e-based systems. most integer instructions execute in one clock cycle. the fpu is pipelined, so a single- precision multiply-add instruction ca n be issued every clock cycle. the 603e provides independent on-chi p, 16-kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instructi on and data memory management units (mmus). the mmus contain 64-entry, two-way, set-associative da ta and instruction translation lookaside buffers (dtlb and itlb) that provide support for demand- paged virtual memory a ddress translation and variable-sized block translation. the tlbs and caches use a least- recently used (lru) replacement algorithm. the 603e also supports bloc k address translation through the us e of two independent instruction and data block address tran slation (ibat and dbat) arra ys of four entries eac h. effective addresses are compared simultaneously with all four entries in the bat array duri ng block translati on. in accordance with the powerpc architecture, if an effective a ddress hits in both the tlb and bat array, the bat translation takes priority. the 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. the 603e interface protocol allows multiple masters to compete for system re sources through a central external arbiter. the 603e provides a three-state coherency protocol that supports the exclus ive, modified, and in valid cache states. this protocol is a compatible subset of the mesi (m odified/exclusive/shared/inva lid) four-state protocol table 1. powerpc 603e microprocessors from freescale technical designator process core voltage (v) i/o voltage (v) 5-volt tolerant part number pid6-603e 0.5 m cmos, 4lm 3.3 3.3 yes mpc603e pid7v-603e 0.35 m cmos, 5lm 2. 5 3.3 yes xpc603p (end-of-life) pid7t-603e 0.29 m cmos, 5lm 2.5 3.3 yes mpc603r
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 3 features and operates coherently in systems that contain four -state caches. the 603e suppor ts single-beat and burst data transfers for memory accesses, and supports memory-mapped i/o. the 603e uses an advanced, 2.5/3.3-v cmos proc ess technology and maintains full interface compatibility with ttl devices. the pid7t-603e is offered in both pbga and cbga packages. the cbga package supports speed bins of 200, 266, and 300 mhz. the pbga package is a pin-compatible drop in replacement for the cbga; however, this package only supports speeds up to 200 mhz. 2features this section summarizes features of the 603e?s implementation of the powerpc architecture. major features of the 603e are as follows: ? high-performance, superscalar microprocessor ? as many as three instructions issued and retired per clock ? as many as five instructions in execution per clock ? single-cycle execution for most instructions ? pipelined fpu for all single-precisi on and most double-precision operations ? five independent execution un its and two register files ? bpu featuring static branch prediction ? a 32-bit iu ? fully ieee 754-compliant fpu for both single- and double-precision operations ? lsu for data transfer betwee n data cache and gprs and fprs ? sru that executes condition register (cr), special-purpose register ( spr) instructions, and integer add/compare instructions ? 32 gprs for integer operands ? 32 fprs for single- or double-precision operands ? high instruction and data throughput ? zero-cycle branch capability (branch folding) ? programmable static branch prediction on unresolved conditional branches ? instruction fetch unit capable of fetching two inst ructions per clock from the instruction cache ? a six-entry instruction queue th at provides lookahead capability ? independent pipelines with feed-forwarding that reduces data dependencies in hardware ? 16-kbyte data cache?four-way, set-associative physically addressed; lru replacement algorithm ? 16-kbyte instruction cache?four-way, se t-associative physically addressed; lru replacement algorithm ? cache write-back or write-thr ough operation programmable on a pe r page or per block basis ? bpu that performs cr lookahead operations ? address translation facilities for 4-kbyte pa ge size, variable block size, and 256-mbyte segment size
pid7t-603e hardware specifications, rev. 5 4 freescale semiconductor general parameters ? a 64-entry two-way, set-associative itlb ? a 64-entry two-way, set-associative dtlb ? four-entry data and instruction bat arrays providing 128-kbyte to 256-mbyte blocks ? software table search operations and updates supported through fast trap mechanism ? 52-bit virtual and 32-bit physical address ? facilities for enhanced system performance ? a 32- or 64-bit split-transaction exte rnal data bus with burst transfers ? support for one-level address pipelini ng and out-of-order bus transactions ? integrated power management ? low-power 2.5/3.3-volt design ? internal processor/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, and 6:1 ratios ? three power-saving modes: doze, nap, and sleep ? automatic dynamic power reduction when internal functional units are idle ? in-system testability and debugging fe atures through jtag boundary-scan capability 3 general parameters the following list provides a summary of the general parameters of the pid7t-603e: technology 0.29 m cmos, five-layer metal die size 5.65 mm x 7.7 mm (44 mm 2 ) transistor count 2.6 million logic design fully-static package 255 ceramic ball grid array (cbga) or 225 thin map plastic ball grid array (pbga) core power supply 2.5 5% v dc i/o power supply 3.3 5% v dc 4 electrical and thermal characteristics this section provides the ac and dc electrical sp ecifications and thermal characteristics for the pid7t-603e. 4.1 dc electrical characteristics the tables in this section describe the pid7t-603e dc electrical characteristics. this table provides the absolute maximum ratings.
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 5 electrical and thermal characteristics this table provides the recommended operating conditions for the pid7t-603e. this table provides the package thermal characteristics for the pid7t-603e. table 2. absolute maximum ratings characteristic symbol value unit core supply voltage v dd ?0.3 to 2.75 v pll supply voltage av dd ?0.3 to 2.75 v i/o supply voltage ov dd ?0.3 to 3.6 v input voltage v in ?0.3 to 5.5 v storage temperature range t stg ?55 to 150 c note: 1. functional and tested operating conditions are given in ta bl e 3 . absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed ma y affect device reliability or cause permanent damage to the device. 2. caution : v in must not exceed ov dd by more than 2.5 v at any time, including during power-on reset. 3. caution : ov dd must not exceed v dd /av dd by more than 1.2 v at any time, including during power-on reset. 4. caution : v dd /av dd must not exceed ov dd by more than 0.4 v at any time, including during power-on reset. table 3. recommended operating conditions characteristic symbol value unit core supply voltage v dd 2.375 to 2.625 v pll supply voltage av dd 2.375 to 2.625 v i/o supply voltage ov dd 3.135 to 3.465 v input voltage v in gnd to 5.5 v die-junction temperature tj 0 to 105 c note: these are the recommended and tested operating conditions. prop er device operation outside of these conditions is not guaranteed. table 4. package thermal characteristics characteristic symbol value cbga value pbga rating package die junction-to-case thermal resistance (typical) ? jc 0.095 8.0 c/w package die junction-to-ball thermal resistance (typical) ? jb 3.5 13 c/w note: for more about thermal management, see section 8, ?system design information .?
pid7t-603e hardware specifications, rev. 5 6 freescale semiconductor electrical and thermal characteristics this table provides the dc electrica l characteristics for the pid7t-603e. this table provides the power consumption for the pid7t-603e. table 5. dc electrical specifications v dd = av dd = 2.5 5% v dc, ov dd = 3.3 5% v dc, gnd = 0 v dc, 0 ? tj ? 105 c characteristic symbol min max unit note input high voltage (all inputs except sysclk) v ih 2.0 5.5 v ? input low voltage (all inputs except sysclk) v il gnd 0.8 v ? sysclk input high voltage cv ih 2.4 5.5 v ? sysclk input low voltage cv il gnd 0.4 v ? input leakage current, v in = 3.465 v i in ?30a1, 2 v in = 5.5 v i in ? 300 a 1, 2 hi-z (off-state) leakage current, v in = 3.465 v i tsi ?30a1, 2 v in = 5.5 v i tsi ? 300 a 1, 2 output high voltage, i oh = ?7 ma v oh 2.4 ? v ? output low voltage, i ol = 7 ma v ol ?0.4v ? capacitance, v in = 0 v, f = 1 mhz (excludes ts , abb , dbb , and artry )c in ?10.0pf 3 capacitance, v in = 0 v, f = 1 mhz (for ts , abb , dbb , and artry )c in ?15.0pf 3 notes : 1. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk, and jtag signals). 2. the leakage is measured for nominal ov dd and v dd or both ov dd and v dd must vary in the same direction (for example, both ov dd and v dd vary by either +5% or -5%). 3. capacitance is periodically sampled rather than 100% tested. table 6. power consumption processor (cpu) frequency unit 100 mhz 133 mhz 166 mhz 200 mhz 233 mhz 266 mhz 300 mhz full-on mode (dpm enabled) typical 1.1 1.6 2.1 2.5 3.0 3.5 4.0 w maximum 1.6 2.4 3.2 4.0 4.6 5.3 6.0 w doze mode typical 0.55 0.7 0.9 1.1 1.3 1.5 1.8 w nap mode typical 50 60 75 85 100 120 130 mw sleep mode ty p i c a l 4 5 5 0 5 5 6 5 7 5 9 0 1 0 0 m w sleep mode?pll disabled
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 7 electrical and thermal characteristics 4.2 ac electrical characteristics this section provides the ac electri cal characteristics for the pid7t-6 03e. these specifications are for 200, 266, and 300 mhz processor speed grades. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg[0?3] signals. all timings are specified respective to the rising edge of sysclk. pll_cfg signals should be set prior to power up and not altered afterwards. 4.2.1 clock ac specifications this table provides the clock ac timing specifications as defined in figure 1 . after fabrication, parts are sorted by maximum processor core frequency as shown in section 4.2.1, ?clock ac specifications ,? and tested for conformance to the ac specifications for that frequency. parts are so ld by maximum processor core frequency; see section 9, ?ordering information .? typical 40 40 40 40 40 40 40 mw sleep mode?pll and sysclk disabled typical 15 15 15 15 15 15 15 mw maximum 25 25 25 25 25 80 100 mw note: 1. these values apply for all valid pll_cfg[0?3] settings and do not include output driver power (ov dd ) or analog supply power (av dd ). ov dd power is system dependent but is typically ? 10% of v dd . worst-case av dd = 15 mw. 2. typical power is an average value measured at v dd = av dd = 2.5 v, ov dd = 3.3v, in a system exec uting typical applications and benchmark sequences. 3. maximum power is measured at 2.625 v using a worst-case instruction mix. table 7. clock ac timing specifications v dd = av dd = 2.5 5% v dc, ov dd = 3.3 5% v dc, gnd = 0 v dc , 0 ? tj ? 105 c num characteristic 200 mhz pbga 200 mhz cbga 266 mhz cbga 300 mhz cbga unit note min max min max min max min max processor frequency 100 200 80 200 150 266 180 300 mhz 1, 6 vco frequency 300 400 300 400 300 532 360 600 mhz 1 sysclk frequency 25 66.67 25 66.67 25 75 33.3 75 mhz 1 1 sysclk cycle time 13.3 40 13.3 40 13.3 40 13.3 30 ns 2, 3 sysclk rise and fall time ? 2.0 ? 2.0 ? 2.0 ? 2.0 ns 2 4 sysclk duty cycle measured at 1.4 v 40.0 60.0 40.0 60.0 40.0 60.0 40.0 60.0 % 3 table 6. power consumption (continued) processor (cpu) frequency unit 100 mhz 133 mhz 166 mhz 200 mhz 233 mhz 266 mhz 300 mhz
pid7t-603e hardware specifications, rev. 5 8 freescale semiconductor electrical and thermal characteristics this figure provides the sysc lk input timing diagram. figure 1. sysclk input timing diagram 4.2.2 input ac specifications this table provides the input ac timing specifications for the pid7t-603e as defined in figure 2 and figure 3 . sysclk jitter ? 150 ? 150 ? 150 ? 150 ps 4 pid7t internal pll-relock time ? 100 ? 100 ? 100 ? 100 ? s3, 5 note: 1. caution : the sysclk frequency and pll_cfg[0?3] settings must be chosen such that t he resulting sysclk (bus) frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0?3] signal description in section 8, ?system design information ,? fo r va l i d pll_cfg[0?3] settings. 2. rise and fall times for the sysclk i nput are measured from 0.4 v to 2.4 v. 3. timing is guaranteed by design and characterization, and is not tested. 4. cycle-to-cycle jitter, and is guaranteed by design. the tota l input jitter (short term and long term combined) must be under 150 ps to guarantee the input/output timing of section 4.2.2, ?input ac specifications ,? and section 4.2.3, ?output ac specifications .? 5. relock timing is guaranteed by design and characterization, a nd is not tested. pll-relock time is the maximum time required for pll lock after a stable v dd , ov dd , av dd , and sysclk are reached during the power-on reset sequence. this specification also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time (100 ? s) during the power-on reset sequence. 6. operation below 150 mhz is supported only by pll_cfg[0?3] = 0b0101. refer to section 8.1, ?pll configuration ? for additional information. table 7. clock ac timing specifications (continued) v dd = av dd = 2.5 5% v dc, ov dd = 3.3 5% v dc, gnd = 0 v dc , 0 ? tj ? 105 c num characteristic 200 mhz pbga 200 mhz cbga 266 mhz cbga 300 mhz cbga unit note min max min max min max min max vm cvil cvih sysclk 2 3 4 vm = midpoint voltage (1.4 v) 4 1 vm vm
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 9 electrical and thermal characteristics this figure provides the input ti ming diagram for the pid7t-603e. figure 2. input timing diagram table 8. input ac timing specifications 1 v dd = av dd = 2.5 5% v dc, ov dd = 3.3 5% v dc, gnd = 0 v dc , 0 ? tj ? 105 c num characteristic 200, 266, 300 mhz unit notes min max 10a address/data/transfer a ttribute inputs valid to sysclk (input setup) 2.5 ? ns 2 10b all other inputs valid to sysclk (input setup) 3.5 ? ns 3 10c mode select inputs valid to hreset (input setup) (for drtry , qack and tlbisync ) 8?t sysclk 4, 5, 6, 7 11a sysclk to address/data/transfer attr ibute inputs invalid (input hold) 1.0 ? ns 2 11b sysclk to all other inputs invalid (input hold) 1.0 ? ns 3 11c hreset to mode select inputs invalid (input hold) (for drtry , qack , and tlbisync ) 0 ? ns 4, 6, 7 note: 1. input specifications are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the 1.4 v of the rising edge of the input sysclk. input and output timings are measured at the pin. 2. address/data/transfer attribute input signals are composed of the followin g?a[0?31], ap[0?3], tt[0?4], tc[0?1], tbst , tsiz[0?2], gbl , dh[0?31], dl[0?31], dp[0?7]. 3. all other input signals are composed of the following?ts , abb , dbb , artry, bg , aack , dbg , dbwo , ta , drtry , tea , dbdis , hreset , sreset , int , smi , mcp , tben, qack , tlbisync . 4. the setup and hold time is with respect to the rising edge of hreset (see figure 3 ). 5. t sysclk is the period of the external clock (sysclk) in nanosec onds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanosec onds) of the para meter in question. 6. these values are guaranteed by design, and are not tested. 7. this specification is for config uration mode only. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. vm sysclk all inputs vm = midpoint voltage (1.4 v) 10a 10b 11a 11b
pid7t-603e hardware specifications, rev. 5 10 freescale semiconductor electrical and thermal characteristics this figure provides the mode select input timing diagram for the pid7t-603e. figure 3. mode select input timing diagram 4.2.3 output ac specifications this table provides the output ac timing specifications for the pid7t-603e as defined in figure 4 . table 9. output ac timing specifications 1 v dd = av dd = 2.5 ?? 5% v dc, ov dd = 3.3 5%, gnd = 0 v dc, 0 ? tj ? 105 c, c l = 50 pf (unless otherwise noted) num characteristic 200, 266, 300 mhz unit note min max 12 sysclk to output driven (output enable time) 1.0 ? ns ? 13a sysclk to output valid (5.5 v to 0.8 v?ts , abb , artry , dbb )? 9.0ns3 13b sysclk to output valid (ts , abb , artry , dbb )? 8 . 0 n s 5 14a sysclk to output valid (5.5 v to 0.8 v?all except ts , abb , artry , dbb ) ?11.0ns3 14b sysclk to output valid (all except ts , abb , artry , dbb )?9 . 0n s5 15 sysclk to output invalid (output hold) 1.0 ? ns 2 16 sysclk to output high impedance (all except artry , abb , dbb )? 8.0ns? 17 sysclk to abb , dbb , high impedance after precharge ? 1.0 t sysclk 4, 6 18 sysclk to artry high impedance before precharge ? 7.5 ns ? 19 sysclk to artry precharge enable 0.2 * t sysclk + 1.0 ? ns 2, 4, 7 20 maximum delay to artry precharge ? 1.0 t sysclk 4, 7 21 sysclk to artry high impedance after precharge ? 2.0 t sysclk 5, 7 mode pins hreset 10c 11c vm = midpoint voltage (1.4 v) vm
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 11 electrical and thermal characteristics this figure provides the output ti ming diagram for the pid7t-603e. figure 4. output timing diagram 4.3 jtag ac timing specifications this table provides the jtag ac ti ming specifications as defined in figure 5 ? figure 8. note: 1. all output specifications are measured fr om the 1.4 v of the rising edge of sysclk to the ttl level (0.8 v or 2.0 v) of the signal in question. both input and output timings are measured at the pin (see figure 4 ). 2. this minimum parameter assumes c l = 0 pf. 3. sysclk to output valid (5.5 v to 0.8 v) includes the extra delay associated with di scharging the external voltage from 5.5 v to 0.8 v instead of from v dd to 0.8 v (5-v cmos levels instead of 3.3-v cmos levels). 4. t sysclk is the period of the external bus clock (sysclk) in nanose conds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 5. output signal transitions from gnd to 2.0 v or v dd to 0.8 v. 6. nominal precharge width for abb and dbb is 0.5 t sysclk . 7. nominal precharge width for artry is 1.0 t sysclk . table 9. output ac timing specifications 1 (continued) v dd = av dd = 2.5 ?? 5% v dc, ov dd = 3.3 5%, gnd = 0 v dc, 0 ? tj ? 105 c, c l = 50 pf (unless otherwise noted) num characteristic 200, 266, 300 mhz unit note min max sysclk 12 14 13 15 16 ts artry abb , dbb vm vm vm = midpoint voltage (1.4 v) vm 13 20 18 17 21 19 15 16 all outputs (except ts , abb , dbb , artry )
pid7t-603e hardware specifications, rev. 5 12 freescale semiconductor electrical and thermal characteristics this figure provides the jtag clock input timing diagram. figure 5. jtag clock input timing diagram table 10. jtag ac timing specifications v dd = av dd = 2.5 5% v dc, ov dd = 3.3 5%, gnd = 0 v dc, 0 ? tj ? 105 c, c l = 50 pf num characteristic min max unit note tck frequency of operation 0 16 mhz ? 1 tck cycle time 62.5 ? ns ? 2 tck clock pulse width measured at 1.4 v 25 ? ns ? 3 tck rise and fall times 0 3 ns ? 4trst setup time to tck rising edge 13 ? ns 1 5trst assert time 40 ? ns ? 6 boundary scan input data setup time 6 ? ns 2 7 boundary scan input data hold time 27 ? ns 2 8 tck to output data valid 4 25 ns 3 9 tck to output high impedance 3 24 ns 3 10 tms, tdi data setup time 0 ? ns ? 11 tms, tdi data hold time 25 ? ns ? 12 tck to tdo data valid 4 24 ns ? 13 tck to tdo high impedance 3 15 ns ? note: 1. trst is an asynchronous signal. the setup time is for test purposes only. 2. non-test signal input timing with respect to tck. 3. non-test signal output timing with respect to tck. tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage (1.4 v)
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 13 electrical and thermal characteristics this figure provides the trst timing diagram. figure 6. trst timing diagram this figure provides the boundary-scan timing diagram. figure 7. boundary-scan timing diagram this figure provides the test access port timing diagram. figure 8. test access port timing diagram 4 5 trst tck vm input data valid output data valid output data valid tck data inputs data outputs data outputs data outputs 6 7 8 8 9 vm vm input data valid output data valid output data valid tck tdi, tms tdo tdo tdo 10 11 12 12 13 vm vm
pid7t-603e hardware specifications, rev. 5 14 freescale semiconductor pin assignments 5 pin assignments part a of figure 9 shows the pinout of the cbga package as viewed from the top surface. part b shows the side profile of the cbga packag e to indicate the dire ction of the top surface view. the pbga package has an identical pinout. part c shows the side profile of the pbga package to indi cate the direction of the top surface view. part a a b c d e f g h j k l m n p r t 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 not to scale part b substrate assembly encapsulant view die
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 15 pinout listings figure 9. pinout of the cbga and pbga packages as viewed from the top surface 6 pinout listings this table provides the pinout listing for the 603e cbga and pbga packages. table 11. pinout listing for the 255-pin cbga and pbga packages signal name pin number active i/o a[0?31] c16, e04, d13, f02, d14, g01, d15, e02, d16, d04, e13, go2, e 15, h01, e16, h02, f13, j01, f14, j02, f15, h03, f16, f04, g13, k01, g15, k02, h16, m01, j15, p01 high i/o aack l02 low i abb k04 low i/o ap[0?3] c01, b04, b03, b02 high i/o ape a04 low o artry j04 low i/o av dd a10 ?? bg l01 low i br b06 low o ci e01 low o ckstp_in d08 low i ckstp_out a06 low o clk_out d07 ?o cse[0?1] b01, b05 high o dbb j14 low i/o dbg n01 low i dbdis h15 low i dbwo g04 low i dh[0?31] p14, t16, r15, t15, r13, r12, p11, n11, r11,t12, t11, r1 0, p09, n09, t10, r09, t09, p08, n08, r08, t08, n07, r07, t07, p 06, n06, r06, t06, r05, n05, t05, t04 high i/o dl[0?31] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n1 2, t13, p03, n03, n04, r03, t01, t02, p04, t03, r04 high i/o part c substrate assembly mold compound view die
pid7t-603e hardware specifications, rev. 5 16 freescale semiconductor pinout listings dp[0?7] m02, l03, n02, l04, r01, p02, m04, r02 high i/o dpe a05 low o drtry g16 low i gbl f01 low i/o gnd c05, c12, e03, e06, e08, e09, e11, e14, f05, f07, f10, f12, g06, g08, g09, g11, h05, h07, h10, h12, j05, j07, j10, j12, k0 6, k08, k09, k11, l05, l07, l10, l12, m03, m06, m08, m09, m11, m14, p05, p12 ?? hreset a07 low i int b15 low i l1_tstclk 1 d11 ?i l2_tstclk 1 d12 ?i lssd_mode 1 b10 low i mcp c13 low i nc (no-connect) b07, b08, c03, c 06, c08, d05, d06, h04, j16 ? ? ov dd c07, e05, e07, e10, e12, g 03, g05, g12, g14, k03, k05, k12, k14, m05, m07, m10, m12, p07, p10 ?? pll_cfg[0?3] a08, b09, a09, d09 high i qack d03 low i qreq j03 low o rsrv d01 low o smi a16 low i sreset b14 low i sysclk c09 ?i ta h 1 4 low i tben c02 high i tbst a14 low i/o tc[0?1] a02, a03 high o tck c11 ?i tdi a11 high i tdo a12 high o tea h13 low i tlbisync c04 low i tms b11 high i trst c10 low i table 11. pinout listing for the 255-pin cbga and pbga packages (continued) signal name pin number active i/o
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 17 package descriptions 7 package descriptions the following sections provide the cbga and pbga package parameters and the mechanical dimensions for the 603e. 7.1 cbga package description the following sections provide the package para meters and mechanical dimensions for the cbga package. 7.1.1 package parameters the package parameters are as provided in the fo llowing list. the package type is 21 mm x 21 mm, 255-lead ceramic ball grid array (cbga). package outline 21 mm x 21 mm interconnects 255 pitch 1.27 mm (50 mil) package height minimum: 2.45 mm maximum: 3.00 mm ball diameter 0.89 mm (35 mil) maximum heat sink force 10 lbs ts j13 low i/o tsiz[0?2] a13, d10, b12 high o tt[0?4] b13, a15, b16, c14, c15 high i/o wt d02 low o v dd 2 f06, f08, f09, f11, g0 7, g10, h06, h08, h09, h11, j06, j08, j09, j11, k07, k10, l06, l08, l09, l11 ?? voltdetgnd 3 f03 low o note: 1. these are test signals for factory use only and must be pulled up to ov dd for normal machine operation. 2. ov dd inputs supply power to the i/o drivers and v dd inputs supply power to the processor core. 3. nc (no-connect) in the pid6-603e; internally tied to gnd in the pid7v-603e and pid7t-603e cbga and pbga package to indicate to the power supply that a low-voltage processor is present. table 11. pinout listing for the 255-pin cbga and pbga packages (continued) signal name pin number active i/o
pid7t-603e hardware specifications, rev. 5 18 freescale semiconductor package descriptions 7.1.2 mechanical dimensions of the cbga package this figure provides the mechanical dimensions and bottom surface nomenclature of the cbga package. figure 10. mechanical dimensi ons and bottom surface nomenclature of the cbga package 7.2 pbga package description the following sections provide the packag e parameters and mech anical dimensions. 7.2.1 package parameters the package type is 23 mm x 23 mm, 255-l ead plastic ball grid array (pbga). package outline 23 mm x 23 mm notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 0.200 f t 255x a 2x a1 corner p n 0.200 2x ? e ? 12345678910111213141516 a b c d e f g h j k l m n p r t e 0.300 t 0.150 d c h 0.150 t b ? f ? k k g s s s s ? t ? dim millimeters inches min max min max a 21.000 bsc 0.827 bsc b 21.000 bsc 0.827 bsc c 2.450 3.000 0.097 0.118 d 0.820 0.930 0.032 0.036 g 1.270 bsc 0.050 bsc h 0.790 0.990 0.031 0.039 k 0.635 bsc 0.025 bsc n 5.000 16.000 0.197 0.630 p 5.000 16.000 0.197 0.630
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 19 package descriptions interconnects 255 pitch 1.27 mm (50 mil) package height minimum: 2.1 mm; maximum: 2.6 mm ball diameter 0.76 mm (30 mil) maximum heat sink force 5 lbs 7.2.2 mechanical dimensions of the pbga package this figure shows the non-jedec pack age mechanical dimensions and bottom surface nomenclature. figure 11. package dimensions for the plastic ball grid array (pbga)?non-jedec standard note that table 11 lists the pinout to this non-jedec standard in order to be consistent with the cbga pinout. this figure shows the jedec pack age dimensions of the pbga package. t a b c d e f g h j k l m n p r 256x bottom view e 0.20 654321 b 0.15 c d d2 e2 a b 0.30 c ab side view dim min max millimeters a 2.10 2.60 a1 0.50 0.70 a2 1.10 1.20 a3 0.50 0.70 b 0.60 0.90 d 23.00 bsc d1 19.05 ref d2 e 23.00 bsc e1 19.05 ref e2 19.40 19.60 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b is measured at the maximum solder ball diameter, parallel to primary datum c. 4. primary datum c and the seating plane are 4x 7 8 9 10 11 12 13 14 15 m m top view (d1) 15x e 15x e (e1) 4x e /2 0.20 c 0.35 c a3 256x c a a1 a2 seating plane e 1.27 bsc 19.40 19.60 16
pid7t-603e hardware specifications, rev. 5 20 freescale semiconductor system design information figure 12. package dimensions for the plastic ball grid array (pbga)?jedec standard note that the pin numberings shown in figure 12 do not match table 11 ; the pinout of the non-jedec standard package (and the cbga pinout) is shown in figure 11 . note that figure 11 should be used in conjunction with table 11 for the complete pinout description. 8 system design information this section provides electrical a nd thermal design recommendations fo r successful application of 603e. u b c d e f g h j k l m n p r t 256x bottom view e 0.20 765432 b 0.15 c d d2 e2 a b 0.30 c ab side view dim min max millimeters a 2.10 2.60 a1 0.50 0.70 a2 1.10 1.20 a3 0.50 0.70 b 0.60 0.90 d 23.00 bsc d1 19.05 ref d2 e 23.00 bsc e1 19.05 ref e2 19.40 19.60 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. dimensions in millimeters. 3. dimension b is measured at the maximum solder ball diameter, parallel to primary datum c. 4. primary datum c and the seating plane are 4x 8 9 10 11 12 13 14 15 16 m m top view (d1) 15x e 15x e (e1) 4x e /2 0.20 c 0.35 c a3 256x c a a1 a2 seating plane e 1.27 bsc 19.40 19.60 17 case 1167-01
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 21 system design information 8.1 pll configuration the 603e pll is configured by the pll_cfg[0?3] si gnals. for a given sysclk (bus) frequency, the pll configuration signals set the internal cpu and vco frequency of operation. the pll configuration for the pid7t-603e is shown in th is table for nomin al frequencies. 8.2 pll power supply filtering the av dd power signal is provided on the 603e to provi de power to the clock generation phase-locked loop. to ensure stability of the internal clock, the power supplied to the av dd input signal should be filtered table 12. pll configuration pll_cfg[0:3] cpu frequency in mhz (vco frequency in mhz) bus-to-core multiplier core-to-vco multiplier bus 25 mhz bus 33.33 mhz bus 40 mhz bus 50 mhz bus 60 mhz bus 66.67 mhz bus 75 mhz 0100 2x 2x ? ? ? ? ? ? 150 (300) 0101 2x 4x ? ? 80 4 (320) 100 (400) 120 (480) 133 (532) 150 (600) 0110 2.5x 2x ? ? ? ? 150 (300) 166 (333) 187 (375) 1000 3x 2x ? ? ? 150 (300) 180 (360) 200 (400) 225 (450) 1110 3.5x 2x ? ? ? 175 (350) 210 (420) 233 (466) 263 (525) 1010 4x 2x ? ? 160 (320) 200 (400) 240 (480) 267 (533) 300 (600) 0111 4.5x 2x ? 150 (300) 180 (360) 225 (450) 270 (540) 300 (600) ? 1011 5x 2x ? 166 (333) 200 (400) 250 (500) 300 (600) ?? 1001 5.5x 2x ? 183 (366) 220 (440) 275 (550) ??? 1101 6x 2x 150 (300) 200 (400) 240 (480) 300 (600) ??? 0011 pll bypass 1111 clock off note: 1. some pll configurations may select bus, cpu, or vco frequencies which are not supported; see section 4.2.1, ?clock ac specifications ,? for valid sysclk and vco frequencies. 2. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note : the ac timing specifications given in this document do not apply in pll-bypass mode. 3. in clock-off mode, no clocking occurs inside the 603e regardless of the sysclk input. 4. 80 mhz operation is not supported for the pbga package (see ta bl e 7 ).
pid7t-603e hardware specifications, rev. 5 22 freescale semiconductor system design information using a circuit similar to the one shown in figure 13 . the circuit should be place d as close as possible to the av dd pin to ensure it filters out as much noise as possible. the 0.1 f capacitor should be closest to the av dd pin, followed by the 10 f capacitor, and finally the 10 ? resistor to v dd . these traces should be kept short and direct. figure 13. pll power supply filter circuit 8.3 decoupling recommendations due to the 603e?s dynamic power ma nagement feature, large addres s, data buses, and high-operating frequencies, it can generate transient power surges and high-fre quency noise in its power supply, especially while driving large capacitive loads. this noise must be prev ented from reaching other components in the 603e system. it requires a clean, ti ghtly regulated source of power. therefore, it is recommended that the system designer places at least one decoupling capacitor at each v dd and ov dd pin of the 603e. it is also recommended that these decoupling capacito rs receive their pow er from separate v dd , ov dd , and gnd power planes in the pcb, ut ilizing short traces to minimize inductance. these capacitors should vary in value from 220 pf to 10 ? f to provide both high- and low-frequency filtering, and should be pl aced as close as possible to their associated v dd or ov dd pin. suggested values for the v dd pins are: 220 pf (ceramic), 0.01 f (ceramic), and 0.1 f (ceramic ). suggested values for the ov dd pins are: 0.01 f (ceramic), 0.1 f (ceramic), a nd 10 f (tantalum). only smt capacitors should be used to minimize lead inductance. in addition, it is recommended that there be severa l bulk storage capacitors distributed around the pcb, feeding the v dd and ov dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should also have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?100 f (avx tps ta ntalum) or 330 f (avx tps tantalum). 8.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to v dd . unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , and gnd pins of the 603e. v dd av dd 10 ? 10 f 0 . 1 f gnd
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 23 system design information 8.5 pull-up resistor requirements the 603e requires high-resistive (weak: 10 k ? ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the nega ted state after they have been actively negated and released by the 603e or other bu s master. these signals are: ts , abb , dbb , and artry . in addition, the 603e has three open-drain style outputs that require pull-up resist ors (weak or stronger: 4.7 k ? ?10 k ? ) if they are used by the system. these signals are: ape , dpe , and ckstp_out . during inactive periods on the bus, the address and tr ansfer attributes on the bus are not driven by any master and may float in the high-impedance state for relatively long pe riods of time. since the 603e must continually monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on the 603e. it is recommended that these signa ls be pulled up through weak (10 k ? ) pull-up resistors or restored in so me manner by the system. the snooped address and transfer attribute inputs are?a[0?31], ap[0?3], tt[0?4], tbst , and gbl . the data bus input receivers are nor mally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. 8.6 thermal management information this section provides thermal mana gement information for the cbga and pbga packages for air-cooled applications. proper thermal contro l design is primarily de pendent upon the system-l evel design?the heat sink, airflow and therma l interface material. this figure shows the upper and lowe r limits of the die junction-to-amb ient thermal resistance for both package styles. the lower limit is shown for the case of a densel y populated pcb with high thermal loading of adjacent and neighboring components.
pid7t-603e hardware specifications, rev. 5 24 freescale semiconductor system design information . figure 14. typical die junction-to -ambient thermal resistance (21 mm cbga and 23 mm wb-pbga) to reduce the die-junction temperature, heat si nks may be attached to the package by several methods?adhesive, spring clip to holes in the printe d-circuit board or package, and mounting clip and screw assembly (both cbga and pgba packages); see figure 15 . caution while choosing a heat sink attachment method, an y attachment mechanism should not degrade the package structural integrit y and/or the package-to-board interconne ct reliability. for additional general information, see this paper?investigation of heat sink attach methodologies and the effects on package structural integrity and interconnect reliability . airf low velocit y (m / s) 0 5 10 15 20 25 30 35 40 0 0.5 1 1.5 2 typical low er limit typical upp er limit
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 25 system design information figure 15. package exploded cross-sectional view with heat sink the board designer can choose between several types of commercially avai lable heat sinks to place on the 603e. ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air veloci ty, spatial volume, ma ss, attachment method, assembly, and cost. adhesive or thermal interface material heat sink cbga package heat sink clip printed-circuit board option adhesive or thermal interface material heat sink pbga package heat sink clip printed-circuit board option
pid7t-603e hardware specifications, rev. 5 26 freescale semiconductor system design information 8.6.1 internal package conduction resistance for this packaging technology, the intrinsi c thermal conduction resi stance (as shown in table 3 ) versus the external thermal resistance paths are shown in this figure for a pack age with an attached heat sink mounted to a pcb. figure 16. package with heat sink mounted to a printed-circuit board 8.6.2 thermal interface materials a thermal interface material is recommended at th e package lid-to-heat sink interface to minimize the thermal contact resistance. for t hose applications where the heat sink is attached by spring clip mechanism, as shown in figure 17 . the thermal performance of thr ee thin-sheet thermal-interface materials (silicone, graphite/oil, flor oether oil), a bare joint, and a jo int with thermal grease as a function of contact pressure. as shown, the performance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a therma l resistance approximately se ven times greater than the thermal grease joint. therefore, th e synthetic grease offers the best thermal performance, considering the low-interface pressure. of course , the selection of any thermal interface material depends on many factors?thermal performance requirements, manufacturability, service temp erature, dielectr ic properties, cost, etc. external resistance external resistance internal resistance (note the internal versus ex ternal package resistance) radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 27 system design information figure 17. thermal performance of select thermal in terface material the board designer can choose between several types of thermal interfac e. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical stre ngth to meet equipment shock/vibration requirements. 8.6.3 heat sink selection example for preliminary heat sink sizing, the die-juncti on temperature can be expressed as follows: t j = t a + t r + ( ? jc + ? int + ? sa ) * p d eqn. 1 where: t j is the die-junction temperature t a is the inlet cabinet ambient temperature t r is the air temperature rise within the computer cabinet ? jc is the die junction-to-case thermal resistance ? int is the adhesive or interface material thermal resistance ? sa is the heat sink base-to-ambient thermal resistance p d is the power dissipated by the device 0 0.5 1 1.5 2 0 1020304050607080 silicone sheet (0.006 inch) bare joint floroether oil sheet (0.007 inch) graphite/oil sheet (0.005 inch) synthetic grease contact pressure (psi) specific thermal resistance (kin 2 /w)
pid7t-603e hardware specifications, rev. 5 28 freescale semiconductor system design information during operation the die-j unction temperatures (t j ) should be maintained less than the value specified in table 3 . the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a ) may range from 30 to 40 c. the air temperature ri se within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistan ce of the thermal interface material ( ? int ) is typically about 1 c/w. assuming a t a of 30 c, a t r of 5 c a cbga package ? jc = 0.095 , and a power consumption (p d ) of 3.0 watts, the following expression for t j is obtained: die-junction temperature: t j = 30 c + 5 c + (0.095 c/w + 1.0 c/w + r sa ) * 3.0 w. for example, the heat sink-to-ambient thermal resistance (r sa ) versus airflow velocity is shown in this figure. figure 18. example of heat sink-to-ambient thermal resistance versus airflow velocity assuming an air velocity of 0.5 m/s, we have an effective r sa of 7 c/w, thus t j = 30c + 5c + (0.095 c/w +1.0 c/w + 7 c/w) * 3.0 w, eqn. 2 resulting in a die-junction temperature of approximately 60 c which is well within the maximum operating temperature of the component. for a pbga package, and assuming a t a of 30 c, a t r of 5 c a pbga package ? jc = 8, and a power consumption (p d ) of 3.0 watts, the following expre ssion for die-junction temperature, t j , is obtained as: t j = 30 c + 5 c + (8 c/w + 1.0 c/w + r sa ) * 3.0 w eqn. 3 assuming an air velocity of 0.5 m/s, we have an effective r sa of 7 c/w, thus 1 3 5 7 8 00.511.522.533.5 example: pin-fin heat sink approach air velocity (m/s) heat sink thermal resistance (oc/w) (25x28x15mm) 2 4 6
pid7t-603e hardware specifications, rev. 5 freescale semiconductor 29 ordering information t j = 30c + 5c + (8 c/w +1.0 c/w + 7 c/w) * 3.0 w, eqn. 4 resulting in a die-j unction temperature of approxima tely 83 c that is well w ithin the maximum operating temperature of the component. commer cially available heat sinks have different heat sink-to-ambient thermal resistances, and may or may not need air flow. though the die junction-to-ambient and the heat sink-to-ambient th ermal resistances are a common figure-of-merit used for comparing the thermal pe rformance of various mi croelectronic packaging technologies, one should exerci se caution when only using this metr ic in determining thermal management because no single parameter can adequa tely describe three-dimensional heat flow. the final die-junction operating temperature is not only a function of th e component-level thermal resistance, but the system-level design and its operati ng conditions. in addition to the component?s power consumption, a number of factors affect the fina l operating die-junction temperature? airflow, board population (local heat flux of adjacent components), heat sink efficiency , heat sink attach, heat si nk placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today?s microelectronic equipment, the comb ined effects of the he at transfer mechanisms (radiation, convection, and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-l evel designs. to expedite system -level thermal an alysis, several ?compact? thermal-package mode ls are available within flotherm?. these are available upon request. 9 ordering information this figure provides the part numbering nomenclature fo r the pid7t-603e. note that the individual part numbers correspond to a maximum pro cessor core frequency. for availabl e frequencies, contact your local freescale sales office. in addition to the processor frequency, the part numbering scheme also consists of a part modifier and application modifier. the part modifi er indicates any enhancement(s) in the part from the original design. the application modifier may specif y special bus frequencie s or application conditions. each part number also contains a revision code. this refers to the di e mask revision number and is specified in the part numbering scheme for iden tification purposes only. figure 19. part number key mpc 603 r rx xxx x x product code part identifier part modifier application modifier (r = remapped, enhanced, low-voltage) (l = any valid pll configuration) package processor frequency (contact freescale sales office) revision level (rx = cbga without lid) (t = extended termperature range) (zt = pbga package) (vg = polymer core cbga without lid)
pid7t-603e hardware specifications, rev. 5 30 freescale semiconductor revision history 10 revision history this table summarizes revisi on history for this document. table 13. document revision history rev. number date substantive change(s) 5 9/2011 ? updated to new freescale template. ? added package info, vg = polymer core cbga without lid on figure 19 . ? deleted thermal heat sink and ther mal interface vendor details from 8.6/-23 and 8.6.2/-26 .
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