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?2007 silicon storage technology, inc. s71340-02-000 10/07 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. csf and combomemory are trademarks of silicon storage technology, inc. these specifications are subject to change without notice. preliminary specification product description the sst34wa3203 and sst34wa3204 are 32 mbit (2 mbit x16) flash memory devices with burst mode data access that utilize a singl e 1.8 v supply. when super voltage vh (11.4v to 12v) is applied to the acc pin, eight word programming is enabled for faster manufacturing- environment programming. the devices feature a 512 kword uniform multi-bank architecture that consists of four banks. the boot block, either the top or bottom block, consists of 15 standard 32 kword blocks and four parameter 8 kword blocks for added granularity. the remaining two banks each contain uniform 32 kword blocks. each 32 kword block is further divided into sixteen uniform 2 kword sectors. blocks and sectors are individually erasable for increased flexibility. any bank can be read while another bank is being erased or programmed, with zero latency. the sst34wa3203/3204 support an erase-suspend mode during which data can be programmed to, or read from, any sector or block that is not being erased. sst34wa3203/3204 support synchronous burst mode read from any address location of the memory array. the burst mode allows sequential data set reading with significantly shorter latency delays than during a random read, including 8-, 16-, 32-words or continuous or without wrap-around. the devices offer an expanded block locking scheme for data protection against any writes. each block can be individually locked. additionally, the top or bottom 8 kword parameter blocks can be individually locked for finer granularity of the top or bottom boot blocks. a 136-words security id, included on the devices, increases system design security. the security id is divided into two segments: an 8-word, 128-bit segment factory programmed with a sst unique id, and a 128- word segment that can be programmed and locked by the user. when not locked, the user programmable bits can be programmed but never erased. designed, manufactured, and tested for applications requiring low power and small form factor the sst34wa3203/3204 is offered in an extended temperature with a small footprint package to meet board space constraints requirem ent. see figure 3 for pin assignments. features: ? organized as 2m x 16 ? single voltage read and write operations ? v dd = 1.7v - 1.95v for program, erase and read ? top or bottom boot block protection ? bottom boot protection - sst34wa3203 ? top boot protection - sst34wa3204 ? multiplexed data and address for reduced i/o count ?a 15 ?a 0 multiplexed as dq 15 ?dq 0 ? addresses are latched by avd# control input when bef# is low ? low power consumption (typical) ? standby current: 4a ? auto low power mode: 4 a ? flexible memory organization ? 4 banks (512 kw) ? 63 uniform 32 kword blocks ? uniform sectors (2kword) for entire memory array ? concurrent memory operation ? read while program (rwp) ? read while erase (rwe) ? erase-suspend/erase-resume capability ? read while erase-suspend ? program while erase-suspend ? read while program during erase-suspend ? synchronous burst mode read (54 mhz/66 mhz) ? continuous, sequential linear burst ? 8/16/32-words with wrap-around burst ? 8/16/32-words without wrap-around burst ? burst access time: 13.5 ns/11.5 ns ? asynchronous random address access: 70 ns ? industry standard cfi interface compatible ? fast program and erase (typical) ? word program time: 10 s ? sector/block erase time: 15 ms ? chip erase time: 30 ms ? expanded block locking ? all blocks locked at power-up ? any block can be locked/unlocked by software ? flash security id ? 128-bit unique id ? factory preset ? 128-word non-erasable, lockable user-programmed id bits (?otp-like?) ? end-of-write detection ? data# polling ? toggle bit ? packages available ? 44-ball vfbga (6 x 8mm) ? superior reliability ? endurance per sector: 1,000,000 cycles (typical) ? greater than 100 years data retention ? all non-pb (lead-free) devices are rohs compliant 32 mbit burst mode concurrent superflash memory sst34wa3203 / sst34wa3204
2 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 device operation commands are used to initiate the memory operation functions of the device. commands are written to the device using standard microprocessor write sequences. the sst34wa3203/3204 device also has an auto low power mode which puts the device in a ?near standby? mode after data has been accessed with a valid read operation. this reduces the i dd active read current. the auto low power mode reduces the typical i dd to stand-by level. the device exits the auto low power mode with any address or control signal transition; therefore, there is no access time penalty for read cycles. . concurrent read/write operation the multi-bank architecture of this device allows zero latency concurrent read/write operation whereby the user can read from one bank while programming or erasing in another bank. with this operation a user can read system code in one bank while updating data in another bank. a unique feature of the sst34wa3203/3204 is ability to read during an erase-suspend even while programming in another bank. this feature is designed to respond to interrupt requests during concurrent operation. see table 2, current read/write state. note: for the purposes of this table, ?write? means to perform sec- tor/block or word-program operations as applicable to the appropriate bank. asynchronous read the default configuration on power-up, or after a hardware reset via the rst# pin, is asynchronous read. to read data from the memory array, the system must assert a valid address on a/dq 15 ?a/dq 0 and a 20 ?a 16 , while avd# and bef# are at v il . during the read, we# remains at v ih and clk is x for asynchronous read, the rising edge of avd# latches the address, and oe# is driven to v il . the data appears on a/dq 15 ?a/dq 0. for details, see figure 4. since the memory array is divided into four banks, each bank remains enabled for read access until the command register contents are altered. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable addresses and stable bef# to valid data at the outputs. the output enable access time (t oe ) is the delay from the falling edge of oe# to valid data at the output. the internal state machine is set to read array data upon device power-up or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. burst mode read (synchronous) the sst34wa3203/3204 default configuration on power- up or after reset is asynchronous read. however, it can be configured to operate in a synchronous read mode with a continuous, sequential linear burst operation or a linear burst operation of 8-, 16-, or 32-words length with wrap- around. before setting the device configuration to burst mode, determine the number of wait states for the initial word access time (t iacc ) and the desired burst mode? continuous with, or without, wrap-around. table 1: critical parameters critical parameters values units max random address access time 70 ns max synchronous access time (54 mhz) 13.5 ns max synchronous access time (66 mhz) 11.5 ns t1.0 1340 table 2: concurrent read/write state current operation in one bank possible operation in any other bank read no operation read write write read write no operation no operation read no operation write t2.0 1340
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 3 ?2007 silicon storage technology, inc. s71340-02-000 10/07 wait states on power up, the sst34wa3203/3204 defaults to asynchronous read operation. the device is automatically enabled for burst mode on the first rising edge on the clk input, while the avd# is held low for one clock cycle and the address is latched on the first rising edge of the clk. prior to activating the clock signal, the system determines how many wait states are desired for the initial word (t iacc ) of each burst session. the system then writes the set configuration register command sequence. the device automatically delays ry/by# by the needed number of clock cycles if data is not ready. refer to the details in ?handshaking feature? section. the initial word is output on the data bus t iacc after the active edge of the first clk cycle. each successive clock cycle automatically increments the addresses counter. subsequent words are output on the data bus t bacc after the active edge of each successive clock cycle. to return the device to asynchronous read mode, either drive bef# to v ih or drive rst# to v il ,. figure 1: synchronous/asynchronous state diagram 8-, 16-, 32-words linear burst mode with wrap- around the sst34wa3203/3204 device supports a synchronous read operation with a linear burst mode of a pre- determined word length with wrap-around. groups of 8, 16, and 32 words can be read in this way as defined in table 3. in 8, 16, and 32-words linear burst mode operation, the starting address of the linear burst sequence is the address written to the device. each successive clock cycle automatically increments the address counter until the top address of the group is reached. once the top address is reached, the address wraps back to the first address of the selected group and continues incrementing from there. an example of an 8-word linear burst mode with wrap- around is as follows: if the starting address in the 8-word mode is 11h (8 words group start = 10h, group end = 17h), the address range to be read would be 10h-17h, and the burst sequence would be 11h -12h -13h - 14h - 15h - 16h - 17h - 10h - and so on. the ry/by# pin will indicate when valid data is present on the data bus. 1340 f01.1 asynchronous read mode only power-up/ hardware reset active clk edge when avd# is low bef# vih rst# vil synchronous read mode only table 3: 8-, 16-, 32-words linear burst mode wrap-around groups group size address ranges 8 words 00000h - 00007h 00008h - 0000fh 00010h - 00017h ? (a) 1 - (a + 7h) 1. a is a multiple of 00008h, b is a multiple of 00010h, and c is a multiple of 00020h. 16 words 00000h - 0000fh 00010h - 0001fh 00020h - 0002fh ? (b) 1 - (b + fh) 32 words 00000h - 0001fh 00020h - 0003fh 00040h - 0005fh ? (c) 1 - (c + 1fh) t3.0 1340
4 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 8-16-32-words linear burst mode without wrap- around the sst34wa3203/3204 device supports a synchronous read operation without a linear burst mode. a fixed number of words predefined as 8-, 16-, or 32-words are read from consecutive addresses starting with the initial word, which is written to the device. once the fixed number of words are read completely, the burst read operation stops and the ry/by# output goes low. there is no group limitation as there is with linear burst with wrap-around. see table 3 for group definitions. an example of an 8-word linear burst mode without wrap- around is as follows: for an 8-word length burst read, if the starting address written to the device is 39h, the burst sequence would be 39-3a-3b-3c-3d-3e-3f-40h, and the read operation will be terminat ed at 40h. in a similar fashion, the 16-word and 32-word modes begin their burst sequence on the starting address written to the device, and continuously read to the predefined word length, of 16 or 32 words. the operation is similar to the continuous burst, but will stop the operation at fixed word length. if the device crosses the first 32-word address boundary during burst read, a latency may occur before data appears for the next address and ry/by# is pulsing low. if the burst read start address is 8-word boundary aligned (a0 = a1 = a2 = 0), the latency does not occur. if the host system crosses the bank boundary, the device will react in the same manner as in the continuous burst. continuous linear burst mode the sst34wa3203/3204 device supports a synchronous read operation with a continuous, sequential linear burst mode read. when in this mode, the addresses are automatically incriminated li nearly with every successive clock active edge. if the device reaches the highest memory location a ddress (fffffh), it will continue the continuous, sequential linear burst read operation by wrapping around to address 00000h. the burst operation will continue sequentially until another address is latched via the avd# pin, until bef# is driven to v ih , or until rst# is driven to v il . when an address is latched via avd# pin with active edge of clk, a new burst read will start with a new initial address. if the continuous, sequential linear burst read sequence crosses a bank boundary into a bank that is performing a programming or erasing operation, the device will provide status information. once the system has completed the status read operation, or the device has completed the program/erase operation, the system is allowed to start a new burst read operation. in this case a new address needs to be latched via the avd# pin. in synchronous, continuous, sequential, linear read array, a latency in output data may occur when a burst sequence crosses the first 32-word address boundary. if the burst read start address is 8-word boundary aligned (a 0 = a 1 = a 2 = 0), the delay does not occur. if the burst read start address is mis-aligned to an 8-word boundary, the delay occurs once per burst-mode read sequence. the ry/by# signal will indicate this delay to the system. burst register the sst34wa3203/3204 defaults to asynchronous read on power-up. however, it can be configured to operate in a synchronous read mode with continuous, sequential linear burst operation and linear burst operation of 8-, 16-, 32- words length with wrap-around. the burst register is used to configure the type of read bus access the memory will perform by setting the desired mode of burst (continuous or wrap-around) and the number of wait states for the initial word access time (t iacc ). the user can set the burst register with the set burst register command. the burst register will retain its information until it is reset via the rst# pin or after power- up. the set burst register command is initiated by executing a three-cycle command sequence. on the last bus cycle, data is c0h, address bits a 11 ?a 0 are 555h, and address bits a 17 ?a 12 set the code to be latched, as shown in table 4. upon power-up or hardware reset using the rst# pin, the device will be in the default state. the burst register can only be changed in read and erase suspend mode.
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 5 ?2007 silicon storage technology, inc. s71340-02-000 10/07 note: the device will be in the default state after hard ware reset (via rst# pin) or after power-up. burst suspend/resume the burst suspend / resume feature allows the system to temporarily suspend a synchronous burst operation during the initial access, before data is available, or after the device is reading data. when the burst operation is suspended, previously latched internal data and the current state are retained. burst suspend occurs when bef# is asserted, we# is de- asserted, and oe# is de-asserted. clk must be halted at v ih or v il . to resume the burst access, oe# is reasserted, and afterwards clk can be restarted. subsequent clk edges resume the burst sequence where it was suspended. when the burst suspend is enabled the device will enter a low power mode, in which the current consumption is reduced to typically 1ma. the ry/by# pin, which is controlled by bef#, will remain active and is not placed into a high-impedance state when oe# is de-asserted. table 4: burst mode configuration command function address value programmable initial wait state a 12 a 14 - a 13 - a 12 values 0 - 0 - 1 = 3 wait states for initial word 0 - 1 - 0 = 4 wait states for initial word 0 - 1 - 1 = 5 wait states for initial word 1 - 0 - 0 = 6 wait states for initial word 1 - 0 - 1 = 7 wait states for initial word (default) 1 - 1 - 0 = reserved 1 - 1 - 1 = reserved a 13 a 14 burst mode ty p e a 15 a 16 - a 15 values 0 - 0 = continuous burst (default) 0 - 1 = 8-word linear burst 1 - 0 = 16-word linear burst 1 - 1 = 32-word linear burst a 16 a 17 0 = linear burst with wrap-around (default) 1 = linear burst without wrap-around t4.0 1340
6 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 writing commands the sst34wa3203/3204 accept address and data information in the form of program commands. to write a command, the system needs to drive bef#, and we# to v il . the addresses are latched on the rising edge of avd# while keeping oe# at v ih , and data is latched on the rising edge of we# while keeping oe# at v ih . word-program operation the sst34wa3203/3204 are programmed on a word-by- word basis. before programming, erase the sector to be programmed. a program operation is accomplished in three phases. first, the software data protection is initiated using the three-word load sequence. next, the word address and word data are loaded. finally, the internal program operation initiates after the rising edge of the fourth we#. the program operation completes within 12 s. the sst34wa3203/3204 features an programming acceleration mode for faster programming. once the device enters the programming acceleration mode, only two write cycles are required to program a word, instead of the four cycles required in the standard program command sequence. during the program operation, the only valid reads within the bank being programmed are status reads (dq 7 data# polling and dq 2 /dq 6 toggle bits). any commands issued during an internal program operation are ignored. when the program operation is complete, the bank will return to read array mode. for program operation timing diagram and flowchart, see figure 8 and figure 22. programming acceleration operation the programming acceleration makes programing faster than using a standard program command sequence because it reduces the standard four-cycle process to two cycles. two unlock cycles initiates the programming acceleration command sequence which is followed by a third write cycle containing 20h as the programming acceleration command. the chip enters the programming acceleration mode. to program in this mode, a two-cycle programming acceleration program command sequence is all that is required. the first cycle contains the programming acceleration command, a0h; the second cycle contains the program address and data. likewise, additional data is programmed. the initial two unlock cycles required in the standard program command sequence is eliminated. this reduces the total programming time. see table 15 for programming acceleration command sequence requirements. the system issues a two-cycle programming acceleration reset command sequence to exit the programming acceleration mode and return to the read mode. the first cycle contains the data 90h, and the second cycle contains the data 00h. eight-word program an eight word program command is provided for fast data programming. at room temperature and normal v dd , the command is only enabled when the acc pin is at supervoltage vh (11.4v to 12v). the eight word program operation is initiated with the a0h command and then the host provides eight consecutive data words. the eight word program is an asynchronous operation and the clk signal is ignored. the system drives bef# low to v il and the initial address is latched on the rising edge of the first avd# pulse while keeping oe# high. data is latched on the rising edge of each we# pulse while keeping oe# high. see figure 10 for ac timings. the initial address a ini must be 8-words boundary aligned (a 0 = a 1 = a 2 = 0), otherwise the part will force the boundary alignment. each subsequent we# pulse will aut omatically increment the address of one word from a ini to a ini + 7 . the user must issue 8 data words to be programmed when in eight word program mode. standby mode the sst34wa3203/3204 enter the standby mode when both the bef# and rst# inputs are held at v dd 0.2 v. the device requires standard access time (t ce ) for read access before it is ready to read data. auto low power mode these devices have the auto lower power mode which puts it in a near standby mode. in asynchronous read mode, this happens when addresses remain stable within t acc + 60 ns after data is accessed with a valid read operation. this reduces the i dd active read current to 3 a, typically. while bef# is low, the device exits auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. while in auto low power mode, output data is latched and always available to the system. in synchronous read mode, after the avd# falling edge, the device automatically enters the auto low power mode when there is no active clk edge within t acc + 60ns. the device exits auto low power mode with an active clk edge.
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 7 ?2007 silicon storage technology, inc. s71340-02-000 10/07 memory architecture the sst34wa3203/3204 features a 4-bank,512 kword uniform multi-bank architecture. of the four banks, the top or bottom banks contain 15 standard 32 kword blocks and four parameter 8 kword bloc ks for added granularity. the remaining three banks each contain uniform 32 kword blocks. all 8 and 32 kword blocks are further divided into 4 or 16 uniform 2 kword sectors, respectively. each block and sector can be individually erased for greater flexibility. the devi ce?s unique bank architecture, allows reads from any bank while another bank is being erased (rwe) or programmed (rwp). the device also supports an erase-suspend mode that allows programming data in any other sector or block other than the one being erase-suspended. it can also read data at any memory sector or block other than the one being erased during the erase-suspend operation. suspend operations cannot be nested because the system needs to complete or resume any previously suspended operation before a new operation can be suspended. sector/block-e rase operation the sector/block-erase operation allows the system to erase the device on a sector-by-sector or block-by-block basis. the sst34wa3203/3204 offers sector-erase and block-erase modes. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode erases either the regular 32 kword blocks or the smaller 8 kword parameter blocks. the sector-erase operation is initiated by executing a six-word command sequence with sector-erase command (50h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-word command sequence with block-erase command (30h) and block address (ba) in the last bus cycle. the sector or block address is latched during the sixth cycle, either on the rising edge of avd# or on the falling edge of we# cycle, whichever occurs last, while the command (30h/50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of-erase operation can be determined using either data# polling or toggle bit methods. see figure 9 for timing waveforms and figure 26 for the flowchart. erase-suspend, eras e-resume opera- tions the erase-suspend command temporarily suspends a sector/block-erase operation which allows data to be read from any memory location, or to be programmed into any sector or block that is not suspended for an erase operation. the operation is executed by issuing the erase- suspend one-word command, b0h. the device automatically enters the erase-suspend read mode within tes, 15 s, after the erase-suspend command is issued. valid data is read from any sector or block that is not suspended from an erase operation. reading at an address location within erase-suspended sectors or blocks will output dq2 toggling and dq6 at ?1?. see table 6, write operation status, for details. while in erase-suspend mode, a word-program operations are allowed for all sectors and blocks, with the exception of the sector or block selected for erase-suspend. if a word program operation is attempted in the suspended sector or block, the command is rejected and the program operation is not performed. the system can also issue the software id entry command during the erase-suspend. after the system has issued the software id exit command, the device automatically reverts to read mode. to resume the sector/block-erase operation that is suspended, the system must issue the erase-resume command. the operation is executed by issuing the erase- resume one-word command, 30h, at any address in the last word sequence. for an erase operation bei ng suspended or re-suspended after resume, the cumulative erase time needed is greater than the erase time of a non-suspended erase operation. the accumulative erase time needed may become very long if the hold time from erase-resume to the next erase- suspend operation, t erh , is less than 330s. the erase-resume command will be ignored until any program operations initiated during erase-suspend are complete. the erase-suspend and program resume operations have no influence on the program operation. see table 5 for details of suspend-resume and concurrent operations.
8 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 chip-erase operation the sst34wa3203/3204 provides a chip-erase operation which allows the user to erase the entire memory array to the ?1? state. this is a quick way to erase the entire device. to initiate the chip-erase execute a six-word command sequence with the chip-erase command, 10h, at address 555h in the last word sequence. the erase operation begins with the rising edge of the sixth we#. during the erase operation, the only valid reads are toggle bit or data# polling. see table 15 for the command sequence, figure 9 for timing diagram, and figure 26 for the flowchart. any commands issued during the chip-erase operation are ignored, including the erase-suspend command. if wp# pin is held to v il , or one or more blocks are locked, the chip erase operation is disabled. write operation status detection the sst34wa3203/3204 optimizes the system write cycle time by providing two software means to detect the completion of a program write cycle or an erase write cycle. the software detection includes two status bits: data# polling (dq7) and toggle bit (dq6). the end-of- write detection mode, which is enabled after the rising edge of we#, initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchronous with the system; therefore, either a data# polling (dq7), or toggle bit (dq6) read may be simultaneous with the completion of the write cycle. if this occurs, the system will get an erroneous result. for example, valid data may appear to conflict with either dq7 or dq6. in order to prevent spurious rejection when an erroneous result occurs, the software routine must include a loop to read the accessed location an additional time. if both reads indicate the completion, then the write cycle has completed. ready (ry/by#) the ry/by# pin is a dedicated status output that indicates valid output data on a/dq15?a/dq0 during synchronous burst reads. when ry/by# is asserted (ry/by# = voh), the output data is valid and can be read. when ry/by# is de-asserted (ry/by# = vol), the system will wait until ry/ by# is re-asserted before expecting the next word of data. two conditions cause the ry/by# output to be low: during the initial access while in burst mode, and when the device is set to continuous burst mode and the address crosses the first 32 word boundary. in asynchronous, non-burst mode, the ry/by# pin does not indicate valid or invalid output data. instead, ry/by# = v oh when bef# = v il , and ry/by# is hi-z when bef# = v ih . data# polling (dq7) when the sst34wa3203/3204 is in the internal program operation, any attempt to read dq7 will produce the complement of the true data. once the program operation is completed, dq7 will produce true data. during internal erase operation, any attemp t to read dq7 will produce a ?0?. once the internal erase operation is completed, dq7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# pulse for program operation. for sector/ block or chip-erase, t he data# polling is valid after the rising edge of sixth we# pulse. see figure 11 for data# polling timing diagram and figure 23 for a flowchart. table 5: erase-suspend and concurrent banks state current operation in one bank possible operation in the same bank possible operation in any other concurrent bank sector/block-erase-suspend read any other sect or/block within the same bank no operation sector/block-erase-suspend read any other sector/blo ck within the same bank program any sector/block sector/block-erase-suspend program any other sector/block within the same bank no operation sector/block-erase-suspend program any other sector/block within the same bank read any sector/block sector/block-erase-suspend no operation read any sector/block sector/block-erase-suspend no operation program any sector/block t5.0 1340
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 9 ?2007 silicon storage technology, inc. s71340-02-000 10/07 toggle bits (dq6 and dq2) during the internal program or erase operation, any consecutive attempts to read dq6 will produce alternating ?1?s and ?0?s. for example, toggling between ?1? and ?0?. when the internal program or erase operation is complete, the dq6 bit will stop toggling. the device is then ready for the next operation. for sector-, block-, or chip-erase, the toggle bit (dq6) is valid after the rising edge of sixth we# pulse. dq6 will be set to ?1? if a read operation is attempted on an erase-suspended sector/block. if the program operation is initiated in a sector/block not selected for erase-suspend mode, dq 6 will toggle. an additional toggle bit is available on dq2, which can be used in conjunction with dq6 to check whether a particular sector is being actively erased or erase-suspended. table 6 shows detailed status bit information. the toggle bit (dq2) is valid after the rising edge of the last we# pulse of the write operation. see figure 12 for toggle bit the timing diagram and figure 23 for a flowchart. note: note: dq7, dq6 and dq2 require a valid address when reading status information. when in erase-suspend mode the system can read either sy nchronously (burst) or asyn- chronously. data protection the sst34wa3203/3204 provides both hardware and software features to protect nonvolatile data from inadvertent writes. hardware data protection the devise provides the foll owing protection features to prevent inadvertent writes: ? noise/glitch protection: a we# or bef# pulse of less than 5 ns will not initiate a write cycle. ? v dd power up/down detection: the write operation is inhibited when v dd is less than 0.9v. ? write inhibit mode: forcing oe# low, bef# high, or we# high will inhibit the wr ite operation. this pre- vents inadvertent writes during power-up or power- down. a cc pin when the a cc pin is brought to the supervoltage vh the eight word program command is enabled. in this case, all blocks are temporarily unprotected regardless of the block locking register. the only device operation available when a cc pin is at v h is eight word programming, the a cc pin must not be held above v ih during other operations. eight word programming is provided for fast data programming in the manufacturing environment. the device will return to normal operations when voltage is set to v ih on a cc pin and each block locking stat us will depend on the block locking register value (this is the value that each block had before the application of v h on a cc ). the a cc pin must not be left floating or unconnected. when the a cc pin is brought to v il the device is locked. the a cc pin should be at v ih for normal operations. wp# pin the sst34wa3203/3204 provides a hardware block protection which protects the 8 kwords for blocks ba0 and ba1 (sst34wa3203), and/or ba65 and ba66 (sst34wa3204). bax stands for block address as specified in table 10 and 11. the 8 kword blocks, located in the top or bottom blocks, are protected when wp# is held to v il . the program and erase operation in these bloc ks is disabled independently using the block locking register status. the user can disable the hardware protection for the outermost blocks by driving wp# to v ih . in this case, the protection status of the two outermost blocks will revert to what is indicated by the corresponding block locking registers. wp# will be latched at a specific time in the program or erase sequence. to prevent a write to the outermost blocks, wp# must be held to v il on the last write cycle of the sequence. for example, the 4th write cycle in the program sequence and the 6th write cycle in the erase sequence. if using the programming acceleration feature, on the 2nd program table 6: write operation status status dq7 dq6 dq5 dq2 normal operation standard program dq7# toggle 0 no toggle standard erase 0 toggle 0 toggle erase- suspend mode read from erase-sus- pended sec- tor/block 1 1 0 toggle read from non- erase- suspended sector/block data data data data program dq7# toggle 0 n/a t6.0 1340
10 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 cycle after the programming acceleration command is written, wp# must be held to v il on the 2nd cycle. if the wp# pin is held to v il the chip erase operation is disabled. wp# should be pulled into high state if it is not used. software block locking to prevent accidental data programming or erasing, the block lock command is used. all 32 kword main blocks and 8kw parameter blocks can be independently locked. a locked block can not be able to be programmed or erased. after power-up, all blocks are locked. changing the state-of-lock for a block is done by using the block lock/unlock command (60h). see table 15. in the third cycle the address must point to the block to be locked/unlocked. the status of the a 6 address bit will specify if the block must be locked (a 6 =v il ) or unlocked (a 6 =v ih ). after the third cycle, the state-of-lock of additional blocks in the same bank can be modified. reading the state-of-lock for each block is achieved using the read block locking register command with the address parameter that is within the block address space for details, see table 15. this command will read the block locking register. if the bl ock locking register is 0000h the block is unlocked, if it is 0001h the block is locked. the read block locking register command can be written to a bank which is either in read mode or in erase- suspend-read mode. only one bank at a time can be switched to read block locking register mode. to return the selected bank to read mode, or erase-suspend read mode, the software id exit/block locking exit command must be issued by the system. see table 15. wp# is internally ored with the block locking register. when wp# is low, the blocks are hardware write protected regardless of the state of the write-lock bit for the corresponding block locking registers. clearing the write- protect bit in any register when wp# is low will have no functional effect, even though the register may indicate that the block is no longer locked. after the third cycle, the stat e-of-lock for additional blocks in the same bank can be modified. note: the default read status of all blocks upon power-up is writ e-locked (?01h?). after power-up, when the power supply ( v dd ) is valid, the register is alterable. table 7: block locking register data reserved bits blr[15:1] write-lock bit: blr[0] hex code lock status 000000000000000 0 0000h full access 000000000000000 1 0001h write locked (default state at power-up) t7.0 1340
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 11 ?2007 silicon storage technology, inc. s71340-02-000 10/07 hardware reset (rst#) the rst# pin provides a hardware method of resetting the devices to read array data. when the rst# pin is held low for at least t rp , any in-progress operation will terminate and the device will return to read array mode. when no internal program/erase operation is in progress, a minimum period of t rh is required after rst# is driven high before a valid read can take place. the interrupted erase operation must to be reinitiated after the device resumes normal operation mode to ensure data integrity. the rst# pin is an asynchronous input signal which aborts an on-going erase or program operation and resets the device to read array mode within a time t readyw . if rst# pin is asserted during a read operation, the required time to reset the device is t ready . at this point all outputs are tri-stated, and the device ignores any read/ write operations for the duration of the rst# low pulse. the rst# reset operation w ill also reset the burst configuration register to asynchronous read mode and set the part in read array mode. the current consumption when rst# is held at vss +/- 0.2v, is reduced to i dd stand-by values. software data protection (sdp) the sst34wa3203/3204 provides the jedec approved software data protection scheme for all data alteration operations, such as program and erase. any single word program operation requires the inclusion of the three-word sequence. the three-word load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations; for instance, during the system power-up or power-down. any erase operation requires the inclusion of six- word sequence. these devices are shipped with the software data protection permanently enabled. see table 15 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode within t rc . the contents of dq15- dq8 can be v il or v ih , but no other value, during any sdp command sequence. common flash memory interface (cfi) the sst34wa3203/3204 contains the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must write a one word command or a three-word sequence, with 98h? the cfi query command?to address 555h in the last word sequence. once the device enters the cfi query mode, the system can read the cfi data at the addresses given in tables 18 through 22. the system can write the cfi entry command when the device is in read array mode and also when the device is in product identification mode. the system must write the cfi exit command to return to read mode or erase-suspend read mode from the cfi query mode. security id the sst34wa3203/3204 device offers a 136-word security id space. the secure id space is divided into two segments?one 8-word, 128-bit factory programmed segment and one 128-word user programmed segment. the first segment is programmed and locked at sst with a unique 128-bit number. the user segment is left un- programmed for the customer to program as desired. to program the user segment of the security id, the security id word-program command is required. check the end-of-write status of the security id by reading the toggle bits. do not use data# polling to detect the end-of- write. once the programming is complete, the sec id must be locked using the user sec id program lock-out, which disables any future corruption of this space. neither sec id segment?user nor factory programmed?can be erased, regardless of whether or not the sec id is locked. the secure id space can be queried by executing a three- word command sequence with enter sec id command (88h) at address 555h in the last byte sequence. to exit this mode, the exit sec id command should be executed. refer to table 8 for more details. the security id space is located at addresses 000000h to 0000ffh. the factory programmed segment is located at addresses 000000h to 000007h. the user segment is located at address 000080h to 0000ffh. the security id locked/unlocked status can be read at address 000007fh. see table 15. if dq 3 = ?1? the user segment of the security id is unlocked. when dq 3 = ?0?, the user segment of the security id is locked. once the query security id command is executed, the system can read the security id space with normal read cycles using the valid address range 0000000h to 00000ffh. see table 8 for more details. . table 8: security id valid range security id segment start address end address factory programmed 000000h 000007h user programmed 000080h 0000ffh sec id locked/ unlocked status 00007fh t8.0 1340
12 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 product identification the product identification mode identifies the devices and the manufacturer. for software operation details see table 15, for software id entry command sequence flowchart see figure 24. the product identification mode (pim) is entered by issuing two unlock cycles. this must be followed by a third cycle that contains the bank address (ba using a 20 to a 19 ) and the product identification mode command. after this third cycle, the addressed bank enters the product identification mode. the system can read the manufacturer id or the device id any number of times without re-issuing the pim command sequence. the product identification command may be written to a bank that is either in read mode or in erase-suspend read mode. the product identification command cannot be written while the device is programming or erasing another bank. if the system addresses a different bank, memory array data is read from the device following normal asynchronous read operation. no subsequent data will be made available if the device is in synchronous mode. the system must issue the software id exit command in order to return the bank previously set in product identification mode into read mode or erase-suspend read mode. note: bk x = bank address, using a 20 to a 19 . product identificatio n mode / cfi mode / security id / block locking exit in order to return the device to the standard read array mode, the software product identification / cfi / security id / block locking modes must be exited. exit is accomplished by issuing the software product identification / cfi / security id / block locking modes exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read array mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. the software product identification / cfi / security id / block locking query/exit command cannot be executed concurrent to program/ erase operations. see table 15 for the software command code, figure 25 for a flowchart. handshaking feature the device is equipped with a handshaking feature that brings out the fastest initial latency of this burst mode flash memory by simply monitoring the ry/by# signal from the device to determine when the initial word of burst data is ready to be read. in this handshaking mode, the microprocessor does not need to set its register the number of initial wait clocks . the device will indicate when the initial word of burst data is valid by the rising edge of ry/by# after oe goes low. if the handshaking feature is not used for burst mode performance optimization, then the host system must set the appropriate number of wait states in the flash device depending on clock frequency. see table 4 for more information. v dd power-up/power-down sequencing there are no restrictions on v dd sequencing during power- up or power-down. setting rst# to v il level is required during the entire v dd power sequence until the respective supplies reach their operating voltages. once v dd reach their respective operating voltages, setting rst# to v ih level is allowed. table 9: product identification address data manufacturer?s id bk x 0000h 00bfh device id sst34wa3203 bk x 0001h 975bh sst34wa3204 bk x 0001h 975ah t9.0 1340
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 13 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 2: logic diagram 1340 b01.0 state control command register data latch input/output buffers cell matrix y-gating x-decoder y-decoder address latch burst address counter burst state control chip enable output enable logic pgm voltage generator timer erase voltage generator rd/by# buffer v dd v ss rd/by# v dd detector a/dq15-a/dq0 we# rst# a cc bef# oe# a/dq15-a/dq0 a max -a16 a max -a0 avd# clk
14 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 10: sst34wa3203, 8 mbit x4 concurrent superflash multi-bank memory organization (1 of 2) bank block block size address range a ba0 8 kwords 000000h?001fffh ba1 8 kwords 002000h?003fffh ba2 8 kwords 004000h?005fffh ba3 8 kwords 006000h?007fffh ba4 32 kwords 008000h?00ffffh ba5 32 kwords 010000h?017fffh ba6 32 kwords 018000h?01ffffh ba7 32 kwords 020000h?027fffh ba8 32 kwords 028000h?02ffffh ba9 32 kwords 030000h?037fffh ba10 32 kwords 038000h?03ffffh ba11 32 kwords 040000h?047fffh ba12 32 kwords 048000h?04ffffh ba13 32 kwords 050000h?057fffh ba14 32 kwords 058000h?05ffffh ba15 32 kwords 060000h?067fffh ba16 32 kwords 068000h?06ffffh ba17 32 kwords 070000h?077fffh ba18 32 kwords 078000h?07ffffh b ba19 32 kwords 080000h?087fffh ba20 32 kwords 088000h?08ffffh ba21 32 kwords 090000h?097fffh ba22 32 kwords 098000h?09ffffh ba23 32 kwords 0a0000h?0a7fffh ba24 32 kwords 0a8000h?0affffh ba25 32 kwords 0b0000h?0b7fffh ba26 32 kwords 0b8000h?0bffffh ba27 32 kwords 0c0000h?0c7fffh ba28 32 kwords 0c8000h?0cffffh ba29 32 kwords 0d0000h?0d7fffh ba30 32 kwords 0d8000h?0dffffh ba31 32 kwords 0e0000h?0e7fffh ba32 32 kwords 0e8000h?0effffh ba33 32 kwords 0f0000h?0f7fffh ba34 32 kwords 0f8000h?0fffffh c ba35 32 kwords 100000h?107fffh ba36 32 kwords 108000h?10ffffh ba37 32 kwords 110000h?117fffh ba38 32 kwords 118000h?11ffffh ba39 32 kwords 120000h?127fffh ba40 32 kwords 128000h?12ffffh ba41 32 kwords 130000h?137fffh ba42 32 kwords 138000h?13ffffh
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 15 ?2007 silicon storage technology, inc. s71340-02-000 10/07 ba43 32 kwords 140000h?147fffh ba44 32 kwords 148000h?14ffffh ba45 32 kwords 150000h?157fffh ba46 32 kwords 158000h?15ffffh ba47 32 kwords 160000h?167fffh ba48 32 kwords 168000h?16ffffh ba49 32 kwords 170000h?177fffh ba50 32 kwords 178000h?17ffffh d ba51 32 kwords 180000h?187fffh ba52 32 kwords 188000h?18ffffh ba53 32 kwords 190000h?197fffh ba54 32 kwords 198000h?19ffffh ba55 32 kwords 1a0000h?1a7fffh ba56 32 kwords 1a8000h?1affffh ba57 32 kwords 1b0000h?1b7fffh ba58 32 kwords 1b8000h?1bffffh ba59 32 kwords 1c0000h?1c7fffh ba60 32 kwords 1c8000h?1cffffh ba61 32 kwords 1d0000h?1d7fffh ba62 32 kwords 1d8000h?1dffffh ba63 32 kwords 1e0000h?1e7fffh ba64 32 kwords 1e8000h?1effffh ba65 32 kwords 1f0000h?1f7fffh ba66 32 kwords 1f8000h?1fffffh t10.0 1340 table 10: sst34wa3203, 8 mbit x4 concurrent superflash multi-bank memory organization (2 of 2) bank block block size address range
16 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 11: sst34wa3204, 8 mbit x4 concurrent superflash multi-bank memory organization (1 of 2) bank block block size address range a ba0 32 kwords 000000h?007fffh ba1 32 kwords 008000h?00ffffh ba2 32 kwords 010000h?017fffh ba3 32 kwords 018000h?01ffffh ba4 32 kwords 020000h?027fffh ba5 32 kwords 028000h?02ffffh ba6 32 kwords 030000h?037fffh ba7 32 kwords 038000h?03ffffh ba8 32 kwords 040000h?047fffh ba9 32 kwords 048000h?04ffffh ba10 32 kwords 050000h?057fffh ba11 32 kwords 058000h?05ffffh ba12 32 kwords 060000h?067fffh ba13 32 kwords 068000h?06ffffh ba14 32 kwords 070000h?077fffh ba15 32 kwords 078000h?07ffffh ba16 32 kwords 080000h?087fffh ba17 32 kwords 088000h?08ffffh ba18 32 kwords 090000h?097fffh b ba19 32 kwords 098000h?09ffffh ba20 32 kwords 0a0000h?0a7fffh ba21 32 kwords 0a8000h?0affffh ba22 32 kwords 0b0000h?0b7fffh ba23 32 kwords 0b8000h?0bffffh ba24 32 kwords 0c0000h?0c7fffh ba25 32 kwords 0c8000h?0cffffh ba26 32 kwords 0d0000h?0d7fffh ba27 32 kwords 0d8000h?0dffffh ba28 32 kwords 0e0000h?0e7fffh ba29 32 kwords 0e8000h?0effffh ba30 32 kwords 0f0000h?0f7fffh ba31 32 kwords 0f8000h?0fffffh ba32 32 kwords 100000h?107fffh ba33 32 kwords 108000h?10ffffh ba34 32 kwords 110000h?117fffh c ba35 32 kwords 118000h?11ffffh ba36 32 kwords 120000h?127fffh ba37 32 kwords 128000h?12ffffh ba38 32 kwords 130000h?137fffh ba39 32 kwords 138000h?13ffffh ba40 32 kwords 140000h?147fffh ba41 32 kwords 148000h?14ffffh ba42 32 kwords 150000h?157fffh
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 17 ?2007 silicon storage technology, inc. s71340-02-000 10/07 ba43 32 kwords 158000h?15ffffh ba44 32 kwords 160000h?167fffh ba45 32 kwords 168000h?16ffffh ba46 32 kwords 170000h?177fffh ba47 32 kwords 178000h?17ffffh ba48 32 kwords 180000h?187fffh ba49 32 kwords 188000h?18ffffh ba50 32 kwords 190000h?197fffh d ba51 32 kwords 198000h?19ffffh ba52 32 kwords 1a0000h?1a7fffh ba53 32 kwords 1a8000h?1affffh ba54 32 kwords 1b0000h?1b7fffh ba55 32 kwords 1b8000h?1bffffh ba56 32 kwords 1c0000h?1c7fffh ba57 32 kwords 1c8000h?1cffffh ba58 32 kwords 1d0000h?1d7fffh ba59 32 kwords 1d8000h?1dffffh ba60 32 kwords 1e0000h?1e7fffh ba61 32 kwords 1e8000h?1effffh ba62 32 kwords 1f0000h?1f7fffh ba63 8 kwords 1f8000h?1f9fffh ba64 8 kwords 1fa000h?1fbfffh ba65 8 kwords 1fc000h?1fdfffh ba66 8 kwords 1fe000h?1fffffh t11.0 1340 table 11: sst34wa3204, 8 mbit x4 concurrent superflash multi-bank memory organization (2 of 2) bank block block size address range
18 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 pin description figure 3: pin assignments for 44-ball fbga (6 x 8 mm) ry/by# nc v ss clk v dd we# a cc a19 a17 nc v ddq a16 a20 avd# nc rst# wp# a18 bef# v ssq v ss a/dq7 a/dq6 a/dq13 a/dq12 a/dq3 a/dq2 a/dq9 a/dq8 oe# a/dq15 a/dq14 v ssq a/dq5 a/dq4 a/dq11 a/dq10 v ddq a/dq1 a/dq0 1340 44-vfbga p01.0 top view (balls facing down) 6 5 4 3 c d e f g h j k l m
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 19 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 12: pin descriptions symbol name functions a 20 -a 16 address inputs to provide memory addresses. a/dq 15 -a/dq 0 multiplexed address/data sixteen least-significant bi t addresses are multiplexed with data input/output. the outputs are in tri-state when oe# or bef# is high. bef# chip enable to activate the device when bef# is low. oe# output enable to gate the data output buffers we# write enable to control the write operations rst# hardware reset to reset and return the device to read mode ry/by# ready output to output the status of a burst read. ?low? = data not valid, ?high? = data valid clk clock to increment the internal address c ounter (after the initial output delay) when the part is in burst mode. clk is not required in asynchronous mode. avd# address valid input to indicate to the device that a valid address is present on the address bus wp# write protect to protect and unprotect top or bottom 8 kword (4 outermost sectors) from erase or program operation. a cc vpp power supply supervoltage vh (11.4v to 12v) input to enable eight word programming. when at v il locks all sectors. should be at v ih for all other conditions. v ddq i/o power supply to provide power for input/output buffers. v dd power supply to provide 1.7-1.95v power supply voltage. v dd and v ddq need to be shorted together in the application circuit. v ss ground v ssq ground for i/o power supply v ss and v ssq need to be shorted together in the application circuit. nc no connection unconnected pins t12.1 1340 table 13: operation mode selection mode bef# oe# we# avd# clk 1 1. default clock active edge is the rising edge. a/dq15-0 a 20 -16 rst# asynchronous read v il v il v ih pulse low x 2 2. x can be v il or v ih , but no other value. i/o ain v ih program v il v ih v il pulse low xi/o ain v ih erase v il v ih v il pulse low x i/o sector or block address, xxh 2 for chip-erase v ih standby v ih xxxxhigh z x v ih write inhibit x v il xxxi/o/ doutx v ih xxv ih x x high z / dout x v ih hardware reset xxxxxhigh z x v il product identification mode (manufacturer) v il v il v ih v il x manufacturer?s id (00bfh) see table 9 see table 9 product identification mode (device) v il v il v ih v il xdevice id 3 (xxxxh) 3. device id for sst34wa3203 is 975bh and for sst34wa3204 is 975ah. see table 9 see table 9 t13.0 1340
20 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 14: burst mode selection mode bef# oe# we# avd# clk 1 1. the address latch is reset by bef# going high, ther e is no need to wait for the clk pulse to reset it. dq address rst# load starting burst address v il v ih v ih pulse low active edge x ain v ih automatic address advance during burst read v il v il v ih v ih active edge dout x v ih terminate current burst read (with bef#) v ih xv ih x active edge high z x v ih terminate current burst read with rst# xxv ih x x high z x v il terminate current burst read and start a new burst read v il xv ih pulse low active edge high z / x ain v ih burst suspend v il v ih v ih v ih x high z x v ih t14.0 1340
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 21 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 15: software command sequence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr data addr data addr data addr data addr data word-program 555h aah 2aah 55h 555h a0h wa 3 data sector-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa x 4 50h block-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h ba x 4 30h chip-erase 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h erase-suspend xxxh b0h erase-resume xxxh 30h block lock/ unlock 5 xxxh 60h xxxh 60h bla x 6 60h read block lock- ing register 555h aah 2aah 55h bk x 55 5h 4 90h see ta b l e 1 7 see table 17 entry/query security id 7 555h aah 2aah 55h bk x 8 555h 88h user security id program 555h aah 2aah 55h 555h a5h siwa 9 data user security id program lock- out 555h aah 2aah 55h 555h 85h xx 0000h software id entry 10, 11 555h aah 2aah 55h bk x 55 5h 12 90h see ta b l e 1 7 see table 17 cfi query entry bk x x55h 98h software id exit 8, 13, 11 /cfi exit/sec id exit xxh f0h cfi query entry (3 cycles) 555h aah 2aah 55h bk x 55 5h 98h software id exit/ cfi exit/ security id exit (3 cycles) 555h aah 2aah 55h 555h f0h set burst mode configuration register 555h aah 2aah 55h cr x 55 5h 14 c0h eight word pro- gram xxh a0h 15 see table 16 for bus cycle seq. see table 16 for bus cycle seq. programming acceleration mode entry 555h aah 2aah 55h 555h 20h programming acceleration pro- gram 16 xxh a0h wa data programming acceleration pro- gram reset 17 xxh 90h xxh 00h t15.0 1340 1. address format a 11 -a 0 (hex) addresses a 12 - a 20 can be v il or v ih , but no other value, for command sequence of sst34wa3203/3204.
22 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence 3. wa = program word address. 4. sa x for sector-erase; uses a 20 -a 11 address lines ba x for block-erase; uses a 20 -a 13 address lines 5. blr indicates block locking register data: 0000h = block unlocked, 0001h = block locked. 6. bla x indicates the address of the block to be locked/unlocked; uses a 20 -a 13 address lines. this is composed by the bloc k address (ba) and either a 6 = 1 to unlock or a 6 = 0 to lock. 7. with a 20 -a 8 = 0; security id information is read with a 7 -a 0 sst factory unique id is read at address range: 000000h to 000007h (128-bit). this segment is always locked by sst. user id is read at address r ange: 000080h to 0000ffh (128-words). lock status of user segment is read with a 7 to a 0 = 00007fh. unlocked: dq 3 = 1 / locked: dq 3 = 0. 8. bk x indicates the bank address: uses a 20 -a 19 address lines. 9. siwa: security id program word address: user id can be written at address range: 000080h to 0000ffh (128-words). 10. the device does not remain in software product identification mode if powered down. 11. with a 18 -a 1 =0 and a 20 -a 19 = bk (bank address), address of the bank that is being switched to software id mode: sst manufacturer id = 00bfh, is read with a1 = 0 and a0 = 0 sst34wa3203 device id = 975bh, is read with a1 = 0 and a0 = 1 sst34wa3204 device id = 975ah, is read with a1 = 0 and a0 = 1 12. if users never lock after programming, sec id can be programm ed over the previously unprogramm ed bits (data=1) using the sec id mode again (the programmed ?0? bits cannot be reversed to ?1?). va lid word-addresses for user security id are from 000080h to 0000ffh. 13. both software id exit operations are equivalent. 14. cr = burst mode configuration register value on a 17 -a 12 (see programmable wait state configuration section). 15. eight word program command can only be executed if acc is at the supervoltage vh. acc must be at the supervoltage vh before the ?a0h? command is issued in order to enable the eight words program command. 16. the programming acceleration command sequence is required prior to this command sequence. 17. the programming acceleration reset command is required to return to normal read mode when the chip is in the programming acceleration mode. table 16: eight word program software command sequence bus cycle address 1 1. address format a 11 -a 0 (hex). addresses a 12 - a 20 can be v il or v ih , but no other value, for command sequence of sst34wa3203/3204. data 2 2. dq15-dq8 can be v il or v ih , but no other value, for command sequence. comment 1 xxxxh 3 3. x can be v il or v ih , but no other value. a0h eight word program command 2wa 4 4. wa: program word address of first word to be programmed. in eight-word program mode wa must be 8-word boundary aligned (a 0 =a 1 =a 2 =0). data a will program ?data a? at address wa 3 xxxxh data b will program ?data b? at address wa + 1 4 xxxxh data c will program ?data c? at address wa +2 5 xxxxh data d will program ?data d? at address wa +3 6 xxxxh data e will program ?data e? at address wa +4 7 xxxxh data f will program ?data f? at address wa +5 8 xxxxh data g will program ?data g? at address wa +6 9 xxxxh data h will program ?data h? at address wa +7 t16.1340
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 23 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 17: software id and read block locking registers command sequence 1st bus cycle (write) 2nd bus cycle (write) 3rd bus cycle (write) 4th bus cycle (read) addr 1 data 2 addr data addr data addr data software id entry: manufac- turer id 555h aah 2aah 55h bk x 555h 3 90h bk x x00 00bfh software id entry: device id 555h aah 2aah 55h bk x 555h 90h bk x x01 xxxxh 4 software id entry: read block locking status 555h aah 2aah 55h bk x 555h 3 90h ba x x02 blr 5 t17.0 1340 1. address format a 11 -a 0 (hex). addresses a 12 -a 20 can be v il or v ih , but no other value, for command sequence of sst34wa3203/3204. 2. dq 15 -dq 8 can be v il or v ih , but no other value, for command sequence. 3. bkx indicates the bank address: uses a 20 -a 19 address lines. bax indicates the address of the block to be locked/unlocked; uses a 20 -a 13 address lines. this is composed by the block address (bax). 4. sst34wa3203 is 975bh and for sst34wa3204 is 975ah 5. blr indicates block locking register data : 0000h = block unlocked, 0001h = block locked. table 18: cfi query identification string 1, 2 1. refer to cfi publication 100 for more details. 2. must use the same bkx when in cfi query entry mode. address data description 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0001h primary oem command set 14h 0007h 15h 0040h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t18.0 1340
24 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 19: system interface information 1 address data description 1bh 0017h v dd min (program/erase) dq7-dq4: volts, dq3-dq0: 100 millivolts 1ch 0019h v dd max (program/erase) dq7-dq4: volts, dq3-dq0: 100 millivolts 1dh 00b4h acc min (00h = no acc pin) 1eh 00c0h acc max (00h = no acc pin) 1fh 0003h typical time out for word-program 2 n s (2 3 = 8 s) 20h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 0005h typical time out for chip-erase 2 n ms (2 5 = 32 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 3 = 16 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 5 = 64 ms) t19.1 1340 1. must use the same bkx when in cfi query entry mode. table 20: device geometry information - sst34wa3203 1 1. must use the same bkx when in cfi query entry mode address data description 27h 0016h device size = 2 n bytes (16h = 22; 2 22 = 4 mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase block sizes supported by device 2dh 0003h block information (y + 1 = number of blocks; z x 256b = block size) 2eh 0000h y = 03h + 1 = 4 blocks 2fh 0040h 30h 0000h z = 40h x 256 bytes = 16 kbytes/block 31h 003eh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 3eh + 1 = 63 blocks 33h 0000h 34h 0001h z = 100h x 256 bytes = 64 kbyte/block 35h 0000h 36h 0000h 37h 0000h 38h 0000h 39h 0000h 3ah 0000h 3bh 0000h 3ch 0000h t20.1 1340
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 25 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 21: device geometry information - sst34wa3204 1 1. must use the same bkx when in cfi query entry mode. address data description 27h 0016h device size = 2 n bytes (16h = 22; 2 22 = 4 mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase block sizes supported by device 2dh 003eh block information (y + 1 = number of blocks; z x 256b = block size) 2eh 0000h y = 3eh + 1 = 63 blocks 2fh 0000h 30h 0001h z = 100h x 256 bytes = 64 kbyte/block 31h 0003h block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 03h + 1 = 4 blocks 33h 0040h 34h 0000h z = 40h x 256 bytes = 16 kbytes/block 35h 0000h 36h 0000h 37h 0000h 38h 0000h 39h 0000h 3ah 0000h 3bh 0000h 3ch 0000h t21.1 1340
26 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 22: primary vendor-specific extended query 1 address data description 40h 0050h query unique ascii string ?pri? 41h 0052h 42h 0049h 43h 0031h major version number, ascii 44h 0033h minor version number, ascii 45h 0005h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon technology (bits 5-2) 0001 = 0.18 m 46h 0002h erase-suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h block protect 0 = not supported, x = number of blocks in per group 48h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 0005h sector protect/unprotect scheme 00 = not supported, 01 = supported 4ah 0018h simultaneous operation number of sectors in all banks except boot bank 4bh 0001h burst mode type 00 = not supported, 01 = supported 4ch 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 00b4h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 00c0h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 00xxh top/bottom boot sector flag 01h = bottom boot device, 02h = top boot device 50h 0000h program suspend. 00h = not supported 57h 0004h bank organization: x = number of banks 58h 0013h (sst34wa3203) 0010h (sst34wa3204) bank a region information. x = number of blocks in bank 59h 0010h bank b region information. x = number of blocks in bank 5ah 0010h bank c region information. x = number of blocks in bank 5bh 0010h (sst34wa3203) 0013h (sst34wa3204) bank d region information. x = number of blocks in bank t22.1 1340 1. must use the same bkx when in cfi query entry mode.
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 27 ?2007 silicon storage technology, inc. s71340-02-000 10/07 electrical specifications absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +125c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0 .5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v voltage on acc pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +14v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds 1. please consult the factory for the latest information. output short circuit current 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 2. outputs shorted for no more than one second. no more than one output shorted at a time. operating range range ambient temp v dd extended -20c to +85c 1.7v-1.95v ac conditions of test input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 20 and 21
28 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 dc characteristics table 23: dc operating characteristics v dd = 1.7-1.95v symbol parameter freq limits test conditions min max units i dd 1 1. address input = v il t/ v ih t, v dd = v dd max active v dd current asynchronous read 5 mhz 10 ma bef#=v il , oe#=we#=v ih , array background is 55aah program and erase 40 ma bef#=we#=v il , oe#=a cc =v ih concurrent read/write 60 ma bef#=v il , oe#=v ih i ddb active v dd burst read current 54 mhz 30 ma bef#=v il , oe#=v ih , we#=v ih , array background is 55aah i sb standby v dd current 50 a bef#= 0.1v rst#= v dd -0.1v all other inputs= 0.1v or v dd -0.1v i alp 2 2. device enters the auto low power mode when addresses are stable for t acc + 60ns. auto low power v dd current 50 a bef#= 0.1v rst#= v dd -0.1v oe#= v dd -0.1v we#= v dd -0.1v all other inputs= 0.1v or v dd -0.1v i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max i h supervoltage current for acc eight-word program 10 ma v dd =v dd max, a cc =v h max v il input low voltage 0.4 v v dd =v dd min v ih input high voltage v dd - 0.4 v v dd =v dd max v ol output low voltage 0.1 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.1 v i oh =-100 a, v dd =v dd min v h supervoltage for acc eight-word program 11.4 12 v v dd = 1.8v v lko low v dd lock-out voltage 1.0 1.4 v t23.0 1340 table 24: capacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum ci/o 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. i/o pin capacitance vi/o = 0v 10 pf cin 1 input capacitance vin = 0v 10 pf t24.0 1340 table 25: reliability characteristics symbol parameter minimum spec ification units test method nend 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. endurance 100,000 cycles jedec standard tdr 1 data retention 100 years jedec standard a103 ilth 1 latch up 100 + i dd ma jedec standard 78 t25.0 1340
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 29 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 26: synchronous/burst read (54mhz/66mhz) cycle timing parameters v dd = 1.7-1.95v 1 1. not 100% tested. symbol parameter 54 mhz 66 mhz units min max min max t iacc initial access time 87.5 70 ns t bacc burst access time, valid clock to output delay 13.5 11.5 ns t acs address setup time to clk 2 2. test conditions: output load: v dd : 30pf input pulse levels: 0.0v to v dd input: 0.5 x v dd input rise and fall times: 5ns timing measurements reference level output: 0.5 x v dd 54 ns t ach address hold time from clk 2 76 ns t bdh data hold time from next clock cycle 3 3 ns t oe oe# to data valid (oe# to ry/by# valid) 13.5 11.5 ns t cez bef# to high-z 10 10 ns t oez oe# to high-z 10 10 ns t ces bef# setup time to clk 5 4 ns t racc ry/by# access time from clk 13.5 11.5 ns t ry/by#s ry/by# setup time to clk 5 4 ns t avds avd# setup time to clk 5 4 ns t avdh avd# hold time from clk 7 6 ns t avdo avd# high to oe# low 7 6 ns t cka clk to access resume 13.5 11.5 ns t oech oe# hold time from clk for burst-suspend 5 4 ns t aah address hold time from rising edge of avd# 7 6 ns t26.1340
30 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 27: asynchronous read cycle timing parameters v dd = 1.7-1.95v symbol parameter 54 mhz 66 mhz units min max min max t ce access time from bef# low 70 70 ns t acc asynchronous access time 1 70 70 ns t avdp avd# low time 12 11 ns t aas address setup time to rising edge of avd# 5 4 ns t aah address hold time from rising edge of avd# 7 6 ns t oe oe# to data valid 13.5 11.5 ns t oeh output enable hold time from we# high (read operation) 0 0 ns output enable hold time from we# high (toggle and data poll) 10 10 ns t oez output enable to high-z 2 10 10 ns t cez bef# to high-z 2 10 10 ns t27.0 1340 1. asynchronous access time is from the last of either stable addresses or the falling edge of avd# 2. not 100% tested table 28: program/erase cycle timing parameters 1 1. not 100% tested. symbol parameter 54 mhz 66 mhz units min max min max t bp word-program time 15 15 s t wc write cycle time 70 45 ns t avdp avd# low time 12 11 ns t clah bef# low to avd# high 10 10 ns t ds data setup time to we# 40 25 ns t dh data hold time to we# 00 ns t ghwl read recovery time before write 00 ns t ch bef# hold time to we# 00 ns t wp we# pulse width 45 25 ns t wph we# pulse width high 25 20 ns t srw latency between read and write operations 00 ns t cs bef# set up time to we# 00 ns t ahwl avd# high to we# low 65 ns t ida software id access and exit time 150 150 ns t se sector erase time 25 25 ms t be block erase time 25 25 ms t sce chip erase time 50 50 ms t es erase suspend latency time 15 15 s t erh erase-resume hold time to the next erase-suspend 330 330 s t vh rise time to the supervoltage vh 500 500 ns t vlht voltage transition time 11s t28.0 1340
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 31 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 29: power up timings 1 1. not 100% tested. symbol parameter minimum units tpu-read power-up to read operation 100 s tpu-write power-up to write operation 100 s t rsth rst# low hold time after v dd /v ddq setup 50 s t29.0 1340 table 30: hardware reset symbol parameter min max units treadyw rst# pin low to read mode (during embedded algorithm) 1 1. not 100% tested. 35 us tready rst# pin low to read mode (not during embedded algorithm) 1 500 ns trp rst# pulse width 500 ns trh rst# high time before read 200 ns trpd rst# low to stand-by mode 20 us t30.0 1340
32 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 4: asynchronous mode read table 31: clock input ac parameter 1 symbol parameter 54 mhz 66 mhz units min max min max f clk clk frequency 54 66 mhz t clk clk period 18.5 15 ns t ch clk high time from 90% v dd ? 90% v dd 4.5 3.5 ns t cl clk low time from 10% v dd ? 10% v dd 4.5 3.5 ns t chcl clk fall / rise time from 90% ? 10% / 10% ? 90% 3 3 ns t chlh clk high / low time from 50% v dd ? 50% v dd 7.5 6.5 ns t31.0 1340 1. not 100% tested. 1340 f11.0 bef# t avdp a/dq 15 - a/dq 0 a 20 -a 16 note: ra = read address, rd = read data. we# oe# t aah valid rd t aas ra t ce t oe t oeh t oez avd# ra t acc
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 33 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 5: clk synchronous burst mode read figure 6: 8-word linear burst with wrap-around clk bef# a 20 ? a 16 ry/by# a/dq 15 ? a/d 0 1340 f9.0 avd# aa oe# t ces 15.2 ns typ. (66 mhz) t cez t avds t avdh aa t acs t bdh t bacc da +1 da + 2 da da +n t oez t ach t iacc t oe t racc t rd/by# t avdo t aah t bdh clk bef# a 20 ? a 16 ry/by# d q 15 ? a/dq 0 1340 f10.0 avd# aa oe# t ces ( 54 mhz) t avds t acs t ach t iacc t oe t racc t rd/by# 12 3 4 5 6 7 t bacc aa da +1 da + 2 da da +n t aah note: figure assumes seven wait states for initial access , 54 mhz clock, and automatic detect synchronous read. d0-d7 in data waveform indicate the order of data with in a given 8-word address range, from lowest to highest. data will wrap around within the 8 words, non-stop unless the reset# is asserted low, or avd# locks in another address. the device will output rd/by# with valid data.
34 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 7: burst suspend figure 8: program operation timings d19 d20 a/dq 15 -a/dq 0 a 20 -a 16 clk v ih d20 d22 d21 d23 d24 d25 d26 1340 f21.2 avd# oe# ry/by# bef# v il t oech t oe v ih program command sequence (last two cycles) t cs read status data pa va va a0h pd complete in progress t pu-read t wp t wc t wph t ahwl tbp t ch t dh t ds t clah t avdp t aas clk avd# a 20 -a 16 a/dq 15 -a/dq 0 bef# oe# we# v dd t aah 555h va va pa 1340 f12.0 note: pa= program address, pd = program data, va = valid address for reading status bits. ?in progress? and ?complete? refer to status of program operation. a max to a 12 are don?t care during sdp command sequence cycles. clk is don?t care. addresses are latched on the rising edge of avd.
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 35 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 9: chip/block/sector erase command sequence 1340 f13.2 erase command sequence (last two cycles) read status data sa/ba va va 55h 50h complete in progress clk avd# a 20 -a 16 a/dq 15 -a/dq 0 bef# oe# we# v dd 2aah sa/ba va va 555h for chip erase 30h for block erase 10h for chip erase t avdp t clah t aah t aas t ds t dh t ch t wp t pu-read t cs t wph t wc t se /t be /t sce note: sa is the sector address for sector erase. ba is the block address for block erase. address bits a 20 to a 12 are don?t care during sdp cycl es in the command sequence.
36 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 10: eight words programming figure 11: data# polling timings (during embedded algorithms) 1340 f8.0 a 20 - a 16 we# 555h data a a0h a ini data a+1 . . . data a+2 data a+6 oe# bef# t bp t vlht t vh v h v dd a cc v ih a/dq 15 -a/dq 0 avd# data a+7 t ds t aas t aah a ini t dh 1340 f14.0 avd# we# a 20 -a 16 oe# bef# status data va t ce a/dq 15 -a/dq 0 va status data t ch t oeh t acc t oe t cez t oez va va note: va = valid address. two read cycles are required to determine status. when the embedded algorithm operation is complete , the data# polling will output true data. avd# must toggle between data reads.
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 37 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 12: toggle bit timings (during embedded algorithms) figure 13: latency with boundary crossing 1340 f15.0 avd# we# a 20 -a 16 oe# bef# status data va t ce a/dq 15 -a/dq 0 va status data t ch t oeh t acc t oe t cez t oez va va note: va = valid address. two read cycle s are required to determine status. when the embedded algorithm operation is complete, the data# polling will output true data. avd# must toggle between data reads. address boundary occurs every 32 words, beginning at address 00001fh (00003fh, 00005fh, etc.). address 000000h is also a boundary crossing. a/dq 15 -a/dq 0 ry/by# avd# address (hex) clk (stays high) d29 d30 d31 d32 d33 d34 d35 d36 1d 1e 1f 1f 1f 20 21 21 22 23 c29 c30 c31 c31 c31 c32 c32 c33 c34 c35 latency 1340 f17.0 t racc note: cxx indicates which clock triggers dxx at the output. for example, c30 triggers d30. the figure shows that the device does not cross a bank when performing an erase or program operation. the latency with boundary crossing happens at the 32-word boundary.
38 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 14: boundary crossing into program/erase bank figure 15: example of wait state insertion a/dq 15 -a/dq 0 ry/by# avd# address (hex) clk (stays high) (stays high) d253 d254 d255 read status c253 c254 c255 c256 c257 1340 f18.0 3fffd 3fffe 3ffff 40000 40001 bef#/oe# (stays low) note: cxxx indicates which clock triggers dxxx at the output. for example, c253 triggers d253. the figure shows that the device cross a bank when performing an erase or program operation. a/dq 15 -a/dq 0 oe# avd# clk d0 d1 0 1 2 3 4 5 1 2 3 4 5 6 7 total number of clock cycles following avd# falling edge rising edge of next clock cycle following last wait state triggers next burst data 1340 f19.0 number of clock cycles programmed wait state decoding addresses: a14, a13, a12 = ?101? => 5 programmed, 7 total a14, a13, a12 = ?100? => 4 programmed, 6 total a14, a13, a12 = ?011? => 3 programmed, 5 total a14, a13, a12 = ?010? => 2 programmed, 4 total a14, a13, a12 = ?001? => 1 programmed, 3 total note: figure assumes address. d0 is not an address boundary, active clock edge is rising, and wait state is set to ?101.?
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 39 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 16: back-to-back read/write cycle timings figure 17: v dd power up diagram 1340 f20.0 bef# a/dq 15 -a/dq 0 a 20 -a 16 we# oe# t wc avd# t dh pd/50h pa / s a t rc t rc t wc t wph t wp t ds t aah t aas ra t oeh t oe t oez t oeh t acc rd ra rd aah t ghwl last cycle in program or sector erase copmmand sequence begin another write or program command sequence read status (at least two cycles) in same bank and/or array data from other bank 555h ra ra pa / s a t srw note: breakpoints in waveforms indicate that t he system may alternately r ead array data from the ? non-busy bank? while checking the status of the program or erase operation in the ?busy? bank. the system should read status tw ice to ensure valid information. rst# t rsth v dd /v ddq 1340 f23.1 v dd min v il
40 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 18: reset timings figure 19: clock input ac waveform bef#, oe# rst# t rp t readyw reset timings not during embedded algorithms reset timings during embedded algorithms 1340 f24.0 bef#, oe# rst# t rp t ready t rh 1340 f25.1 v il v ih clk t clk t ch/l t chcl t chlh
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 41 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 20: ac input/output reference waveforms figure 21: a test load example 1340 f26.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for logic ?1? and v ilt (0.1v dd ) for logic ?0.? measurement reference points for inputs and out- puts are v it (0.5vdd) and v ot (0.5v dd ). input rise and fall times 10%?90% are <5ns. note: v it = v input te s t v ot = v output te s t v iht = v input high te s t v ilt = v input low te s t 1340 f27.0 to tester to dut c l
42 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 22: word-program algorithm 1340 f28.0 start load data: xxaah address: 555h load data: xx55h address: 2aah load data: xxa0h address: 555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed note: x can be v il or v ih , but not other value.
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 43 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 23: wait options 1340 f29.0 wait t bp , t sce , t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
44 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 24: software id/cfi entry command flowcharts 1340 f30.0 load data: xxaah address: 555h sec id query entry command sequence load data: xx55h address: 2aah load data: xx88h address: 555h wait t ida read sec id load data: xxaah address: 555h cfi query entry command sequence load data: xx55h address: 2aah load data: xx98h address: 555h wait t ida read cfi data load data: xxaah address: 555h software product id entry command sequence load data: xx55h address: 2aah load data: xx90h address: 555h wait t ida read software id note: x can be v il or v ih , but not other value.
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 45 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 25: software id/cfi exit command flowcharts 1340 f31.0 load data: xxaah address: 555h software id exit/cfi exit/sec id exit command sequence load data: xx55h address: 2aah load data: xxf0h address: 555h wait t ida return to normal operation load data: xxf0h address: xxh wait t ida return to normal operation note: x can be v il or v ih , but not other value.
46 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 figure 26: erase command sequence 1340 f32.0 load data: xxaah address: 555h chip-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx10h address: 555h load data: xxaah address: 555h wait t sce chip erased to ffffh load data: xxaah address: 555h sector-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx50h address: sa x load data: xxaah address: 555h wait t se sector erased to ffffh load data: xxaah address: 555h block-erase command sequence load data: xx55h address: 2aah load data: xx80h address: 555h load data: xx55h address: 2aah load data: xx30h address: ba x load data: xxaah address: 555h wait t be block erased to ffffh note: x can be v il or v ih , but not other value.
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 47 ?2007 silicon storage technology, inc. s71340-02-000 10/07 product ordering information valid combinations for sst34wa3203 sst34wa3203-70-5e- mvje valid combinations for sst34wa3204 sst34wa3204-70-5e- mvje note: valid combinations ar e those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations an d to determine availability of new combinations. environmental attribute e 1 = non-pb package modifier j = 44 balls package type mv= vfbga (6mm x 8mm x 0.92mm, 0.3mm ball size) temperature range e = extended = -20c to +85c minimum endurance 5=100,000 cycles read access speed 70 = 70 ns boot block protection 3 = bottom boot block 4 = top boot block psram density 0 = zero psram flash density 32 = 2m x16 voltage w = 1.7-1.95v product series 34 = concurrent superflash with mux and burst 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. device speed suffix1 suffix2 sst34w a32 0 x -xx -x x -xx x x
48 preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 ?2007 silicon storage technology, inc. s71340-02-000 10/07 package diagrams figure 27: 44-ball very fine-pitch ball grid array (vfbga) 6mm x 8mm sst package code: mvj note: 1. although many dimensions are similar to those of jedec publication 95, mo-225, this specific package is not registered . 2. all linear dimensions are in millimeters. 3. coplanarity: 0.08 mm 4. ball opening size is 0.25 mm ( 0.05 mm) p n m l k j h g f e d c b a 8 7 6 5 4 3 2 1 0.50 0.50 bottom view 0.3 0.05 (44x) a1 indicator 3.50 6.50 a1 corner top view 44-fbga-mvj-6x8-0.0 1mm detail side view seating plane 0.21 0.06 0.08 a b c d e f g h j k l m n p 8 7 6 5 4 3 2 1 0.92 0.08 8.00 0.08 6.00 0.08
preliminary specification 32 mbit burst mode concur rent superflash memory sst34wa3203 / sst34wa3204 49 ?2007 silicon storage technology, inc. s71340-02-000 10/07 table 32: revision history number description date 00 ? initial release feb 2007 01 ? changed a 18 to a 19 globally. changed a 17 to a 18 in table note 11 on page 22. ? moved bank labels b, c, and d in table 10. ? changed program-/erase-suspend to erase-suspend in table 15. ? changed program-/erase-resume to erase-resume in table 15. ? changed bax555h to bkx555h in table 15. ? changed 0008h to 0010h two places in table 22. ? changed ?program-/erase-suspend? to ?erase-suspend? in table 28. ? corrected product ordering information?package type/package modifier. may 2007 02 ? updated ?wait states? on page 3 ? changed ?a cc pin? and ?wp# pin? on page 9 ? added reference in ?handshaking feature? on page 12 ? added footnote to tables 18, 19, 20, 21, and 22 oct 2007 silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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