functional block diagram ad22057 out gnd in+ inC +v s ofs a1 a2 a1 a2 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a single-supply sensor interface amplifier ad22057 general description the ad22057 is a single-supply difference amplifier for ampli- fying and low-pass filtering small differential voltages (typically 100 mv fs at a gain of 40) from sources having a large common- mode voltage. supply voltages from +3.0 v to +36 v can be used. the input common-mode range extends from below ground to +24 v using features gain of 3 20. alterable from 3 1 to 3 160 input cmr from below ground to 6 3 (v s C 1 v) output span 20 mv to (v s C 0.2) v 1-, 2-, 3-pole low-pass filtering available accurate midscale offset capability differential input resistance 400 k v drives 1 k v load to +4 v using v s = +5 v supply voltage: +3.0 v to +36 v transient spike protection and rfi filters included peak input voltage (40 ms): 60 v reversed supply protection: C34 v operating temperature range: C40 8 c to +125 8 c applications current sensing motor control interface for pressure transducers, position indicators, strain gages, and other low level signal sources accelerometers a +5 v supply with excellent rejection of this common-mode voltage. this is achieved by the use of a special resistive attenua- tor at the input, laser trimmed to a very high differential balance. provisions are included for optional low-pass filtering and gain adjustment. an accurate midscale offset feature allows bipolar signals to be amplified. ad22057 single-pole low-pass filtering, gain: 40 power darlington 100m v 200k v c +5v analog output 4v per amp corner frequency = 0.796hz- m f analog ground solenoid load +v s (car battery) cmos driver chassis figure 1. typical application circuit for a current sensor interface one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999
ordering guide model temperature range package descriptions package options ad22057n C40 c to +125 c plastic dip n-8 ad22057r C40 c to +125 c plastic soic so-8 ad22057r-reel C40 c to +125 c tape and reel so-8* *quantities must be in increments of 2,500 pieces each. ad22057Cspecifications rev. a C2C (t a = +25 8 c, v s = +5 v, v cm = 0, r l = 10 k v unless otherwise noted) parameter comments test conditions min typ max units inputs (pins 1 and 8) +cmr positive common-mode range t a = t min to t max +24 v cmr negative common-mode range t a = t min to +85 c C1.0 v cmrr lf common-mode rejection ratio f 10 hz 80 90 db cmrr hf common-mode rejection ratio f = 1 khz 80 90 db r incm common-mode input resistance pin 1 or pin 8 to pin 2 180 240 300 k w r match matching of resistances 0.5 % r indiff differential input resistance pin 1 to pin 8 280 400 k w preamplifier g cl closed-loop gain 1 9.7 10.0 10.3 v/v v o output voltage range (pin 3) +0.01 +4.8 v r o output resistance 2 97 100 103 k w output buffer g cl closed-loop gain 1 r load 3 10 k w 1.94 2.0 2.06 v/v v o output voltage range 3 +0.02 +4.8 v r o output resistance (pin 5) v o 3 0.1 v dc 2.0 w overall system g gain 1 v o 3 0.1 v dc 19.9 20.0 20.1 v/v gain drift t a = t min to t max C62.5 +62.5 ppm/ c v os input offset voltage 4 C1 0.03 1 mv offset drift t a = t min to t max C12.5 +12.5 m v/ c ofs midscale offset (pin 7) scaling 0.49 0.50 0.51 v/v input resistance pin 7 to pin 2 2.5 3.0 k w i osc short-circuit output current 7 11 25 ma t a = t min to t max 527ma bw C3 db C3 db bandwidth v o = +1 v dc 20 30 khz sr slew rate 0.2 v/ m s n sd noise spectral density 4 f = 100 hz to 10 khz 0.2 m v/ ? hz psr power supply rejection v s = 5 v, v o = 1 v to 4.2 v v s = 24 v, v o = 1 v to 22 v t a = t min to t max v os input offset voltage 4 20.0 m v/v g gain 0.05 %/v power supply v s operating range t a = t min to t max 3536v i s quiescent supply range 5 t a = +25 c, v s = +5 v 200 500 m a temperature range t op operating temperature range C40 +125 c package plastic mini-dip (n-8) ad22057n plastic soic (so-8) ad22057r notes 1 specified for default mode i.e., with no external components. the overall gain is trimmed to 0.5% while the individual gains of a1 and a2 may be subject to a maximum 3% tolerance. note that the actual gain in a particular application can be modified by the use of external resistor networks. 2 the actual output resistance of a1 is only a few ohms, but access to this output, via pin 3, is always through a 100 k w resistor, which is trimmed to 3%. 3 for v cm 20 v. for v cm > 20 v, v ol . 1 mv/v v cm . 4 referred to the input (pins 1 and 8). 5 with v dm = 0 v. differential mode signals are referred to as v dm , while v cm refers to common-mode voltages. specifications subject to change without notice.
ad22057 C3C rev. a absolute maximum ratings* supply voltage . . . . . . . . . . . . . . . . . . . . . . . . +3.0 v to +36 v peak input voltage (40 ms) . . . . . . . . . . . . . . . . . . . . . . +60 v v ofs (pin 7 to pin 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +20 v reversed supply voltage protection . . . . . . . . . . . . . . . C34 v operating temperature . . . . . . . . . . . . . . . . C40 c to +125 c storage temperature . . . . . . . . . . . . . . . . . . C65 c to +150 c output short circuit duration . . . . . . . . . . . . . . . . indefinite lead temperature range (soldering 60 sec) . . . . . . . . +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; the functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. pin configurations plastic mini-dip package (n-8) plastic soic package (so-8) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad22057 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. product description the ad22057 is a single-supply difference amplifier consisting of a precision balanced attenuator, a very low drift preamplifier and an output buffer amplifier (a1 and a2, respectively, in figure 2). it has been designed so that small differential sig- nals (v dm in figure 3) can be accurately amplified and filtered in the presence of large common-mode voltages (v cm ) without the use of any other active components. ad22057 out gnd in+ inC +v s ofs a1 a2 a1 a2 figure 2. simplified schematic the resistive attenuator network is situated at the input to the ad22057 (pins 1 and 8), allowing the common-mode voltage at pins 1 and 8 to be six times greater than that which can be toler- ated by the actual input to a1. as a result, the input common- mode range extends to 6 (v s C 1 v). two small filter capacitors (not shown in figure 2) have been included at the inputs of a1 to minimize the effects of any spuri- ous rf signals present in the signal. internal feedback around a1 sets the closed-loop gain of the preamplifier to 10 from the input pins; the output of a1 is connected to pin 3 via a 100 k w resistor, which is trimmed to 3% (r12 in figure 2) to facilitate the low-pass filtering of the signal of interest (see low-pass filtering section). the inclusion of an additional resistive network allows the output of a1 to be offset to an optional voltage of one half of that supplied to pin 7; in many cases this offset would be +v s /2 by tying pin 7 to +v s (pin 6), permitting the conditioning and processing of bipolar signals (see strain gage interface section). the output buffer a2 has a gain of 2, setting the precalibrated, overall gain of the ad22057, with no external components, to 20. (this gain is easily user-configurablesee a ltering the gain section for details.) the dynamic properties of the ad22057 are optimized for inter- facing to transducers; in particular, current sensing shunt resistors. its rejection of large, high frequency, common-mode signals makes it superior to that of many alternative approaches. this is due to the very careful design of the input attenuator and the close integration of this highly balanced, high impedance system with the preamplifier. applications the ad22057 can be used wherever a high gain, single-supply differencing amplifier is required, and where a finite input resis- tance (240 k w to ground, 400 k w between differential inputs) can be tolerated. in particular, the ability to handle a common- mode input considerably larger than the supply voltage is fre- quently of value. also, the output can run down to within 20 mv of ground, provided it is not called on to sink any load current. finally, the output can be offset to half of a full-scale reference voltage (with a tolerance of 2%) to allow a bipolar input signal. altering the gain the gain of the preamplifier, from the attenuator input (pins 1 and 8) to its output at pin 3, is 10 and that of the output buffer, from pin 4 to pin 5, is 2, thus making the overall de- fault gain 20. the overall gain is accurately trimmed (to within 0.5%). in some cases, it may be desirable to provide for some variation in the gain; for example, in absorbing the scaling error of a transducer. warning! esd sensitive device top view (not to scale) 8 7 6 5 1 2 3 4 Cin gnd a1 +in offset +v s out a2 ad22057 top view (not to scale) 8 7 6 5 1 2 3 4 Cin gnd a1 a2 +in offset +v s out ad22057
ad22057 C4C rev. a figure 3 shows a general method for trimming the gain, either upward or downward, by an amount dependent on the resistor, r. the gain range, expressed as a percentage of the overall gain, is given by (10 m w /r)%. thus, the adjustment range would be 2% for r = 5 m w ; 10% for r = 1 m w , etc. ad22057 +in ofs +v s out Cin gnd a1 a2 v dm v cm r (see text) v dm = differential voltage, v cm = commom-mode voltage analog output 6 gain adjust 20k v min analog common figure 3. altering gain to accommodate transducer scaling error in addition to the method above, another method may be used to vary the gain. many applications will call for a gain higher than 20, and some require a lower gain. both of these situa- tions are readily accommodated by the addition of one external resistor, plus an optional potentiometer if gain adjustment is required (for example, to absorb a calibration error in a trans- ducer). decreasing the gain. see figure 4. since the output of the preamplifier has an output resistance of 100 k w , an external resistor connected from pin 4 to ground will precisely lower the gain by a factor r/(100k+r). when configuring the ad22057 for any gain, the maximum input and the power supply being used should be considered, since either the preamplifier or the output buffer will reach its full-scale output (approxim ately v s C 0.2 v) with large differential input voltages. the input of the ad22057 is limited to no greater than (v C 0.2)/10, for overall gains less than 10, since the preamplifier, with its fixed gain of 10, reaches its full scale output before the output buffer. for v s = 5 v this is 0.48 v. for gains greater than 10, however, the swing at the buffer output reaches its full-scale first and limits the ad22057 input to (v s C 0.2)/g, where g is the overall gain. in creasing the power supply voltage increases the allowable m aximum input. for v s = 5 v and a nominal gain of 20, the maximum input is 240 mv. the overall bandwidth is unaffected by changes in gain using this method, although there may be a small offset voltage due to the imbalance in source resistances at the input to a2. in many cases this can be ignored but, if desired, can be nulled by insert- ing a resistor in series with pin 4 (at point x in figure 4) of value 100 k w minus the parallel sum of r and 100 k w . for example, with r = 100 k w (giving a total gain of 10), the op- tional offset nulling resistor is 50 k w . ad22057 +in ofs +v s out Cin gnd a1 a2 v dm v cm r analog output analog common point x (see text) gain = CCCCCCCCC 20r r + 100k v r = 100k CCCCCCCCC gain 20 C gain figure 4. achieving gains less than 20 increasing the gain. the gain can be raised by connecting a resistor from the output of the buffer amplifier (pin 5) to its noninverting input (pin 4) as shown in figure 5. the gain is now multiplied by the factor r/(rC100k); for example, it is doubled for r = 200 k w . overall gains of up to 160 (r = 114 k w ) are readily achievable in this way. note, however, that the accu- racy of the gain becomes critically dependent on resistor value at high gains. also, the effective input offset voltage at pins 1 and 8 (about six times the actual offset of a1) limits the parts use in very high gain, dc-coupled applications. the gain may be trimmed by using a fixed and variable resistor in series (see, for example, figure 10). ad22057 +in ofs +v s out Cin gnd a1 a2 v dm v cm analog output analog common point x (see text) gain = CCCCCCCCC 20r r C 100k v r = 100k CCCCCCCCC gain gain C 20 r figure 5. achieving gains greater than 20 once again, a small offset voltage will arise from an imbalance in source resistances and the finite bias currents inherently present at the input of a2. in most applications this additional offset error (about 130 m v at 40) will be comparable with the specified offset range and will therefore introduce negligible skew. it may, however, be essentially eliminated by the addition of a resistor in series with the parallel sum of r and 100 k w (i.e., at point x in figure 5) so the total series resistance is maintained at 100 k w . for example, at a gain of 30, when r = 300 k w and the parallel sum of r and 100 k w is 75 k w , the padding resistor should be 25 k w . a 50 k w pot would provide an offset range of about 2.25 mv referred to the output, or 75 m v referred to the attenuator input. a specific example is shown in figure 12. low-pass filtering in many transducer applications it is necessary to filter the sig- nal to remove spurious high frequency components, including noise, or to extract the mean value of a fluctuating signal with a peak-to-average ratio (par) greater than unity. for example, a full wave rectified sinusoid has a par of 1.57, a raised cosine has a par of 2 and a half wave sinusoid has a par of 3.14. signals having large spikes may have pars of 10 or more. when implementing a filter, the par should be considered so the output of the ad22057 preamplifier (a1) does not clip before a2 does, since this nonlinearity would be averaged and appear as an error at the output. to avoid this error both ampli- fiers should be made to clip at the same time. this condition is achieved when the par is no greater than the gain of the second amplifier (2 for the default configuration). for example, if a par of 5 is expected, the gain of a2 s hould be increased to 5. low-pass filters can be implemented in several ways using the features provided by the ad22057. in the simplest case, a single-pole filter (20 db/decade) is formed when the output of a1 is connected to the input of a2 via the internal 100 k w resis- tor by strapping pins 3 and 4, and a capacitor added from this node to ground, as shown in figure 6. the dc gain remains 20, and the gain trim shown in figure 3 may still be used. if a resis- tor is added across the capacitor to lower the gain, the corner
ad22057 C5C rev. a frequency will increase; it should be calculated using the parallel sum of the resistor and 100 k w . ad22057 +in ofs +v s out Cin gnd a1 a2 v dm v cm analog output analog common corner frequency = 1 2 p c 3 100k v that is, 1.59hz- m f (c is in farads) c figure 6. connections for single-pole, low-pass filter if the gain is raised using a resistor, as shown in figure 5, the corner frequency is lowered by the same factor as the gain is raised. thus, using a resistor of 200 k w (for which the gain would be doubled) the corner frequency is now 0.796 hz- m f, (0.039 m f for a 20 hz corner). ad22057 +in ofs +v s out Cin gnd a1 a2 v dm v cm analog output analog common corner frequency = 1hz- m f c c 255k v figure 7. connections for conveniently scaled, two-pole, low-pass filter a two-pole filter (with a roll-off of 40 db/decade) can be imple- mented using the connections shown in figure 7. this is a sallen & key form based on a 2 amplifier. it is useful to remem- ber that a two-pole filter with a corner frequency f 2 and a one-pole filter with a corner at f 1 have the same attenuation at the frequency (f 2 2 /f 1 ) . the attenuation at that frequency is 40 log(f 2 /f 1 ). this is illustrated in figure 8. using the standard resistor value shown, and equal c apacitors (in figure 7), the corner frequency is conveniently scaled at 1 hz- m f (0.05 m f for a 20 hz corner). a maximally flat response occurs when the resistor is lowered to 196 k w and the scaling is then 1.145 hz- m f. the output offset is raised by about 4 mv (equivalent to 200 m v at the input pins). attenuation f 1 f 2 40log (f 2 /f 1 ) frequency C20db/decade C40db/decade ( f 2 2 /f 1 ) a 1-pole filter, corner f 1 , and a 2-pole filter, corner f 2 , have the same attenuation, C40log (f 2 /f 1 ), at frequency f 2 2 /f 1 figure 8. comparative responses of one- and two-pole low-pass filters a three-pole filter (with roll-off 60 db/decade) can be formed by adding a passive rc network at the output forming a real pole. a three-pole filter with a corner frequency f 3 has the same attenuation a one-pole filter of corner f 1 has at a frequency ? f 3 3 /f 1 , where the attenuation is 30 log (f 3 /f 1 ) (see the graph in figure 9). using equal capacitor values, and a resistor of 160 k w , the corner-frequency calibration remains 1 hz- m f. attenuation f 1 f 3 30log (f 3 /f 1 ) frequency C20db/decade C60db/decade (f 3 3 /f 1 ) C30log (f 3 /f 1 ), at frequency (f 3 3 /f 1) a 1-pole filter, corner f 1 , and a 3-pole filter, corner f 3 , have the same attenuation, figure 9. comparative responses of one- and three-pole low-pass filters current sensor interface a typical automotive application making use of the large common-mode range is shown in figure 10. ad22057 +in ofs +v s out Cin gnd a1 a2 100m v solenoid load power darlington cmos driver +v s (battery) chassis c 191k v 20k v +5v analog output 4v per amp 6 5% sensor calibration corner frequency = 0.796hz- m f (0.22 m f for f = 3.6hz) analog common flyback diode figure 10. current sensor interface. gain is 40, single- pole low-pass filtering the current in a load, here shown as a solenoid, is controlled by a power transistor that is either cut off or saturated by a pulse at its base; the duty-cycle of the pulse determines the average current. this current is sensed in a small resistor. the aver- age differential voltage across this resistor is typically 100 mv, although its peak value will be higher by an amount that depends on the inductance of the load and the control fre- quency. the common-mode voltage, on the other hand, extends from roughly 1 v above ground, when the transistor is satu- rated, to about 1.5 v above the battery voltage, when the tran- sistor is cut off and the diode conducts. if the maximum battery voltage spikes up to +20 v, the common- mode voltage at the input can be as high as 21.5 v. this can be measured using even a +5 v supply for the ad22057.
ad22057 C6C rev. a to produce a full-scale output of +4 v, a gain 40 is used, adjust- able by 5% to absorb the tolerance in the sense resistor. there is sufficient headroom to allow at least a 10% overrange (to +4.4 v). the roughly triangular voltage across the sense resistor is aver- aged by a single-pole low-pass filter, here set with a corner fre- quency of f c = 3.6 hz, which provides about 30 db of attenuation at 100 hz. a higher rate of attenuation can be obtained by a two-pole filter having f c = 20 hz, as shown in figure 11. al- though this circuit uses two separate capacitors, the total capaci- tance is less than half that needed for the single-pole filter. ad22057 +in ofs +v s out Cin gnd a1 a2 100m v solenoid load power darlington cmos driver +v s (battery) chassis c 432k v 50k v +5v analog output corner frequency = 1hz- m f (0.05 m f for f c = 20hz) analog common flyback diode 127k v c figure 11. illustration of two-pole low-pass filtering strain gage interface: midscale offset feature the ad22057 can be used to interface a strain gage to a subse- quent process where only a single supply voltage is available. in this application, the midscale offset feature is valuable, since the output of the bridge may have either polarity. figure 12 shows typical connections. ad22057 +in ofs +v s out Cin gnd a1 a2 r l 10k v +v s analog output analog common 100k v v os null optional lp filter 125k v (sets gain to 3 100) v g r r r r figure 12. typical connections for a strain gage interface using the offset feature the offset is obtained by connecting pin 7 (ofs) to the supply voltage. in this way, the output of the ad22057 is centered to midway between the supply and ground. in many systems the supply will also serve as the reference voltage for a subsequent a/d converter. alternatively, pin 7 may be tied to the reference voltage from an independent source. the ad22057 is trimmed to guarantee an accuracy of 2% on the 0.5 ratio between the voltage on pin 7 and the output. an ac excitation of up to 2 v can also be used because the common-mode range of the ad22057 extends to C1 v. assum- ing a full-scale bridge output (v g ) of 10 mv, a gain of 100 might be used to provide an output of 1 v (a full-scale range of +1.5 v to +3.5 v). this gain is achieved using the method discussed in connection with figure 5. note that the gain- setting resistor does not affect the accuracy of the midscale offset. (however, if the gain were lowered, using a resistor to ground, this offset would no longer be accurate.) a v os nulling pot is included for illustrative purposes. one-, two- and three- pole filtering can also be implemented, as discussed in the low-pass filtering section. using the midscale offset feature figure 13 shows a more detailed schematic of the output am- plifier a2. because this is a single supply device, the output stage has no pull-down transistor. such a transistor would limit the minimum output to several hundred millivolts above ground. when using the ad22057 in unipolar mode (pin 7 grounded), the resistors making up the feedback network also act as a pull-down for the output stage. a2 10k v 95k v +v s 20k v ofs out 20k v r l gnd figure 13. detailed schematic of output amplifier a2 if the output is called upon to source current (not sink), then it can swing almost completely to ground (within 20 mv). how- ever, if the offset pin is connected to some positive voltage source, this source will pull up the output voltage, thereby limiting the minimum output swing. with no external load the minimum output voltage possible is v ofs /2. for example, if pin 7 is connected to +5 v, the minimum output voltage is equal to the offset voltage of 2.5 v. by adding an additional load, as shown, the output swing toward ground can be extended. the relationship is described by: v out > 1 2 v ofs r l r l + 20 k w * *this 20 k w resistor is internal to the ad22057 and can vary by 30%. where r l is an externally applied load resistor. however, r l cannot be made arbitrarily small since this would require exces- sive current from the output. the output current should be limited to 5 ma total.
ad22057 C7C rev. a application hints frequency compensation as are all closed-loop op amp circuits, the ad22057 is sensitive to capacitive loading at its output. however, the ad22057 is sensitive at higher output voltages due to nonlinear effects in the rail-to-rail des ign of the buffer amplifier (a 2). in this amplifier the output stage gain increases with increasing output voltage. this behavior does not affect dc parameters such as gain accuracy or linearity; however, it can compromise ac sta- bility. when operating from a power supply of 5 v or less (and, therefore, v out < 5 v), the ad22057 can drive capacitive loads up to 25 pf with no external components. when operat- ing at higher supply voltages (which are associated with higher output voltages) and/or driving larger capacitive loads, an exter- nal compensation network should be used. figure 14 shows an r-c snubber circuit loading the output of the ad22057. this combination, in conjunction with the internal 20 k w resis- tance, forms a lag network. this network attenuates the open- loop gain of the amplifier at higher frequencies. the ratio of r lag to the load seen by the ad22057 determines the high frequency attenuation seen by the op amp. if r lag is made 1/20th of the total load resistance ( ? 20 k w i r l ), then 26 db of attenuation is obtained at higher frequencies. the capacitor (c lag ) is used to control the frequency of the compensation network. it should be set to form a 5 m s time constant with the resistor (r lag ). table i shows the recommended values of r lag and c lag for various values of external load resistor r l . ten percent tolerance on these components is acceptable. alternatively, the signal may be taken from the midpoint of r lag Cc lag . this output is particularly useful when driving cmos analog-to-digital converters. for more information see the section driving charged redistributed a/d converters. note that when implementing this network large signal re- sponse is compromised. this occurs because there is no active pull-down and the lag capacitor must discharge through the internal feedback resistor (20 k w ) giving a fairly long-time constant. for example if c lag = 0.01 m f, the large signal negative slew char acteristic is a decaying exponential with a time constant of ? 200 m s. table i. compensation components vs. external load resistor r l r lag c lag >100 k w 470 w 0.01 m f > 50 k w 390 w 0.01 m f > 20 k w 270 w 0.047 m f > 10 k w 200 w 0.047 m f > 5 k w 100 w 0.1 m f > 2 k w 47 w 0.22 m f driving charge redistribution a/d converters when driving cmos adcs, such as those embedded in popu- lar microcontrollers, the charge injection ( d q) can cause a significant deflection in the ad22057 output voltage. though generally of short duration, this deflection may persist until after the sample period of the adc has expired. it is due to the relatively high open-loop output impedance of the ad22057. the effect can be significantly reduced by including the same r-c network recommended for improving stability (see fre- quency compensation section). the large capacitor in the lag network helps to absorb the additional charge, effectively lower- ing the high frequency output impedance of the ad22057. for these applications the output signal should be taken from the midpoint of the r lag Cc lag combination as shown in figure 15. since the perturbations from the analog-to-digital converter are small, the output of the ad22057 will appear to be a low impedance. the transient response will, therefore, have a time constant governed by the product of the two lag compo- nents, c lag r lag . for the values shown in figure 15, this time constant is programmed at approximately 10 m s. there- fore, if samples are taken at several tens of microseconds or m ore, there will be negligible stacking up of the charge injections. 10k v +v s 10k v load ad22057 a2 r lag c lag r l c l figure 14. using an r-c network for compensation 0.01 m f 1k v 10k v +v s 10k v ad22057 a2 m processor a/d in figure 15. recommended circuit for driving cmos a/d converters understanding the ad22057 figure 16 shows the main elements of the ad22057. the signal inputs at pins 1 and 8 are first applied to dual resistive attenua- tors r1 through r4, whose purpose is to reduce the common- mode voltage at the input to the preamplifier. the attenuated signal is then applied to a feedback amplifier based on the very low drift op amp, a1. the differential voltage across the inputs is accurately amplified in the presence of common-mode volt- ages of many times the supply voltage. the overall common- mode response is minimized by precise laser trimming of r3 and r4, giving the ad22057 a common-mode rejection ratio (cmrr) of at least 80 db (10,000:1). the common-mode range of a1 extends from slightly below ground to 1 v below +v s (at the minimum temperature of C40 c). since an attenuation ratio of about 6 is used, the input common-mode range is C1 v to +24 v using a +5 v supply. small filter capacitors c1 and c2 are included to minimize the effects of spurious rf signals at the inputs, which might cause dc errors due to the rectification effects at the input to a1. at high frequencies, even a small imbalance in these components would seriously degrade the cmrr, so a special high frequency trim is also carried out during manufacture.
ad22057 C8C rev. a printed in u.s.a. ad22057 a1 a2 +v s r12 100k v a2 c1 5pf r1 200k v r18 1k v a1 r19 1k v c2 5pf r4 41k v r9 10k v r7 250 v r17 95k v r15 10k v out r16 10k v r14 20k v r13 20k v r5 2.6k v r3 41k v gnd ofs r6 250k v r8 9k v r2 200k v r11 2k v r10 2k v in+ inC figure 16. simplified schematic of ad22057, including component values outline dimensions dimensions shown in inches and (mm). plastic soic package (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19)
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