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m68hc05 microcontrollers freescale.com mc68hc05rc9 mc68hc05rc18 general release specification hc05rc18grs/d rev. 2.1 08/2005

mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor list of sections 3 non-disclosure agreement required general release specification ? mc68hc05rc18 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . 15 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 section 3. central processing unit . . . . . . . . . . . . . . . . . 35 section 4. interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 section 5. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 section 6. parallel input/output (i /o) . . . . . . . . . . . . . . 55 section 7. low-power modes . . . . . . . . . . . . . . . . . . . . . 59 section 8. core timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 section 9. carrier modulator transmitter (cmt) . . . . . . 69 section 10. instruction set. . . . . . . . . . . . . . . . . . . . . . . . 87 section 11. electrical specificati ons . . . . . . . . . . . . . . 105 section 12. mechanical specifications . . . . . . . . . . . . 113 section 13. ordering information. . . . . . . . . . . . . . . . . 117 appendix a. mc68hc05rc9 . . . . . . . . . . . . . . . . . . . . 121
non-disclosure agreement required list of sections general release specif ication mc68hc05rc18 ? rev. 2.1 4 list of sections freescale semiconductor
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor table of contents 5 non-disclosure agreement required general release specification ? mc68hc05rc18 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.2 irq (maskable interrupt request) . . . . . . . . . . . . . . . . . . . 23 1.5.3 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.5 lprst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.6 iro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.7 pa0?pa7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.8 pb0?pb7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.9 pc0?pc3 (pc4?pc7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.1 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.2 rom security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.3 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
non-disclosure agreement required table of contents general release specif ication mc68hc05rc18 ? rev. 2.1 6 table of contents freescale semiconductor section 3. central processing unit 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4 index register (x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.5 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.7 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3 cpu interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.4 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.5 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.6 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6.1 external interrupt (irq /port b keyscan) . . . . . . . . . . . . . . . 43 4.6.2 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6.3 carrier modulator tr ansmitter interrupt (cmt ) . . . . . . . . . . 45 4.7 core timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 external reset (reset ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4 low-power exte rnal reset (lprst ) . . . . . . . . . . . . . . . . . . . . 50 5.5 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.5.1 power-on reset (por). . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.5.2 computer operating properly reset (copr) . . . . . . . . . . . 51 5.5.3 illegal address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
table of contents mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor table of contents 7 non-disclosure agreement required section 6. parallel input/output (i/o) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.6 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 section 7. low-power modes 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.4 stop recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.5 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.6 low-power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 section 8. core timer 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.3 core timer control and status register . . . . . . . . . . . . . . . . . . 65 8.4 core timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.5 computer operating prop erly (cop) reset . . . . . . . . . . . . . . . 67 8.6 timer during wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 section 9. carrier modu lator transmitter (cmt) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.3 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
non-disclosure agreement required table of contents general release specif ication mc68hc05rc18 ? rev. 2.1 8 table of contents freescale semiconductor 9.4 carrier generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.4.1 time counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.4.2 carrier generator data registers (chr1, clr1, chr2, and clr2) . . . . . . . . . . . . . . . . . 74 9.5 modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.1 time mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.5.2 fsk mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.5.3 extended space operation . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.5.4 modulator peri od data registers (mdr1, mdr2, and mdr3) . . . . . . . . . . . . . . . . . . . . . . 84 9.6 wait mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.7 stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 section 10. instruction set 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 10.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 10.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 10.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . 92 10.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . 93 10.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.4.4 bit manipulation instru ctions . . . . . . . . . . . . . . . . . . . . . . . . 96 10.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
table of contents mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor table of contents 9 non-disclosure agreement required section 11. electrical specifications 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 11.4 operating temperature ra nge. . . . . . . . . . . . . . . . . . . . . . . . 107 11.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.6 dc electrical characteristics (5.0 vd c). . . . . . . . . . . . . . . . . . 108 11.7 dc electrical characteristics (2.2 vd c). . . . . . . . . . . . . . . . . . 109 11.8 control timing (2.2 vdc to 5.0 v dc ) . . . . . . . . . . . . . . . . . . . . 111 section 12. mechanic al specifications 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.3 28-pin plastic dual-in-line pa ckage (case 710-02) . . . . . . . 114 12.4 28-pin small outlin e integrated circuit package (case 751f-04). . . . . . . . . . . . . . . . . . . . . . . . . . 114 12.5 44-pin plastic leaded chip carrier package (case 777-02). . . . . . . . . . . . . . . . . . . . . . . . . . .115 section 13. ordering information 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.3 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . .118 13.5 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.6 rom verification units (rvus). . . . . . . . . . . . . . . . . . . . . . . . 120 13.7 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
non-disclosure agreement required table of contents general release specif ication mc68hc05rc18 ? rev. 2.1 10 table of contents freescale semiconductor appendix a. mc68hc05rc9 a.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 a.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor list of figures 11 non-disclosure agreement required general release specification ? mc68hc05rc18 list of figures figure title page 1-1 mc68hc05rc18 block diagram . . . . . . . . . . . . . . . . . . . . .18 1-2 28-pin dip pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1-3 28-pin soic pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1-4 44-pin plcc pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 1-5 crystal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1-6 2-pin ceramic resonat or connections . . . . . . . . . . . . . . . . 25 1-7 3-pin ceramic resonat or connections . . . . . . . . . . . . . . . . 25 1-8 external clock source connections. . . . . . . . . . . . . . . . . . . 26 2-1 mc68hc05rc18 memory ma p . . . . . . . . . . . . . . . . . . . . . . 30 2-2 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3-2 stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4-1 interrupt processing fl owchart. . . . . . . . . . . . . . . . . . . . . . . 42 4-2 irq function block diagram . . . . . . . . . . . . . . . . . . . . . . . .43 5-1 reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5-2 reset and por timing diagram . . . . . . . . . . . . . . . . . . . . . 49 5-3 cop watchdog timer loca tion . . . . . . . . . . . . . . . . . . . . . . 53 6-1 port b pullup options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6-2 i/o circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7-1 stop recovery timing dia gram . . . . . . . . . . . . . . . . . . . . . . 60 7-2 stop/wait flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8-1 core timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8-2 core timer control and status re gister (ctcsr) . . . . . . . 65
non-disclosure agreement required list of figures general release specif ication mc68hc05rc18 ? rev. 2.1 12 list of figures freescale semiconductor figure title page 8-3 timer counter register (ctcr). . . . . . . . . . . . . . . . . . . . . . 67 9-1 carrier modulator transmitter module block diagram . . . . . 71 9-2 carrier generator block diagram. . . . . . . . . . . . . . . . . . . . .72 9-3 carrier data register (chr1 , clr1, chr2, and clr2) . . . 74 9-4 modulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9-5 cmt operation in time mode . . . . . . . . . . . . . . . . . . . . . . . 78 9-6 extended space operation . . . . . . . . . . . . . . . . . . . . . . . . . 80 9-7 modulator control and status register (mcsr) . . . . . . . . . 81 9-8 modulator data registers (m dr1, mdr2, and m dr3) . . . . 84 11-1 maximum supply current versus internal clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 a-1 mc68hc05rc9 memory map . . . . . . . . . . . . . . . . . . . . . 122
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor list of tables 13 non-disclosure agreement required general release specification ? mc68hc05rc18 list of tables table title page 4-1 vector address for interrupts and reset . . . . . . . . . . . . . . 41 5-1 cop watchdog timer recommendations . . . . . . . . . . . . . 52 6-1 i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8-1 rti and cop rates at 4.096-mhz oscillator. . . . . . . . . . . 66 10-1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . 92 10-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . 93 10-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . 95 10-4 bit manipulation instruct ions . . . . . . . . . . . . . . . . . . . . . . . 96 10-5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10-7 opcode map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 13-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
non-disclosure agreement required list of tables general release specif ication mc68hc05rc18 ? rev. 2.1 14 list of tables freescale semiconductor
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor general description 15 non-disclosure agreement required general release specification ? mc68hc05rc18 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5 signal description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.2 irq (maskable interrupt request) . . . . . . . . . . . . . . . . . . . 23 1.5.3 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.5.3.1 crystal resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 1.5.3.2 ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 1.5.3.3 external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 1.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.5 lprst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.6 iro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.7 pa0?pa7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.8 pb0?pb7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 1.5.9 pc0?pc3 (pc4?pc7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
non-disclosure agreement required general description general release specif ication mc68hc05rc18 ? rev. 2.1 16 general description freescale semiconductor 1.2 introduction the mc68hc05rc18 is a gene ral-purpose, low-co st addition to the m68hc05 family of micr ocontroller units (mcus) and is suitable for remote control applications. it contai ns the hc05 central processing unit (cpu) core, including th e 14-stage core timer wi th real-time interrupt (rti) and computer operating pr operly (cop) watchdog systems. on- chip peripherals include a carrier modulator transmitter (cmt). the 16- kbyte memory map has 15,936 byte s of user rom and 352 bytes of ram. there are 20 input-output (i/o) lines (eight having keyscan logic and pullups) and a low-power re set pin. the mc68hc05rc18 is available in a 28-pin small outline integrated circuit (soic) package, a 29-pin dual-in-line package (dip), or a 44-pin pl astic leaded chip carrier (plcc). four additional i/o lines are available for bond out in higher pin count packages. 1.3 features features of the mc 68hc05rc18 include: low cost hc05 core 28-pin soic, 28-pin dip, or 44-pin plcc packages on-chip oscillator with crystal/ceramic resonator 4.2-mhz maximum oscillator fr equency at 2.2 to 5.0 volt supply fully static operation 15,936 bytes of user rom 64 bytes of burn-in rom 352 bytes of on-chip ram 14-stage core timer with r eal-time interrupt (rti) and computer operating proper ly (cop) watchdog circuits carrier modulator tr ansmitter (cmt) support ing baseband, pulse length modulator (plm), and frequency shift keying (fsk) protocols
general description mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor general description 17 non-disclosure agreement required low-power reset pin 20 bidirectional input/output (i/o ) lines (four additional i/o lines available for bond out in higher pin count packages) mask programmable inte rrupts and pullups on eight port pins (pb0?pb7) high-current infrared (ir) drive pin high-current port pins (pc0?pc3) power-saving stop and wait modes mask selectable options: ? cop watchdog timer ? stop instruction disable ? edge-sensitive or edge- and level-sensitiv e interrupt trigger ? port b interrupts for keyscan, with two optional pullup strengths note: a line over a signal name indicates an active-low signal. for example, reset is active low.
non-disclosure agreement required general description general release specif ication mc68hc05rc18 ? rev. 2.1 18 general description freescale semiconductor figure 1-1. mc68hc 05rc18 block diagram 2 accumulator index register stack pointer program counter condition code register oscillator internal reset cop cpu m68hc05 cpu alu cpu registers control port a data direction register port b data direction register pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 processor clock core timer sram ? 352 bytes rom ? 15,936 bytes system system rti system irq 0 0 0 0 0 0 0 1 1 1 1 1 c z n i h keyscan pullups burn-in rom ? 64 bytes lprst iro port c data direction register pc0 pc1 pc2 pc3 pc4* pc5* pc6* pc7* * marked pins are available only in higher pin count (>28) packages. irqen irqen osc2 v dd v ss osc1 carrier modulator transmitter
general description mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor general description 19 non-disclosure agreement required 1.4 mask options the mc68hc05rc18 has a total of 13 mask options, including: eight port b interrupt enables (one for each pin) port b pullup enable port b strong /weak pullup select irq sensitivity cop enable/disable stop enable/disable the following are nonprogramm able options in that they are selected at the time of code submi ssion when masks are made: pb7ie ? port b7 interrupt enable this option enables or disables the interrupt generation on port b bit 7. 1 = enables the interrupt 0 = disables the interrupt pb6ie ? port b6 interrupt enable this option enables or disables the interrupt generation on port b bit 6. 1 = enables the interrupt 0 = disables the interrupt pb5ie ? port b5 interrupt enable this option enables or disables the interrupt generation on port b bit 5. 1 = enables the interrupt 0 = disables the interrupt pb4ie ? port b4 interrupt enable this option enables or disables the interrupt generation on port b bit 4. 1 = enables the interrupt 0 = disables the interrupt pb3ie ? port b3 interrupt enable this option enables or disables the interrupt generation on port b bit 3. 1 = enables the interrupt 0 = disables the interrupt
non-disclosure agreement required general description general release specif ication mc68hc05rc18 ? rev. 2.1 20 general description freescale semiconductor pb2ie ? port b2 interrupt enable this option enables or disables the interrupt generation on port b bit 2. 1 = enables the interrupt 0 = disables the interrupt pb1ie ? port b1 interrupt enable this option enables or disables the interrupt generation on port b bit 1. 1 = enables the interrupt 0 = disables the interrupt pb0ie ? port b0 interrupt enable this option enables or disables the interrupt generation on port b bit 0. 1 = enables the interrupt 0 = disables the interrupt pullen ? pullup enable this option will disable all pullups or enable the pullups of any port b pin that has its interrupt enabled. 1 = enables pullups for enabled interrupts, others disabled. 0 = disables all pullups swpusel ? strong /weak pullup select this option selects between either t he strong pullup or the weak pullup for any of the po rt b pullups that are enabled. 1 = selects the weak pullups 0 = selects the strong pullups copen ? cop enable when the cop option is selected (copen = 1), th e cop watchdog timer is enabled. when the cop option is deselecte d (copen = 0), the cop watchdog timer is disabled. stopen ? stop in struction enable when the stop option is sele cted (stopen = 1), the stop instruction is enabled. when the stop option is deselec ted (stopen = 0), the stop instruction is disabled.
general description mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor general description 21 non-disclosure agreement required note: when the stop instruction is disabled , executing a stop instruction is equivalent to executing a wait instruct ion, except that the core timer is reset. irq ? irq sensitivity when the irq option is select ed (level = 1), edge- and level- sensitive irq is enabled. when the irq option is deselected (level = 0), edge-only sensitive irq is enabled. 1.5 signal description the mc68hc05rc18 is available in 1. 28-pin dual-in-line package (dip) see figure 1-2 2. 28-pin small outli ne integrated circuit (soic) package see figure 1-3 3. 44-pin plastic leaded chip carrier (plcc) package see figure 1-4 the signals are descr ibed in the foll owing subsections. figure 1-2. 28- pin dip pinout pb4 pb5 pb6 pb7 pa0 pa1 pa2 pa3 pa4 pa5 osc1 osc2 v dd v ss pc1 pc2 pc3 pb1 pb2 pc0 pb0 pb3 irq reset pa7 pa6 lprst iro 5 6 7 8 9 10 11 12 13 14 2 3 1 4 24 23 22 21 20 19 18 17 16 15 27 26 28 25
non-disclosure agreement required general description general release specif ication mc68hc05rc18 ? rev. 2.1 22 general description freescale semiconductor figure 1-3. 28-pin soic pinout figure 1-4. 44-pin plcc pinout pa2 pa3 pa4 pa5 pa1 pa0 pb7 pb6 pb5 pb3 pb2 pb1 pb0 pb4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 reset iro v ss lprst pc3 pc2 pc1 pc0 pa7 pa6 osc1 osc2 v dd irq pc6 nc pc5 nc pb7 pb6 pb5 pb4 nc pc7 pa0 pa1 nc nc reset iro v ss lprst nc pc4 pc3 pc2 nc osc1 osc2 v dd irq nc nc pb3 pb2 pb1 pb0 nc pa2 pa3 pa4 pa5 nc pa6 pa7 pc0 pc1 nc 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 39 38 37 36 35 34 33 32 31 30 29 6 5 4 3 2 1 44 43 42 41 40 note: nc = no connect all no connects should be tied to an appropriate logic level (either v dd or v ss ).
general description mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor general description 23 non-disclosure agreement required 1.5.1 v dd and v ss power is supplied to the microcontroller?s digital circuits using these two pins. v dd is the positive supply and v ss is ground. 1.5.2 irq (maskable interrupt request) this pin has a us er-specified mask option that provides one of two different choices of interrupt tri ggering sensitivity. the options are: 1. negative edge-sensit ive triggering only 2. both negative edge-sensitive and level-sensitive triggering the mcu completes the curr ent instruction before it responds to the interrupt reques t. when irq goes low for at least one t ilih , a logic 1 is latched internally to signify that an interrupt has bee n requested. when the mcu completes its current instruction, the interr upt latch is tested. if the interrupt latch contains a logic 1 and the inte rrupt mask bit (i bit) in the condition code register is clea r, the mcu then begins the interrupt sequence. if the option is selected to include level-sensit ive triggering, the irq input requires an external resistor to v dd for wired-or operation. the irq pin contains an internal schmitt trigger as part of its input to improve noise immunity. refer to section 4. interrupts for more detail. 1.5.3 osc1 and osc2 the osc1 and osc2 pins are the cont rol connections for the 2-pin on- chip oscillator. the oscillator can be driven by any of the following: crystal resonator ceramic resonator external clock signal
non-disclosure agreement required general description general release specif ication mc68hc05rc18 ? rev. 2.1 24 general description freescale semiconductor note: the frequency of the inter nal oscillator is f osc . the mcu divides the internal oscillator by two to prod uce the internal clock with a frequency of f op . 1.5.3.1 crystal resonator the circuit in figure 1-5 shows a crystal oscillat or circuit for an at-cut, parallel resonant crystal. follow t he crystal supplier?s recommendations, because the crystal parameters deter mine the exter nal component values required to provide reliabl e startup and maximu m stability. the load capacitance values used in th e oscillator circui t design should account for all stray layo ut capacitances. to mini mize output distortion, mount the crystal and ca pacitors as close as possible to the pins. figure 1-5. crystal connections note: use an at-cut crystal and not a strip or tuning fork crystal. the mcu might overdrive or have th e incorrect characterist ic impedance for a strip or tuning fork crystal. osc1 osc2 mcu 10 m ? * 30 pf* 30 pf* 4.2 mhz xtal * starting value only. follow crystal supplier?s recommenda- . tions regarding component values that will pr ovide reliable . startup and maximum stability.
general description mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor general description 25 non-disclosure agreement required 1.5.3.2 ceramic resonator to reduce cost, use a ceramic res onator instead of a crystal. use the circuit shown in figure 1-6 for a 2-pin ceramic re sonator or the circuit shown in figure 1-7 for a 3-pin ceramic resonator and follow the resonator manufacturer ?s recommendations. figure 1-6. 2-pin cera mic resonator connections figure 1-7. 3-pin cera mic resonator connections osc1 osc2 mcu r c c resonator ceramic osc1 osc2 mcu c c resonator ceramic
non-disclosure agreement required general description general release specif ication mc68hc05rc18 ? rev. 2.1 26 general description freescale semiconductor 1.5.3.3 external clock signal the external component values r equired for maximu m stability and reliable starting depend upon the resonator par ameters. the load capacitance values used in the oscill ator circuit desi gn should include all stray layout capacitances. to mini mize output distor tion, mount the resonator and capacitors as close as possible to the pins. (see figure 1-8 .) figure 1-8. external clock source connections 1.5.4 reset this active-low pin is used to reset the mcu to a known startup state by pulling reset low. the reset pin contains an internal schmitt trigger as part of its input to im prove noise immunity. see section 5. resets . 1.5.5 lprst the lprst pin is an active-low pin and is used to put the mcu into low- power reset mode. in lo w-power reset mode, the mcu is held in reset with all processor clocks and cr ystal oscillator halted. the lp rst pin contains an internal schmitt trigger as part of its input to improve noise immunity. see section 5. resets . 1.5.6 iro the iro pin is the high-cu rrent source and sink output of the carrier modulator transmitter subsystem whic h is suitable fo r driving ir led biasing logic. see section 9. carrier modul ator transmitter (cmt) . < osc1 osc2 mcu external clock unconnected
general description mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor general description 27 non-disclosure agreement required 1.5.7 pa0?pa7 these eight i/o lines comprise port a. the state of any pin is software programmable and all port a lines ar e configured as inputs during power-on or reset. fo r detailed information on i/o programming, see 6.6 input/output programming . 1.5.8 pb0?pb7 these eight i/o lines comprise port b. the state of any pin is software programmable and all port b lines ar e configured as inputs during power-on or reset. each port b i/o line has a mask optionable interrupt/pullup for keyscan. for detailed information on i/o programming, see 6.6 input/output programming . 1.5.9 pc0?pc3 (pc4?pc7) these eight i/o lines comprise port c. pc0?pc3 are high -current pins. pc4?pc7 are standard dr ive pins and are availa ble only in higher pin count (>28) packages. the state of any pin is software programmable and all port c lines are configured as input during power- on or reset. for detailed information on i/o programming, see 6.6 input/output programming . note: only four bits of po rt c are bonded out in 28-pin packages for the mc68hc05rc18, although port c is truly an 8-bit port. since pins pc4?pc7 are unbonded, soft ware should include t he code to set their respective data direction register lo cations to outputs to avoid floating inputs. note: any unused inputs and i/o po rts should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the mc68hc05rc18 do not require terminat ion, termination is recommended to reduce the possibility of static damage.
non-disclosure agreement required general description general release specif ication mc68hc05rc18 ? rev. 2.1 28 general description freescale semiconductor
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor memory 29 non-disclosure agreement required general release specification ? mc68hc05rc18 section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.3.1 rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.2 rom security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.3 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.2 introduction this section describes the organization of the on-chip memory. 2.3 memory map the mc68hc05rc18 has a 16-kbyte memory map consisting of user rom, ram, burn-in ro m, control registers, and input/output (i/o). figure 2-1 is a memory map of the mcu. figure 2-2 is a more detailed memory map of the i/o register section.
non-disclosure agreement required memory general release specif ication mc68hc05rc18 ? rev. 2.1 30 memory freescale semiconductor figure 2-1. mc68hc05rc18 memory map i/o 32 bytes ram 160 bytes stack 64 bytes ram 128 bytes user rom 15,920 bytes burn-in rom & vectors user vectors 16 bytes $0000 $001f $0020 $00bf $00c0 $00ff $0100 $017f $0180 $3faf $3fb0 $3fef $3ff0 $3fff 0000 0031 0032 0191 0192 0255 0383 0384 16,303 16,304 16,367 16,368 16,383 0256 port a data register port b data register port c data register port a data direction register port b data direction register port c data direction register core timer control & status reg. reserved $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0f 64 bytes reserved reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq/ptb keyscan pullups irq/ptb keyscan pullups ir timer vector (low byte) ir timer vector (high byte) core timer vector (low byte) $3ff0 $3ff5 $3ff6 $3ff7 $3ff8 $3ff9 $3ffa $3ffb $3ffc $3ffd $3ffe unused $3fff reserved reserved reserved $18 $1f reserved $1e $10 $11 $12 $13 $14 $15 $16 $17 cmt chr1 cmt clr1 cmt chr2 cmt clr2 cmt mcsr cmt mdr1 cmt mdr2 cmt mdr3 core timer vector (high byte) unused $0a core timer counter register . . . . . . . ... .. vector (high byte) vector (low byte) reserved . . . . . . .
memory mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor memory 31 non-disclosure agreement required addr register name bit 7654321bit 0 $00 port a data register pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 $01 port b data register pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 $02 port c data register pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 $03 reservedrrrrrrrr $04 port a data direction register ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 $05 port b data direction register ddr b7 ddrb6 ddrb5 ddrb4 d drb3 ddrb2 ddrb1 ddrb0 $06 port c data direction register ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 $07 reservedrrrrrrrr $08 timer control and status regist er ctof rtif tofe rtie tofc rtfc rt1 rt0 $09 timer counter register $0a reservedrrrrrrrr $0b reservedrrrrrrrr $0c reservedrrrrrrrr $0d reservedrrrrrrrr $0e reservedrrrrrrrr $0f reservedrrrrrrrr $10 carrier generator high data register 1 (chr1) iroln cmtpol ph5 ph4 ph3 ph2 ph1 ph0 $11 carrier generator low data register 1 (clr1) irolp 0 pl5 pl4 pl3 pl2 pl1 pl0 $12 carrier generator high data register 2 (chr2) 0 0 sh5 sh4 sh3 sh2 sh1 sh0 $13 carrier generator low data register 2 (clr2) 0 0 sl5 sl4 sl3 sl2 sl1 sl0 $14 modulator control and status register (mcsr) eoc 0 eimsk exmrk base mode eocie mcgen $15 modulator data register 1 (mdr1) mb11 mb10 mb9 mb8 sb11 sb10 sb9 sb8 $16 modulator data register 2 (mdr2) mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0 r= reserved figure 2-2. i/o registers
non-disclosure agreement required memory general release specif ication mc68hc05rc18 ? rev. 2.1 32 memory freescale semiconductor 2.3.1 rom the user rom consists of 15,920 byte s of rom located from $0180 to $3faf and 16 bytes of user vectors locate d from $3ff0 to $3fff. the burn-in rom is loca ted from $3fb0 to $3fef. ten of the user vectors, $3ff6 through $3f ff, are dedicated to reset and interrupt vectors. the six remaining locati ons ? $3ff0, $3ff1, $3ff2, $3ff3, $3ff4, and $3ff5 ? are general- purpose user rom locations. 2.3.2 rom security security has been incorporated into the mc68hc 05rc18 to help prevent external viewing of the ro m contents. by having unique data values at locations $2000?$2008, customers can help ensure that their software remains proprietary. 1 $17 modulator data register 3 (mdr3) sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 $18 reservedrrrrrrrr $19 reservedrrrrrrrr $1a reservedrrrrrrrr $1b reservedrrrrrrrr $1c reservedrrrrrrrr $1d reservedrrrrrrrr $1e reservedrrrrrrrr r= reserved addr register name bit 7654321bit 0 figure 2-2. i/o r egisters (continued) 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the rom difficult for unauthorized users.
memory mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor memory 33 non-disclosure agreement required 2.3.3 ram the user ram consists of 352 bytes of a shared stac k area. the ram starts at address $0020 and ends at address $0 17f. the stack begins at address $00ff. the sta ck pointer can access 64 bytes of ram in the range $00ff to $00c0. note: using the stack area for data stor age or temporary work locations requires care to prevent the area from being overwritt en due to stacking from an interrupt or subroutine call.
non-disclosure agreement required memory general release specif ication mc68hc05rc18 ? rev. 2.1 34 memory freescale semiconductor
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor central processing unit 35 non-disclosure agreement required general release specification ? mc68hc05rc18 section 3. central processing unit 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.3 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4 index register (x). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 3.5 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.7 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.2 introduction this section describes the regist ers of the mc68h c05rc18 central processor unit (cpu). the mcu contains five r egisters as shown in figure 3-1 . the interrupt stacki ng order is shown in figure 3-2 . figure 3-1. programming model a 70 x 70 hinzc ccr 11 sp 70 pc 13 0 accumulator index register program counter stack pointer condition code register 0 0 0 0 0 13 0
non-disclosure agreement required central processing unit general release specif ication mc68hc05rc18 ? rev. 2.1 36 central processing unit freescale semiconductor figure 3-2. stacking order 3.3 accumulator (a) the accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.4 index register (x) the index register is an 8-bit register used fo r the indexed addressing value to create an effective address. the index register may also be used as a temporary storage area. 3.5 condition code register (ccr) the ccr is a 5-bit register in which the h, n, z, and c bits are used to indicate the results of the instructio n just executed, and the i bit is used to enable or disable inte rrupts. these bits can be individually tested by index register pcl accumulator condition code register pch 111 70 stack i n t e r r u p t decreasing unstack r e t u r n increasing note: since the stack pointer decrements during pushes, the pcl is stacked first, followed by pch, etc. pulling from the stack is in the reverse order. memory addresses memory addresses 70 a 70 x
central processing unit mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor central processing unit 37 non-disclosure agreement required a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. interrupt (i) when this bit is set, the timer and external inte rrupt are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the i bit is cleared. negative (n) when set, this bit indicate s that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicate s that the result of the last arithmetic, logical, or data manipulat ion was zero. carry/borrow (c) when set, this bit indicates that a ca rry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit is also affected during bit test and branch instructions and during shifts and rotates. ccr hinzc
non-disclosure agreement required central processing unit general release specif ication mc68hc05rc18 ? rev. 2.1 38 central processing unit freescale semiconductor 3.6 stack pointer (sp) the stack pointer contains the address of the next free location on the stack. during an mcu reset or the re set stack pointer (r sp) instruction, the stack pointer is set to loca tion $00ff. the stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the eight most significant bits are permanently set to 00000011. these eight bits are appended to the six least significant register bits to produce an address wi thin the range of $00ff to $00c0. subroutines and interr upts may use up to 64 (decimal) locations. if 64 locati ons are exceeded, the st ack pointer wraps around and loses the previously stored inform ation. a subroutine call occupies two locations on the stack; an in terrupt uses five locations. 3.7 program counter (pc) the program counter is a 13-bit register that contains the address of the next byte to be fetched. note: the hc05 cpu core is capa ble of addressing 16-bit locations. for this implementation, however, the addressing register s are limited to a 16- kbyte memory map. 13 7 0 00000011 sp 13 0 pc
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor interrupts 39 non-disclosure agreement required general release specification ? mc68hc05rc18 section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 4.3 cpu interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.4 reset interrupt sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.5 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.6 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6.1 external interrupt (irq /port b keyscan) . . . . . . . . . . . . . . . 43 4.6.2 external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6.3 carrier modulator tr ansmitter interrupt (cmt ) . . . . . . . . . . 45 4.7 core timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 introduction the mcu can be interrupt ed four different ways, which are discussed in this section. they are: 1. nonmaskable software interrupt instruction (swi) 2. external asynchronous interrupt (irq /port b keyscan) 3. internal carrie r modulator tran smitter interrupt 4. internal core timer interrupt
non-disclosure agreement required interrupts general release specif ication mc68hc05rc18 ? rev. 2.1 40 interrupts freescale semiconductor 4.3 cpu interrupt processing interrupts cause the processor to save register co ntents on the stack and to set the interrupt mask (i bit) to prevent addi tional interrupts. unlike reset, hardware interrupts do not ca use the current inst ruction execution to be halted, but are considered pending until th e current instruction is complete. if interrupts are not ma sked (i bit in the ccr is clear) when the cpu receives an interrupt request, the pr ocessor will proceed with interrupt processing. otherwise, the next inst ruction is fetched and executed. if an interrupt occurs, the processor comple tes the current instruction, stacks the current cpu regist er state, sets the i bit to inhibit further interrupts, and finally checks the p ending hardware interr upts. if more than one interrupt is pending after the stacking operation, the in terrupt with the highest vector location shown in table 4-1 will be serviced first. the swi is executed the same as any other in struction, regardless of the i-bit state. when an interrupt is to be process ed, the cpu fetches the address of the appropriate interrupt so ftware service routine fr om the vector table at locations $3ff6?$3fff as defined in table 4-1 . the m68hc05 cpu does not support interruptible instructions. the maximum latency to the first instruct ion of the interrup t service routine must include the longest instruction execut ion time plus stacking overhead. latency = (longest instruction execution time + 10) x t cyc seconds an rti instruction is used to signif y when the interrupt software service routine is completed. the rti instruction causes t he register contents to be recovered from the stack and normal processi ng to resume at the next instruction that was to be exec uted when the interr upt took place. figure 4-1 shows the sequence of events that occurs during interrupt processing.
interrupts mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor interrupts 41 non-disclosure agreement required 4.4 reset interrupt sequence the reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in figure 4-1 . a low-level input on the reset pin or an internally genera ted rst signal, causes the program to vector to its starting address, which is specified by the contents of memory locations $3ffe and $3fff. the i bit in the condition code register is also set. th e mcu is configured to a known state during this type of reset. 4.5 software interrupt (swi) the swi is an executable instruction and a nonmaskable interrupt since it is executed regardless of the state of the i bit in the ccr. if the i bit is zero (interrupts enabled), the swi instruction exec utes after interrupts that were pending before the swi was fetched or before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the content s of memory lo cations $3ffc and $3ffd. table 4-1. vector address for interrupts and reset register flag name interrupt cpu interrupt vector address n/a n/a reset reset $3ffe?$3fff n/a n/a software interrupt swi $3ffc?$3ffd n/a n/a external interrupts* irq $3ffa?$3ffb mcsr eoc end of cycle interrupt cmt $3ff8?$3ff9 ctcsr ctof, rtif real time interrupt core timer overflow core timer $3ff6?$3ff7 *external interrupts include irq and port b keyscan sources.
non-disclosure agreement required interrupts general release specif ication mc68hc05rc18 ? rev. 2.1 42 interrupts freescale semiconductor figure 4-1 . interrupt processing flowchart n restore registers from stack: ccr, a, x, pc. load pc from appropriate vector. set i bit in cc register. stack pc, x, a, ccr. clear irq request latch fetch next instruction. execute instruction. n y y n i bit in ccr set? swi instruction ? n y rti instruction ? y from reset y internal cmt interrupt? n n y internal core timer interrupt? irq /port b keyscan external interrupts? eimsk clear? y n
interrupts mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor interrupts 43 non-disclosure agreement required 4.6 hardware interrupts all hardware interrupts e xcept reset are maskable by the i bit in the ccr. if the i bit is set, all hardware interrupts (internal and external) are disabled. clearing the i bit e nables the hardware interrupts. the three types of hardw are interrupts, which are explained in the following sections, are: 1. external interrupt 2. core timer interrupt 3. carrier modulator transmitter interrupt 4.6.1 external interrupt ( irq /port b keyscan) the irq pin provides an asynchronous in terrupt to the cpu. a block diagram of the irq f unction is shown in figure 4-2 . note: the bih and bil instructions will apply to the level on the irq pin itself and to the output of the logic or function with t he port b irq interrupts. the states of the indivi dual port b pins can be checked by reading the appropriate port b pins as inputs. figure 4-2. irq func tion block diagram irq latch r irq pin level (mask option) to irq processing in cpu port b to bih & bil instruction sensing irq clear v dd eimsk
non-disclosure agreement required interrupts general release specif ication mc68hc05rc18 ? rev. 2.1 44 interrupts freescale semiconductor the irq pin is one source of an exter nal interrupt. all port b pins (pb0?pb7) act as other external in terrupt sources if their interrupt feature is enabled as s pecified by the user. when edge sensitivity is selected for the irq interrupt, it is sensitive to two cases: 1. falling edge on the irq pin 2. falling edge on any port b pin with interrupt enabled when edge and level sensitivity is select ed for the irq in terrupt, it is sensitive to three cases: 1. low level on the irq pin 2. falling edge on the irq pin 3. falling edge or low le vel on any port b pin with interrupt enabled external interrupts can also be ma sked by setting the eimsk bit in the mscr register of the ir remote timer. see 9.5.4 modulat or period data registers (m dr1, mdr2, and mdr3) for details. when masked, any external interrupt received sets the inte rrupt latch and remains pending within the interrupt module until the eimsk bi t is cleared, at that point, the external interrupt will be fo rwarded to the cpu for processing. reset clears the interrupt latch, as will the cpu w hen it finishes processing the external interrupt. 4.6.2 external interrupt timing if the interrupt mask bit (i bit) of th e ccr is set, all maskable interrupts (internal and external) ar e disabled. clearin g the i bit enables interrupts. the interrupt request is latched immedi ately following the falling edge of the irq source. the interrupt request is then synchronized internally and serviced as specified by t he contents of $3ffa and $3ffb. either a level-sensit ive and edge-sensitive tri gger or an edge-sensitive- only trigger is availabl e via the mask programm able option for the irq pin.
interrupts mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor interrupts 45 non-disclosure agreement required 4.6.3 carrier modulator transmitter interrupt (cmt) a cmt interrupt is gener ated when the end of cycl e flag (eoc) and the end of cycle interrupt enable (eocie) bits are set in the modulator control and status register (mcsr) . this interrupt wi ll vector to the interrupt service routine located at the address specified by the contents of memory locations $3ff8 and $3 ff9. note that the cmt will not generate any new interr upts while the chip is in wait mode, regardless of the state of the stat us register (mcsr). 4.7 core timer interrupt this timer can create two types of inte rrupts. a timer overflow interrupt occurs whenever the 8-bit timer rolls over from $ff to $00 and the enable bit tofe is set. a real-tim e interrupt occurs whenever the programmed time elapses and the enable bit rtie is set. either of these interrupts vectors to the same interr upt service routine, located at the address specified by the contents of memory locations $3ff6 and $3ff7.
non-disclosure agreement required interrupts general release specif ication mc68hc05rc18 ? rev. 2.1 46 interrupts freescale semiconductor
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor resets 47 non-disclosure agreement required general release specification ? mc68hc05rc18 section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.3 external reset (reset ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.4 low-power exte rnal reset (lprst ) . . . . . . . . . . . . . . . . . . . . 50 5.5 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.5.1 power-on reset (por). . . . . . . . . . . . . . . . . . . . . . . . . . . .50 5.5.2 computer operating properly reset (copr) . . . . . . . . . . . 51 5.5.2.1 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5.2.2 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5.2.3 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.5.2.4 cop watchdog time r considerations . . . . . . . . . . . . . . . 52 5.5.2.5 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.5.3 illegal address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.2 introduction the mcu can be reset from five sour ces: two external inputs and three internal restart conditions. the reset and lprst pins are inputs as shown in figure 5-1 . all the internal peripheral modules will be reset by the internal reset si gnal (rst). refer to figure 5-2 for reset timing detail.
non-disclosure agreement required resets general release specif ication mc68hc05rc18 ? rev. 2.1 48 resets freescale semiconductor 5.3 external reset (reset ) the reset pin is one of the two external sources of a reset. this pin is connected to a schmitt trigger inpu t gate to provide an upper and lower threshold voltage separated by a mi nimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active-low input wi ll generate the rs t signal and reset the cpu and periphera ls. termination of the external reset input or the internal cop watchdog reset ar e the only reset sources that can place the mcu in a nonuser ope rating mode. por and lprst place the mcu in user mode while the illegal address re set has no effect on operating mode. figure 5-1. reset block diagram note: activation of the rst si gnal is generally referred to as reset of the device, unless otherwise specified. cpu latch reset cop watchdog (copr) rst osc data address ph2 to other peripherals s irq mode select to irq logic latch r power-on reset (por) v dd illegal address (illaddr) address clocked d d lprst to oscillator module
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor resets 49 resets non-disclosure agreement required pch pcl osc1 2 reset internal processor internal address bus 1 3ffe 3fff v dd 4064 t cyc t cyc t rl internal data bus 1 3ffe 3ffe 3ffe 3ffe new pc 3fff notes: 1. internal timing signal and bus inform ation is not available externally. 2. osc1 line is not meant to represent fr equency. it is only used to represent time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. 4. v dd must fall to a level lower than v por to be recognized as a power-on reset on the next rise of v dd . 3 new new op code pcl pch new pc new pc op code new pc clock 1 0 v > v por 4 figure 5-2. reset and por timing diagram
non-disclosure agreement required resets general release specif ication mc68hc05rc18 ? rev. 2.1 50 resets freescale semiconductor 5.4 low-power external reset (lprst ) this pin is connected to a schmitt tri gger input gate to provide an upper and lower threshold voltage separat ed by a minimum amount of hysteresis. the lprst pin is one of th e two external sources of a reset. this external reset occurs whenever the lprst pin is pulled below the lower threshold and remains in reset until the lprst pin rises above the upper threshold. this acti ve-low input will, in addition to generating the rst signal and resetting the cpu and peripherals , halt all internal processor clocks and the cr ystal oscillator. the m cu will remain in this low-power reset condition as l ong as a logic 0 remains on lp rst . when a logic 1 is applied to lp rst , processor clocks wil l be re-enabled with the mcu remaining in re set until the 4064 internal processor clock cycle (t cyc ) oscillator stabilization delay is completed. if any other reset function is active at the end of this 4064-cycl e delay, the rst signal remains in the re set condition unti l the other reset condition(s) end. 5.5 internal resets the three internally gener ated resets are the initial power-on reset function, the cop watchdog timer reset, and the ill egal address detector. termination of the external reset input or the inte rnal cop watchdog timer are the only reset sources that can place the mc u into a non-user operating mode. por and lprst place the mcu in us er mode while the illegal address reset has no effect on operating mode. 5.5.1 power-on reset (por) the internal por is generated on power- up to allow the clock oscillator to stabilize. the por is strictly for power turn -on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 4064 internal processor bus clock cycles (ph2) after the o scillator becomes active. the por generates the rst signal that resets the cpu. if any other reset function is acti ve at the end of this 4064-cycle delay, the rst signal remains in the re set condition until the ot her reset condition(s) ends.
resets mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor resets 51 non-disclosure agreement required caution: the v dd voltage should rise sufficiently fast to reach the minimum operating voltage for th e given oscillator frequency before the 4064- cycle internal processor clock timeout period expires. if v dd rises too slowly, then either the reset or lprst pin should be driven low (less than v il ) until v dd reaches the minimu m operating level for the oscillator frequency. 5.5.2 computer operating properly reset (copr) the mcu contains a watchdog timer that automatically ti mes out if not reset (cleared) within a specific time by a program reset sequence. if the cop watchdog timer is allowed to time out, an internal reset is generated to reset the mcu. the cop reset function is enabled or disabled by a mask option and is verified during production testing. 5.5.2.1 resetting the cop writing a zero to the copf bit prev ents a cop reset. this action resets the counter and begins the timeout pe riod again. the copf bit is bit 0 of address $3ff0. a read of address $3ff0 re turns user data programmed at that location. 5.5.2.2 cop during wait mode the cop continues to operat e normally during wait mode. the software should pull the device out of wait mode periodica lly and reset the cop by writing to the copf bi t to prevent a cop reset. 5.5.2.3 cop during stop mode when stop is executed, the cop c ounter will be cl eared and held in that state until the stop state is exited. this is true whether stop is enabled and the chip enters an actual stop state (when all clocks are stopped) or if stop is disabled and only the internal ph1 and ph2 are stopped (a wait-like state). if a rese t is used to exit stop mode, the cop counter is held in rese t until 4064 por cycles ar e completed, at which
non-disclosure agreement required resets general release specif ication mc68hc05rc18 ? rev. 2.1 52 resets freescale semiconductor time counting will begi n. if an external irq is used to exit stop mode, the cop counter does not wait for the completion of th e 4064 por cycles but does count these cycles. 5.5.2.4 cop watchdog timer considerations the cop watchdog timer is active in all modes of operation if enabled by a mask option. if the cop watchdog timer is selected by a mask option, any execution of the stop in struction (either intentionally or inadvertently due to the cpu being disturbed) caus es the oscillator to halt and prevents the co p watchdog timer from timing out. if the cop watchdog timer is selected by a mask option, the cop resets the mcu when it times out. therefore, it is recommended that the cop watchdog be disabled for a system that mu st have intentional uses of the wait mode for periods longer t han the cop timeout period. the recommended interactions and c onsiderations for the cop watchdog timer, stop instructi on, and wait instruction are summarized in table 5-1 . table 5-1. cop watchdog timer reco mmendations if the following conditions exist: then the cop watchdog timer should be: wait time wait time less than cop timeout enable or disable cop by mask option wait time more than cop timeout disable cop by mask option any length wait time disable cop by mask option
resets mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor resets 53 non-disclosure agreement required 5.5.2.5 cop register the cop register is shar ed with the lsb of the unimplemented user interrupt vector at lo cation $3ff0 as shown in figure 5-3 . reading this location returns whatever user data has been programmed at this location. writing a 0 to the copr bit in this location clears the cop watchdog timer. 5.5.3 illegal address an illegal address reset is gener ated when the cpu attempts to fetch an instruction from i/o addre ss space ($0000 to $001f). address: $3ff0 bit 7654321bit 0 read: xxxxxxxx write: copr reset:??????? 0 = unimplemented figure 5-3. cop watchdog timer location
non-disclosure agreement required resets general release specif ication mc68hc05rc18 ? rev. 2.1 54 resets freescale semiconductor
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor parallel input/output (i/o) 55 non-disclosure agreement required general release specification ? mc68hc05rc18 section 6. parallel input/output (i/o) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.6 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 6.2 introduction in user mode, 24 lines (four of wh ich are unavailable in the standard 28- pin package) are arranged as three 8-bit i/o ports. these ports are programmable as either inputs or output s under software control of the data direction registers. note: to avoid a glitch on the output pins, write data to the i/o port data register before writing a one to the corresponding data direction register. 6.3 port a port a is an 8-bit bidire ctional port which does not share any of its pins with other subsystems. the port a data register is at $0000 and the data direction register (ddr) is at $0004. reset does not affect the data register, but clears the dat a direction register, ther eby returning the ports to inputs. writin g a one to a ddr bit sets t he corresponding port bit to output mode.
non-disclosure agreement required parallel input/output (i/o) general release specif ication mc68hc05rc18 ? rev. 2.1 56 parallel input/output (i/o) freescale semiconductor 6.4 port b port b is an 8-bit bidire ctional port which does not share any of its pins with other subsystems. the address of the port b data register is $0001 and the data direction re gister (ddr) is at address $0005. reset does not affect the data regist er, but clears the data dire ction regist er, thereby returning the ports to inputs. wr iting a one to a ddr bit sets the corresponding port bit to output mode. each of the port b pins has a mask programmable inte rrupt generation option, any of which can be enabled. when an interrupt option is enabled, this pin may also have a pullup resistor enabled. there is a c hoice between two pullup strengths, either of which may be active for the enabled inte rrupts. the choice of whether to enable the pull ups and which strength to choose will be the same for all enabled in terrupts circuits. the edge or edge and level sensitivity of the irq pin will also pertain to the enabled port b pins. be careful when using port b pins t hat have the inte rrupt generation enabled. before switching from an output to an input, the data should be preconditioned to a logic 1 to prev ent an interrupt from being generated or the i bit of the c ondition code register shoul d be set to prevent any such generated interrupt from taking immediate effect. figure 6-1. port b pullup options pb7 v dd ddr bit normal port circuitry as shown in figure 2-4 irq to interrupt logic mask option (pb7ie) from all other port b pins irqen v dd strong weak mask option (strong /weak sel) mask option (pullup / enable )
parallel input/output (i/o) mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor parallel input/output (i/o) 57 non-disclosure agreement required 6.5 port c port c is an 8-bit bidirectional port (pc0?pc7) which does not share any of its pins with other subsystems. the port c da ta register is at $0002 and the data direction regi ster (ddr) is at $0006. reset does not affect the data register, but cl ears the data direction regi ster, thereby returning the ports to inputs. writing a 1 to a ddr bit sets the corresponding port bit to output mode. port c pins pc4?pc7 are available only in higher pin count (>28 pin) packages. note: only four bits of po rt c are bonded out in 28-pin packages for the mc68hc05rc18, although port c is truly an 8-bit port. since pins pc4?pc7 are unbonded, soft ware should include t he code to set their respective data direction register lo cations to outputs to avoid floating inputs. 6.6 input/output programming port pins can be programmed as inputs or output s under software control. the direction of the pins is determined by the state of the corresponding bit in the por t data direction register (ddr). each i/o port has an associated ddr. any i/o port pi n is configured as an output if its corresponding ddr bit is se t to a logic 1. a pin is configured as an input if its corresponding ddr bit is cleared to a logic 0. at power-on or reset, all ddrs are cleared, which configures all pins as inputs. the data directi on registers are capable of being written to or read by the processor. during the programmed out put state, a read of the data register actually reads t he value of the output data latch and not the i/o pin.
non-disclosure agreement required parallel input/output (i/o) general release specif ication mc68hc05rc18 ? rev. 2.1 58 parallel input/output (i/o) freescale semiconductor
parallel input/output (i/o) mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor parallel input/output (i/o) 59 non-disclosure agreement required figure 6-2. i/o circuitry table 6-1. i/o pin functions access ddr i/o pin functions write 0 the i/o pin is in input mode. data is written into the output data latch. write 1 data is written into the output data latch and output to the i/o pin. read 0 the state of the i/o pin is read. read 1 the i/o pin is in an output mode. the output data latch is read. data direction register bit i/o pin input reg bit input i/o output internal hc05 connections latched output data bit
non-disclosure agreement required parallel input/output (i/o) general release specif ication mc68hc05rc18 ? rev. 2.1 60 parallel input/output (i/o) freescale semiconductor
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor low-power modes 59 non-disclosure agreement required general release specification ? mc68hc05rc18 section 7. low-power modes 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.3 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.4 stop recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 7.5 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7.6 low-power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 7.2 introduction this section describes the low-pow er modes, which are stop mode and wait mode. 7.3 stop mode the stop instruction places the mcu in its lowest pow er-consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing, in cluding timer operation. when stop mode is entered, all core ti mer counter bits are cleared. the i bit in the ccr is cleared to enable interrupts, but all interrupts are held pending until the device is brought out of stop mode. all other registers and memory remain unaltered. all input/output lines remain unchanged. note: if an external interrupt is pending when stop mode is entered, then stop mode will be exit ed immediately. the eimsk bit is not clear ed automatically by the execution of a stop instruction. care should be taken to clear this bit before entering stop mode.
non-disclosure agreement required low-power modes general release specif ication mc68hc05rc18 ? rev. 2.1 60 low-power modes freescale semiconductor 7.4 stop recovery the processor can be brought out of stop mode only by an external interrupt, lprst , or reset . refer to figure 7-1 . figure 7-1. stop rec overy timing diagram 3ffe 3ffe 3ffe 3ffe 3fff internal address bus internal clock irq 3 irq 2 reset osc1 1 t ilch 4064 t cyc reset or interrupt vector fetch t lih t rl notes: 1. represents the internal gating of the osc1 pin 2. irq pin edge-sensitive mask option 3. irq pin level- and edge-sensitive mask option lprst t lprl
low-power modes mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor low-power modes 61 non-disclosure agreement required 7.5 wait mode the wait instruction places the mcu in a low power-consumption mode, but the wait mode consumes more power than the stop mode. all cpu action is suspended, but the co re timer, the oscillator, and any enabled module remain active. any interr upt or reset will cause the mcu to exit wait mode. the user must shut off subsystem s to reduce power consumption. wait current specif ications assume cpu operation only and do not include current consumpt ion by any other subsystems. during wait mode, the i bit in the ccr is cleared to enable inte rrupts. all other registers, memory, and input/output lin es remain in their previous states. the timer can be enabled to allo w a periodic exit from wait mode. 7.6 low-power reset low-power reset mode is entered when a logic 0 is detected on the lprst pin. when in this mode (as long as lprst is held low), the mcu is held in reset and all internal cl ocks and the crystal oscillator (if used) are halted. applying a logic 1 to lprst will cause the part to exit low- power reset mode and begin count ing out the 4064-cycle oscillator stabilization period. once this ti me has elapsed, the mcu will begin operation from the rese t vectors ($3ffe?$3fff).
non-disclosure agreement required low-power modes general release specif ication mc68hc05rc18 ? rev. 2.1 62 low-power modes freescale semiconductor figure 7-2. stop/wait flowchart turn on oscillator. wait for time delay to stabilize. 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine restart processor clock. 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine y y y y y n n n n n stop wait reset oscillator active. core timer clock active. processor clocks stopped. stop oscillator and all clocks. clear i bit. cmt timer internal interrupt? core timer internal interrupt? n y y cmt timer clock active. external (irq )? (ptb keyscan interrupt or lprst? reset or lprst? interrupt) external (irq )? (ptb keyscan interrupt interrupt)
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor core timer 63 non-disclosure agreement required general release specification ? mc68hc05rc18 section 8. core timer 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.3 core timer control and status register . . . . . . . . . . . . . . . . . . 65 8.4 core timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.5 computer operating prop erly (cop) reset . . . . . . . . . . . . . . . 67 8.6 timer during wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.2 introduction the core timer for this device is a 14- stage multifunctional ripple counter. features include timer overflow, power-on reset (p or), real-time interrupt (rti), and cop watchdog timer. as seen in figure 8-1 , the internal peri pheral clock is divided by four and then drives an 8-bit ripple counter. the value of this 8- bit ripple counter can be read by the cpu at any time by accessing the core timer counter register (ctcr) at address $09. a timer overflow function is implemented on the last stage of this counter, giving a possible interrupt rate of the internal peripheral cloc k (e)/1024. this point is then followed by three more stages, with the result ing clock (e/4096) driving the real- time interrupt circuit (rti). the rti circuit consists of three divider stages with a one-of -four selector. the ou tput of the rti ci rcuit is further divided by eight to drive the mask optional co p watchdog timer circuit. the rti rate selector bits and the rti and ctof enable bits and flags are located in the timer control and status register at location $08.
non-disclosure agreement required core timer general release specif ication mc68hc05rc18 ? rev. 2.1 64 core timer freescale semiconductor figure 8-1. core timer block diagram cop clear internal bus $09 core timer counter register (ctcr) 5-bit counter ctof rtif tofe rtie rt1 interrupt circuit $08 rti select circuit status register rt0 timer control & overflow circuit detect cop watchdog timer ( 8) to reset logic 8 8 rtfc tofc e 2 10 tcbp ctcsr ctcr internal peripheral clock (e) to interrupt logic rti out e 2 12 por e 2 2 4 e 2 15 e 2 14 e 2 13 e 2 12 2 3
core timer mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor core timer 65 non-disclosure agreement required 8.3 core timer cont rol and status register the ctcsr contains the timer interrup t flag, the timer interrupt enable bits, and the real-time inte rrupt rate select bits. figure 8-2 shows the value of each bit in the ct csr when coming out of reset. ctof ? core timer overflow ctof is a read-only status bit set when the 8-bit ripple counter rolls over from $ff to $00. cl earing the ctof is do ne by writing a one to tofc. writing to this bit has no effect. reset clears ctof. rtif ? real-time interrupt flag the real-time interrupt ci rcuit consists of a 3-stage divider and a one- of-four selector. the clock frequency t hat drives the rt i circuit is e/2 12 (or e 4096) with three add itional divider stage s giving a maximum interrupt period of 16 m illiseconds at a bus rate of 2.024 mhz. rtif is a clearable, read-only status bit and is set when the output of the chosen (one-of-four selection) stage goes active. clearing the rtif is done by writing a one to rtfc. writi ng has no effect on this bit. reset clears rtif. tofe ? timer overflow enable when this bit is set, a cpu inte rrupt request is generated when the ctof bit is set. re set clears this bit. rtie ? real-time interrupt enable when this bit is set, a cpu inte rrupt request is generated when the rtif bit is set. reset clears this bit. address: $0008 bit 7654321bit 0 read: ctof rtif tofe rtie 00 rt1 rt0 write: tofc rtfc reset:00000011 = unimplemented figure 8-2. core timer contro l and status register (ctcsr)
non-disclosure agreement required core timer general release specif ication mc68hc05rc18 ? rev. 2.1 66 core timer freescale semiconductor tofc ? timer overflow flag clear when a one is written to this bit, ct of is cleared. writing a zero has no effect on the ctof bit. this bit always reads as zero. rtfc ? real-time interrupt flag clear when a one is written to th is bit, rtif is cleared. writing a zero has no effect on the rtif bit. thi s bit always reads as zero. rt1?rt0 ? real-time interrupt rate select these two bits select one of four t aps from the real -time interrupt circuit. refer to table 8-1 . reset sets these two bits which selects the lowest periodic rate and gives the maximum time in which to alter these bits if necessary. care sh ould be taken when altering rt0 and rt1 if the timeout period is imminent or uncertain . if the selected tap is modified during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. to avoid problems, the cop should be cleared before changing rti taps. table 8-1. rti and cop rates at 4.096-mhz oscillator rti rate 2.048-mhz bus rt1?rt0 minimum cop rates 2.048-mhz bus maximum cop rates 2.048-mhz bus 2 ms 2 12 e00 (2 15 ?2 12 )/e 14 ms (2 15 )/e 16 ms 4 ms 2 13 e01 (2 16 ?2 13 )/e 28 ms (2 16 )/e 32 ms 8 ms 2 14 e10 (2 17 ?2 14 )/e 56 ms (2 17 )/e 64 ms 16 ms 2 15 e11 (2 18 ?2 15 )/e 112 ms (2 18 )/e 128 ms
core timer mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor core timer 67 non-disclosure agreement required 8.4 core timer counter register the timer counter register is a read-only register that contains the current value of the 8- bit ripple counter at th e beginning of the timer chain. this counter is clocked by the cpu clock (e/4 ) and can be used for various functions, including a soft ware input captur e. extended time periods can be attained using the to f function to incr ement a temporary ram storage location, thereby simu lating a 16-bit (or more) counter. the power-on cycle and the low-power reset both serve to clear the entire counter chain and begin clocki ng the counter. after 4064 cycles, the power-on/low-power reset circuit is released, which again clears the counter chain and allows the device to co me out of reset. at this point, if reset is not asserted, the timer st arts counting up from zero and normal device operation begins. wh en a reset other than por and low- power reset is asserted any time dur ing operation, the counter chain is cleared but the 4064-cycle stabiliza tion period is not invoked. 8.5 computer operati ng properly (cop) reset the cop watchdog timer function is implemented on this device by using the output of the rti circuit and further di viding it by eight. the minimum cop reset rates are listed in figure 8-1 . if the cop circuit times out, an internal reset is generat ed and the normal reset vector is fetched. preventing a cop timeout, or clearing the cop is accomplished by writing a zero to bit 0 of addr ess $3ff0. when the cop is cleared, only the final divide-by-eight stage (output of the rti) is cleared. address $0009 bit 7654321bit 0 read: d7 d6 d5 d4 d3 d2 d1 d0 write: reset:00000000 = unimplemented figure 8-3. timer count er register (ctcr)
non-disclosure agreement required core timer general release specif ication mc68hc05rc18 ? rev. 2.1 68 core timer freescale semiconductor if the cop watchdog timer is allowed to time out, an internal reset is generated to rese t the mcu. the cop remains enabled after executi on of the wait instruction and all associated operations apply. if the stop in struction is disabled, execution of stop instruction causes the cpu to enter wait mode just as if a wait mode instruction ha d been executed (except that when stop mode is exited, the cop timer is cl eared). thus, it is recommended that stop mode be disabled in devices that have the cop enabled , as this will prevent the cop from being dis abled by the stop instruction. this cop?s objective is to make it impossible for this device to become stuck or locked up and to be sure the cop is able to rescue t he part from any situation where it might entr ap itself in abnormal or unintended behavior. this functi on is a mask option. 8.6 timer during wait mode the cpu clock halts during wait mode, but the time r remains active. if interrupts are enabled, a timer interr upt will cause the pr ocessor to exit wait mode. the cop is always enabled while in user mode.
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor carrier modulator transmitter (cmt) 69 non-disclosure agreement required general release specification ? mc68hc05rc18 section 9. carrier modulator transmitter (cmt) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 9.3 overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 9.4 carrier generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.4.1 time counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.4.2 carrier generator data registers (chr1, clr1, chr2, and clr2) . . . . . . . . . . . . . . . . . 74 9.5 modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.5.1 time mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 9.5.2 fsk mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.5.3 extended space operation . . . . . . . . . . . . . . . . . . . . . . . . . 80 9.5.3.1 end of cycle (eoc) interrupt . . . . . . . . . . . . . . . . . . . . . 81 9.5.3.2 modulator control and status regist er . . . . . . . . . . . . . . 81 9.5.4 modulator peri od data registers (mdr1, mdr2, and mdr3) . . . . . . . . . . . . . . . . . . . . . . 84 9.6 wait mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.7 stop mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 9.2 introduction the carrier modulator transmitter (c mt) module provides a means to generate the protocol timi ng and carrier signals for a wide variety of encoding schemes. the cmt incorporat es hardware to off-load the critical and/or lengthy timing re quirements associated with code generation from the cpu, releasing much of its bandwidth to handle other tasks such as code data gener ation, data decompression, or keyboard scanning. the cmt does not incl ude dedicated hardware configurations for specific protocol s but is intended to be sufficiently programmable in its functi on to handle the timing requirements of most
non-disclosure agreement required carrier modulator transmitter (cmt) general release specif ication mc68hc05rc18 ? rev. 2.1 70 carrier modulator transmitter (cmt) freescale semiconductor protocols with minimal cpu interv ention. when t he modulator is disabled, certain cmt r egisters can be used to change the state of the infrared out pin (iro) directly. this f eature allows for the generation of future protocols not r eadily producible by the current architecture. 9.3 overview the module consists of carrier gener ator, modulator, and transmitter output blocks. the block diagram is shown in figure 9-1 . the carrier generator has a resolution of 500 ns with a 2-mhz oscillator. the user independently may define the high and low ti mes of the carrier signal to determine both period and dut y cycle. the carrier generator can generate signals with periods between 1 s (1 mhz) and 64 s (15.6 khz) in steps of 500 ns. the po ssible duty cycle options will depend upon the number of counts r equired to complete t he carrier period. for example, a 400-khz sign al has a period of 2.5 s and will therefore require 5 x 500 ns count s to generate. these counts may be split between high and low times so the dut y cycles available will be 20% (one high, four low), 40% (two high, thr ee low), 60% (three high, two low) and 80% (four high, one low). for lowe r frequency signals with larger periods, higher resolution (as a perce ntage of the total period) duty cycles are possible. the ca rrier generator may sele ct between two sets of high and low times. when operating in norm al mode (subsequently referred to as time mode), just one set will be used. when operating in fsk (frequency shift key) mode, the generator wi ll toggle between the two sets when instructed to do so by the modulat or, allowing the user to dynamically switch between two carrier frequencies without cpu intervention. when the b ase bit in the modulator control and status register (mcsr) is set, the carrier output to the modulator is held high continuously to allow for the gener ation of baseband protocols. see 9.4 carrier generator . the modulator provides a simple method to cont rol protocol timing. the modulator has a resolution of 4 s with a 2-mhz oscilla tor. it can count system clocks to provide re al-time control or it can count carrier clocks for self-clocked protocol s. the modulator can eit her gate the carrier onto the modulator outpu t (time), control the logi c level of the modulator
carrier modulator transmitter (cmt) mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor carrier modulator transmitter (cmt) 71 non-disclosure agreement required output (baseband), or directly route the carrier to t he modulator output while providing a signal to switch the carrier generat or between high/low time register buffers (fsk). see 9.5 modulator . the transmitter output block controls the state of the infrared out pin (iro). the modulator output is gated on to the iro pin when the modulator/carrier generator is enabled. ot herwise, the iro pin is controlled by the state of the iro latch, which is directly accessible to the cpu by means of bit 7 of the carrier generator data registers chr1 and clr1. the iro latch can be written to on either e dge of the internal bus clock (f osc /2), allowing for ir waveforms which have a resolution of twice the bus clock frequency (f osc ). see 9.4.2 carrier generator data registers (chr1, clr1, chr2, and clr2) . figure 9-1. carrier modulator tr ansmitter module block diagram f osc carrier generator modulator carrier out modulator out modulator/ transmitter output base mode primary/secondary select cpu interface iro pin eoc flag f osc 2 db ab eoc interrupt eoc enable . interrupt carrier enable
non-disclosure agreement required carrier modulator transmitter (cmt) general release specif ication mc68hc05rc18 ? rev. 2.1 72 carrier modulator transmitter (cmt) freescale semiconductor 9.4 carrier generator the carrier signal is ge nerated by counting a predetermined number of input clocks (500 ns for a 2-mhz oscill ator) for both the carrier high time and the carrier low time. the period is determined by the total number of clocks counted. the duty c ycle is determined by t he ratio of high time clocks to total clocks counted. the hi gh and low time values are user programmable and are held in two registers. an al ternate set of high/low count values is held in another set of registers to allow the generation of dual frequency fsk (frequency shift keying) protocols without cpu intervention. the mcgen bit in t he mcsr must be set and the base bit in the mcsr must be cleared to enable carrier generator clocks. the block diagram is shown in figure 9-2 . figure 9-2. carrier generator block diagram clk 6-bit up counter =? =? clr clock and output control primary high count register secondary high count register count register select control mode primary/ select carrier out secondary base f osc modulator/ carrier generator enable primary low count register secondary low count register
carrier modulator transmitter (cmt) mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor carrier modulator transmitter (cmt) 73 non-disclosure agreement required 9.4.1 time counter the high/low time counter is a 6-bit up counter. af ter each increment, the contents of the counter are compared with the appr opriate high or low count value register . when this value is reached, the counter is reset and the compare is redirect ed to the other count va lue register. assuming that the high time count compare register is currently acti ve, a valid compare will cause the carrier output to be dr iven low. the counter will continue to increment and when re aching the value stored in the selected low count value register, it will be cleared and will cause the carrier output to be driven high. the cycle r epeats, automatically generating a periodic signal which is directed to t he modulator. the lowest frequency (maxim um period) and highes t frequency (minimum period) which can be gener ated are defined as: f max = f osc (2 x 1) hz f min = f osc (2 x (2 6 ? 1)) hz in the general case, the carrie r generator output frequency is: f out = f osc (highcount + lowcount) hz where: 0 < highcount < 64 and 0 < lowcount < 64 note: these equations assume the div2 bit (b it 6) of the mcsr is clear. when the div2 bit is set, the carrier gener ator frequency will be half of what is shown in these equations. the duty cycle of the carrier signal is controlled by varying the ratio of high time to low + high time. as the input clock period is fixed, the duty cycle resolution will be pr oportional to the number of c ounts required to generate the desired carrier period. duty cycle highcount highcount lowcount + ---------------------------------------------------------------- =
non-disclosure agreement required carrier modulator transmitter (cmt) general release specif ication mc68hc05rc18 ? rev. 2.1 74 carrier modulator transmitter (cmt) freescale semiconductor 9.4.2 carrier generator data registers (chr1, clr1, chr2, and clr2) the carrier generator contains one 8-bit data register: primary high time (chr1); one 7-bit da ta register: primary low ti me (clr1); and two 6-bit data registers: secondary high time (chr2) and secondary low time (clr2). bit 7 of chr1 and chr2 is used to read and write the iro latch . chr1 address $0010 bit 7654321bit 0 read: iroln cmtpol ph5 ph4 ph3 ph2 ph1 ph0 write: reset:0 0uuuuuu u = unaffected clr1 address $0011 bit 7654321bit 0 read: irolp0 pl5pl4pl3pl2pl1pl0 write: reset:0 0uuuuuu u = unaffected chr2 address $0012 bit 7654321bit 0 read: 0 0 sh5 sh4 sh3 sh2 sh1 sh0 write: reset:0 0uuuuuu u = unaffected clr2 address $0013 bit 7654321bit 0 read: 0 0 sl5sl4sl3sl2sl1sl0 write: reset:0 0uuuuuu u = unaffected figure 9-3. carrier data register (chr1, clr1, chr2, and clr2)
carrier modulator transmitter (cmt) mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor carrier modulator transmitter (cmt) 75 non-disclosure agreement required ph0?ph5 and pl0?pl5 ? primary carrier high and low time data values when selected, these bits contain the number of input clocks required to generate the carrier high and low time periods . when operating in time mode (see 9.5.1 time mode ), this register pair is always selected. when operati ng in fsk mode (see 9.5.2 fsk mode ), this register pair and the sec ondary register pair ar e alternately selected under control of the m odulator. the primary ca rrier high and low time values are undefined out of reset. these bits must be written to nonzero values before the carrie r generator is enabled to avoid spurious results. note: writing to chr1 to update ph0?ph5 or to clr1 to update pl0?pl5 will also update the iro latch. when mcg en (bit 0 in the mcsr) is clear, the iro latch value appear s on the iro output pin. care should be taken that bit 7 of the data to be written to chr1 or chl1 should contain the desired state of the iro latch. additionally, writing to chr1 to update ph0?ph5 will also update the cmt polarity bit. care should be taken th at bit 6 of the data to be written to chr1 should cont ain the desired state of the polarity bit. sh0?sh5 and sl0?sl5 ? secondary carrier high and low time data values when selected, these bits contain the number of input clocks required to generate the carrier high and low time periods . when operating in time mode (see 9.5.1 time mode ), this register pair is never selected. when operating in fsk mode (see 9.5.2 fsk mode ), this register pair and the primary register pair are alte rnately selected under control of the modulator. the secon dary carrier high and low time values are undefined out of reset. these bits mu st be written to nonzero values before the carrier generator is enabled when operating in fsk mode. cmtpol ? cmt output polarity this bit controls the polarity of the cmt output (iro). when this bit is a zero, then the cmt output is active high. when this bit is set to one the cmt output is active low, in other words invert ed. the reset state of this bit is zero.
non-disclosure agreement required carrier modulator transmitter (cmt) general release specif ication mc68hc05rc18 ? rev. 2.1 76 carrier modulator transmitter (cmt) freescale semiconductor iroln and irolp ? iro latch control reading iroln or irolp reads the state of t he iro latch. writing iroln updates the iro latch with the data being written on the negative edge of the inter nal processor clock (f osc /2). writing irolp updates the iro latch on the positive edge of the inte rnal processor clock; for example, one f osc period later. the iro la tch is clear out of reset. note: writing to chr1 to update iroln or to clr1 to update irolp will also update the primary carrier high and low data values. care should be taken that bits 5?0 of the data to be written to chr1 or chl1 should contain the desired val ues for the primary ca rrier high or low data. in addition, writing to chr1 to update irol n will update the cmt polarity bit. care should be taken that bit 6 of t he data to be written to chr1 should contain the desired values for the polarity bit. 9.5 modulator the modulator consists of a 12-bit down c ounter with underflow detection which is loaded from the modulation ma rk period from the mark buffer register, mbuff. when this c ounter underflows, the modulator gate is clos ed and a 12-bit comparator is enabled which continually compares the logical comple ment of the contents of the (still) decrementing counter with the content s of the modulation space period register, sreg. when a match is obtained, the m odulator control gate is opened again. shoul d sreg = 0, the match will be im mediate and no space period will be generated (for inst ance, for fsk protocols which require successive bursts of diff erent frequencies). when the match occurs, the counter is reloaded with the contents of mbuff, sreg is reloaded with the contents of its buffer, sbuff, and the cycle repeats. the mcgen bit in the mcsr must be set to enabl e the modulator timer. the 12-bit mbuff and s buff registers are a ccessed through three 8- bit modulator period register s, mdr1, mdr2, and mdr3. the modulator can operate in two modes , time and fsk. in time mode, the modulator counts cl ocks derived from the system oscillator and
carrier modulator transmitter (cmt) mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor carrier modulator transmitter (cmt) 77 non-disclosure agreement required modulates a single-carrie r frequency or no carri er (baseband). in fsk mode, the modulator counts carrier periods and instru cts the carrier generator to alternat e between two carrier frequencies whenever a modulation period (mark + space counts) expires. figure 9-4. modulat or block diagram 9.5.1 time mode when the modulator oper ates in time mode, the modulation mark and space periods consist of zero or an integer number of f osc 8 clocks (= 250 khz @ 2 mhz osc). this provides a modulator resolution of 4 s and a maximum mark and space peri ods of about 16 ms (each). however, to prevent carrier glitches which could affect carrier spectral purity, the modulator co ntrol gate and carrier cl ock are synchronized. the carrier signal is activated wh en the modulator gate opens. the modulator gate can only close when t he carrier signal is low (the output =? 0 counter f osc eoc flag mbuff sbuff sreg * 13-bit down counter * * denotes hidden register 12 bits 12 bits ms bit 12 12 control/status register modulator eoc interrupt enable base mode 3 8 clock control carrier out load mbuff/sbuff system control eoc flag set modulator gate out primary/secondary select . . modulator modulator/ carrier generator. enable extended space div2
non-disclosure agreement required carrier modulator transmitter (cmt) general release specif ication mc68hc05rc18 ? rev. 2.1 78 carrier modulator transmitter (cmt) freescale semiconductor logic level during space periods is low). if the carrier generator is in baseband mode (base bi t in mcsr is high), the modulator output will be at a logic 1 for the duration of t he mark period and at a logic 0 for the duration of a s pace period. see figure 9-5 . the mark and space time equations are: setting the div2 bit in the mcsr will double mark and space times. figure 9-5. cmt operat ion in time mode t mark mbuff 1 + () 8 f osc ---------------- ------------------ ----------- -s sec = t space sbuff 8 f osc --------------- --------------- s sec = modulator gate f osc 8 time mode output baseband output mark space mark mark space carrier frequency
carrier modulator transmitter (cmt) mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor carrier modulator transmitter (cmt) 79 non-disclosure agreement required 9.5.2 fsk mode when the modulator operates in fsk mode, the m odulation mark and space periods consist of an integer number of carr ier clocks (space period can be zero). when the mark period expires, the space period is transparently started (as in time mode); however, in fsk mode the carrier switches between data register s in preparation for the next mark period. the carrier g enerator toggles between primary and secondary data register values w henever the modul ator mark period expires. the space period provides an interpulse gap (no carrier), bu t if sbuff = 0, then the modulator and carrier generator will switch between carrier frequencies without a gap or any carrier glit ches (zero space). using timing data for carr ier burst and interpulse gap length calculated by the cpu, fsk mode can automatically gener ate a phase-coherent, dual-frequency fsk signal with prog rammable burst and interburst gaps. the mark and space time equations for fsk mode are: where f cg is the frequency output from the carrier generator, setting the div2 bit in the mcsr will double mark and space times. t mark mbuff 1 + f c g ------------------- ------------ s sec = t space sbuff f cg -------------------- -s sec =
non-disclosure agreement required carrier modulator transmitter (cmt) general release specif ication mc68hc05rc18 ? rev. 2.1 80 carrier modulator transmitter (cmt) freescale semiconductor 9.5.3 extended space operation in either time or fs k mode, the space period can be made longer than the maximum possible value of sbuf f. setting the ex spc bit in the mcsr will force the modul ator to treat the next modulation period (beginning with the next load of mbuff/sbuff) as a space period equal in length to th e mark and space count s combined. subsequent modulation periods will consist entirely of thes e extended space periods with no mark periods. cl earing exspc will return the modulator to standard operation at t he beginning of the next modulation per iod. to calculate the length of an extended space in time mode, use the equation: where the subscripts 1, 2, ... n re fer to the modulation periods that elapsed while the ex spc bit was set. similarly, to calculate the length of an extended space in fsk mode, use the equation: where f cg is the frequency output from the carrier generator. for an example of extended space operation, see figure 9-6 . note: the exspc feature can be used to emulate a zero mark event. figure 9-6. extended space operation ((sbuff 1 )+(mbuff 2 +1+sbuff 2 ) +... (mbuff n +1+sbuff n )) x 8 f osc t exspace = secs ((sbuff 1 )+(mbuff 2 +1+sbuff 2 )+... (mbuff n +1+sbuff n )) f cg t exspace = secs set exspc clear exspc
carrier modulator transmitter (cmt) mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor carrier modulator transmitter (cmt) 81 non-disclosure agreement required 9.5.3.1 end of cycle (eoc) interrupt at the end of each cycle (when the co unter is reloaded from mbuff), the end of cycle (eoc) flag is set. if the interrupt enable bit was previously set, an interrupt will also be issued to the cpu. the eoc interrupt provides a means for the us er to reload new mark/space values into the mbuff and sbuff registers. as the eoc interrupt is coincident with reloading the counter, mbuff does not require ad ditional buffering and may be updated with a new value for the next period from within the eoc interrupt service r outine (isr). to allow both mark and space period values to be updated from within the same isr, sreg is buffered by sbuff. the contents written to sbuff are tr ansferred to the active register sreg at the end of every cycle irrespective of the state of the eoc flag. the eoc flag is cleared by a read of the modulator control and status register (mcsr) followed by an access of mdr2 or mdr3. the eoc flag must be cleared within the isr to prevent an other interrupt being generated af ter exiting the isr. if the eoc interr upt is not being used (ie = 0), the eoc flag need not be cleared. 9.5.3.2 modulator contr ol and status register the modulator control and status register (mcsr) contains the modulator and carrier generator enable (mcgen), interrupt enable (ie), mode select (mode), baseband enable (base), extended space (exspc), and external interrupt mask (eimsk) control bits, divide-by- two prescaler (div2) bit, and the end of cycle (eoc) status bit. address: $0014 bit 7654321bit 0 read: eoc div eimsk exspc base mode ie mcgen write: reset:00000000 = unimplemented figure 9-7. modulator contro l and status regi ster (mcsr)
non-disclosure agreement required carrier modulator transmitter (cmt) general release specif ication mc68hc05rc18 ? rev. 2.1 82 carrier modulator transmitter (cmt) freescale semiconductor eoc ? end of cycle status flag 1 = end of modulator cycle (c ounter = sbuff) has occurred 0 = current modulatio n cycle in progress eoc is set when a match occurs bet ween the contents of the space period register, sreg, and the down counter. thi s is recognized as the end of the modul ation cycle. at this time, the counter is initialized with the (possibly new) contents of the mark period buffer, mbuff, and the space period regist er, sreg, is loaded with the (possibly new) contents of the space per iod buffer, sbuff. this flag is cleared by a read of the mcsr followed by an access of mdr2 or mdr3. the eoc flag is cleared by reset. div2 ? divide-by-two prescaler 1 = divide-by-two prescaler enabled 0 = divide-by-two prescaler disabled the divide-by-two prescaler causes the cmt to be clocked at the bus rate when enabled and 2 x the bu s rate when disabled (f osc ). since this bit is not double buffered, it s hould not be set during a transmission. eimsk ? external interrupt mask 1 = irq and keyscan interrupts masked 0 = irq and keyscan interrupts enabled the external interrupt mask bit is used to mask irq and keyscan interrupts. this bit is cleared by reset. exspc ? extended space enable 1 = extended space enabled 0 = extended space disabled for a description of the extended space enable bit, see 9.5.3 extended space operation . this bit is cleared by reset.
carrier modulator transmitter (cmt) mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor carrier modulator transmitter (cmt) 83 non-disclosure agreement required base ? baseband enable 1 = baseband enabled 0 = baseband disabled when set, the base bit disables t he carrier generator and forces the carrier output high for generation of baseband pr otocols. when base is clear, the carrier gener ator is enabled and the carrier output toggles at the frequency determined by val ues stored in the carrier data registers. see 9.5.1 time mode . this bit is cleared by reset. this bit is not double buffered and shoul d not be writt en to during a transmission. mode ? mode select 1 = cmt operates in fsk mode. 0 = cmt operates in time mode. for a description of cmt oper ation in time mode, see 9.5.1 time mode . for a description of cmt operation in fs k mode, see 9.5.2 fsk mode . this bit is cleared by reset. this bit is not double buffered and should not be written to during a transmission. ie ? interrupt enable 1 = cpu interrupt enabled 0 = cpu interrupt disabled a cpu interrupt will be requested when eoc is set if ie was previously set. if ie is clear, eoc wi ll not request a cpu interrupt. mcgen ? modulator and carrier g enerator enable 1 = modulator and carr ier generator enabled 0 = modulator and carr ier generator disabled setting mcgen will initialize the carrier generator and modulator and will enable all clocks. once enabl ed, the carrier generator and modulator will functi on continuously. when mc gen is cleared, the current modulator cycle will be allowed to expi re before all carrier and modulator clocks are disabled (to save pow er) and the modulator output is forced low. to prevent spurious oper ation, the user should initialize all data and control regi sters before enabli ng the system. this bit is cleared by reset.
non-disclosure agreement required carrier modulator transmitter (cmt) general release specif ication mc68hc05rc18 ? rev. 2.1 84 carrier modulator transmitter (cmt) freescale semiconductor 9.5.4 modulator period data registers (mdr1, mdr2, and mdr3) the 12-bit mbuff and s buff registers are a ccessed through three 8- bit registers, mdr1, mdr2, and m dr3. mdr2 and mdr3 contain the least significant eight bits of mbuff and sbuff resp ectively. mdr1 contains the two most significant nibbles of mbuff and sbuff. in many applications, per iods greater than those obt ained by eight bits will not be required. splitting the registers up in this manner allows the user to clear mdr1 and generat e 8-bit periods with ju st two data writes. mdr1 address $0015 bit 7654321bit 0 read: mb11 mb10 mb9 mb8 sb11 sb10 sb9 sb8 write: reset: unaffected by reset mdr2 address $0016 bit 7654321bit 0 read: mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0 write: reset: unaffected by reset mdr3 address $0017 bit 7654321bit 0 read: sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 write: reset: unaffected by reset figure 9-8. modulator data regi sters (mdr1, m dr2, and mdr3)
carrier modulator transmitter (cmt) mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor carrier modulator transmitter (cmt) 85 non-disclosure agreement required 9.6 wait mode operation during wait mode t he cmt, if enabled, will continue to operate normally. however, there will be no new codes or changes of pattern mode while in wait mode, as the cpu is not oper ating. in addition, the cmt will not generate any new interrupts while the chip is in wait mode, although if it has one pending when wait mode is entered then that pending interrupt will serve to pull the ch ip out of wait mode. note: although the cmt will not generate any new interrupts while wait mode is active, a previously generated cmt interr upt that is still pending will bring the mcu out of wait mode. 9.7 stop mode operation during stop mode, the cmt halts all operation. no registers are affected.
non-disclosure agreement required carrier modulator transmitter (cmt) general release specif ication mc68hc05rc18 ? rev. 2.1 86 carrier modulator transmitter (cmt) freescale semiconductor
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor instruction set 87 non-disclosure agreement required general release specification ? mc68hc05rc18 section 10. instruction set 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 10.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 10.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 10.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 10.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . 92 10.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . 93 10.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.4.4 bit manipulation instru ctions . . . . . . . . . . . . . . . . . . . . . . . . 96 10.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 10.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
non-disclosure agreement required instruction set general release specif ication mc68hc05rc18 ? rev. 2.1 88 instruction set freescale semiconductor 10.2 introduction the mcu instruction set has 62 inst ructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multip ly (mul) instruction. the mul instruction allows un signed multiplication of the contents of the accumulator (a) and the index regi ster (x). the high-order product is stored in the index regist er, and the low-order pr oduct is stored in the accumulator. 10.3 addressing modes the cpu uses eight addre ssing modes for flexibi lity in accessing data. the addressing modes provide eight di fferent ways for the cpu to find the data required to execute an inst ruction. the eight addressing modes are: inherent immediate direct extended indexed, no offset indexed, 8-bit offset indexed, 16-bit offset relative
instruction set mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor instruction set 89 non-disclosure agreement required 10.3.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti ) and stop (stop). some of t he inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (i nca). inherent instructio ns require no operand address and are one byte long. 10.3.2 immediate immediate instructions ar e those that contain a va lue to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and ar e two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 10.3.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opc ode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 10.3.4 extended extended instructions use three by tes and can access any address in memory. the first byte is the opcode ; the second and third bytes are the high and low bytes of the operand address. when using the freescale assembler, the programmer does not need to specify whether an ins truction is direct or extended. the assembler automatically selects the shorte st form of the instruction.
non-disclosure agreement required instruction set general release specif ication mc68hc05rc18 ? rev. 2.1 90 instruction set freescale semiconductor 10.3.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresse s within the first 256 memory locations. the index register contai ns the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000?$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently us ed ram or i/o location. 10.3.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsig ned byte in the index regist er to the unsigned byte following the opcode. the sum is t he effective address of the operand. these instructions can a ccess locations $0000?$01fe. indexed 8-bit offset instru ctions are useful for se lecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and coul d extend as far as lo cation 510 ($01fe). the k value is typically in the index regi ster, and the address of the beginning of the table is in the byte following the opcode. 10.3.7 indexed,16-bit offset indexed, 16-bit offset inst ructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index regi ster to the two unsigned bytes following the opcode. the sum is t he effective address of the operand. the first byte after the opc ode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecti ng the kth element in an n-element table anywhere in memory. as with direct and extended addressi ng, the freescale assembler determines the shortest fo rm of indexed addressing.
instruction set mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor instruction set 91 non-disclosure agreement required 10.3.8 relative relative addressing is only for branch instru ctions. if the branch condition is true, the cpu finds the effectiv e branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, two?s complement byte that gives a branching range of ?128 to +127 bytes from the address of the next location after the branch instruction. when using the freescale assembler, the programmer does not need to calculate the offset, because the a ssembler determines the proper offset and verifies that it is with in the span of the branch. 10.4 instruction types the mcu instructions fa ll into the follow ing five categories: register/memory instructions read-modify-write instructions jump/branch instructions bit manipulation instructions control instructions
non-disclosure agreement required instruction set general release specif ication mc68hc05rc18 ? rev. 2.1 92 instruction set freescale semiconductor 10.4.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use tw o operands. one operand is in either the accumulator or the index register . the cpu finds t he other operand in memory. table 10-1. register/memory instructions instruction mnemonic add memory byte and carr y bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and ca rry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub
instruction set mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor instruction set 93 non-disclosure agreement required 10.4.2 read-modify-write instructions these instructions read a memory lo cation or a register, modify its contents, and write the m odified value back to the memory location or to the register. note: do not use read-modify-write oper ations on write-only registers. table 10-2. read-modify -write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) 1. unlike other read-modify-w rite instructions, bclr and bset use only direct addressing. bit set bset (1) clear register clr complement (one?s complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (two?s complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 2. tst is an exception to the read-modify-write sequence be- cause it does not writ e a replacement value.
non-disclosure agreement required instruction set general release specif ication mc68hc05rc18 ? rev. 2.1 94 instruction set freescale semiconductor 10.4.3 jump/branch instructions jump instructions allo w the cpu to interrupt the normal se quence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instru ction (jsr) have no regi ster operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if th e test condition is not met, the branch is not performed. the brclr and brset instructions c ause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the by te to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the sp ecified bit tests true. t he bit to be tested and its condition (set or cl ear) is part of the opcode. the span of branching is from ?128 to +127 from t he address of the next lo cation after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register.
instruction set mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor instruction set 95 non-disclosure agreement required table 10-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr
non-disclosure agreement required instruction set general release specif ication mc68hc05rc18 ? rev. 2.1 96 instruction set freescale semiconductor 10.4.4 bit manipulation instructions the cpu can set or clear any writabl e bit in the first 256 bytes of memory, which includes i/o register s and on-chip ram locations. the cpu can also test and branch based on t he state of any bi t in any of the first 256 memory locations. table 10-4. bit mani pulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset
instruction set mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor instruction set 97 non-disclosure agreement required 10.4.5 control instructions these instructions act on cpu regi sters and control cpu operation during program execution. table 10-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait
non-disclosure agreement required instruction set general release specif ication mc68hc05rc18 ? rev. 2.1 98 instruction set freescale semiconductor 10.5 instruction set summary table 10-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a (a) + (m) + (c) ? t ? ? t ? t ? t imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a (a) + (m) ? t ? ? t ?? imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a (a) (m) ? ? ? t ? ? imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) ? ? ? t ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right ? ? ? t ?? dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 bclr n opr clear bit n mn 0 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? z = 1 ????? rel 27 rr 3 bhcc rel branch if half-carry bit clear pc (pc) + 2 + rel ? h = 0 ????? rel 28 rr 3 bhcs rel branch if half-carry bit set pc (pc) + 2 + rel ? h = 1 ????? rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? c z = 0 ????? rel 22 rr 3 bhs rel branch if higher or same pc (pc) + 2 + rel ? c = 0 ????? rel 24 rr 3 c b0 b7 0 b0 b7 c
instruction set mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor instruction set 99 non-disclosure agreement required bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ????? rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ????? rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) ? ? ? t ? ? imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? c = 1 ????? rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? c z = 1 ????? rel 23 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? i = 0 ????? rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? n = 1 ????? rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? i = 1 ????? rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? z = 0 ????? rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? n = 0 ????? rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ? 1 = 1 ????? rel 20 rr 3 brclr n opr rel branch if bit n clear pc (pc) + 2 + rel ? mn = 0 ???? ? t dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 + rel ? 1 = 0 ????? rel 21 rr 3 brset n opr rel branch if bit n set pc (pc) + 2 + rel ? mn = 1 ???? t ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn 1 ????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ????? rel ad rr 6 clc clear carry bit c 0 ???? 0 inh 98 2 cli clear interrupt mask i 0 ? 0 ??? inh 9a 2 table 10-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc
non-disclosure agreement required instruction set general release specif ication mc68hc05rc18 ? rev. 2.1 100 instruction set freescale semiconductor clr opr clra clrx clr opr ,x clr ,x clear byte m $00 a $00 x $00 m $00 m $00 ?? 0 1 ? dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) ? (m) ? ? ? t ?? imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (a) x (x ) = $ff ? (x) m (m ) = $ff ? (m) m (m ) = $ff ? (m) ?? ? t ? t 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) ? (m) ? ? ? t t ? t ? imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 ?? ? t ? t ? dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a (a) (m) ? ? ? t ? ? imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 ?? ? t ? t ? dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc jump address ????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 10-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc
instruction set mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor instruction set 101 non-disclosure agreement required jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n (n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc effective address ????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a (m) ? ? ? t ? ? imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x (m) ? ? ? t ? t ? imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) ? ? ? t ?? dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right ? ? 0 ?? dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a (x) (a) 0 ??? 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ?? ? t ?? dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation ????? inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a (a) (m) ? ? ? t ? ? imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit ? ? ? t ?? dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 10-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7
non-disclosure agreement required instruction set general release specif ication mc68hc05rc18 ? rev. 2.1 102 instruction set freescale semiconductor ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit ? ? ? t ?? dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp $00ff ????? inh 9c 2 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ? t ???? inh 80 9 rts return from subroutine sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ????? inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a (a) ? (m) ? (c) ? ? t ? ?? imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c 1 ???? 1 inh 99 2 sei set interrupt mask i 1 ? 1 ??? inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m (a) ? ? ? t ? ? dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and e nable irq pin ? 0 ? ? ? inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m (x) ? ? ? t ? ? dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a (a) ? (m) ? ? ??? imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ? 1 ??? inh 83 10 tax transfer accumulator to index register x (a) ????? inh 97 2 table 10-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc b0 b7 c
instruction set mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor instruction set 103 non-disclosure agreement required tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) ? $00 ? ? ?? ? dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a (x) ????? inh 9f 2 wait stop cpu clock and enable interrupts ? 0 t ??? inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow flag pc program counter ccr condition code register pch p rogram counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit o ffset addressing rr relative pr ogram counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry flag z zero flag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix1 indexed, 8-bit offset addressing mode loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative flag ? set or cleared n any bit ? not affected table 10-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc
instruction set non-disclosure agreement required general release specif ication mc68hc05rc18 ? rev. 2.1 104 instruction set freescale semiconductor table 10-7. opcode map bit manipulation branch read-modif y-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789abcdef 0 5 brset0 3dir 5 bset0 2dir 3 bra 2rel 5 neg 2dir 3 nega 1inh 3 negx 1inh 6 neg 2ix1 5 neg 1ix 9 rti 1inh 2 sub 2imm 3 sub 2dir 4 sub 3ext 5 sub 3ix2 4 sub 2ix1 3 sub 1ix 0 1 5 brclr0 3dir 5 bclr0 2dir 3 brn 2rel 6 rts 1inh 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 5 cmp 3ix2 4 cmp 2ix1 3 cmp 1ix 1 2 5 brset1 3dir 5 bset1 2dir 3 bhi 2rel 11 mul 1inh 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 5 sbc 3ix2 4 sbc 2ix1 3 sbc 1ix 2 3 5 brclr1 3dir 5 bclr1 2dir 3 bls 2rel 5 com 2dir 3 coma 1inh 3 comx 1inh 6 com 2ix1 5 com 1ix 10 swi 1inh 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 5 cpx 3ix2 4 cpx 2ix1 3 cpx 1ix 3 4 5 brset2 3dir 5 bset2 2dir 3 bcc 2rel 5 lsr 2dir 3 lsra 1inh 3 lsrx 1inh 6 lsr 2ix1 5 lsr 1ix 2 and 2imm 3 and 2dir 4 and 3ext 5 and 3ix2 4 and 2ix1 3 and 1ix 4 5 5 brclr2 3dir 5 bclr2 2dir 3 bcs/blo 2rel 2 bit 2imm 3 bit 2dir 4 bit 3ext 5 bit 3ix2 4 bit 2ix1 3 bit 1ix 5 6 5 brset3 3dir 5 bset3 2dir 3 bne 2rel 5 ror 2dir 3 rora 1inh 3 rorx 1inh 6 ror 2ix1 5 ror 1ix 2 lda 2imm 3 lda 2dir 4 lda 3ext 5 lda 3ix2 4 lda 2ix1 3 lda 1ix 6 7 5 brclr3 3dir 5 bclr3 2dir 3 beq 2rel 5 asr 2dir 3 asra 1inh 3 asrx 1inh 6 asr 2ix1 5 asr 1ix 2 ta x 1inh 4 sta 2dir 5 sta 3ext 6 sta 3ix2 5 sta 2ix1 4 sta 1ix 7 8 5 brset4 3dir 5 bset4 2dir 3 bhcc 2rel 5 asl/lsl 2dir 3 asla/lsla 1inh 3 aslx/lslx 1inh 6 asl/lsl 2ix1 5 asl/lsl 1ix 2 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 5 eor 3ix2 4 eor 2ix1 3 eor 1ix 8 9 5 brclr4 3dir 5 bclr4 2dir 3 bhcs 2rel 5 rol 2dir 3 rola 1inh 3 rolx 1inh 6 rol 2ix1 5 rol 1ix 2 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 5 adc 3ix2 4 adc 2ix1 3 adc 1ix 9 a 5 brset5 3dir 5 bset5 2dir 3 bpl 2rel 5 dec 2dir 3 deca 1inh 3 decx 1inh 6 dec 2ix1 5 dec 1ix 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 5 ora 3ix2 4 ora 2ix1 3 ora 1ix a b 5 brclr5 3dir 5 bclr5 2dir 3 bmi 2rel 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 5 add 3ix2 4 add 2ix1 3 add 1ix b c 5 brset6 3dir 5 bset6 2dir 3 bmc 2rel 5 inc 2dir 3 inca 1inh 3 incx 1inh 6 inc 2ix1 5 inc 1ix 2 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix c d 5 brclr6 3dir 5 bclr6 2dir 3 bms 2rel 4 tst 2dir 3 tsta 1inh 3 tstx 1inh 5 tst 2ix1 4 tst 1ix 2 nop 1inh 6 bsr 2rel 5 jsr 2dir 6 jsr 3ext 7 jsr 3ix2 6 jsr 2ix1 5 jsr 1ix d e 5 brset7 3dir 5 bset7 2dir 3 bil 2rel 2 stop 1inh 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 5 ldx 3ix2 4 ldx 2ix1 3 ldx 1ix e f 5 brclr7 3dir 5 bclr7 2dir 3 bih 2rel 5 clr 2dir 3 clra 1inh 3 clrx 1inh 6 clr 2ix1 5 clr 1ix 2 wait 1inh 2 txa 1inh 4 stx 2dir 5 stx 3ext 6 stx 3ix2 5 stx 2ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor electrical specifications 105 non-disclosure agreement required general release specification ? mc68hc05rc18 section 11. electrical specifications 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 11.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 11.4 operating temperature ra nge. . . . . . . . . . . . . . . . . . . . . . . . 107 11.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 11.6 dc electrical characteristics (5.0 vd c). . . . . . . . . . . . . . . . . . 108 11.7 dc electrical characteristics (2.2 vd c). . . . . . . . . . . . . . . . . . 109 11.8 control timing (2.2 vdc to 5.0 vdc) . . . . . . . . . . . . . . . . . . . . 111 11.2 introduction this section contains mcu electr ical specifications and timing information.
non-disclosure agreement required electrical specifications general release specif ication mc68hc05rc18 ? rev. 2.1 106 electrical specifications freescale semiconductor 11.3 maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. the mcu contains circuitry to pr otect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note: this device is not guar anteed to operate properly at the maximum ratings. refer to 11.6 dc electrical characteristics (5.0 vdc) and 11.7 dc electrical charact eristics (2.2 vdc) for guaranteed operating conditions. rating symbol value unit supply voltage v dd ?0.3 to +7.0 v input voltage v in v ss ?0.3 to v dd +0.3 v current drain per pin excluding v dd and v ss i25ma operating temperature range mc68hc05rc18 (standard) t a t l to t h 0 to +70 o c storage temperature range t stg ?65 to +150 o c
electrical specifications mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor electrical specifications 107 non-disclosure agreement required 11.4 operating temperature range 11.5 thermal characteristics characteristic symbol value unit operating temperature range mc68hc05rc18 (standard) t a t l to t h 0 to +70 c characteristic symbol value unit thermal resistance pdip soic ja 60 60 c/w
non-disclosure agreement required electrical specifications general release specif ication mc68hc05rc18 ? rev. 2.1 108 electrical specifications freescale semiconductor 11.6 dc electrical ch aracteristics (5.0 vdc) characteristic symbol min typ max unit output voltage i load = 10.0 a i load = ?10.0 a v ol v oh ? v dd ? 0.1 ? ? 0.1 ? v output high voltage (i load = ?4 ma) port a, port b, port c (bits 4?7) (i load = ?20 ma) iro (i load = ?4 ma) port c (bits 0?3) v oh v dd ?0.8 v dd ?0.8 v dd ?0.8 v dd ?0.2 v dd ?0.4 v dd ?0.2 ? ? ? v output low voltage (i load = 6 ma) port a, port b, port c (bits 4?7) (i load = 35 ma) iro (i load = 20 ma) port c (bits 0?3) v ol ? ? ? 0.2 0.4 0.2 0.5 0.8 0.5 v input high voltage port a, port b, port c, irq , reset , lprst , osc1 v ih 0.7 x v dd ?v dd v input low voltage port a, port b, port c, irq , reset , lprst , osc1 v il v ss ? 0.2 x v dd v supply current (see notes) run wait stop 25 o c 0 o c to +70 o c i dd ? ? ? ? 2.4 0.3 0.5 0.5 4.0 1.0 10.0 20.0 ma ma a a i/o ports hi-z leakage current port a, port b, port c i oz ?10 ? 10 a input current reset , lprst , irq , osc1 pb0?pb7 with strong pullups enabled (v in = 0.2 x v dd ) 9 pb0?pb7 with strong pullups enabled (v in = 0.7 x v dd ) pb0?pb7 with weak pullups enabled (v in = 0.2 x v dd ) pb0?pb7 with weak pullups enabled (v in = 0.7 x v dd ) i in ?1 ?70 ?40 ?15 ?5 ? ?136 ?79 ?48 ?20 1 ?210 ?130 ?80 ?60 a capacitance ports (as input or output) reset , lprst , irq c out c int ? ? ? ? 12 8 pf notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted 2. all values shown reflect average measurements. 3. typical values at midpoint of voltage range, 25 o c only 4. wait i dd : only core timer active 5. run (operating) i dd , wait i dd : measured using external square wave clock source (f osc = 4.2 mhz), all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 6. wait, stop i dd : all ports configured as inputs, v il = 0.2 v, v ih = v dd ?0.2 v 7. stop i dd is measured with osc1 = v ss . 8. wait i dd is affected linearly by the osc2 capacitance. 9. strong pullups are designed to be capable of pulling to v ih within 1 s for a 100 pf, 4-k ? load.
electrical specifications mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor electrical specifications 109 non-disclosure agreement required 11.7 dc electrical ch aracteristics (2.2 vdc) characteristic symbol min typ max unit output voltage i load = 10.0 a i load = ?10.0 a v ol v oh ? v dd ? 0.1 ? ? 0.1 ? v output high voltage (i load = ?1.2 ma) port a, port b, port c (bits 4?7) (i load = ?6 ma) iro (i load = ?1.2 ma) port c (bits 0?3) v oh v dd ? 0.3 v dd ? 0.8 v dd ? 0.3 v dd ? 0.1 v dd ? 0.3 v dd ? 0.1 ? ? ? v output low voltage (i load = 2.0 ma) port a, port b, port c (bits 4?7) (i load = 11 ma) iro (i load = 7.0 ma) port c (bits 0?3) v ol ? ? ? 0.1 0.2 0.1 0.3 0.8 0.3 v input high voltage port a, port b, port c, irq , reset , lprst , osc1 v ih 0.7 x v dd ?v dd v input low voltage port a, port b, port c, irq , reset , lprst , osc1 v il v ss ? 0.2 x v dd v supply current (see notes) run wait stop 25 o c 0 o c to +70 o c i dd i dd i dd i dd ? ? ? ? 0.75 0.1 0.1 0.1 1.0 0.3 1.0 4.0 ma ma a a i/o ports hi-z leakage current port a, port b, port c i oz ?4 ? 4 a input current reset , lprst , irq , osc1 pb0?pb7 with strong pullups enabled (v in = 0.4 x v dd ) 9 pb0?pb7 with strong pullups enabled (v in = 0.7 x v dd ) pb0?pb7 with weak pullups enabled (v in = 0.4 x v dd ) pb0?pb7 with weak pullups enabled (v in = 0.7 x v dd i in ?0.4 ?8 ?5 ?2 ?1 ? ?21 ?16 ?6 ?2 0.4 ?35 ?28 ?15 ?12 a capacitance ports (as input or output) reset , lprst , irq c out c int ? ? ? ? 12 8 pf notes: 1. v dd = 2.2 vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted 2. all values shown reflect average measurements. 3. typical values at midpoint of voltage range, 25 o c only 4. wait i dd : only core timer active 5. run (operating) i dd , wait i dd : measured using external square wave clock source (f osc = 4.2 mhz), all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 6. wait, stop i dd : all ports configured as inputs, v il = 0.2 v, v ih = v dd ?0.2 v 7. stop i dd is measured with osc1 = v ss . 8. wait i dd is affected linearly by the osc2 capacitance. 9. strong pullups are designed to be capable of pulling to v ih within 25 s for a 100 pf, 4-k ? load.
non-disclosure agreement required electrical specifications general release specif ication mc68hc05rc18 ? rev. 2.1 110 electrical specifications freescale semiconductor figure 11-1. maximum supply curr ent versus internal clock frequency r u n i d d r u n i d d w a i t i d d w a i t i d d 0 1.0 2.0 3.0 4.0 0.5 2.0 1.0 1.5 v dd = 5.5 v t a = ?0 c to 70 c supply current (ma) 02.5 internal clock frequency (mhz) xtal 2 2.1 0.5 2.0 1.0 1.5 v dd = 2.4 v t a = ?0 c to 70 c supply current (ma) 02.5 internal clock frequency (mhz) xtal 2 2.1 0 0.2 0.6 0.8 1.0 0.3 0.4 stop i dd (20 a) stop i dd (4 a)
electrical specifications mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor electrical specifications 111 non-disclosure agreement required 11.8 control timing (2.2 vdc to 5.0 vdc) characteristic symbol min max unit frequency of operation crystal external clock f osc f osc ? dc 4.2 4.2 mhz mhz internal operating frequency crystal (f osc /2) external clock (f osc /2) f op f op ? dc 2.1 2.1 mhz mhz cycle time t cyc 480 ? ns crystal oscillator startup time (see note 3) t oxov ?100ms stop recovery startup time (crystal oscillator) ( see note 3) t ilch ?100ms reset pulse width t rl 1.5 ? t cyc interrupt pulse width low (edge-triggered) t ilih 125 ? ns interrupt pulse period t ilil see note 2 ? t cyc osc1 pulse width t oh , t ol 90 ? ns notes: 1. v dd = 2.2 to 5.5 vdc, v ss = 0 vdc, t a = 0 o c to +70 o c, unless otherwise noted 2. the minimum period, t ilil , should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 t cyc . 3. these features, are not tested.
non-disclosure agreement required electrical specifications general release specif ication mc68hc05rc18 ? rev. 2.1 112 electrical specifications freescale semiconductor
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor mechanical specifications 113 non-disclosure agreement required general release specification ? mc68hc05rc18 section 12. mechanical specifications 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 12.3 28-pin plastic dual-in-line pa ckage (case 710-02) . . . . . . . 114 12.4 28-pin small ou tline integrated circuit package (case 751f-04) . . . . . . . . . . . . . . . . . . . .114 12.5 44-pin plastic leaded chip ca rrier package (case 777-02) . 115 12.2 introduction this section describes th e dimensions of the d ual-in-line package (dip), small outline integr ated circuit (soic), and pl astic leaded chip carrier (plcc) mcu packages. the following figures show the latest packages at the time of this publication. to make sure that you have the latest package specifications, please visi t the freescale website at http://freescale.com. follow wwweb on-line instru ctions to retrieve the current mechanical specifications.
non-disclosure agreement required mechanical specifications general release specif ication mc68hc05rc18 ? rev. 2.1 114 mechanical specifications freescale semiconductor 12.3 28-pin plastic dual-i n-line package (case 710-02) 12.4 28-pin small outline integrat ed circuit package (case 751f-04)

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mechanical specifications mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor mechanical specifications 115 non-disclosure agreement required 12.5 44-pin plastic leaded chip carrier package (case 777-02) -n- -l- -m- d y d k v w 1 44 brk b z u x view d-d s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t g1 s l-m s 0.010 (0.25) n s t k1 f h s l-m m 0.007(0.180) n s t z g g1 r a e j view s c s l-m m 0.007(0.180) n s t s l-m m 0.007(0.180) n s t 0.004 (0.10) -t- seating plane view s dim min max min max millimeters inches a 0.685 0.695 17.40 17.65 b 0.685 0.695 17.40 17.65 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.650 0.656 16.51 16.66 u 0.650 0.656 16.51 16.66 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 g1 0.610 0.630 15.50 16.00 k1 0.040 1.02 s l-m s 0.010 (0.25) n s t s l-m m 0.007(0.180) n s t 2 10 notes: 1. datums -l-, -m-, and -n- are determined where top of lead sholders exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimension r and u do not include mold flash. allowable mold flash is 0.010 (0.25) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of the mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. diminsion h does not include dambar protrusion or intrusion. the dambar protusion(s) shall not cause the h diminsion to be greater than 0.037 (0.940116). the dambar intrusion(s) shall not cause the h diminision to smaller than 0.025 (0.635).
non-disclosure agreement required mechanical specifications general release specif ication mc68hc05rc18 ? rev. 2.1 116 mechanical specifications freescale semiconductor
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor ordering information 117 non-disclosure agreement required design specification ? mc68hc05rc18 section 13. ordering information 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.3 mcu ordering forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 13.4 application program media. . . . . . . . . . . . . . . . . . . . . . . . . . .118 13.5 rom program verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 13.6 rom verification units (rvus). . . . . . . . . . . . . . . . . . . . . . . . 120 13.7 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 13.2 introduction this section contains instructions for ordering custom-masked rom mcus. 13.3 mcu ordering forms to initiate an order for a rom-bas ed mcu, first obtain the current ordering form for the mcu from a freescale repres entative. submit the following items when ordering mcus: a current mcu order ing form that is completely filled out (contact your freescale sale s office for assistance.) a copy of the customer specificat ion if the custom er specification deviates from the freescale specification for the mcu customer?s application program on one of the media listed in 13.4 application program media
non-disclosure agreement required ordering information general release specif ication mc68hc05rc18 ? rev. 2.1 118 ordering information freescale semiconductor the current mcu ordering form is also available through the freescale freeware bulletin board service (b bs). the telephone nu mber is (512) 891-free. after making the connection, type bbs in lowercase letters. then press the return key to start the bbs software. 13.4 application program media please deliver the app lication program to fr eescale in one of the following media: macintosh ?1 3 1/2-inch diskette (double-sided 800 k or double-sided high-density 1.4 m) ms-dos ?2 or pc-dos tm 3 3 1/2-inch diskett e (double-sided 720 k or double-sided hi gh-density 1.44 m) ms-dos ? or pc-dos tm 5 1/4-inch diske tte (double-sided double-density 360 k or doubl e-sided high-density 1.2 m) use positive logic fo r data and addresses. when submitting the appl ication program on a di skette, clearly label the diskette with the fo llowing information: customer name customer part number project or product name file name of object code date name of operating system that formatted diskette formatted capacity of diskette on diskettes, the applic ation program must be in freescale?s s-record format (s1 and s9 records), a char acter-based object file format generated by m6805 cross a ssemblers and linkers. 1. macintosh is a registered tr ademark of apple computer, inc. 2. ms-dos is a registered trademark of microsoft corporation. 3. pc-dos is a trademark of international business machines corporation.
ordering information mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor ordering information 119 non-disclosure agreement required note: begin the application progr am at the first user rom location. program addresses must correspond exactly to the available on-chip user rom addresses as shown in the memory m ap. write $00 in all non-user rom locations or leave all nonuser rom lo cations blank. refer to the current mcu ordering form for additional requirements. freescale may request pattern re-submission if nonuser areas contain any nonzero code. if the memory map has two user ro m areas with the same addresses, then write the two areas in separat e files on the diske tte. label the diskette with both filenames. in addition to the object code, a file containing the source code can be included. freescale keeps this code confidential and uses it only to expedite rom pattern generat ion in case of any diff iculty with the object code. label the diskett e with the filename of the source code. 13.5 rom program verification the primary use for the on-chip ro m is to hold the customer?s application program. the customer develops and debugs the application program and then submits the mcu order along with the application program. freescale inputs the customer?s application program code into a computer program that generates a listing verify file. the li sting verify file represents the memory m ap of the mcu. the listing verify file contains the user rom code and may also contain nonuser rom code, such as self-check code. freescale sends the customer a comput er printout of the listing verify file along with a listing verify form. to aid the customer in c hecking the listing verify file, freescale will program the listing verify file into customer-supplied blank preformatted macintosh or dos disks. all original patter n media are filed for contractual purposes and are not returned. check the listing verify fi le thoroughly, then comple te and sign the listing verify form and return the listing verify form to freescale. the signed listing verify form constitutes the contractual agreement for the creation of the custom mask.
non-disclosure agreement required ordering information general release specif ication mc68hc05rc18 ? rev. 2.1 120 ordering information freescale semiconductor 13.6 rom verification units (rvus) after receiving the signed listing verify form, fr eescale manufactures a custom photographic mask. the mask contains the customer?s application program and is used to process silicon wafers. the application program cannot be cha nged after the manufacture of the mask begins. freescale then produces 10 mc us, called rvus, and sends the rvus to the customer . rvus are usually packaged in unmarked ceramic and tested to 5 vd c at room temper ature. rvus are not tested to environmental extremes because thei r sole purpose is to demonstrate that the cu stomer?s user rom pattern was properly implemented. the 10 rvus are free of charge with the minimum order quantity. these units are not to be used for qualif ication or production. rvus are not guaran teed by freescale quality assurance. 13.7 mc order numbers table 13-1 shows the mc or der numbers for the available package types. table 13-1. mc order numbers package type operating temperature range mc order number 28-pin plastic dual in-line package (dip) 0 c to 70 c mc68hc05rc18p 28-pin small out line integrated circuit package (soic) 0 c to 70 c mc68hc05rc18dw 44-pin plastic leaded chip carrier (plcc) 0 c to 70 c mc68hc05rc18fn
mc68hc05rc18 ? rev. 2.1 general release specification freescale semiconductor 121 non-disclosure agreement required general release specification ? mc68hc05rc18 appendix a. mc68hc05rc9 a.1 contents a.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 a.3 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 a.2 introduction appendix a introduces the mc68hc 05rc9. the technical data applying to the mc68hc05rc18 applies to the mc68hc05 rc9 with the exceptions given in this appendix. a.3 memory map both the mc68hc05rc9 and the mc68hc05rc18 have 16-kbyte memory maps consisting of us er rom, ram, burn-in rom, and input/output (i/o). however, th e user rom for the mc68hc05rc9 consists of only 8112 bytes of rom. figure a-1 shows the mc68hc05rc9 me mory map in user mode.
non-disclosure agreement required general release specif ication mc68hc05rc18 ? rev. 2.1 122 freescale semiconductor figure a-1. mc68hc05rc9 memory map i/o 32 bytes ram 160 bytes stack 64 bytes ram 128 bytes user rom 8112 bytes burn-in rom & vectors user vectors 16 bytes $0000 $001f $0020 $00bf $00c0 $00ff $0100 $017f $0180 $3faf $3fb0 $3fef $3ff0 $3fff 0000 0031 0032 0191 0192 0255 0383 0384 16303 16304 16367 16368 16383 0256 port a data register port b data register port c data register port a data direction register port b data direction register port c data direction register core timer control & status reg. reserved $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0f 64 bytes reserved reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq/ptb keyscan pullups irq/ptb keyscan pullups cmt timer vector (low byte) cmt timer vector (high byte) core timer vector (low byte) $3ff0 $3ff5 $3ff6 $3ff7 $3ff8 $3ff9 $3ffa $3ffb $3ffc $3ffd $3ffe unused $3fff reserved reserved reserved $18 $1f reserved $1e $10 $11 $12 $13 $14 $15 $16 $17 cmt timer chr1 cmt timer clr1 cmt timer chr2 cmt timer clr2 cmt timer mcsr cmt timer mdr1 cmt timer mdr2 cmt timer mdr3 core timer vector (high byte) unused $0a core timer counter register . . . . . . . ... .. vector (high byte) vector (low byte) reserved . . . . . . . $1fff $2000 unused

how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. rev. 2.1 hc05rc18grs/d 08/2005

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