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| sh7065 hardware manual ade-602-166 rev. 1.0 8/25/99 hitachi, ltd.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. rev. 1.0, 08/99, page i of 875 preface the sh7065 is a single-chip risc (reduced instruction set computer) microcomputer that has an original hitachi risc type cpu and high-performance dsp unit as its core, and also includes peripheral functions necessary for system configuration. the cpu of the sh7065 has a risc type instruction set, with basic instructions executed in one system clock cycle, for a higher instruction execution speed. it employs an internal 32-bit configuration, and offers enhanced data processing performance. on-chip supporting functions necessary for system configuration include large-capacity rom and ram, timers, an sci, and a/d and d/a converters. in addition, an external memory access support function allows efficient connection of memory and peripheral lsis. these functions enable system costs to be greatly reduced. there are two versions of the sh7065, with different kinds of on-chip rom: a mask rom version and a flash memory version. flash memory programs can be written with a programmer that supports sh7065 programming, and the flash memory can also be programmed and erased by software. this hardware manual describes the hardware of the sh7065. details of instructions can be found in the programming manual. related manual sh-1/sh-2/sh-dsp programming manual (ade-602-063c) details of the development environment system are available from your hitachi sales representative. rev. 1.0, 08/99, page iii of 875 contents section 1 overview ............................................................................................................. 1 1.1 features of sh7065.......................................................................................................... .1 1.2 block diagram ............................................................................................................... ... 8 1.3 pin arrangement and pin functions ................................................................................. 9 1.3.1 pin arrangement .................................................................................................. 9 1.3.2 pin functions ....................................................................................................... 10 section 2 cpu ...................................................................................................................... 21 2.1 register configuration...................................................................................................... 21 2.1.1 general registers ................................................................................................. 21 2.1.2 control registers ................................................................................................. 23 2.1.3 system registers.................................................................................................. 26 2.1.4 dsp registers ...................................................................................................... 27 2.1.5 notes on guard bits and overflow treatment..................................................... 30 2.1.6 initial register values.......................................................................................... 31 2.2 data formats................................................................................................................ ..... 32 2.2.1 register data formats.......................................................................................... 32 2.2.2 memory data formats ......................................................................................... 32 2.2.3 immediate data formats...................................................................................... 33 2.2.4 dsp type data formats ...................................................................................... 33 2.2.5 dsp type instructions and data formats............................................................ 35 2.3 features of cpu core instructions ................................................................................... 40 2.4 instruction formats ......................................................................................................... .. 43 2.4.1 cpu instruction addressing modes .................................................................... 43 2.4.2 dsp data addressing .......................................................................................... 47 2.4.3 cpu instruction formats ..................................................................................... 53 2.4.4 dsp instruction formats...................................................................................... 57 2.5 instruction set ............................................................................................................. ...... 63 2.5.1 cpu instruction set ............................................................................................. 63 2.5.2 dsp data transfer instruction set....................................................................... 79 2.5.3 dsp operation instruction set............................................................................. 83 section 3 operating modes ............................................................................................... 97 3.1 operating mode selection ................................................................................................ 97 3.1.1 operating modes.................................................................................................. 99 3.1.2 pin configuration................................................................................................. 100 3.1.3 register configuration......................................................................................... 100 3.2 register descriptions ....................................................................................................... . 101 3.2.1 mode status register (msr) ............................................................................... 101 rev. 1.0, 08/99, page iv of 875 3.2.2 mode control register (modecr) .................................................................... 102 section 4 clock pulse generator (cpg) and power-down modes ..................... 103 4.1 overview.................................................................................................................... ....... 103 4.1.1 features................................................................................................................ 10 3 4.1.2 block diagram of cpg........................................................................................ 104 4.1.3 cpg pin configuration ........................................................................................ 106 4.1.4 cpg register configuration ................................................................................ 106 4.2 clock operating modes .................................................................................................... 107 4.3 cpg register description ................................................................................................. 109 4.3.1 frequency control register (frqcr)................................................................. 109 4.4 changing the frequency ................................................................................................... 127 4.5 output clock control........................................................................................................ 128 4.6 oscillator.................................................................................................................. ......... 129 4.6.1 connecting a crystal resonator........................................................................... 129 4.6.2 external clock input methods ............................................................................. 130 4.6.3 notes on board design ........................................................................................ 131 4.7 oscillation stoppage detection function.......................................................................... 133 4.8 power-down modes ......................................................................................................... 134 4.8.1 states in power-down modes.............................................................................. 134 4.8.2 pin configuration................................................................................................. 135 4.9 register descriptions ....................................................................................................... . 136 4.9.1 standby control register (sbycr) .................................................................... 136 4.9.2 module stop control registers 1 and 2 (mstpcr1, mstpcr2) ...................... 137 4.9.3 module clock control registers 1 to 5 (mclkcr1 to mclkcr5) ................. 138 4.10 sleep mode ................................................................................................................. ...... 141 4.10.1 transition to sleep mode..................................................................................... 141 4.10.2 exit from sleep mode.......................................................................................... 142 4.11 software standby mode.................................................................................................... 14 2 4.11.1 transition to software standby mode ................................................................. 142 4.11.2 exit from software standby mode ...................................................................... 144 4.11.3 software standby mode application example.................................................... 145 4.12 hardware standby mode .................................................................................................. 146 4.12.1 transition to hardware standby mode ................................................................ 146 4.12.2 exit from hardware standby mode ..................................................................... 146 4.12.3 hardware standby mode timing......................................................................... 146 4.13 module standby function................................................................................................. 147 4.13.1 transition to module standby function .............................................................. 147 4.13.2 exit from module standby function ................................................................... 149 4.14 module clock division function...................................................................................... 149 4.14.1 clock definitions ................................................................................................. 149 4.14.2 transition to module clock division function ................................................... 150 4.14.3 exit from module clock division function ........................................................ 152 rev. 1.0, 08/99, page v of 875 4.14.4 notes on use of module clock division function .............................................. 152 section 5 exception handling ......................................................................................... 153 5.1 overview.................................................................................................................... ....... 153 5.1.1 exception handling types and priority............................................................... 153 5.1.2 timing of exception source detection and start of exception handling ........... 154 5.1.3 exception vector table ....................................................................................... 154 5.2 power-on reset .............................................................................................................. .. 157 5.3 address errors .............................................................................................................. .... 158 5.3.1 address error sources ......................................................................................... 158 5.3.2 address error exception handling ...................................................................... 159 5.4 interrupts .................................................................................................................. ......... 159 5.4.1 interrupt sources.................................................................................................. 159 5.4.2 interrupt priority .................................................................................................. 160 5.4.3 interrupt exception handling............................................................................... 160 5.5 instruction exceptions...................................................................................................... . 161 5.5.1 types of instruction exception ............................................................................ 161 5.5.2 trap instruction.................................................................................................... 161 5.5.3 slot illegal instructions ........................................................................................ 162 5.5.4 general illegal instructions.................................................................................. 162 5.6 cases in which exceptions are not accepted ................................................................. 163 5.6.1 after a delayed branch instruction ..................................................................... 163 5.6.2 after an instruction for which interruption is prohibited ................................... 163 5.6.3 instructions in repeat loops................................................................................ 164 5.7 stack status after exception handling.............................................................................. 165 5.8 usage notes ................................................................................................................. ..... 166 5.8.1 stack pointer (sp) value ..................................................................................... 166 5.8.2 vector base register (vbr) value ..................................................................... 166 5.8.3 address errors occurring in address error exception handling stacking ......... 166 section 6 interrupt controller (intc) ........................................................................... 167 6.1 overview.................................................................................................................... ....... 167 6.1.1 features................................................................................................................ 16 7 6.1.2 block diagram..................................................................................................... 168 6.1.3 pin configuration................................................................................................. 169 6.1.4 register configuration......................................................................................... 169 6.2 interrupt sources........................................................................................................... .... 170 6.2.1 nmi interrupt....................................................................................................... 170 6.2.2 user break interrupt ............................................................................................ 170 6.2.3 external interrupts ............................................................................................... 170 6.2.4 on-chip peripheral module interrupts ................................................................ 172 6.2.5 interrupt exception vectors and priority order................................................... 172 6.3 register descriptions ....................................................................................................... . 179 rev. 1.0, 08/99, page vi of 875 6.3.1 interrupt priority registers a to l (ipra to iprl)............................................. 179 6.3.2 interrupt control register 1 (icr1)..................................................................... 180 6.3.3 interrupt control register 2 (icr2)..................................................................... 181 6.3.4 irq status register (isr).................................................................................... 182 6.4 operation ................................................................................................................... ....... 184 6.4.1 interrupt operation sequence .............................................................................. 184 6.4.2 interrupt response time...................................................................................... 186 6.4.3 stack status after interrupt exception handling.................................................. 188 6.5 sampling of signals irq3 to irq0 in irl mode............................................................. 189 6.6 data transfer by means of interrupt request signal........................................................ 190 6.6.1 to designate a source as a dmac activation source, not a cpu interrupt source ................................................................................. 190 6.6.2 to designate a source as a cpu interrupt source, not a dmac activation source.......................................................................... 190 6.7 usage notes ................................................................................................................. ..... 191 6.7.1 irq3 to irq0 sampling and interrupt source determination in irl interrupt mode.......................................................................................... 191 6.7.2 irq pin noise cancellation function.................................................................. 191 section 7 user break controller (ubc) ....................................................................... 193 7.1 overview.................................................................................................................... ....... 193 7.1.1 features................................................................................................................ 19 3 7.1.2 block diagram..................................................................................................... 194 7.1.3 register configuration......................................................................................... 195 7.2 register descriptions ....................................................................................................... . 195 7.2.1 user break address register (ubar) ................................................................ 195 7.2.2 user break address mask register (ubamr) ................................................... 197 7.2.3 user break bus cycle register (ubbr) ............................................................. 198 7.3 operation ................................................................................................................... ....... 201 7.3.1 user break operation sequence .......................................................................... 201 7.3.2 instruction fetch cycle break.............................................................................. 202 7.3.3 data access cycle break..................................................................................... 202 7.3.4 x memory bus or y memory bus cycle break.................................................. 203 7.3.5 program counter (pc) value saved .................................................................... 203 7.4 examples of use ............................................................................................................. .. 204 7.5 usage notes ................................................................................................................. ..... 207 7.5.1 changes to ubc register settings ...................................................................... 207 7.5.2 repeat condition breaks ..................................................................................... 207 section 8 bus state controller (bsc) ........................................................................... 209 8.1 overview.................................................................................................................... ....... 209 8.1.1 features................................................................................................................ 20 9 8.1.2 block diagram..................................................................................................... 211 rev. 1.0, 08/99, page vii of 875 8.1.3 pin configuration................................................................................................. 212 8.1.4 register configuration......................................................................................... 213 8.1.5 address format.................................................................................................... 214 8.2 register descriptions ....................................................................................................... . 217 8.2.1 bus control register (bcr) ................................................................................ 217 8.2.2 area control registers 1 (acr1_0 to acr1_5)................................................. 218 8.2.3 wait control registers (wcr_0 to wcr_3) ...................................................... 222 8.2.4 dram control register 1 (dcr1) ..................................................................... 224 8.2.5 dram control register 2 (dcr2) ..................................................................... 226 8.2.6 dram control register 3 (dcr3) ..................................................................... 228 8.2.7 refresh timer control/status register (rtcsr) ................................................ 230 8.2.8 refresh timer counter (rtcnt)........................................................................ 234 8.2.9 refresh time constant register (rtcor) ......................................................... 235 8.2.10 refresh count register (rfcr) .......................................................................... 236 8.3 operation ................................................................................................................... ....... 237 8.3.1 endian/access size and data alignment............................................................. 237 8.3.2 areas .................................................................................................................... 2 43 8.3.3 normal space access .......................................................................................... 244 8.3.4 dram interface .................................................................................................. 255 8.3.5 multiplexed address/data i/o interface.............................................................. 271 8.3.6 waits between access cycles.............................................................................. 276 8.3.7 bus arbitration .................................................................................................... 278 8.4 number of access cycles ................................................................................................. 279 8.5 usage notes ................................................................................................................. ..... 287 section 9 direct memory access controller (dmac) ............................................ 289 9.1 overview.................................................................................................................... ....... 289 9.1.1 features................................................................................................................ 28 9 9.1.2 block diagram..................................................................................................... 291 9.1.3 pin configuration................................................................................................. 292 9.1.4 register configuration......................................................................................... 293 9.2 register descriptions ....................................................................................................... . 295 9.2.1 dma source address registers 0 to 3 (sar0 to sar3) .................................... 295 9.2.2 dma destination address registers 0 to 3 (dar0 to dar3)............................ 295 9.2.3 dma transfer count registers 0 to 3 (dmatcr0 to dmatcr3) .................. 296 9.2.4 dma channel control registers 0 to 3 (chcr0 to chcr3)............................. 297 9.2.5 next source address registers 0 to 3 (nsar0 to nsar3) ................................ 304 9.2.6 next destination address registers 0 to 3 (ndar0 to ndar3) ....................... 304 9.2.7 next transfer count registers 0 to 3 (ndmatcr0 to ndmatcr3) .............. 305 9.2.8 chain transfer count registers 0 to 3 (chncnt0 to chncnt3).................... 305 9.2.9 dma operation register (dmaor)................................................................... 306 9.3 operation ................................................................................................................... ....... 308 9.3.1 dma transfer procedure .................................................................................... 308 rev. 1.0, 08/99, page viii of 875 9.3.2 dma transfer requests ...................................................................................... 310 9.3.3 channel priorities................................................................................................. 313 9.3.4 types of dma transfer....................................................................................... 317 9.3.5 number of bus cycle states and dreq pin sampling timing .......................... 324 9.3.6 parallel operation of dma and cpu .................................................................. 338 9.3.7 dma transfer when external bus is released .................................................. 338 9.3.8 chain transfer ..................................................................................................... 340 9.4 example of use.............................................................................................................. ... 342 9.4.1 example of dma transfer between on-chip sci and external memory .......... 342 9.5 usage notes ................................................................................................................. ..... 343 section 10 16-bit timer pulse unit (tpu) .................................................................. 345 10.1 overview................................................................................................................... ........ 345 10.1.1 features................................................................................................................ 3 45 10.1.2 block diagram..................................................................................................... 349 10.1.3 pin configuration................................................................................................. 350 10.1.4 register configuration......................................................................................... 352 10.2 register descriptions ...................................................................................................... .. 354 10.2.1 timer control registers (tcr) ........................................................................... 354 10.2.2 timer mode registers (tmdr) .......................................................................... 359 10.2.3 timer i/o control registers (tior).................................................................... 361 10.2.4 timer interrupt enable registers (tier) ............................................................ 378 10.2.5 timer status registers (tsr) .............................................................................. 380 10.2.6 timer counters (tcnt) ...................................................................................... 383 10.2.7 timer general registers (tgr)........................................................................... 384 10.2.8 timer start register (tstr)................................................................................ 384 10.2.9 timer sync register (tsyr)............................................................................... 385 10.3 interface to bus master .................................................................................................... . 386 10.3.1 16-bit registers ................................................................................................... 386 10.3.2 8-bit registers ..................................................................................................... 386 10.4 operation .................................................................................................................. ........ 388 10.4.1 overview.............................................................................................................. 388 10.4.2 basic functions.................................................................................................... 389 10.4.3 synchronous operation........................................................................................ 394 10.4.4 buffer operation .................................................................................................. 397 10.4.5 cascaded operation ............................................................................................. 401 10.4.6 pwm modes ........................................................................................................ 402 10.4.7 phase counting mode .......................................................................................... 408 10.5 interrupts ................................................................................................................. .......... 416 10.5.1 interrupt sources and priorities............................................................................ 416 10.5.2 dmac activation................................................................................................ 418 10.5.3 a/d converter activation.................................................................................... 418 10.6 operation timing........................................................................................................... ... 419 rev. 1.0, 08/99, page ix of 875 10.6.1 input/output timing ............................................................................................ 419 10.6.2 interrupt signal timing........................................................................................ 423 10.7 usage notes ................................................................................................................ ...... 427 section 11 motor management timer (mmt) ........................................................... 437 11.1 overview................................................................................................................... ........ 437 11.1.1 features................................................................................................................ 4 37 11.1.2 block diagram..................................................................................................... 438 11.1.3 pin configuration................................................................................................. 439 11.1.4 register configuration......................................................................................... 439 11.2 register descriptions ...................................................................................................... .. 441 11.2.1 timer mode register (tmdr) ............................................................................ 441 11.2.2 timer control register (tcnr) .......................................................................... 442 11.2.3 timer status register (tsr)................................................................................ 443 11.2.4 timer counter (tcnt)........................................................................................ 445 11.2.5 timer buffer registers (tbr) ............................................................................. 445 11.2.6 timer general registers (tgr)........................................................................... 446 11.2.7 timer dead time counters (tdcnt)................................................................. 446 11.2.8 timer dead time data register (tddr)............................................................ 446 11.2.9 timer period buffer register (tpbr) ................................................................. 447 11.2.10 timer period data register (tpdr).................................................................... 447 11.3 operation .................................................................................................................. ........ 447 11.3.1 sample setting procedure .................................................................................... 448 11.3.2 overview of operation ........................................................................................ 449 11.3.3 output protection functions ................................................................................ 456 11.4 interrupts ................................................................................................................. .......... 457 11.4.1 compare match interrupts ................................................................................... 457 11.4.2 dma controller activation ................................................................................. 457 11.4.3 a/d converter activation.................................................................................... 457 11.5 operation timing........................................................................................................... ... 457 11.5.1 input/output timing ............................................................................................ 457 11.5.2 interrupt signal timing........................................................................................ 460 11.6 usage notes ................................................................................................................ ...... 462 11.7 port output enable (poe)................................................................................................. 46 4 11.7.1 overview.............................................................................................................. 464 11.7.2 register description............................................................................................. 466 11.7.3 operation ............................................................................................................. 470 section 12 compare match timer (cmt) ................................................................... 471 12.1 overview................................................................................................................... ........ 471 12.1.1 features................................................................................................................ 4 71 12.1.2 block diagram..................................................................................................... 472 12.1.3 register configuration......................................................................................... 473 rev. 1.0, 08/99, page x of 875 12.2 register descriptions ...................................................................................................... .. 474 12.2.1 compare match timer start register (cmstr) ................................................. 474 12.2.2 compare match timer control/status registers 0 and 1 (cmcsr0, cmcsr1) 475 12.2.3 compare match counters 0 and 1 (cmcnt0, cmcnt1).................................. 476 12.2.4 compare match constant registers 0 and 1 (cmcor0, cmcor1).................. 477 12.3 operation .................................................................................................................. ........ 478 12.3.1 cyclic count operation ....................................................................................... 478 12.3.2 cmcnt count timing........................................................................................ 479 12.4 interrupts ................................................................................................................. .......... 480 12.4.1 interrupt sources.................................................................................................. 480 12.4.2 timing of compare match flag setting .............................................................. 480 12.4.3 timing of compare match flag clearing............................................................ 481 12.5 usage notes ................................................................................................................ ...... 481 section 13 watchdog timer ............................................................................................. 485 13.1 overview................................................................................................................... ........ 485 13.1.1 features................................................................................................................ 4 85 13.1.2 block diagram..................................................................................................... 486 13.1.3 pin configuration................................................................................................. 487 13.1.4 register configuration......................................................................................... 487 13.2 register descriptions ...................................................................................................... .. 488 13.2.1 timer counter (tcnt)........................................................................................ 488 13.2.2 timer control/status register (tcsr)................................................................ 488 13.2.3 reset control/status register (rstcsr) ............................................................ 490 13.2.4 notes on register access..................................................................................... 491 13.3 operation .................................................................................................................. ........ 493 13.3.1 operation in watchdog timer mode ................................................................... 493 13.3.2 operation in interval timer mode ....................................................................... 495 13.3.3 operation when clearing software standby mode............................................. 495 section 14 serial communication interface (sci) .................................................... 497 14.1 overview................................................................................................................... ........ 497 14.1.1 features................................................................................................................ 4 97 14.1.2 block diagrams ................................................................................................... 499 14.1.3 pin configuration................................................................................................. 500 14.1.4 register configuration......................................................................................... 500 14.2 register descriptions ...................................................................................................... .. 502 14.2.1 receive shift register (scrsr).......................................................................... 502 14.2.2 receive fifo data register (scfrdr) ............................................................. 502 14.2.3 transmit shift register (sctsr) ........................................................................ 503 14.2.4 transmit fifo data register (scftdr) ............................................................ 503 14.2.5 serial mode register (scsmr)........................................................................... 504 14.2.6 serial control register (scscr)......................................................................... 507 rev. 1.0, 08/99, page xi of 875 14.2.7 serial status 1 register (sc1ssr)....................................................................... 511 14.2.8 serial status 2 register (sc2ssr)....................................................................... 516 14.2.9 bit rate register (scbrr).................................................................................. 519 14.2.10 fifo control register (scfcr) ......................................................................... 528 14.2.11 fifo data count register (scfdr) ................................................................... 530 14.2.12 fifo error register (scfer) ............................................................................. 531 14.2.13 irda mode register (scimr) ............................................................................ 532 14.3 operation .................................................................................................................. ........ 533 14.3.1 overview.............................................................................................................. 533 14.3.2 operation in asynchronous mode ....................................................................... 536 14.3.3 multiprocessor communication function............................................................ 547 14.3.4 operation in synchronous mode ......................................................................... 555 14.3.5 use of transmit/receive fifo buffers ............................................................... 565 14.3.6 operation in irda mode...................................................................................... 568 14.4 sci interrupt sources and the dmac .............................................................................. 571 14.5 usage notes ................................................................................................................ ...... 572 section 15 a/d converter ................................................................................................. 577 15.1 overview................................................................................................................... ........ 577 15.1.1 features................................................................................................................ 5 77 15.1.2 block diagram..................................................................................................... 577 15.1.3 pin configuration................................................................................................. 579 15.1.4 register configuration......................................................................................... 580 15.2 register descriptions ...................................................................................................... .. 581 15.2.1 a/d data registers a to d (addra0 to addrd0, addra1 to addrd1) .. 581 15.2.2 a/d control/status registers (adcsr0, adcsr1)........................................... 582 15.2.3 a/d control registers (adcr0, adcr1) .......................................................... 584 15.3 cpu interface.............................................................................................................. ...... 585 15.4 operation .................................................................................................................. ........ 587 15.4.1 single mode (multi = 0) .................................................................................. 587 15.4.2 multi mode .......................................................................................................... 589 15.4.3 input sampling and a/d conversion time ......................................................... 591 15.4.4 external trigger input timing............................................................................. 592 15.5 interrupt sources and dma transfer requests ................................................................ 593 15.6 a/d conversion accuracy definitions ............................................................................. 593 15.7 usage notes ................................................................................................................ ...... 594 15.7.1 analog voltage settings ...................................................................................... 594 15.7.2 handling of analog input pins ............................................................................ 595 15.7.3 note on ph0 and ph1 output.............................................................................. 596 15.7.4 port i pfc settings............................................................................................... 596 section 16 d/a converter ................................................................................................. 597 16.1 overview................................................................................................................... ........ 597 rev. 1.0, 08/99, page xii of 875 16.1.1 features................................................................................................................ 5 97 16.1.2 block diagram..................................................................................................... 597 16.1.3 pin configuration................................................................................................. 598 16.1.4 register configuration......................................................................................... 598 16.2 register descriptions ...................................................................................................... .. 599 16.2.1 d/a data registers 0 and 1 (dadr0, dadr1) ................................................. 599 16.2.2 d/a control register (dacr) ............................................................................ 599 16.3 operation .................................................................................................................. ........ 601 16.4 usage note................................................................................................................. ....... 602 section 17 pin function controller (pfc) ................................................................... 603 17.1 overview................................................................................................................... ........ 603 17.2 register configuration..................................................................................................... . 617 17.3 register descriptions ...................................................................................................... .. 618 17.3.1 port a io register h (paiorh) ......................................................................... 618 17.3.2 port a io register l (paiorl) .......................................................................... 619 17.3.3 port a control registers h1 and h2 (pacrh1, pacrh2) ............................... 619 17.3.4 port a control registers l1 and l2 (pacrl1, pacrl2) ................................. 623 17.3.5 port b io register h (pbiorh).......................................................................... 626 17.3.6 port b io register l (pbiorl)........................................................................... 627 17.3.7 port b control register h2 (pbcrh2) ............................................................... 627 17.3.8 port b control registers l1 and l2 (pbcrl1, pbcrl2).................................. 630 17.3.9 port c io register h (pciorh).......................................................................... 632 17.3.10 port c io register l (pciorl)........................................................................... 632 17.3.11 port c control registers h1 and h2 (pccrh1, pccrh2) ................................ 633 17.3.12 port c control registers l1 and l2 (pccrl1, pccrl2).................................. 637 17.3.13 port d io register h (pdiorh) ......................................................................... 642 17.3.14 port d io register l (pdiorl) .......................................................................... 643 17.3.15 port d control registers h1 and h2 (pdcrh1, pdcrh2) ............................... 644 17.3.16 port d control registers l1 and l2 (pdcrl1, pdcrl2) ................................. 650 17.3.17 port e io register h (peiorh) .......................................................................... 656 17.3.18 port e io register l (peiorl)........................................................................... 656 17.3.19 port e control register h2 (pecrh2)................................................................ 657 17.3.20 port e control register l (pecrl)..................................................................... 660 17.3.21 port f io register l (pfiorl) ........................................................................... 661 17.3.22 port f control register l2 (pfcrl2) ................................................................. 662 17.3.23 port g io register (pgior)................................................................................ 664 17.3.24 port g control register h1 (pgcrh1)............................................................... 665 17.3.25 port h io register (phior)................................................................................ 666 17.3.26 port h control register (phcr).......................................................................... 667 17.3.27 function control register (fcr)......................................................................... 668 rev. 1.0, 08/99, page xiii of 875 section 18 i/o ports (i/o) ................................................................................................. 669 18.1 overview................................................................................................................... ........ 669 18.2 port a..................................................................................................................... ........... 669 18.2.1 register configuration......................................................................................... 670 18.2.2 port a data register h (padrh) ....................................................................... 671 18.2.3 port a data register l (padrl) ........................................................................ 672 18.3 port b ..................................................................................................................... ........... 673 18.3.1 register configuration......................................................................................... 674 18.3.2 port b data register h (pbdrh)........................................................................ 674 18.3.3 port b data register l (pbdrl)......................................................................... 675 18.4 port c ..................................................................................................................... ........... 676 18.4.1 register configuration......................................................................................... 678 18.4.2 port c data register h (pcdrh)........................................................................ 678 18.4.3 port c data register l (pcdrl)......................................................................... 679 18.5 port d..................................................................................................................... ........... 680 18.5.1 register configuration......................................................................................... 682 18.5.2 port d data register h (pddrh) ....................................................................... 682 18.5.3 port d data register l (pddrl) ........................................................................ 683 18.6 port e ..................................................................................................................... ........... 684 18.6.1 register configuration......................................................................................... 685 18.6.2 port e data register h (pedrh) ........................................................................ 685 18.6.3 port e data register l (pedrl) ......................................................................... 686 18.7 port f..................................................................................................................... ............ 687 18.7.1 register configuration......................................................................................... 687 18.7.2 port f data register l (pfdrl) ......................................................................... 688 18.8 port g..................................................................................................................... ........... 689 18.8.1 register configuration......................................................................................... 689 18.8.2 port g data register h (pgdrh) ....................................................................... 689 18.9 port h..................................................................................................................... ........... 691 18.9.1 register configuration......................................................................................... 691 18.9.2 port h data register (phdr).............................................................................. 691 18.10 port i .................................................................................................................... ............. 693 18.10.1 register configuration......................................................................................... 693 18.10.2 port i data register (pidr) ................................................................................. 694 section 19 256 kb flash memory (f-ztat) ............................................................. 695 19.1 features ................................................................................................................... .......... 695 19.2 overview................................................................................................................... ........ 696 19.2.1 block diagram..................................................................................................... 696 19.2.2 mode transitions ................................................................................................. 697 19.2.3 on-board programming modes........................................................................... 698 19.2.4 flash memory emulation in ram ...................................................................... 700 rev. 1.0, 08/99, page xiv of 875 19.2.5 differences between boot mode and user program mode ................................. 701 19.2.6 block configuration ............................................................................................ 702 19.3 pin configuration.......................................................................................................... .... 703 19.4 register configuration..................................................................................................... . 704 19.5 register descriptions ...................................................................................................... .. 705 19.5.1 flash memory control register 1 (flmcr1)..................................................... 705 19.5.2 flash memory control register 2 (flmcr2)..................................................... 708 19.5.3 erase block register 1 (ebr1) ........................................................................... 709 19.5.4 erase block register 2 (ebr2) ........................................................................... 709 19.5.5 ram emulation register (ramer)................................................................... 710 19.6 on-board programming modes........................................................................................ 712 19.6.1 boot mode ........................................................................................................... 712 19.6.2 user program mode............................................................................................. 717 19.7 programming/erasing flash memory ............................................................................... 718 19.7.1 program mode ..................................................................................................... 718 19.7.2 program-verify mode.......................................................................................... 719 19.7.3 erase mode (n = 1 for addresses h'00000 to h'07fff, n = 2 for addresses h'08000 to h'3ffff)........................................................... 727 19.7.4 erase-verify mode (n = 1 for addresses h'00000 to h'07fff, n = 2 for addresses h'08000 to h'3ffff)........................................................... 728 19.8 protection ................................................................................................................. ......... 734 19.8.1 hardware protection ............................................................................................ 734 19.8.2 software protection.............................................................................................. 735 19.8.3 error protection.................................................................................................... 735 19.9 flash memory emulation in ram ................................................................................... 737 19.10 note on flash memory programming/erasing ................................................................. 739 19.11 flash memory programmer mode .................................................................................... 739 19.11.1 socket adapter pin correspondence diagram..................................................... 740 19.11.2 operation in programmer mode .......................................................................... 742 19.11.3 memory read mode ............................................................................................ 743 19.11.4 auto-program mode ............................................................................................ 746 19.11.5 auto-erase mode................................................................................................. 748 19.11.6 status read mode ................................................................................................ 750 19.11.7 status polling ....................................................................................................... 751 19.11.8 programmer mode transition time .................................................................... 751 19.11.9 cautions concerning memory programming ...................................................... 752 19.12 usage notes ............................................................................................................... ....... 753 19.13 cautions on transition from f-ztat to mask rom version ......................................... 753 section 20 256 kb mask rom ....................................................................................... 755 20.1 overview................................................................................................................... ........ 755 section 21 xram and yram ....................................................................................... 757 rev. 1.0, 08/99, page xv of 875 21.1 overview................................................................................................................... ........ 757 21.2 operation .................................................................................................................. ........ 758 section 22 electrical characteristics .............................................................................. 759 22.1 absolute maximum ratings ............................................................................................. 759 22.2 electrical characteristics................................................................................................. .. 760 22.2.1 dc characteristics (1).......................................................................................... 760 22.2.2 dc characteristics (2).......................................................................................... 762 22.3 ac characteristics ......................................................................................................... ... 763 22.3.1 clock timing ....................................................................................................... 764 22.3.2 control signal timing ......................................................................................... 766 22.3.3 bus timing .......................................................................................................... 768 22.3.4 direct memory access controller timing .......................................................... 783 22.3.5 16-bit timer pulse unit (tpu) timing ............................................................... 786 22.3.6 motor management timer (mmt) timing ......................................................... 787 22.3.7 output enable (poe) timing .............................................................................. 788 22.3.8 i/o port timing.................................................................................................... 789 22.3.9 watchdog timer timing...................................................................................... 790 22.3.10 serial communication interface timing.............................................................. 791 22.3.11 a/d converter timing......................................................................................... 792 22.3.12 a/d converter characteristics ............................................................................. 794 22.3.13 d/a converter characteristics ............................................................................. 794 appendix a on-chip peripheral module registers .................................................. 795 appendix b pin states ....................................................................................................... 815 b.1 pin states in reset, power-down state, and bus-released state ..................................... 815 b.2 bus-related signal pin states........................................................................................... 818 appendix c i/o port block diagrams ........................................................................... 826 appendix d package dimensions .................................................................................. 874 appendix e product lineup ............................................................................................. 875 rev. 1.0, 08/99, page 1 of 875 section 1 overview 1.1 features of sh7065 the sh7065 is a cmos single-chip microcomputer featuring an sh-dsp corea functionally enhanced version of the superh risc engine using an original hitachi architecturewith the same signal processing capability as a general-purpose digital signal processor (dsp), together with peripheral functions required for system configuration. the sh-dsp core offers enhancement of the dsp functions (multiply and multiply-and- accumulate) of the superh risc engine, and provides full dsp type data bus functionality, enabling efficient execution of various kinds of signal processing and image processing. with this cpu, it has become possible to create low-cost, high-performance/high-functionality systems even for applications such as realtime control, which could not previously be handled by microcomputers because of their high-speed processing requirements. in addition, the sh7065 includes on-chip peripheral functions necessary for system configuration, such as large-capacity rom and ram, timers, a serial communication interface (sci), a/d converter, d/a converter, interrupt controller (intc), and i/o ports. an external memory access support function allows efficient connection of memory and peripheral lsis, greatly reducing system cost. there are two versions of the sh7065, with different kinds of on-chip rom: an f-ztat version with on-chip flash memory, and a mask rom version. in the f-ztat version, programs can be written and rewritten with a hitachi-recommended rom programmer, or on-board. rev. 1.0, 08/99, page 2 of 875 table 1.1 features item specifications cpu original hitachi architecture 32-bit internal configuration general register machine ? sixteen 32-bit general registers ? six 32-bit control registers (including three added for dsp use) ? ten 32-bit system registers (including six added for dsp use) risc (reduced instruction set computer) type instruction set ? fixed 16-bit instruction length for improved code efficiency ? load-store architecture (basic operations are executed between registers) ? delayed branch instructions reduce pipeline disruption during branches ? c-oriented instruction set instruction execution time: one instruction per cycle address space: architecture supports 4 gbytes enhanced on-chip multiplier: ? 16 16 ? 32 multiply operations executed in one to three cycles ? 32 32 ? 64 multiply operations executed in two to four cycles ? 32 32 + 64 ? 64 multiply-and-accumulate operations executed in two to four cycles five-stage pipeline rev. 1.0, 08/99, page 3 of 875 table 1.1 features (cont) item specifications dsp dsp engine ? multiplier ? arithmetic logic unit (alu) ? shifter ? dsp registers multiplier ? 16 bits 16 bits ? 32 bits ? single-cycle multiplier dsp registers ? two 40-bit data registers ? six 32-bit data registers ? modulo register (mod, 32 bits) added to control registers ? repeat counter (rc) added to status register (sr) ? repeat start register (rs, 32 bits) and repeat end register (re, 32 bits) added to control registers dsp data bus ? extended harvard architecture ? simultaneous access to two data buses and one instruction bus parallel processing ? maximum of four parallel processes ? alu operations, multiplication, and two loads or stores address processors ? two address processors ? address operations to access two memories dsp data addressing modes ? increment and index ? each with or without modulo addressing repeat control: zero-overhead repeat (loop) control instruction set ? 16-bit length (in case of load or store only) ? 32-bit length (including alu operations and multiplication) ? added system control instructions for accessing dsp registers fifth and last pipeline stage is dsp stage rev. 1.0, 08/99, page 4 of 875 table 1.1 features (cont) item specifications interrupt controller (intc) nine external interrupt pins (nmi, irq0 to irq7 ) 15 external interrupt sources (encoded input) can also be selected for pins irq0 to irq3 16 programmable priority levels nmi noise canceler function interrupt acceptance can be reported externally ( irqou t pin) user break controller (ubc) requests an interrupt when the cpu or dmac generates a bus cycle with specific set conditions simplifies configuration of an on-chip debugger bus state controller (bsc) supports external expansion memory access ? 32-bit external data bus address space divided into six areas (four areas in sram space, two areas in dram space), with the following parameters settable for each area: ? bus size (8/16/32 bits) ? number of wait cycles ? sram, dram, and edo dram easily connectable by space type setting ? output of ras and cas signals for dram and edo dram ? addressing multiplexing supported internally, allowing direct connection of dram and edo dram dram and edo dram burst access functions ? dram and edo dram fast access mode supported dram and edo dram refresh functions ? programmable refresh interval ? cas-before-ras refreshing and self-refreshing supported ? up to eight consecutive cas-before-ras refreshes possible wait cycles can be inserted using an external wait signal can access i/o devices that use address/data multiplexing big-endian or little-endian mode can be set independently for each area rev. 1.0, 08/99, page 5 of 875 table 1.1 features (cont) item specifications direct memory access controller (dmac) (4 channels) dma transfer possible for the following devices: ? external memory, external i/o, on-chip supporting modules (excluding dmac, bsc, ubc) dma transfer requests by external pins (for two channels) and on-chip peripheral modules, plus auto-request cycle steal or burst transfer relative channel priorities can be set selection of dual or single address mode transfer chain mode transfer possible transfer data width: 8/16/32 bits 4-gbyte address space, maximum 4g (4,294,967,296) transfers tend output can be asserted for each channel at the end of dma transfer timer pulse unit (tpu) (6 channels) maximum 16 kinds of waveform output or maximum 16 kinds of input/output processing based on six 16-bit timer channels 16 dual-function output compare registers/input capture registers total of 16 independent comparators selection of eight counter input clocks input capture function pulse output modes ? one-shot, toggle, pwm phase counting mode ? two-phase encoder count processing capability motor management timer (mmt) (1 channel) non-overlap waveform output for 6-phase inverter control dead times generated by dead time counters any pwm duty from 0% to 100% can be set toggle output possible in synchronization with pwm cycle data transfer can be performed by dmac activation a/d converter conversion start trigger can be generated output-off functions rev. 1.0, 08/99, page 6 of 875 table 1.1 features (cont) item specifications compare-match timer (cmt) (2 channels) 16-bit free-running counter one compare register interrupt request generated by compare-match watchdog timer (wdt) (1 channel) can be switched between watchdog timer and interval timer function internal reset, external signal, or interrupt generated by count overflow serial communication interface (sci) (3 channels) for each channel: selection of asynchronous or synchronous mode simultaneous transmission/reception (full-duplex) capability built-in dedicated baud rate generator multiprocessor communication function separate 16-stage fifo registers for transmission and reception, enabling continuous high-speed communication selection of msb-first or lsb-first transfer selection of base clock of 4/8/16 times the bit rate in asynchronous mode built-in irda interface (conforming to irda 1.0) i/o ports total of 118 port pins: 110 input/output, 8 input input/output voltage level for some ports can be set by i/o circuit power supply pv cc a/d converter 10 bits 4 channels 2 modules conversion can be activated by external trigger d/a converter 8 bits 2 channels on-chip memory rom: 256 kbytes x-ram: 4 kbytes y-ram: 4 kbytes rev. 1.0, 08/99, page 7 of 875 table 1.1 features (cont) item specifications operating modes operating modes ? expanded romless mode ? expanded rom mode ? single-chip mode processing states ? program execution state ? exception handling state ? bus-released state power-down modes ? sleep mode ? hardware standby mode ? software standby mode ? module standby function ? module clock division function clock pulse generator (cpg) built-in clock pulse generator selection of crystal or external clock as clock source built-in clock-multiplication pll circuits built-in pll circuit for phase synchronization between external clock and internal clock internal clock and on-chip peripheral module clock frequencies can be scaled independently package 176-pin plastic lqfp (lqfp2424-176), 0.5 mm pitch product lineup sh7065: 256 kb flash (under development)/mask (under development) operating frequency: 60 mhz (max.) rev. 1.0, 08/99, page 8 of 875 1.2 block diagram buffer rom cpu dsp y-ram user break controller interrupt controller bus state controller clock pulse generator serial communication interface motor management timer timer pulse unit compare-match timer a/d converter d/a converter watchdog timer i/o ports external bus interface internal address bus (cab) 32-bit internal data bus (idb) internal y address bus 16-bit internal y data bus internal x address bus 64-bit internal rom bus 16-bit internal x data bus peripheral address bus 16-bit peripheral data bus x-ram operating mode controller direct memory access controller 32-bit internal data bus (cdb) internal address bus (iab) figure 1.1 block diagram rev. 1.0, 08/99, page 9 of 875 1.3 pin arrangement and pin functions 1.3.1 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 pv ss pe14/irq6 pe13/irq5 pe12/irq4 pv cc pc0/a0 pc1/a1 pc2/a2 pc3/a3 v ss pc4/a4 pc5/a5 v ss pc6/a6 pc7/a7 pc8/a8 v cc pc9/a9 pc10/a10 pc11/a11 v ss pc12/a12 pc13/a13 pc14/a14/tioc3c v ss v cc pc15/a15/tioc3d pc16/a16/tioc3a pc17/a17/tioc3b pc18/a18/tioc4a v ss pc19/a19/tioc4b pc20/a20/tioc5a pc21/a21/tioc5b pc22/a22/tioc1a/tclka pc23/a23/tioc1b/tclkb pc24/a24/tioc3a/tclkc v ss v cc pc25/a25/tioc3b/tclkd pa25/cs5 pa24/cs4 pa23/cs3 pa22/cs2 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pllv ss pllcap2 pllcap1 pllv cc v ss ckio v cc hstby v ss res nmi md5 fwe * md4 v cc md3 md2 md1 extal v ss xtal md0 v ss pd0/d0 pd1/d1 pd2/d2 pd3/d3 v cc pd4/d4 pd5/d5 pd6/d6 v ss pd7/d7 pd8/d8/tioc1a pd9/d9/tioc1b pd10/d10/tioc2a pd11/d11/tioc2b pd12/d12/tioc4a pd13/d13/tioc4b pd14/d14/tioc5a v cc pd15/d15/tioc5b pd16/d16/poe0 v ss 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 fp-176 (top view) v ss ck v ss pa1/oe1 pa0/oe0 pf3/dreq0/tioc0a pf2/drak0/tioc0c v cc pf1/dack0/tioc0b pa19/bs pf5/dack1/rxd1/tioc2b pf6/drak1/txd1/tioc2a pf7/dreq1/irqout/tioc0d wdtovf v ss av ss ph0/da0 ph1/da1 pi0/an0 pi1/an1 pi2/an2 pi3/an3 pi4/an4 pi5/an5 pi6/an6 pi7/an7 av cc pv cc pg31/rxd2 pg30/txd2 pg29/sck2 pb7/back pb6/breq pv ss pe23/irq7/pwob pe22/irq6/pvob pe21/irq5/puob pe20/irq4/pco/pci pe19/irq3/pwoa pe18/irq2/pvoa pv cc pe17/irq1/puoa/sck0 pe16/irq0/sck1/ah pe15/irq7 v ss pd17/d17/poe1/adtrg pd18/d18/poe2/irq4 pd19/d19/poe3/irq5 pd20/d20/puoa/irq6 pd21/d21/pvoa/irq7 pd22/d22/pwoa/sck0 pd23/d23/pco/pci/sck1 pd24/d24/puob v cc pd25/d25/pvob pd26/d26/pwob v ss pd27/d27/tclka/tioc3c pd28/d28/tclkb/tioc3d pd29/d29/sck2/tioc4a pd30/d30/txd2/tioc4b pd31/d31/rxd2/tioc5a v cc pb13/rdwr pb16/casll0 pb17/caslh0 pb18/cashl0/rxd0 pb19/cashh0/txd0 v ss pb20/casll1 pb21/caslh1 pb22/cashl1/rxd1/tend1 pb23/cashh1/txd1/tend0 pa8/ras0 v cc pa9/ras1 pa12/wait pa13/wrll/llbs v ss pa14/wrlh/lhbs pa15/wrhl/hlbs/tclkd/tioc3b pa16/wrhh/hhbs/tclkc/tioc3a pa17/wr pa18/rd v cc pa20/cs0 pa21/cs1 v ss note: * vss in the mask version (can be pulled down with a resistance of 5.0 k w to 10 k w ) figure 1.2 pin arrangement rev. 1.0, 08/99, page 10 of 875 1.3.2 pin functions table 1.2 summarizes the pin functions. table 1.2 pin functions type symbol i/o name function power supply vcc input power supply for connection to the power supply. connect all v cc pins to the system power supply. the chip will not operate if there are any open pins. apply the same voltage to all v cc pins. * vss input ground for connection to ground. connect all v ss pins to the system ground. the chip will not operate if there are any open pins. pvcc input i/o circuit power supply power supply for the i/o circuits. the chip will not operate if there are any open pins. apply the same voltage to all pv cc pins. * pvss input i/o circuit ground ground for the i/o circuits. the chip will not operate if there are any open pins. clock pllvcc input pll power supply on-chip pll oscillator power supply. the chip will not operate if there are any open pins. pllvss input pll ground on-chip pll oscillator ground. the chip will not operate if there are any open pins. pllcap1 input pll capacitance on-chip pll oscillator 1 external capacitance pin. pllcap2 input pll capacitance on-chip pll oscillator 2 external capacitance pin. extal input external clock for connection to a crystal resonator. an external clock can also be input to the extal pin. xtal output crystal for connection to a crystal resonator ckio i/o system clock i/o used as external clock input or internal clock output pin. ck output system clock output internal clock output pin. note: * apply v cc after pv cc has been applied and has stabilized. rev. 1.0, 08/99, page 11 of 875 table 1.2 pin functions (cont) type symbol i/o name function system control res input power-on reset executes a power-on reset when driven low. wdtovf output watchdog timer overflow wdt overflow output signal breq input bus request driven low when an external device requests release of the bus. back output bus request acknowledge indicates that the bus has been granted to an external device. the device that output the breq signal recognizes that the bus has been acquired when it receives the back signal. hstby input hardware standby hardware standby input pin. drive high when not used. operating mode control md0Cmd5 input mode setting these pins determine the operating mode. do not change the input values during operation. fwe input flash write enable on-chip flash memory program/erase hardware protection pin. interrupts nmi input nonmaskable interrupt nonmaskable interrupt request pin. acceptance at the rising edge or falling edge can be selected. irq0 C irq7 input interrupt request 0 to 7 maskable interrupt request pins. level input or edge input can be selected. irqout output interrupt request output indicates that an interrupt request has been generated. enables interrupt generation to be recognized in the bus- released state. address bus a0Ca25 output address bus address output pins. data bus d0Cd31 i/o data bus 32-bit bidirectional data bus. bus control cs0 C cs5 output chip select 0 to 5 chip select signals for external memory or devices. rd output read indicates reading from an external device. rdwr output read/write used as the dram write directive signal. wrll output ll write indicates writing of bits 7 to 0 of external data. wrlh output lh write indicates writing of bits 15 to 8 of external data. rev. 1.0, 08/99, page 12 of 875 table 1.2 pin functions (cont) type symbol i/o name function bus control wrhl output hl write indicates writing of bits 23 to 16 of external data. wrhh output hh write indicates writing of bits 31 to 24 of external data. wait input wait input for wait cycle insertion in bus cycles during external space access llbs output ll byte strobe indicates access to bits 7 to 0 of external data. lhbs output lh byte strobe indicates access to bits 15 to 8 of external data. hlbs output hl byte strobe indicates access to bits 23 to 16 of external data. hhbs output hh byte strobe indicates access to bits 31 to 24 of external data. wr output write indicates the data bus input/output direction. also used as the write directive for byte-strobe type memory. ras0 C ras1 output row address strobe 0, 1 dram row address strobe timing signals casll0 C casll1 output ll column address strobe 0, 1 output when accessing bits 7 to 0 of dram data. caslh0 C caslh1 output lh column address strobe 0, 1 output when accessing bits 15 to 8 of dram data. cashl0 C cashl1 output hl column address strobe 0, 1 output when accessing bits 23 to 16 of dram data. cashh0 C cashh1 output hh column address strobe 0, 1 output when accessing bits 31 to 24 of dram data. oe0 C oe1 output output enable 0, 1 output enable signal for use of edo dram in ras down mode. ah output address hold address hold timing signal for a device using a multiplexed address/data bus. bs output bus cycle start indicates the start of a bus cycle. rev. 1.0, 08/99, page 13 of 875 table 1.2 pin functions (cont) type symbol i/o name function direct memory access controller (dmac) dreq0 C dreq1 input dma transfer request (channels 0, 1) input pins for external requests for dma transfer. drak0 C drak1 output dreq request acknowledg- ment (channels 0, 1) these pins output the input sampling acknowledgment for external requests for dma transfer. dack0 C dack1 output dma transfer strobe (channels 0, 1) these pins output a strobe to the external i/o in external dma transfer requests. tend0 C tend1 output dma transfer end (channels 0, 1) these pins go low at the end of dma transfer. timer pulse unit (tpu) tclkaC tclkd input tpu timer clock input tpu counter external clock input pins. tioc0aC tioc0d i/o tpu input capture/output compare (channel 0) channel 0 input capture input/output compare output/pwm output pins. tioc1aC tioc1b i/o tpu input capture/output compare (channel 1) channel 1 input capture input/output compare output/pwm output pins. tioc2aC tioc2b i/o tpu input capture/output compare (channel 2) channel 2 input capture input/output compare output/pwm output pins. tioc3aC tioc3d i/o tpu input capture/output compare (channel 3) channel 3 input capture input/output compare output/pwm output pins. tioc4aC tioc4b i/o tpu input capture/output compare (channel 4) channel 4 input capture input/output compare output/pwm output pins. tioc5aC tioc5b i/o tpu input capture/output compare (channel 5) channel 5 input capture input/output compare output/pwm output pins. rev. 1.0, 08/99, page 14 of 875 table 1.2 pin functions (cont) type symbol i/o name function pci input counter clear input counter clear input pin. pco output pwm cycle output pin for toggle output synchronized with pwm cycle. puoaC puob output pwm u-phase output pwm u-phase waveform output pin. pvoaC pvob output pwm v-phase output pwm v-phase waveform output pin. pwoaC pwob output pwm w-phase output pwm w-phase waveform output pin. motor management timer (mmt) poe0 C poe3 input port output enable input these pins input request signals to place large-current pins in the high-impedance state. txd0C txd2 output transmit data (channels 0 to 2) transmit data output pins. rxd0C rxd2 input receive data (channels 0 to 2) receive data input pins. serial communication interface (sci) sck0C sck2 i/o serial clock (channels 0 to 2) clock input/output pins. avcc input analog power supply for connection to analog power supply. analog power supply avss input analog ground for connection to analog power supply ground. an0Can7 input analog input analog signal input pins a/d converter adtrg input a/d conversion trigger input external input for starting a/d conversion d/a converter da0Cda1 output analog output d/a converter analog signal output pins rev. 1.0, 08/99, page 15 of 875 table 1.2 pin functions (cont) type symbol i/o name function i/o ports pa 18 i/o general port general input/output port pins. input or output can be specified bit by bit. pb 11 i/o general port general input/output port pins. input or output can be specified bit by bit. pc 26 i/o general port general input/output port pins. input or output can be specified bit by bit. pd 32 i/o general port general input/output port pins. input or output can be specified bit by bit. pe 12 i/o general port general input/output port pins. input or output can be specified bit by bit. pf 6 i/o general port general input/output port pins. input or output can be specified bit by bit. pg 3 i/o general port general input/output port pins. input or output can be specified bit by bit. ph 2 i/o general port general input/output port pins. input or output can be specified bit by bit. pi 8 input general port general input port pins. note: unused input pins must be pulled up or pulled down with a resistance of 4.7 k w to 10 k w . rev. 1.0, 08/99, page 16 of 875 table 1.3 pin function list no. * control power supply function 1 function 2 function 3 function 4 function 5 1 pllvcc 2 plvss 3 pllcap1 4 pllcap2 5 avcc 6 avss 7 vcc extal 8 vcc xtal 9vccckio 10vccck 11 vcc res 12 vcc wdtovf 13 vcc hstby 14vccmd5 15vccmd4 16vccmd3 17vccmd2 18vccmd1 19vccmd0 20vccnmi 21vccfwe 22 vcc general input/output (pa25) cs5 23 vcc general input/output (pa24) cs4 24 vcc general input/output (pa23) cs3 25 vcc general input/output (pa22) cs2 26 vcc general input/output (pa21) cs1 27 vcc general input/output (pa20) cs0 28 vcc general input/output (pa19) bs 29 vcc general input/output (pa18) rd 30 vcc general input/output (pa17) wr note: * these numbers are not the package pin numbers. rev. 1.0, 08/99, page 17 of 875 table 1.3 pin function list (cont) no. * control power supply function 1 function 2 function 3 function 4 function 5 31 vcc general input/output (pa16) wrhh hhbs tclkc tioc3a 32 vcc general input/output (pa15) wrhl hlbs tclkd tioc3b 33 vcc general input/output (pa14) wrlh lhbs 34 vcc general input/output (pa13) wrll llbs 35 vcc general input/output (pa12) wait 36 vcc general input/output (pa9) ras1 37 vcc general input/output (pa8) ras0 38 vcc general input/output (pb23) cashh1 txd1 tend0 39 vcc general input/output (pb22) cashl1 rxd1 tend1 40 vcc general input/output (pb21) caslh1 41 vcc general input/output (pb20) casll1 42 vcc general input/output (pb19) cashh0 txd0 43 vcc general input/output (pb18) cashl0 rxd0 44 vcc general input/output (pb17) caslh0 45 vcc general input/output (pb16) casll0 46 vcc general input/output (pb13) rdwr 47 vcc general input/output (pc25) a25 tioc3b tclkd 48 vcc general input/output (pc24) a24 tioc3a tclkc 49 vcc general input/output (pc23) a23 tioc1b tclkb 50 vcc general input/output (pc22) a22 tioc1a tclka 51 vcc general input/output (pc21) a21 tioc5b 52 vcc general input/output (pc20) a20 tioc5a 53 vcc general input/output (pc19) a19 tioc4b 54 vcc general input/output (pc18) a18 tioc4a 55 vcc general input/output (pc17) a17 tioc3b 56 vcc general input/output (pc16) a16 tioc3a 57 vcc general input/output (pc15) a15 tioc3d 58 vcc general input/output (pc14) a14 tioc3c 59 vcc general input/output (pc13) a13 60 vcc general input/output (pc12) a12 note: * these numbers are not the package pin numbers. rev. 1.0, 08/99, page 18 of 875 table 1.3 pin function list (cont) no. * control power supply function 1 function 2 function 3 function 4 function 5 61 vcc general input/output (pc11) a11 62 vcc general input/output (pc10) a10 63 vcc general input/output (pc9) a9 64 vcc general input/output (pc8) a8 65 vcc general input/output (pc7) a7 66 vcc general input/output (pc6) a6 67 vcc general input/output (pc5) a5 68 vcc general input/output (pc4) a4 69 vcc general input/output (pc3) a3 70 vcc general input/output (pc2) a2 71 vcc general input/output (pc1) a1 72 vcc general input/output (pc0) a0 73 vcc general input/output (pd31) d31 rxd2 tioc5a 74 vcc general input/output (pd30) d30 txd2 tioc4b 75 vcc general input/output (pd29) d29 sck2 tioc4a 76 vcc general input/output (pd28) d28 tclkb tioc3d 77 vcc general input/output (pd27) d27 tclka tioc3c 78 vcc general input/output (pd26) d26 pwob 79 vcc general input/output (pd25) d25 pvob 80 vcc general input/output (pd24) d24 puob 81 vcc general input/output (pd23) d23 pco pci sck1 82 vcc general input/output (pd22) d22 pwoa sck0 83 vcc general input/output (pd21) d21 pvoa irq7 84 vcc general input/output (pd20) d20 puoa irq6 85 vcc general input/output (pd19) d19 poe3 irq5 86 vcc general input/output (pd18) d18 poe2 irq4 87 vcc general input/output (pd17) d17 poe1 adtrg 88 vcc general input/output (pd16) d16 poe0 89 vcc general input/output (pd15) d15 tioc5b 90 vcc general input/output (pd14) d14 tioc5a note: * these numbers are not the package pin numbers. rev. 1.0, 08/99, page 19 of 875 table 1.3 pin function list (cont) no. * control power supply function 1 function 2 function 3 function 4 function 5 91 vcc general input/output (pd13) d13 tioc4b 92 vcc general input/output (pd12) d12 tioc4a 93 vcc general input/output (pd11) d11 tioc2b 94 vcc general input/output (pd10) d10 tioc2a 95 vcc general input/output (pd9) d9 tioc1b 96 vcc general input/output (pd8) d8 tioc1a 97 vcc general input/output (pd7) d7 98 vcc general input/output (pd6) d6 99 vcc general input/output (pd5) d5 100 vcc general input/output (pd4) d4 101 vcc general input/output (pd3) d3 102 vcc general input/output (pd2) d2 103 vcc general input/output (pd1) d1 104 vcc general input/output (pd0) d0 105 vcc general input/output (pa1) oe1 106 vcc general input/output (pa0) oe0 107 pvcc general input/output (pe23) irq7 pwob 108 pvcc general input/output (pe22) irq6 pvob 109 pvcc general input/output (pe21) irq5 puob 110 pvcc general input/output (pe20) irq4 pco pci 111 pvcc general input/output (pe19) irq3 pwoa 112 pvcc general input/output (pe18) irq2 pvoa 113 pvcc general input/output (pe17) irq1 puoa sck0 114 pvcc general input/output (pe16) irq0 sck1 ah 115 vcc general input/output (pf7) dreq1 irqout tioc0d 116 vcc general input/output (pf6) drak1 txd1 tioc2a 117 vcc general input/output (pf5) dack1 rxd1 tioc2b 118 avcc general input (pi7) an7 119 avcc general input (pi6) an6 120 avcc general input (pi5) an5 note: * these numbers are not the package pin numbers. rev. 1.0, 08/99, page 20 of 875 table 1.3 pin function list (cont) no. * control power supply function 1 function 2 function 3 function 4 function 5 121 avcc general input (pi4) an4 122 avcc general input (pi3) an3 123 avcc general input (pi2) an2 124 avcc general input (pi1) an1 125 avcc general input (pi0) an0 126 avcc general input/output (ph1) da1 127 avcc general input/output (ph0) da0 128 pvcc general input/output (pe12) irq4 129 pvcc general input/output (pe13) irq5 130 pvcc general input/output (pe14) irq6 131 pvcc general input/output (pe15) irq7 132 pvcc general input/output (pg31) rxd2 133 pvcc general input/output (pg30) txd2 134 pvcc general input/output (pg29) sck2 135 vcc general input/output (pf2) drak0 tioc0c 136 vcc general input/output (pf1) dack0 tioc0b 137 vcc general input/output (pf3) dreq0 tioc0a 138 pvcc general input/output (pb7) back 139 pvcc general input/output (pb6) breq note: * these numbers are not the package pin numbers. rev. 1.0, 08/99, page 21 of 875 section 2 cpu 2.1 register configuration the sh7065 has sixteen 32-bit general registers, six 32-bit control registers, and ten 32-bit system registers. as the sh7065 is upward-compatible with the sh-1 and sh-2 at the object code level, a number of registers have been added to those provided in previous superh microcomputers. the additions comprise three control registers (the repeat start register (rs), repeat end register (re), and modulo register (mod)), one system register (the dsp status register (dsr)), and six registers (a0, a1, x0, x1, y0, and y1) within the dsp data registers. with superh microcomputer type instructions, general registers are used in the same way as in the sh-1 and sh-2, but with dsp type instructions, general registers are used as address and index registers for accessing memory. 2.1.1 general registers there are sixteen 32-bit general registers (rn), designated r0 to r15. the general registers are used for data processing and address calculation. with superh microcomputer type instructions, r0 is used as an index register. with a number of instructions, r0 is the only register that can be used. r15 is used as the stack pointer (sp). in exception handling, r15 is used to reference the stack when saving and restoring the status register (sr) and program counter (pc). with dsp type instructions, eight of the sixteen general registers are used for addressing of x and y data memory and data memory (single data) that uses the i-bus. to access x memory, r4 and r5 are used as x address register [ax] and r8 is used as x index register [ix]. to access y memory, r6 and r7 are used as y address register [ay] and r9 is used as y index register [iy]. to access single data that uses the i-bus, r2, r3, r4, and r5 are used as single data address register [as] and r8 is used as single data index register [is]. dsp type instructions can access can access x and y data memory simultaneously. two sets of address pointers are provided to specify the x and y data memory addresses. the general registers are shown in figure 2.1. rev. 1.0, 08/99, page 22 of 875 r0 * 1 r1 r2, [as] * 3 r3, [as] * 3 r4, [as, ax] * 3 r5, [as, ax] * 3 r6, [ay] * 3 r7, [ay] * 3 r8, [ix, is] * 3 r9, [iy] * 3 r10 r11 r12 r13 r14 r15, sp * 2 0 31 notes: 1. the r0 register is used as the index register in indexed register indirect addressing mode and indexed gbr indirect addressing mode. with certain instructions, r0 only is used as the source register and destination register. 2. the r15 register is used as the stack pointer (sp) during exception handling. 3. used as the memory address register or memory index register with dsp type instructions. figure 2.1 general register configuration in assembler, the symbols r2, r3 ... r9 are used. if it is wished to use a name that indicates the role of a register for dsp type instructions, a different register name (alias) can be used. the coding in assembler is as follows. ix: .reg (r8) rev. 1.0, 08/99, page 23 of 875 the name ix is the alias for r8. other aliases are assigned as follows. ax0: .reg (r4) ax1: .reg (r5) ix: .reg (r8) ay0: .reg (r6) ay1: .reg (r7) iy: .reg (r9) as0: .reg (r4); definition when an alias is required for single data transfer. as1: .reg (r5); definition when an alias is required for single data transfer. as2: .reg (r2); definition when an alias is required for single data transfer. as3: .reg (r3); definition when an alias is required for single data transfer. is: .reg (r8); definition when an alias is required for single data transfer. 2.1.2 control registers there are six 32-bit control registers: the status register (sr), repeat start register (rs), repeat end register (rs), global base register (gbr), vector base register (vbr), and modulo register (mod). the sr register shows the processing status. the gbr register is used as the base address in gbr indirect addressing mode, and is used for data transfer involving on-chip peripheral module registers, etc. the vbr register is used as the base address of the exception handling vector area, including interrupts. the rs register and re register are used to control program repeats (loops). the number of loops is specified in the repeat counter (rc) in the sr register, the repeat start address is specified in the rs register, and the repeat end address is specified in the re register. however, the address values stored in the rs register and re register are not necessarily the same as the physical repeat start address and end address. the mod register is used in modulo addressing for repeat data buffering. the modulo addressing specification is made with the dmx or dmy bit in the sr register, the modulo end address (me) is specified in the upper 16 bits of the mod register, and the modulo start address (ms) in the lower 16 bits. the dmx and dmy bits cannot both specify modulo addressing simultaneously. modulo addressing can be used with the x and y data transfer instructions (movx, movy), but not with the single data transfer instruction (movs). figure 2.2 shows the control register, and table 2.1 shows the bits in the sr register. rev. 1.0, 08/99, page 24 of 875 st imask rf1 rf0 q m dmx dmy 0000 0000 rc 31 28 27 16 15 12 11 10 9 8 7 4 3 2 1 0 status register (sr) repeat start register (rs) repeat end register (re) global base register (gbr) vector base register (vbr) modulo register (mod) me: modulo end address ms: modulo start address 31 31 31 31 31 0 0 0 0 0 16 15 rs re gbr vbr me ms figure 2.2 control register configuration rev. 1.0, 08/99, page 25 of 875 table 2.1 sr register bits bits name (abbreviation) function 27C16 repeat counter (rc) these bits specify number of repeats in repeat (loop) control (2 to 4095). 11 y pointer modulo addressing specification (dmy) 1: modulo addressing mode is enabled for y memory address pointer ay (r6, r7). 10 x pointer modulo addressing specification (dmx) 1: modulo addressing mode is enabled for x memory address pointer ax (r4, r5). 9m bit 8q bit used by div0s/u and div1 instructions. 7C4 interrupt request mask (imask) these bits show the interrupt request acceptance level (0 to 15). 3, 2 repeat flags (rf1, rf0) used for zero-overhead repeat (loop) control. set as follows when the setrc instruction is used. 1-step repeat: 00 re C rs = C4 2-step repeat: 01 re C rs = C2 3-step repeat: 11 re C rs = 0 4 or more steps:10 re C rs > 0 1 saturation operation bit (s) used with mac and dsp instructions. 1: specifies a saturation operation (preventing overflow) 0 t bit with movt, cmp/cond, tas, tst, bt, bt/s, bf, bf/s, sett, clrt, and dt instructions: 0: indicates true 1: indicates false with addv/c, subv/c, div0u/s, div1, negc, shar/l, shlr/l, rotr/l. and rotcr/l instructions: 1: indicates occurrence of carry, borrow, overflow, or underflow 31C28, 15C12 0 bits 0: always read as 0. only 0 should be written to these bits. special load/store instructions are provided for accessing the rs, re, and mod registers. for example, the coding for accessing the rs register is as follows. ldc rm,rs; rm ? rs ldc.l @rm+,rs; (rm) ? rs, rm+4 ? rm stc rs,rn; rs ? rn stc.l rs,@-rn; rn-4 ? rn, rs ? (rn) rev. 1.0, 08/99, page 26 of 875 the instructions for setting an address in the rs and re registers for zero-overhead repeat control are as follows. ldrs @(disp,pc); disp 2 + pc ? rs ldre @(disp,pc); disp 2 + pc ? re the gbr and vbr registers are the same as the previous superh microcomputer registers. in the sh7065, four control bits (dmx, dmy, rf1, and rf0) and an rc counter have been added to the sr register, and the rs, re, and mod registers are provided as new registers. 2.1.3 system registers there are four 32-bit system registers: the multiply and accumulate register high (mach), multiply and accumulate register low (macl), procedure register (pr), and program counter (pc). mach and macl store the results of multiply or multiply and accumulate operations*, pr stores the return destination address of a subroutine procedure, and pc shows the executing program address and controls the processing flow. pc shows the address 4 bytes ahead of the currently executing instruction. these registers are the same as the superh microcomputer registers. macl pr pc mach 31 0 0 0 31 31 multiply and accumulate register high (mach) multiply and accumulate register low (macl) procedure register (pr) program counter (pc) figure 2.3 system register configuration note: * these registers are used only when executing an instruction supported by the sh-1 and sh-2. they are not used with the new multiply instruction provided in the sh-dsp (pmuls). rev. 1.0, 08/99, page 27 of 875 in the sh7065, of the dsp unit registers (dsp registers) described below, the dsp status register (dsr) and five of the eight data registers (a0, x0, x1, y0, and y1) are treated as system registers. a0 is a 40-bit register, but when data is output from the a0 register the guard bit field (a0g) is ignored, and when data is input to the a0 register the msb is copied into the guard bit field (a0g). 2.1.4 dsp registers the dsp unit has eight data registers and one control register as dsp registers. the dsp data registers comprise two 40-bit registers, a0 and a1, and six 32-bit registers, m0, m1, x0, x1, y0, and y1. registers a0 and a1 each have an 8-bit guard bit field, designated a0g and a1g, respectively. the dsp data registers are used as dsp instruction operands in dsp data transfer and processing. instructions that access the dsp data registers are of three types, for dsp data processing, and x and y data transfer processing. the control register is the 32-bit dsp status register (dsr), which shows operation results. the dsr register contains bits that indicate the result of an operationthe signed greater than bit (gt), zero value bit (z), negative value bit (n), overflow bit (v), and dsp condition bit (dc)and also condition select bits (cs) that control the dc bit setting. the dc bit is a status flag that closely resembles the t bit of the superh microcomputer cpu core. in the case of a conditional dsp type instruction, execution during dsp data processing is controlled in accordance with the dc bit. this control extends only to dsp unit execution, and only dsp registers are updated. it has no effect on address calculation or superh microcomputer cpu core execution instructions such as load/store instructions. the cs control bits (bits 2 to 0) specify the conditions for setting the dc bit. dsp type instructions include unconditional dsp type instructions and conditional dsp type instructions. in unconditional dsp type data processing, with the exception of the pmuls, movx, movy, and movs instructions, the status bits and dc bit are updated. conditional dsp type instructions are executed in accordance with the dc bit setting, but the dsr register is not updated regardless of whether or not these instructions are executed. the dsp registers are shown in figure 2.4, and the dsr register bit functions are summarized in table 2.2. rev. 1.0, 08/99, page 28 of 875 39 32 31 0 a0g a1g a0 a1 m0 m1 x0 x1 y0 y1 dsp data registers dsp status register (dsr) gt z n v cs[2:0] dc 876543210 31 figure 2.4 dsp register configuration rev. 1.0, 08/99, page 29 of 875 table 2.2 dsr register bits bits name (abbreviation) function 31C8 reserved 0: always read as 0. the write value should also be 0. 7 signed greater than (gt) indicates that the operation result is positive (except zero) or that operand 1 is greater than operand 2. 1: operation result is positive or operand 1 is greater than operand 2 6 zero value (z) indicates that the operation result is zero (0) or that operand 1 is equal to operand 2. 1: operation result is zero (0) or operands are equal 5 negative value (n) indicates that the operation result is negative or that operand 1 is smaller than operand 2. 1: operation result is negative or operand 1 is smaller than operand 2 4 overflow (v) indicates that the operation result has overflowed. 1: operation result has overflowed 3C1 condition select (cs) these bits specify the mode for selecting the operation result status to be set in the dc bit. do not set these bits to 110 or 111. 000: carry/borrow mode 001: negative value mode 010: zero mode 011: overflow mode 100: signed greater than mode 101: signed greater than or equal to mode 0 dsp condition (dc) sets the status of the operation result in the mode specified by the cs bits. 0: specified mode status has not occurred (false) 1: specified mode status has occurred rev. 1.0, 08/99, page 30 of 875 the dsr register is treated as a system register by cpu core instructions. the following load/store instructions are used for data transfer to and from the dsr register. sts dsr,rn; sts.l dsr,@-rn; lds rn,dsr; lds.l @rn+,dsr; the a0, x0, x1, y0, and y1 registers are also treated as system registers by cpu core instructions. the following load/store instructions are used for data transfer to and from these registers. sts dm,rn; sts.l dm,@-rn; lds rn,dm; lds.l @rn+,dm; (dm: a0, x0, x1, y0, or y1) 2.1.5 notes on guard bits and overflow treatment data operations in the dsp unit are basically 32-bit operations, but these operations are always executed with a 40-bit length including the 8-bit guard field. if the guard bit field does not match the value of the msb of the 32-bit field, the operation result is treated as overflow. in this case, the n bit shows the correct status of the operation result regardless of whether or not overflow has occurred. this also applies when the destination operand is a 32-bit register. the 8-bit guard bit field is always assumed to present, and each status flag is updated. if overflow occurs that prevents the result from being indicated correctly despite the use of the guard bits, the n flag will not be able to show the correct status. rev. 1.0, 08/99, page 31 of 875 2.1.6 initial register values register values after a reset are shown in table 2.3. table 2.3 initial register values type registers initial value r0Cr14 undefined general registers r15 (sp) sp value in vector address table sr i3 to i0 = 1111 (h'f); reserved bits, rc, dmy, and dmx cleared to 0; other bits undefined rs re undefined gbr undefined vbr h'0000 0000 control registers mod undefined mach, macl, pr undefined system registers pc pc value in vector address table a0, a0g, a1, a1g, m0, m1, x0, x1, y0, y1 undefined dsp registers dsr h'0000 0000 rev. 1.0, 08/99, page 32 of 875 2.2 data formats 2.2.1 register data formats the register operand data size is always longword (32 bits). when data in memory is loaded into a register, if the memory operand data size is byte (8 bits) or word (16 bits), it is sign-extended to longword length. 31 0 longword figure 2.5 register data format 2.2.2 memory data formats byte, word, and longword data formats can be used. byte data can be located at any address, while word data must start at address 2n and longword data at address 4n. if data is accessed other than at these boundaries, an address error will result, and the result of the access cannot be guaranteed. in particular, since the program counter (pc) and status register (sr) are stored in longword format in the stack area indicated by the stack pointer (sp: r15), the setting musty be made so that stack pointer value is 4n. 31 0 15 23 7 byte byte byte byte word word address 2n address 4n longword address m address m + 2 address m + 1 address m + 3 big-endian 31 0 15 23 7 byte byte byte byte word word address 2n address 4n longword address m + 3 address m + 1 address m + 2 address m little-endian figure 2.6 memory data format rev. 1.0, 08/99, page 33 of 875 2.2.3 immediate data formats byte immediate data is placed inside the instruction code. with the mov, add, and cmp/eq instructions, immediate data is sign-extended and a longword operation is performed with a register. with the tst, and, or, and xor instructions, on the other hand, a longword operation is performed after zero-extending the immediate data. therefore, when immediate data is used with an and instruction, the upper 24 bits of the destination register are always cleared. word and longword immediate data should be placed in a table in memory, not inside the instruction code. the table in memory should be referenced with an immediate data transfer instruction (mov) using pc relative addressing mode with displacement. 2.2.4 dsp type data formats the sh7065 has three different data formats for instructions: fixed-point data format, integer data format, and logical data format. in the dsp type fixed-point data format, there is a binary point between bit 31 and bit 30. there are three kinds of formatwith guard bits, without guard bits, and multiplication inputeach with a different valid bit length and range of expressable values. in the dsp type integer data format, there is a binary point between bit 16 and bit 15. there are three kinds of formatwith guard bits, without guard bits, and shift amounteach with a different valid bit length and range of expressable values. the shift amount for an arithmetic shift (psha) is a 7-bit area, and values from C64 to +63 can be expressed, but only values from C32 to +32 are actually valid. similarly, the shift amount for a logical shift (pshl) is a 6-bit area, but only values from C16 to +16 are actually valid. there is no radix point in the dsp type logical data format. the data format and valid data length are determined by the dsp register. the three dsp type data formats and the position of the binary point in each are shown in figure 2.7, together with a superh type data format for reference. rev. 1.0, 08/99, page 34 of 875 s s s s s s s s (16 bits) dsp type logical superh type integer (word) [for reference] dsp type integer dsp type fixed-point with guard bits without guard bits multiplication input with guard bits without guard bits arithmetic shift (psha) logical shift (pshl) 39 39 39 39 32 32 31 31 31 31 31 31 31 31 31 22 21 0 0 0 0 0 0 0 0 0 C2 8 to +2 8 C 2 C31 C1 to +1 C 2 C31 C1 to +1 C 2 C15 C2 23 to +2 23 C1 C2 15 to +2 15 C1 C32 to +32 C16 to +16 C2 31 to +2 31 C1 16 15 16 16 16 16 16 15 15 15 15 15 : sign bit : binary point : not related to processing (ignored) s 30 30 30 figure 2.7 dsp type data formats rev. 1.0, 08/99, page 35 of 875 2.2.5 dsp type instructions and data formats the data format and valid data length are determined by the dsp type instruction and dsp register. there are three types of instruction that access dsp data registers: dsp data processing instructions, x and y data transfer processing instructions, and single data transfer processing instructions. dsp data processing: when the a0 or a1 register is used as the source register in dsp fixed- point data processing, the guard bits (bits 39 to 32) are valid. when a register other than a0 or a1 (register m0, m1, x0, x1, y0, or y1) is used as the source register, the sign-extension of that register data is used as the data in bits 39 to 32. when the a0 or a1 register is used as the destination register, the guard bits (bits 39 to 32) are valid. when a register other than a0 or a1 is used as the destination register, bits 39 to 32 of the result data are ignored. in dsp integer data processing, the situation is the same as for dsp fixed-point data processing, except that the lower word (lower 16 bits: bits 15 to 0) of the source register is ignored, and the lower word of the destination register is cleared to 0. in dsp logical data processing, the upper word (upper 16 bits: bits 31 to 16) of the source register is valid. the lower word and the guard bits of the a0 and a1 registers are ignored. the upper word of the destination register is valid. the lower word and the guard bits of the a0 and a1 registers are cleared to 0. x and y data transfer: the movx.w and movy.w instructions access x and y memory via the 16-bit x and y data buses. the data loaded into a register and the data stored from a register is always the upper word (upper 16 bits: bits 31 to 16). in a load, movx.w loads x memory with the x0 or x1 register as the destination register, while movy.w loads y memory with the y0 or y1 register as the destination register. data is loaded into the upper word of the register, while the lower word is cleared to 0. data in the upper word of the a0 or a1 register can be stored in x or y memory with a data transfer instruction, but data cannot be stored from any other register. the guard bits and lower word of the a0 or a1 register are ignored. single data transfer: the movs.w and movs.l instructions can access any memory via the data bus (cdb). all the dsp registers are connected to the cdb bus, and are used as the source and destination registers in a data transfer. there are two data transfer modes: word and longword. in word mode, with the exception of the a0g and a1g registers, a load is performed to, or store performed from, the upper word of a dsp register. in longword mode, with the exception of the a0g and a1g registers, a load is performed to, or store performed from, the 32 bits of a dsp register. in a single data transfer, the a0g and a1g registers can be handled as independent registers. the load and store data length for the a0g and a1g registers is 8 bits. rev. 1.0, 08/99, page 36 of 875 when a dsp register is used as the source register in word mode, if data is stored from a register other than a0g or a1g, the upper word of the register is transferred. in the case of the a0 and a1 registers, the guard bits are ignored. when the a0g or a1g register is used as the source register in word mode, only 8 bits of data are stored from the register, and the upper bits are sign-extended. when a dsp register is used as the destination register in word mode, with the exception of the a0g and a1g registers, data is loaded into the upper word of the register. when data is loaded into a register other than a0g or a1g, the lower word of the register is cleared to 0. in the case of the a0 and a1 registers, the data sign is extended and loaded into the guard bits, and the lower word is cleared to 0. when the a0g or a1g register is used as the destination register in word mode, the lowest 8 bits of the data are loaded into the register, and the a0 or a1 register is not cleared to 0, but retains its prior value. when a dsp register is used as the source register in longword mode, if data is stored from a register other than a0g or a1g, the 32 bits of the register are transferred. when the a0 or a1 register is used as the source register, the guard bits are ignored. when the a0g or a1g register is used as the source register in longword mode, only 8 bits of data are stored from the register, and the upper bits are sign-extended. when a dsp register is used as the destination register in longword mode, with the exception of the a0g and a1g registers, data is loaded into the 32 bits of the register. in the case of the a0 and a1 registers, the data sign is extended and loaded into the guard bits. when the a0g or a1g register is used as the destination register in longword mode, the lowest 8 bits of the data are loaded into the register, and the a0 or a1 register is not cleared to 0, but retains its prior value. the register data formats used with dsp instructions are shown in tables 2.4 and 2.5. with some instructions, not all registers can be accessed. for example, with the pmuls instruction, the a1 register can be specified as the source register, but the a0 register cannot. see the descriptions of the instructions for details. the relationship between the dsp registers and the buses in data transfer is shown in figure 2.8. rev. 1.0, 08/99, page 37 of 875 table 2.4 dsp instruction source register data formats guard bits register bits registers instructions 39C32 31C16 15C0 fixed-point, pdmsb, psha 40-bit data 40-bit data 40-bit data integer 24-bit data 24-bit data dsp operations logical, pshl, pmuls 16-bit data movx/y.w, movs.w 16-bit data a0, a1 data transfer movs.l 32-bit data 32-bit data movs.w data a0g, a1g data transfer movs.l data fixed-point, pdmsb, psha sign * 32-bit data 32-bit data integer sign * 16-bit data dsp operations logical, pshl, pmuls 16-bit data movs.w 16-bit data x0, x1 y0, y1 m0, m1 data transfer movs.l 32-bit data note: * the sign is extended and stored in the alu guard bits. rev. 1.0, 08/99, page 38 of 875 table 2.5 dsp instruction destination register data formats guard bits register bits registers instructions 39C32 31C16 15C0 fixed-point, psha, pmuls (sign extension) 40-bit result 40-bit result integer, pdmsb (sign extension) 24-bit result cleared to 0 dsp operations logical, pshl cleared to 0 16-bit result cleared to 0 movs.w sign extension 16-bit result cleared to 0 a0, a1 data transfer movs.l sign extension 32-bit data 32-bit data movs.w data not updated not updated a0g, a1g data transfer movs.l data not updated not updated fixed-point, psha, pmuls 32-bit result 32-bit result dsp operations integer, logical, pdmsb, pshl 16-bit result cleared to 0 movx.w, movy.w, movs.w 16-bit data cleared to 0 x0, x1 y0, y1 m0, m1 data transfer movs.l 32-bit data 32-bit data rev. 1.0, 08/99, page 39 of 875 39 32 31 0 a0g a1g a0 a1 m0 m1 x0 x1 y0 y1 dsr cdb xdb ydb movs.w, movs.l 32 bits 16 bits 16 bits 16 bits 32 bits movx.w, movy.w movs.w, movs.l 16 8 bits 70 [7:0] figure 2.8 relationship between dsp registers and buses in data transfer rev. 1.0, 08/99, page 40 of 875 2.3 features of cpu core instructions the cpu core instructions are risc type instructions with the following features: fixed 16-bit length: all instructions have a fixed length of 16 bits. this improves program code efficiency. one instruction per state: pipelining is used, and basic instructions can be executed in one state (equivalent to 16.7 ns at 60 mhz operation). data size: the basic data size for operations is longword. byte, word, or longword can be selected as the memory access size. memory byte or word data is sign-extended and operated on as longword data. immediate data is sign-extended to longword size for arithmetic operations or zero-extended to longword size for logical operations. table 2.6 word data sign extension sh7065 cpu description example of other cpu mov.w @(disp,pc),r1 add r1,r0 . . . . . . . . .data.w h'1234 sign-extended to 32 bits, r1 becomes h'00001234, and is then operated on by the add instruction. add.w #h'1234,r0 note: immediate data is referenced by @(disp,pc). load/store architecture: basic operations are executed between registers. in operations involving memory, data is first loaded into a register (load/store architecture). however, bit manipulation instructions such as and are executed directly on memory. delayed branching: unconditional branch instructions, etc., are executed as delayed branches. with a delayed branch instruction, the branch is made after execution of the instruction (called the slot instruction) immediately following the delayed branch instruction. this minimizes disruption of the pipeline when a branch is made. with a delayed branch, the actual branch operation occurs after execution of the slot instruction. however, instruction execution for register updating, etc., excluding the branch operation, is performed in delayed branch instruction ? delay slot instruction order. for example, even though the contents of the register holding the branch destination address are changed in the delay slot, the branch destination address remains as the register contents prior to the change. rev. 1.0, 08/99, page 41 of 875 table 2.7 delayed branch instructions sh7065 cpu description example of other cpu bra trget add r1,r0 add is executed before branch to trget. add.w r1,r0 bra trget multiply/multiply and accumulate operations: a 16 16 ? 32 multiply operation is executed in 1 to 3 states, and a 16 16 + 64 ? 64 multiply and accumulate operation in 2 to 3 states. a 32 32 ? 64 multiply operation and a 32 32 + 64 ? 64 multiply and accumulate operation are each executed in 2 to 4 states. t bit: the result of a comparison is indicated by the t bit in the status register (sr), and a conditional branch is performed according to whether the result is true or false. processing speed has been improved by keeping the number of instructions that modify the t bit to a minimum. table 2.8 t bit sh7065 cpu description example of other cpu cmp/ge r1,r0 bt trget0 bf trget1 if r0 3 r1, the t bit is set. a branch is made to trget0 if r0 3 r1, or to trget1 if r0 < r1. cmp.w r1,r0 bge trget0 blt trget1 add #C1,r0 cmp/eq #0,r0 bt trget the t bit is not set by add. if r0 = 0, the t bit is set. a branch is made if r0 = 0. sub.w #1,r0 beq trget immediate data: byte immediate data is placed inside the instruction code. word and longword immediate data is not placed inside the instruction code, but in a table in memory. the table in memory is referenced with an immediate data transfer instruction (mov) using pc relative addressing mode with displacement. rev. 1.0, 08/99, page 42 of 875 table 2.9 immediate data referencing type sh7065 cpu example of other cpu 8-bit immediate mov #h'12,r0 mov.b #h'12,r0 16-bit immediate mov.w @(disp,pc),r0 . . . . . . . . .data.w h'1234 mov.w #h'1234,r0 32-bit immediate mov.l @(disp,pc),r0 . . . . . . . . .data.l h'12345678 mov.l #h'12345678,r0 note: immediate data is referenced by @(disp,pc). absolute addresses: when data is referenced by absolute address, the absolute address value is placed in a table in memory beforehand. with the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using register indirect addressing mode. table 2.10 absolute address referencing type sh7065 cpu example of other cpu absolute address mov.l @(disp,pc),r1 mov.b @r1,r0 . . . . . . . . .data.l h'12345678 mov.b @h'12345678,r0 16-bit/32-bit displacement: when data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a table in memory beforehand. with the method whereby immediate data is loaded when an instruction is executed, this value is transferred to a register and the data is referenced using indexed register indirect addressing mode. table 2.11 displacement referencing type sh7065 cpu example of other cpu 16-bit displacement mov.w @(disp,pc),r0 mov.w @(r0,r1),r2 . . . . . . . . .data.w h'1234 mov.w @(h'1234,r1),r2 rev. 1.0, 08/99, page 43 of 875 2.4 instruction formats 2.4.1 cpu instruction addressing modes the following table shows addressing modes and effective address calculation methods for instructions executed by the cpu core. table 2.12 addressing modes and effective addresses for cpu instructions addressing mode instruction format effective address calculation method calculation formula register direct rn effective address is register rn. (operand is register rn contents.) register indirect @rn effective address is register rn contents. rn rn rn register indirect with post- increment @rn+ effective address is register rn contents. a constant is added to rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn rn 1/2/4 + rn + 1/2/4 rn after instruction execution byte: rn + 1 ? rn word: rn + 2 ? rn longword: rn + 4 ? rn register indirect with pre- decrement @-rn effective address is register rn contents, decremented by a constant beforehand: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. rn 1/2/4 rn C 1/2/4 C rn C 1/2/4 byte: rn C 1 ? rn word: rn C 2 ? rn longword: rn C 4 ? rn (instruction executed with rn after calculation) rev. 1.0, 08/99, page 44 of 875 table 2.12 addressing modes and effective addresses for cpu instructions (cont) addressing mode instruction format effective address calculation method calculation formula register indirect with displacement @(disp:4,rn) effective address is register rn contents with 4-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. rn 1/2/4 + disp (zero-extended) rn + disp 1/2/4 byte: rn + disp word: rn + disp 2 longword: rn + disp 4 indexed register indirect @(r0,rn) effective address is sum of register rn and r0 contents. rn r0 rn + r0 + rn + r0 gbr indirect with displacement @(disp:8, gbr) effective address is register gbr contents with 8-bit displacement disp added. after disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. gbr 1/2/4 + disp (zero-extended) gbr + disp 1/2/4 byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4 indexed gbr indirect @(r0,gbr) effective address is sum of register gbr and r0 contents. gbr r0 gbr + r0 + gbr + r0 rev. 1.0, 08/99, page 45 of 875 table 2.12 addressing modes and effective addresses for cpu instructions (cont) addressing mode instruction format effective address calculation method calculation formula pc-relative with displacement @(disp:8,pc) effective address is pc with 8-bit displacement disp added. after disp is zero- extended, it is multiplied by 2 (word) or 4 (longword), according to the operand size. with a longword operand, the lower 2 bits of pc are masked. pc h'fffffffc + 2/4 & * * : with longword operand disp (zero-extended) pc + disp 2 or pc & h'fffffffc + disp 4 word: pc + disp 2 longword: pc & h'fffffffc + disp 4 disp:8 effective address is pc with 8-bit displacement disp added after being sign- extended and multiplied by 2. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 pc-relative disp:12 effective address is pc with 12-bit displacement disp added after being sign- extended and multiplied by 2. pc 2 + disp (sign-extended) pc + disp 2 pc + disp 2 rev. 1.0, 08/99, page 46 of 875 table 2.12 addressing modes and effective addresses for cpu instructions (cont) addressing mode instruction format effective address calculation method calculation formula pc-relative rn effective address is sum of pc and rn. pc rn + pc + rn pc + rn #imm:8 8-bit immediate data imm of tst, and, or, or xor instruction is zero-extended. #imm:8 8-bit immediate data imm of mov, add, or cmp/eq instruction is sign-extended. immediate #imm:8 8-bit immediate data imm of trapa instruction is zero-extended and multiplied by 4. rev. 1.0, 08/99, page 47 of 875 2.4.2 dsp data addressing two different memory accesses are made with dsp instructions. the two kinds of instructions are x and y data transfer instructions (movx.w, movy.w) and single data transfer instructions (movs.w, movsl). the data addressing is different for these two kinds of instruction. an overview of the data transfer instructions is given in table 2.13. table 2.13 overview of data transfer instructions x/y data transfer processing (movx.w, movy.w) single data transfer processing (movs.w, movs.l) address register ax: r4, r5; ay: r6, r7 as: r2, r3, r4, r5 index register ix: r8, iy: r9 is: r8 nop/inc (+2)/index addition: post-updating nop/inc (+2, +4)/index addition: post-updating addressing dec (C2, C4): pre-updating modulo addressing possible not possible data bus xdb, ydb cdb data length 16 bits (word) 16/32 bits (word/longword) bus contention no yes memory x/y data memory entire memory space source register dx, dy: a0, a1 ds: a0/a1, m0/m1, x0/x1, y0/y1, a0g, a1g destination register dx: x0/x1, dy: y0/y1 ds: a0/a1, m0/m1, x0/x1, y0/y1, a0g, a1g x/y data addressing: with dsp instructions, the x and y data memory can be accessed simultaneously using the movx.w and movy.w instructions. two address pointers are provided for dsp instructions to enable simultaneous access to x and y data memory. only pointer addressing can be used with dsp instructions; immediate addressing is not available. address registers are divided into two, with register r4 or r5 functioning as the x memory address register (ax), and register r6 or r7 as the y memory address register (ay). the following three kinds of addressing can be used with x and y data transfer instructions. 1. non-update address register addressing: the ax and ay registers are address pointers. they are not updated. 2. addition index register addressing: the ax and ay registers are address pointers. after a data transfer, the value of the ix or iy register is added to each (post-updating). rev. 1.0, 08/99, page 48 of 875 3. increment address register addressing: the ax and ay registers are address pointers. after a data transfer, they are each incremented by 2 (post-updating). there is an index register for each address pointer. the r8 register is the index register (ix) for the x memory address register (ax), and the r9 register is the index register (iy) for the y memory address register (ay). the x and y data transfer instructions perform word-length processing, and use 16-bit access to the x/y data memory. a value of 2 is therefore added to the address register in the increment processing. to perform decrementing, C2 is set in the index register and addition index register addressing is specified. in x/y data addressing, only bits 1 to 15 of the address pointer are valid. when using x/y data addressing, 0 must always be written to bit 0 of the address pointer and index register. x/y data transfer addressing is shown in figure 2.9. when accessing x and y memory using the x and y buses, the upper word of ax (r4 or r5) and ay (r6 or r7) is ignored. the result of @ay+ or @ay+iy is stored in the lower word of ay, while the upper word retains its original value. alu au r8[ix] r4[ax] r5[ax] r9[iy] r6[ay] r7[ay] +2 (inc) +2 (inc) +0 (no update) +0 (no update) note: three address processing methods: 1. increment 2. index register addition (ix/iy) 3. no update post-updating is used in all cases. the address pointer can be decremented by setting C2/C4 in the index register. au: adder provided for dsp addressing figure 2.9 x and y data transfer addressing rev. 1.0, 08/99, page 49 of 875 single data addressing: dsp instructions include two single data transfer instructions (movs.w, movs.l) that load data into, or store data from, a dsp register. with these instructions, one of registers r2 to r5 is used as the single data transfer address register (as). the following four kinds of addressing can be used with single data transfer instructions. 1. non-update address register addressing: the as register is an address pointer. it is not updated. 2. addition index register addressing: the as register is an address pointer. after a data transfer, the value of the is register is added to the as register (post-updating). 3. increment address register addressing: the as register is an address pointer. after a data transfer, the as register is incremented by 2 or 4 (post-updating). 4. decrement address register addressing: the as register is an address pointer. before a data transfer, C2 or C4 is added to the as register (i.e. 2 or 4 is subtracted) (pre-updating). the r8 register is the index register (is) for the address pointer (as). single data transfer addressing is shown in figure 2.10. rev. 1.0, 08/99, page 50 of 875 alu r8[is] r4[as] r5[as] +2/+4 (inc) +0 (no update) r3[as] r2[as] C2/C4 (dec) 31 31 0 31 0 0 mab iab post-updating pre-updating note: four address processing methods: 1. no update 2. index register addition (is) 3. increment 4. decrement figure 2.10 single data transfer addressing modulo addressing: like other dsps, the sh7065 has a modulo addressing mode. address registers are updated in the same way in this mode. when the address pointer value reaches the preset modulo end address, the address pointer value becomes the modulo start address. modulo addressing is only available for the x and y data transfer instructions (movx.w, movy.w). modulo addressing mode is specified for the x address register by setting the dmx bit in the sr register, and for the y address register by setting the dmy bit. modulo addressing is valid for either the x or the y address register, only; it cannot be set for both at the same time. therefore, dmx and dmy cannot both be set simultaneously (if they are, the dmy setting will be valid). the mod register is provided to set the start and end addresses of the modulo address area. the mod register contains ms (modulo start) and me (modulo end). an example of the use of the mod register (ms and me fields) is shown below. rev. 1.0, 08/99, page 51 of 875 mov.l modaddr,rn; rn=modend, modstart ldc rn,mod; me=modend, ms=modstart modaddr: .data.w mend; modend .data.w mstart; modstart modstart: .data : modend: .data the start and end addresses are specified in ms and me, then the dmx or dmy bit is set to 1. the address register contents are compared with me, and if they match, start address ms is stored in the address register. the lower 16 bits of the address register are compared with me. the maximum modulo size is 64 kbytes. this is sufficient to access the x and y memory. a block diagram of modulo addressing is shown in figure 2.11. instruction (movx/movy) dmx cont ms cmp me alu au abx aby r4[ax] r6[ay] r5[ax] r7[ay] r8[ix] r9[iy] dmy 31 0 0 0 0 1 1 16 16 15 15 15 31 31 31 +2 +0 +2 +0 15 15 1 1 xab ya b 15 figure 2.11 modulo addressing an example of modulo addressing is given below. ms = h'c008; me = h'c00c; r4 = h'c008; dmx = 1; dmy = 0; (modulo addressing setting for address register ax (r4, r5)) rev. 1.0, 08/99, page 52 of 875 as a result of the above settings, the r4 register changes as follows. r4: h'c008 inc. r4: h'c00a inc. r4: h'c00c inc. r4: h'c008 (reaches modulo end address, so becomes modulo start address) place the data so that the upper 16 bits of the modulo start and end addresses are the same. this is because the modulo start address overwrites only the lower 15 bits of the address register, excluding bit 0. note: when addition indexing is used for dsp data addressing, the address pointer may exceed the me value without actually reaching it. in this case, the address pointer will not return to the modulo start address. not only with modulo addressing, but when x and y data addressing is used, bit 0 is ignored. 0 must always be written to bit 0 of the address pointer, index register, ms, and me. dsp addressing operations: dsp addressing operations in the pipeline execution stage (ex), including modulo addressing, are shown below. if ( operation is movx.w movy.w ) { abx=ax; aby=ay; /* memory access cycle uses abx and aby. the addresses to be used have not been updated */ /* ax is one of r4,5 */ if ( dmx==0 || dmx==1 && dmy == 1 )} ax=ax+(+2 or r8[ix] or +0); /* inc,index,not-update */ else if (! not-update) ax=modulo( ax, (+2 or r8[ix]) ); /* ay is one of r6,7 */ if ( dmy==0 ) ay=ay+(+2 or r9[iy] or +0); /* inc,index,not-update */ else if (! not-update) ay=modulo( ay, (+2 or r9[iy]) ); } else if ( operation is movs.w or movs.l ) { if ( addressing is nop, inc, add-index-reg ) { mab=as; /* memory access cycle uses mab. the address to be used has not been updated */ /* as is one of r2-5 */ rev. 1.0, 08/99, page 53 of 875 as=as+(+2 or +4 or r8[is] or +0); /* inc,index,not-update */ else { /* decrement, pre-update */ /* as is one of r2C5 */ as=as+(-2 or -4); mab=as; /* memory access cycle uses mab. the address to be used has been updated */ } /* the value to be added to the address register depends on addressing operations. for example, (+2 or r8[ix] or +0) means that +2 : if operation is increment r8[ix] : if operation is add-index-reg +0 : if operation is not-update */ function modulo ( addrreg, index ) { if ( adrreg[15:0]==me ) adrreg[15:0]==ms; else adrreg=adrreg+index; return addrreg; } 2.4.3 cpu instruction formats table 2.14 shows the instruction formats, and the meaning of the source and destination operands, of instructions executed by the cpu core. the meaning of the operands depends on the instruction code. the following symbols are used in the table. xxxx: instruction code mmmm: source register nnnn: destination register iiii: immediate data dddd: displacement rev. 1.0, 08/99, page 54 of 875 table 2.14 cpu instruction formats instruction formats source operand destination operand sample instruction 0 type xxxx xxxx xxxx xxxx 15 0 nop nnnn : register direct movt rn control register or system register nnnn : register direct sts mach,rn n type xxxx xxxx xxxx nnnn 15 0 control register or system register nnnn : pre- decrement register indirect stc.l sr,@-rn mmmm : register direct control register or system register ldc rm,sr mmmm : post- increment register indirect control register or system register ldc.l @rm+,sr mmmm : register indirect jmp @rm m type xxxx mmmm xxxx xxxx 15 0 mmmm : pc-relative using rm brafrm rev. 1.0, 08/99, page 55 of 875 table 2.14 cpu instruction formats (cont) instruction formats source operand destination operand sample instruction mmmm : register direct nnnn : register direct add rm,rn mmmm : register direct nnnn : register indirect mov.l rm,@rn mmmm : post- increment register indirect (multiply and accumulate operation) nnnn : * post- increment register indirect (multiply and accumulate operation) mach, macl mac.w @rm+,@rn+ mmmm : post- increment register indirect nnnn : register direct mov.l @rm+,rn mmmm : register direct nnnn : pre- decrement register indirect mov.l rm,@-rn nm type nnnn xxxx xxxx 15 0 mmmm mmmm : register direct nnnn : indexed register indirect mov.l rm,@(r0,rn) md type xxxx dddd 15 0 mmmm xxxx mmmmdddd : register indirect with displacement r0 (register direct) mov.b @(disp,rm),r0 nd4 type dddd nnnn xxxx 15 0 xxxx r0 (register direct) nnnndddd : register indirect with displacement mov.b r0,@(disp,rn) mmmm : register direct nnnndddd : register indirect with displacement mov.l rm,@(disp,rn) nmd type nnnn xxxx dddd 15 0 mmmm mmmmdddd : register indirect with displacement nnnn : register direct mov.l @(disp,rm),rn rev. 1.0, 08/99, page 56 of 875 table 2.14 cpu instruction formats (cont) instruction formats source operand destination operand sample instruction dddddddd : gbr indirect with displacement r0 (register direct) mov.l @(disp,gbr),r0 r0 (register direct) dddddddd : gbr indirect with displacement mov.l r0,@(disp,gbr) dddddddd : pc-relative with displacement r0 (register direct) mova @(disp,pc),r0 d type dddd xxxx 15 0 xxxx dddd dddddddd : pc-relative bf label d12 type dddd xxxx 15 0 dddd dddd dddddddddddd : pc-relative bra label (label=disp+pc) nd8 type dddd nnnn xxxx 15 0 dddd dddddddd : pc-relative with displacement nnnn : register direct mov.l @(disp,pc),rn iiiiiiii : immediate indexed gbr indirect and.b #imm,@(r0,gbr) iiiiiiii : immediate r0 (register direct) and #imm,r0 i type i i i i xxxx 15 0 xxxx i i i i iiiiiiii : immediate trapa #imm ni type nnnn i i i i xxxx 15 0 i i i i iiiiiiii : immediate nnnn : register direct ad #imm,rn note: * in multiply and accumulate instructions, nnnn is the source register. rev. 1.0, 08/99, page 57 of 875 2.4.4 dsp instruction formats the sh7065 includes new instructions for digital signal processing. the new instructions are of the following two kinds. 1. memory and dsp register double and single data transfer instructions (16-bit length) 2. parallel processing instructions processed by the dsp unit (32-bit length) the instruction formats are shown in figure 2.12. cpu core instructions 0 0 0 0 to 1 1 1 0 double data transfer instructions single data transfer instructions parallel processing instructions b field a field a field a field 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 15 15 15 15 0 0 0 0 31 10 10 9 9 16 26 25 figure 2.12 dsp instruction formats rev. 1.0, 08/99, page 58 of 875 double and single data transfer instructions: the format of double data transfer instructions is shown in table 2.15, and that of single data transfer instructions in table 2.16. table 2.15 double data transfer instruction formats type mnemonic 15 14 13 12 11 10 9 8 7 6543210 nopx 1111000 0 0 00 movx.w @ax,dx ax dx 0 01 movx.w @ax+,dx 10 movx.w @ax+ix,dx 11 movx.w da,@ax da 1 01 movx.w da,@ax+ 10 x memory data transfer movx.w da,@ax+ix 11 nopy 111100 0 0 0 00 movy.w @ay,dy ay dy 0 01 movy.w @ay+,dy 10 movy.w @ay+iy,dy 11 movy.w da,@ay da 1 01 movy.w da,@ay+ 10 y memory data transfer movy.w da,@ay+iy 11 ax: 0 = r4, 1 = r5 ay: 0 = r6, 1 = r7 dx: 0 = x0, 1 = x1 dy: 0 = y0, 1 = y1 da: 0 = a0, 1 = a1 rev. 1.0, 08/99, page 59 of 875 table 2.16 single data transfer instruction formats type mnemonic 15 14 13 12 11 10 9 8 7 6543210 movs.w @-as,ds 111101 as ds 0:( * ) 0000 movs.w @as,ds 0:r4 1:( * )01 movs.w @as+,ds 1:r5 2:( * )10 movs.w @as+ix,ds 2:r2 3:( * )11 movs.w ds,@-as 3:r3 4:( * )00 1 movs.w ds,@as 5:a1 0 1 movs.w ds,@as+ 6:( * )10 movs.w ds,@as+ix 7:a0 1 1 movs.l @-as,ds 8:x0 0 0 1 0 movs.l @as,ds 9:x1 0 1 movs.l @as+,ds a:y0 1 0 movs.l @as+ix,ds b:y1 1 1 movs.l ds,@-as c:m0 0 0 1 movs.l ds,@as d:a1g 0 1 single data transfer movs.l ds,@as+ e:m1 1 0 movs.l ds,@as+ix f:a0g 1 1 note: * codes reserved for system use. parallel processing instructions: parallel processing instructions are provided for efficient execution of digital signal processing using the dsp unit. they are 32 bits long and allow four simultaneous processes, an alu operation, multiplication, and two data transfers. parallel processing instructions are divided into an a field and a b field. the a field defines data transfer instructions and the b field an alu operation instruction and multiply instruction. these instructions can be defined independently, and the processing is executed in parallel, independently and simultaneously. a field parallel data transfer instructions are shown in table 2.17, and b field alu operation instructions and multiply instructions in table 2.18. rev. 1.0, 08/99, page 60 of 875 table 2.17 a field parallel data transfer instructions nopx movx.w @ax, dx movx.w @ax+, dx movx.w @ax+ix, dx movx.w da, @ax movx.w da, @ax+ movx.w da, @ax+ix nopy movy.w @ay, dy movy.w @ay+, dy movy.w @ay+iy, dy movy.w da, @ay movy.w da, @ay+ movy.w da, @ay+iy mnemonic x memory data transfer category 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 1 0 y memory data transfer 111110 b field ax: 0 = r4, 1 = r5 ay: 0 = r6, 1 = r7 dx: 0 = x0, 1 = x1 dy: 0 = y0, 1 = y1 da: 0 = a0, 1 = a1 0 ax 0 ay 0 dx da 0 dy da 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 b field rev. 1.0, 08/99, page 61 of 875 table 2.18 b field alu operation instructions and multiply instructions pshl #imm, dz psha #imm, dz reserved pmuls se, sf, dg reserved psub sx, sy, du pmuls se, sf, dg padd sx, sy, du pmuls se, sf, dg reserved psubc sx, sy, dz paddc sx, sy, dz pcmp sx, sy reserved reserved reserved pabs sx, dz prnd sx, dz pabs sy, dz prnd sy, dz reserved mnemonic imm. shift category 0:( * 1) 1:( * 1) 2:( * 1) 3:( * 1) 4:( * 1) 5:a1 6:( * 1) 7:a0 8:x0 9:x1 a:y0 b:y1 c:m0 d:( * 1) e:m1 f:( * 1) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 six operand parallel instruction three operand instructions 111110 a field 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 C16 <= imm <= +16 C32 <= imm <= +32 se sf sx sy dg du 0:x0 1:x1 2:y0 3:a1 0:y0 1:y1 2:x0 3:a1 0:x0 1:x1 2:a0 3:a1 0:y0 1:y1 2:m0 3:m1 0:m0 1:m1 2:a0 3:a1 0:x0 1:y0 2:a0 3:a1 0 0 1 1 0 1 0 1 00 dz if cc dz note: 1. codes reserved for system use. rev. 1.0, 08/99, page 62 of 875 table 2.18 b field alu operation instructions and multiply instructions (cont) [if cc] pshl sx, sy, dz [if cc] psha sx, sy, dz [if cc] psub sx, sy, dz [if cc] padd sx, sy, dz reserved [if cc] pand sx, sy, dz [if cc] pxor sx, sy, dz [if cc] por sx, sy, dz [if cc] pdec sx, dz [if cc] pinc sx, dz [if cc] pdec sy, dz [if cc] pinc sy, dz [if cc] pclr dz [if cc] pdmsb sx, dz reserved [if cc] pdmsb sy, dz [if cc] pneg sx, dz [if cc] pcopy sx, dz [if cc] pneg sy, dz [if cc] pcopy sy, dz reserved [if cc] psts mach, dz [if cc] psts macl, dz [if cc] plds dz, mach [if cc] plds dz, macl ( * 2) reserved reserved mnemonic category if cc 01: 10: dct 11: dcf 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 43 2 1 0 conditional three operand instructions 111110 a field 10 11 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 sx 0:x0 1:x1 2:a0 3:a1 0 0 1 1 1 1 0 0 1 0 1 0 1 * 0:( * 1) 1:( * 1) 2:( * 1) 3:( * 1) 4:( * 1) 5:a1 6:( * 1) 7:a0 8:x0 9:x1 a:y0 b:y1 c:m0 d:( * 1) e:m1 f:( * 1) dz 111111 0 0 0 0 sy 0:y0 1:y1 2:m0 3:m1 if cc uncon- ditional if cc notes: 1. codes reserved for system use. 2. [if cc]: dct (dc bit true), dcf (dc bit false) or none (unconditional instruction) rev. 1.0, 08/99, page 63 of 875 2.5 instruction set sh7065 instructions can be divided into three kinds: cpu instructions executed by the cpu core, and dsp data transfer instructions and dsp operation instructions executed by the dsp unit. cpu instructions include several for supporting dsp functions. the instruction sets for each of these three kinds of instructions are described below. 2.5.1 cpu instruction set the cpu instructions are listed by type in table 2.19. table 2.19 cpu instruction types type kinds of instruction op code function number of instructions mov data transfer immediate data transfer peripheral module data transfer structure data transfer 39 mova effective address transfer movt t bit transfer swap upper/lower swap data transfer instructions 5 xtrct extraction of middle of linked registers add binary addition 33 addc binary addition with carry addv binary addition with overflow cmp/cond comparison div1 division div0s signed division initialization div0u unsigned division initialization dmuls signed double-precision multiplication dmulu unsigned double-precision multiplication dt decrement and test exts sign extension arithmetic operation instructions 21 extu zero extension rev. 1.0, 08/99, page 64 of 875 table 2.19 cpu instruction types (cont) type kinds of instruction op code function number of instructions mac multiply and accumulate, double- precision multiply and accumulate 33 mul double-precision multiplication muls signed multiplication mulu unsigned multiplication neg sign inversion negc sign inversion with borrow sub binary subtraction subc binary subtraction with borrow arithmetic operation instructions 21 subv binary subtraction with underflow 6 and logical and 14 not bit inversion or logical or tas memory test and bit set tst logical and t bit state logic operation instructions xor exclusive logical or 10 rotcl 1-bit left shift with t bit 14 rotcr 1-bit right shift with t bit rotl 1-bit left shift rotr 1-bit right shift shal arithmetic 1-bit left shift shar arithmetic 1-bit right shift shll logical 1-bit left shift shlln logical n-bit left shift shlr logical 1-bit right shift shift instructions shlrn logical n-bit right shift rev. 1.0, 08/99, page 65 of 875 table 2.19 cpu instruction types (cont) type kinds of instruction op code function number of instructions 9 bf condition branch, delayed conditional branch (branches if t = 0) 11 bt condition branch, delayed conditional branch (branches if t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure branch instructions rts return from subroutine procedure 14 clrmac mac register clear 71 clrt t bit clear ldc load into control register ldre load into repeat end register ldrs load into repeat start register lds load into system register nop no operation rte return from exception handling setrc repeat count setting sett t bit setting sleep transition to power-down mode stc store from control register sts store from system register system control instructions trapa trap exception handling total: 65 total: 182 rev. 1.0, 08/99, page 66 of 875 the instruction code, operation, and number of execution states of the cpu instructions are shown in the following tables, classified by instruction type, using the format shown below. instruction instruction code operation execution states t bit indicated by mnemonic. explanation of symbols op.sz src, dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement * 2 indicated in msb ?? lsb order. explanation of symbols mmmm : source register nnnn : destination register 0000: r0 0001: r1 ...... 1111: r15 iiii : immediate data dddd : displacement indicates summary of operation. explanation of symbols ? , ? : transfer direction (xx): memory operand m/q/t: flag bits in the sr &: logical and of each bit |: logical or of each bit ^: exclusive logical or of each bit ~: logical not of each bit < rev. 1.0, 08/99, page 67 of 875 table 2.20 data transfer instructions instruction instruction code operation execution states t bit mov #imm,rn 1110nnnniiiiiiii imm ? sign extension ? rn 1 mov.w @(disp,pc),rn 1001nnnndddddddd (disp 2 + pc) ? sign extension ? rn 1 mov.l @(disp,pc),rn 1101nnnndddddddd (disp 4 + pc) ? rn 1 mov rm,rn 0110nnnnmmmm0011 rm ? rn 1 mov.b rm,@rn 0010nnnnmmmm0000 rm ? (rn) 1 mov.w rm,@rn 0010nnnnmmmm0001 rm ? (rn) 1 mov.l rm,@rn 0010nnnnmmmm0010 rm ? (rn) 1 mov.b @rm,rn 0110nnnnmmmm0000 (rm) ? sign extension ? rn 1 mov.w @rm,rn 0110nnnnmmmm0001 (rm) ? sign extension ? rn 1 mov.l @rm,rn 0110nnnnmmmm0010 (rm) ? rn 1 mov.b rm,@-rn 0010nnnnmmmm0100 rn C 1 ? rn, rm ? (rn) 1 mov.w rm,@-rn 0010nnnnmmmm0101 rn C 2 ? rn, rm ? (rn) 1 mov.l rm,@-rn 0010nnnnmmmm0110 rn C 4 ? rn, rm ? (rn) 1 mov.b @rm+,rn 0110nnnnmmmm0100 (rm) ? sign extension ? rn, rm + 1 ? rm 1 mov.w @rm+,rn 0110nnnnmmmm0101 (rm) ? sign extension ? rn, rm + 2 ? rm 1 mov.l @rm+,rn 0110nnnnmmmm0110 (rm) ? rn, rm + 4 ? rm 1 mov.b r0,@(disp,rn) 10000000nnnndddd r0 ? (disp + rn) 1 mov.w r0,@(disp,rn) 10000001nnnndddd r0 ? (disp 2 + rn) 1 mov.l rm,@(disp,rn) 0001nnnnmmmmdddd rm ? (disp 4 + rn) 1 mov.b @(disp,rm),r0 10000100mmmmdddd (disp + rm) ? sign extension ? r0 1 mov.w @(disp,rm),r0 10000101mmmmdddd (disp 2 + rm) ? sign extension ? r0 1 mov.l @(disp,rm),rn 0101nnnnmmmmdddd (disp 4 + rm) ? rn 1 mov.b rm,@(r0,rn) 0000nnnnmmmm0100 rm ? (r0 + rn) 1 mov.w rm,@(r0,rn) 0000nnnnmmmm0101 rm ? (r0 + rn) 1 mov.l rm,@(r0,rn) 0000nnnnmmmm0110 rm ? (r0 + rn) 1 rev. 1.0, 08/99, page 68 of 875 table 2.20 data transfer instructions (cont) instruction instruction code operation execution states t bit mov.b @(r0,rm),rn 0000nnnnmmmm1100 (r0 + rm) ? sign extension ? rn 1 mov.w @(r0,rm),rn 0000nnnnmmmm1101 (r0 + rm) ? sign extension ? rn 1 mov.l @(r0,rm),rn 0000nnnnmmmm1110 (r0 + rm) ? rn 1 mov.b r0,@(disp,gbr) 11000000dddddddd r0 ? (disp + gbr) 1 mov.w r0,@(disp,gbr) 11000001dddddddd r0 ? (disp 2 + gbr) 1 mov.l r0,@(disp,gbr) 11000010dddddddd r0 ? (disp 4 + gbr) 1 mov.b @(disp,gbr),r0 11000100dddddddd (disp + gbr) ? sign extension ? r0 1 mov.w @(disp,gbr),r0 11000101dddddddd (disp 2 + gbr) ? sign extension ? r0 1 mov.l @(disp,gbr),r0 11000110dddddddd (disp 4 + gbr) ? r0 1 mova @(disp,pc),r0 11000111dddddddd disp 4 + pc ? r0 1 movt rn 0000nnnn00101001 t ? rn 1 swap.b rm,rn 0110nnnnmmmm1000 rm ? swap lower 2 bytes ? rn 1 swap.w rm,rn 0110nnnnmmmm1001 rm ? swap upper/lower words ? rn 1 xtrct rm,rn 0010nnnnmmmm1101 middle 32 bits of rm and rn ? rn 1 rev. 1.0, 08/99, page 69 of 875 table 2.21 arithmetic operation instructions instruction instruction code operation execution states t bit add rm,rn 0011nnnnmmmm1100 rn + rm ? rn 1 add #imm,rn 0111nnnniiiiiiii rn + imm ? rn 1 addc rm,rn 0011nnnnmmmm1110 rn + rm + t ? rn, carry ? t 1 carry addv rm,rn 0011nnnnmmmm1111 rn + rm ? rn, overflow ? t 1 overflow cmp/eq #imm,r0 10001000iiiiiiii when r0 = imm, 1 ? t 1 comparison result cmp/eq rm,rn 0011nnnnmmmm0000 when rn = rm, 1 ? t 1 comparison result cmp/hs rm,rn 0011nnnnmmmm0010 when rn 3 rm (unsigned), 1 ? t 1 comparison result cmp/ge rm,rn 0011nnnnmmmm0011 when rn 3 rm (signed), 1 ? t 1 comparison result cmp/hi rm,rn 0011nnnnmmmm0110 when rn > rm (unsigned), 1 ? t 1 comparison result cmp/gt rm,rn 0011nnnnmmmm0111 when rn > rm (signed), 1 ? t 1 comparison result cmp/pl rn 0100nnnn00010101 when rn > 0, 1 ? t 1 comparison result cmp/pz rn 0100nnnn00010001 when rn 3 0, 1 ? t 1 comparison result cmp/str rm,rn 0010nnnnmmmm1100 when any bytes are equal, 1 ? t 1 comparison result div1 rm,rn 0011nnnnmmmm0100 1-step division (rn rm) 1 calculation result div0s rm,rn 0010nnnnmmmm0111 msb of rn ? q, msb of rm ? m, m^q ? t 1 calculation result div0u 0000000000011001 0 ? m/q/t 1 0 dmuls.l rm,rn 0011nnnnmmmm1101 signed, rn rm ? mach, macl 32 32 ? 64 bits 2C4 * dmulu.l rm,rn 0011nnnnmmmm0101 unsigned, rn rm ? mach, macl 32 32 ? 64 bits 2C4 * rev. 1.0, 08/99, page 70 of 875 table 2.21 arithmetic operation instructions (cont) instruction instruction code operation execution states t bit dt rn 0100nnnn00010000 rn C 1 ? rn; when rn = 0, 1 ? t when rn 1 0, 0 ? t 1 comparison result exts.b rm,rn 0110nnnnmmmm1110 rm sign-extended from byte ? rn 1 exts.w rm,rn 0110nnnnmmmm1111 rm sign-extended from word ? rn 1 extu.b rm,rn 0110nnnnmmmm1100 rm zero-extended from byte ? rn 1 extu.w rm,rn 0110nnnnmmmm1101 rm zero-extended from word ? rn 1 mac.l @rm+,@rn+ 0000nnnnmmmm1111 signed, (rn) (rm) + mac ? mac 32 32 + 64 ? 64 bits 3/(2C4) * mac.w @rm+,@rn+ 0100nnnnmmmm1111 signed, (rn) (rm) + mac ? mac 16 16 + 64 ? 64 bits 3/(2) * mul.l rm,rn 0000nnnnmmmm0111 rn rm ? macl 32 32 ? 32 bits 2C4 * muls.w rm,rn 0010nnnnmmmm1111 signed, rn rm ? mac 16 16 ? 32 bits 1C3 * mulu.w rm,rn 0010nnnnmmmm1110 unsigned, rn rm ? mac 16 16 ? 32 bits 1C3 * neg rm,rn 0110nnnnmmmm1011 0 C rm ? rn 1 negc rm,rn 0110nnnnmmmm1010 0 C rm C t ? rn, borrow ? t 1 borrow sub rm,rn 0011nnnnmmmm1000 rn C rm ? rn 1 subc rm,rn 0011nnnnmmmm1010 rn C rm C t ? rn, borrow ? t 1 borrow subv rm,rn 0011nnnnmmmm1011 rn C rm ? rn, underflow ? t 1 underflow note: * the normal number of execution states is shown. the number in parentheses is the number of execution cycles in the case of contention with preceding or following instructions. rev. 1.0, 08/99, page 71 of 875 table 2.22 logic operation instructions instruction instruction code operation execution states t bit and rm,rn 0010nnnnmmmm1001 rn & rm ? rn 1 and #imm,r0 11001001iiiiiiii r0 & imm ? r0 1 and.b #imm,@(r0,gbr) 11001101iiiiiiii (r0 + gbr) & imm ? (r0 + gbr) 3 not rm,rn 0110nnnnmmmm0111 ~rm ? rn 1 or rm,rn 0010nnnnmmmm1011 rn | rm ? rn 1 or #imm,r0 11001011iiiiiiii r0 | imm ? r0 1 or.b #imm,@(r0,gbr) 11001111iiiiiiii (r0 + gbr) | imm ? (r0 + gbr) 3 tas.b @rn 0100nnnn00011011 when (rn) = 0, 1 ? t, 1 ? msb of (rn) 4test result tst rm,rn 0010nnnnmmmm1000 rn & rm; when result = 0, 1 ? t 1test result tst #imm,r0 11001000iiiiiiii r0 & imm; when result = 0, 1 ? t 1test result tst.b #imm,@(r0,gbr) 11001100iiiiiiii (r0 + gbr) & imm; when result = 0, 1 ? t 3test result xor rm,rn 0010nnnnmmmm1010 rn ^ rm ? rn 1 xor #imm,r0 11001010iiiiiiii r0 ^ imm ? r0 1 xor.b #imm,@(r0,gbr) 11001110iiiiiiii (r0 + gbr) ^ imm ? (r0 + gbr) 3 rev. 1.0, 08/99, page 72 of 875 table 2.23 shift instructions instruction instruction code operation execution states t bit rotl rn 0100nnnn00000100 t ? rn ? msb 1 msb rotr rn 0100nnnn00000101 lsb ? rn ? t1lsb rotcl rn 0100nnnn00100100 t ? rn ? t1msb rotcr rn 0100nnnn00100101 t ? rn ? t1lsb shal rn 0100nnnn00100000 t ? rn ? 01msb shar rn 0100nnnn00100001 msb ? rn ? t1lsb shll rn 0100nnnn00000000 t ? rn ? 01msb shlr rn 0100nnnn00000001 0 ? rn ? t1lsb shll2 rn 0100nnnn00001000 rn << 2 ? rn 1 shlr2 rn 0100nnnn00001001 rn >> 2 ? rn 1 shll8 rn 0100nnnn00011000 rn << 8 ? rn 1 shlr8 rn 0100nnnn00011001 rn >> 8 ? rn 1 shll16 rn 0100nnnn00101000 rn << 16 ? rn 1 shlr16 rn 0100nnnn00101001 rn >> 16 ? rn 1 rev. 1.0, 08/99, page 73 of 875 table 2.24 branch instructions instruction instruction code operation execution states t bit bf label 10001011dddddddd when t = 0, disp 2 + pc ? pc; when t = 1, nop 3/1 * bf/s label 10001111dddddddd delayed branch; when t = 0, disp 2 + pc ? pc; when t = 1, nop 2/1 * bt label 10001001dddddddd when t = 1, disp 2 + pc ? pc; when t = 0, nop 3/1 * bt/s label 10001101dddddddd delayed branch; when t = 1, disp 2 + pc ? pc; when t = 0, nop 2/1 * bra label 1010dddddddddddd delayed branch, disp 2 + pc ? pc 2 braf rm 0000mmmm00100011 delayed branch, rm + pc ? pc 2 bsr label 1011dddddddddddd delayed branch, pc ? pr, disp 2 + pc ? pc 2 bsrf rm 0000mmmm00000011 delayed branch, pc ? pr, rm + pc ? pc 2 jmp @rm 0100mmmm00101011 delayed branch, rm ? pc 2 jsr @rm 0100mmmm00001011 delayed branch, pc ? pr, rm ? pc 2 rts 0000000000001011 delayed branch, pr ? pc 2 note: * one state when the branch is not executed. rev. 1.0, 08/99, page 74 of 875 table 2.25 system control instructions instruction instruction code operation execution states t bit clrmac 0000000000101000 0 ? mach, macl 1 clrt 0000000000001000 0 ? t10 ldc rm,sr 0100mmmm00001110 rm ? sr 1 lsb ldc rm,gbr 0100mmmm00011110 rm ? gbr 1 ldc rm,vbr 0100mmmm00101110 rm ? vbr 1 ldc rm,mod 0100mmmm01011110 rm ? mod 1 ldc rm,re 0100mmmm01111110 rm ? re 1 ldc rm,rs 0100mmmm01101110 rm ? rs 1 ldc.l @rm+,sr 0100mmmm00000111 (rm) ? sr, rm + 4 ? rm 3 lsb ldc.l @rm+,gbr 0100mmmm00010111 (rm) ? gbr , rm + 4 ? rm 3 ldc.l @rm+,vbr 0100mmmm00100111 (rm) ? vbr , rm + 4 ? rm 3 ldc.l @rm+,mod 0100mmmm01010111 (rm) ? mod , rm + 4 ? rm 3 ldc.l @rm+,re 0100mmmm01110111 (rm) ? re, rm + 4 ? rm 3 ldc.l @rm+,rs 0100mmmm01100111 (rm) ? rs, rm + 4 ? rm 3 ldre @(disp,pc) 10001110dddddddd disp 2 + pc ? re 1 ldrs @(disp,pc) 10001100dddddddd disp 2 + pc ? rs 1 lds rm,mach 0100mmmm00001010 rm ? mach 1 lds rm,macl 0100mmmm00011010 rm ? macl 1 lds rm,pr 0100mmmm00101010 rm ? pr 1 lds rm,dsr 0100mmmm01101010 rm ? dsr 1 lds rm,a0 0100mmmm01111010 rm ? a0 1 lds rm,x0 0100mmmm10001010 rm ? x0 1 lds rm,x1 0100mmmm10011010 rm ? x1 1 lds rm,y0 0100mmmm10101010 rm ? y0 1 lds rm,y1 0100mmmm10111010 rm ? y1 1 lds.l @rm+,mach 0100mmmm00000110 (rm) ? mach, rm + 4 ? rm 1 lds.l @rm+,macl 0100mmmm00010110 (rm) ? macl, rm + 4 ? rm 1 lds.l @rm+,pr 0100mmmm00100110 (rm) ? pr, rm + 4 ? rm 1 lds.l @rm+,dsr 0100mmmm01100110 (rm) ? dsr, rm + 4 ? rm 1 lds.l @rm+,a0 0100mmmm01110110 (rm) ? a0, rm + 4 ? rm 1 lds.l @rm+,x0 0100mmmm10000110 (rm) ? x0, rm + 4 ? rm 1 rev. 1.0, 08/99, page 75 of 875 table 2.25 system control instructions (cont) instruction instruction code operation execution states t bit lds.l @rm+,x1 0100mmmm10010110 (rm) ? x1, rm + 4 ? rm 1 lds.l @rm+,y0 0100mmmm10100110 (rm) ? y0, rm + 4 ? rm 1 lds.l @rm+,y1 0100mmmm10110110 (rm) ? y1, rm + 4 ? rm 1 nop 0000000000001001 no operation 1 rte 0000000000101011 delayed branch, stack area ? pc/sr 4lsb setrc rm 0100mmmm00010100 re C rs operation result (repeat status) ? rf1, rf0 rm [11:0] ? rc (sr [27:16]) 1 setrc #imm 10000010iiiiiiii re C rs operation result (repeat status) ? rf1, rf0 imm ? rc (sr [23:16]), zeros ? sr [27:24] 11 sett 0000000000011000 1 ? t11 sleep 0000000000011011 sleep 3 * stc sr,rn 0000nnnn00000010 sr ? rn 1 stc gbr,rn 0000nnnn00010010 gbr ? rn 1 stc vbr,rn 0000nnnn00100010 vbr ? rn 1 stc mod,rn 0000nnnn01010010 mod ? rn 1 stc re,rn 0000nnnn01110010 re ? rn 1 stc rs,rn 0000nnnn01100010 rs ? rn 1 stc.l sr,@-rn 0100nnnn00000011 rn C 4 ? rn , sr ? (rn) 2 stc.l gbr,@-rn 0100nnnn00010011 rn C 4 ? rn , gbr ? (rn) 2 stc.l vbr,@-rn 0100nnnn00100011 rn C 4 ? rn , vbr ? (rn) 2 stc.l mod,@-rn 0100nnnn01010011 rn C 4 ? rn , mod ? (rn) 2 stc.l re,@-rn 0100nnnn01110011 rn C 4 ? rn , re ? (rn) 2 stc.l rs,@-rn 0100nnnn01100011 rn C 4 ? rn , rs ? (rn) 2 sts mach,rn 0000nnnn00001010 mach ? rn 1 sts macl,rn 0000nnnn00011010 macl ? rn 1 sts pr,rn 0000nnnn00101010 pr ? rn 1 sts dsr,rn 0000nnnn01101010 dsr ? rn 1 sts a0,rn 0000nnnn01111010 a0 ? rn 1 sts x0,rn 0000nnnn10001010 x0 ? rn 1 rev. 1.0, 08/99, page 76 of 875 table 2.25 system control instructions (cont) instruction instruction code operation execution states t bit sts x1,rn 0000nnnn10011010 x1 ? rn 1 sts y0,rn 0000nnnn10101010 y0 ? rn 1 sts y1,rn 0000nnnn10111010 y1 ? rn 1 sts.l mach,@-rn 0100nnnn00000010 rn C 4 ? rn , mach ? (rn) 1 sts.l macl,@-rn 0100nnnn00010010 rn C 4 ? rn , macl ? (rn) 1 sts.l pr,@-rn 0100nnnn00100010 rn C 4 ? rn , pr ? (rn) 1 sts.l dsr,@-rn 0100nnnn01100010 rn C 4 ? rn , dsr ? (rn) 1 sts.l a0,@-rn 0100nnnn01110010 rn C 4 ? rn , a0 ? (rn) 1 sts.l x0,@-rn 0100nnnn10000010 rn C 4 ? rn , x0 ? (rn) 1 sts.l x1,@-rn 0100nnnn10010010 rn C 4 ? rn , x1 ? (rn) 1 sts.l y0,@-rn 0100nnnn10100010 rn C 4 ? rn , y0 ? (rn) 1 sts.l y1,@-rn 0100nnnn10110010 rn C 4 ? rn , y1 ? (rn) 1 trapa #imm 11000011iiiiiiii pc/sr ? stack area, (imm 4 + vbr) ? pc 8 note: * number of states until transition to sleep state. caution: the table shows the minimum number of execution states. in practice, the number of instruction execution states will be increased in cases such as the following: ? when there is conflict between an instruction fetch and a data access ? when the destination register of a load instruction (memory ? register) is also used by the following instruction ? when the branch destination address of a branch instruction is address 4n + 2 ? depending on the number of cycles of the instruction fetch destination or data access destination (see 8.4, number of access cycles in section 8, bus state controller (bsc), for details). rev. 1.0, 08/99, page 77 of 875 cpu instructions supporting dsp functions: a number of system control instructions have been added to the cpu core instructions to support dsp functions. the rs, re, and mod registers have been added, supporting repeat control and modulo addressing, and a repeat counter (rc) has been added to the status register (sr). ldc and stc instructions have been added in order to access these new additions, while lds and sts instructions have been added to access dsp registers dsr, a0, x0, x1, y0, and y1. another addition is the setrc instruction which sets a value in the repeat counter (rc: bits 27 to 16) and the repeat flags (rf1, rf0: bits 3 and 2) in the sr register. when an immediate operand is used in the setrc instruction, 8-bit immediate data is stored in bits 23 to 16 of sr, and bits 27 to 24 are cleared to 0. when the operand is a register, the 12 bits from bit 11 to bit 0 of the register are stored in bits 27 to 16 of sr. according to the set values of rs and re, 1-instruction repeat (00), 2-instruction repeat (01), 3-instruction repeat (11), or 4-plus-instruction repeat (10) is set. in addition to the ldc instruction, the ldrs and ldre instructions have been added as instructions that set the repeat start address and repeat end address in the rs and re registers. the added instructions are shown in table 2.26. table 2.26 added cpu instructions instruction instruction code operation execution states t bit ldc rm,mod 0100mmmm01011110 rm ? mod 1 ldc rm,re 0100mmmm01111110 rm ? re 1 ldc rm,rs 0100mmmm01101110 rm ? rs 1 ldc.l @rm+,mod 0100mmmm01010111 (rm) ? mod , rm + 4 ? rm 3 ldc.l @rm+,re 0100mmmm01110111 (rm) ? re , rm + 4 ? rm 3 ldc.l @rm+,rs 0100mmmm01100111 (rm) ? rs , rm + 4 ? rm 3 stc mod,rn 0000nnnn01010010 mod ? rn 1 stc re,rn 0000nnnn01110010 re ? rn 1 stc rs,rn 0000nnnn01100010 rs ? rn 1 stc.l mod,@-rn 0100nnnn01010011 rn C 4 ? rn , mod ? (rn) 2 stc.l re,@-rn 0100nnnn01110011 rn C 4 ? rn , re ? (rn) 2 stc.l rs,@-rn 0100nnnn01100011 rn C 4 ? rn , rs ? (rn) 2 lds rm,dsr 0100mmmm01101010 rm ? dsr 1 lds.l @rm+,dsr 0100mmmm01100110 (rm) ? dsr , rm + 4 ? rm 1 lds rm,a0 0100mmmm01111010 rm ? a0 1 lds.l @rm+,a0 0100mmmm01110110 (rm) ? a0 , rm + 4 ? rm 1 rev. 1.0, 08/99, page 78 of 875 table 2.26 added cpu instructions (cont) instruction instruction code operation execution states t bit lds rm,x0 0100mmmm10001010 rm ? x0 1 lds.l @rm+,x0 0100mmmm10000110 (rm) ? x0 , rm + 4 ? rm 1 lds rm,x1 0100mmmm10011010 rm ? x1 1 lds.l @rm+,x1 0100mmmm10010110 (rm) ? x1 , rm + 4 ? rm 1 lds rm,y0 0100mmmm10101010 rm ? y0 1 lds.l @rm+,y0 0100mmmm10100110 (rm) ? y0 , rm + 4 ? rm 1 lds rm,y1 0100mmmm10111010 rm ? y1 1 lds.l @rm+,y1 0100mmmm10110110 (rm) ? y1 , rm + 4 ? rm 1 sts dsr,rn 0000nnnn01101010 dsr ? rn 1 sts.l dsr,@-rn 0100nnnn01100010 rn C 4 ? rn , dsr ? (rn) 1 sts a0,rn 0000nnnn01111010 a0 ? rn 1 sts.l a0,@-rn 0100nnnn01110010 rn C 4 ? rn , a0 ? (rn) 1 sts x0,rn 0000nnnn10001010 x0 ? rn 1 sts.l x0,@-rn 0100nnnn10000010 rn C 4 ? rn , x0 ? (rn) 1 sts x1,rn 0000nnnn10011010 x1 ? rn 1 sts.l x1,@-rn 0100nnnn10010010 rn C 4 ? rn , x1 ? (rn) 1 sts y0,rn 0000nnnn10101010 y0 ? rn 1 sts.l y0,@-rn 0100nnnn10100010 rn C 4 ? rn , y0 ? (rn) 1 sts y1,rn 0000nnnn10111010 y1 ? rn 1 sts.l y1,@-rn 0100nnnn10110010 rn C 4 ? rn , y1 ? (rn) 1 setrc rm 0100mmmm00010100 rm [11:0] ? rc (sr [27:16]) 1 setrc #imm 10000010iiiiiiii imm ? rc (sr [23:16]), 0 ? sr [27:24] 1 ldrs @(disp,pc) 10001100dddddddd disp 2 + pc ? rs 1 ldre @(disp,pc) 10001110dddddddd disp 2 + pc ? re 1 rev. 1.0, 08/99, page 79 of 875 2.5.2 dsp data transfer instruction set the dsp data transfer instructions are listed by type in table 2.27. table 2.27 dsp data transfer instruction types type kinds of instruction op code function number of instructions 4 nopx x memory no operation 14 movx x memory data transfer nopy y memory no operation double data transfer instructions movy y memory data transfer single data transfer instruction 1 movs single data transfer 16 total: 5 total: 30 data transfer instructions are divided into two groups: double data transfer and single data transfer. double data transfer can be executed by dsp parallel processing instructions in combination with dsp operation instructions. parallel processing instructions are 32 bits long, and incorporate a double data transfer instruction in the a field. double data transfer instructions that are not parallel processing instructions, and single data transfer instructions, are 16 bits long. in double data transfer, x memory and y memory can be simultaneously accessed in parallel. instructions are specified one by one from the x and y memory data accesses, respectively. the ax pointer is used to access the x memory, and the ay pointer to access the y memory. double data transfer can only be used to access x and y memory. in single data transfer, access is possible from any area. in single data transfer, the ax pointer and two other pointers are used as the as pointer. rev. 1.0, 08/99, page 80 of 875 table 2.28 double data transfer instructions (x memory data) instruction operation instruction code execution states dc bit nopx no operation 1111000*0*0*00** 1 movx.w @ax,dx (ax) ? msw of dx , 0 ? lsw of dx 111100a*d*0*01** 1 movx.w @ax+,dx (ax) ? msw of dx , 0 ? lsw of dx , ax + 2 ? ax 111100a*d*0*10** 1 movx.w @ax+ix,dx (ax) ? msw of dx , 0 ? lsw of dx , ax + ix ? ax 111100a*d*0*11** 1 movx.w da,@ax msw of da ? (ax) 111100a*d*1*01** 1 movx.w da,@ax+ msw of da ? (ax) , ax + 2 ? ax 111100a*d*1*10** 1 movx.w da,@ax+ix msw of da ? (ax) , ax + ix ? ax 111100a*d*1*11** 1 table 2.29 double data transfer instructions (y memory data) instruction operation instruction code execution states dc bit nopy no operation 111100*0*0*0**00 1 movy.w @ay,dy (ay) ? msw of dy , 0 ? lsw of dy 111100*a*d*0**01 1 movy.w @ay+,dy (ay) ? msw of dy , 0 ? lsw of dy , ay + 2 ? ay 111100*a*d*0**10 1 movy.w @ay+iy,dy (ay) ? msw of dy , 0 ? lsw of dy , ay + iy ? ay 111100*a*d*0**11 1 movy.w da,@ay msw of da ? (ay) 111100*a*d*1**01 1 movy.w da,@ay+ msw of da ? (ay) , ay + 2 ? ay 111100*a*d*1**10 1 movy.w da,@ay+iy msw of da ? (ay) , ay + iy ? ay 111100*a*d*1**11 1 rev. 1.0, 08/99, page 81 of 875 table 2.30 single data transfer instructions instruction operation instruction code execution states dc bit movs.w @-as,ds as C 2 ? as , (as) ? msw of ds , 0 ? lsw of ds 111101aadddd0000 1 movs.w @as,ds (as) ? msw of ds , 0 ? lsw of ds 111101aadddd0100 1 movs.w @as+,ds (as) ? msw of ds , 0 ? lsw of ds , as + 2 ? as 111101aadddd1000 1 movs.w @as+ix,ds (as) ? msw of ds , 0 ? lsw of ds , as + ix ? as 111101aadddd1100 1 movs.w ds,@-as as C 2 ? as , msw of ds ? (as) * 111101aadddd0001 1 movs.w ds,@as msw of ds ? (as) * 111101aadddd0101 1 movs.w ds,@as+ msw of ds ? (as) * , as + 2 ? as 111101aadddd1001 1 movs.w ds,@as+is msw of ds ? (as) * , as + is ? as 111101aadddd1101 1 movs.l @-as,ds as C 4 ? as , (as) ? ds 111101aadddd0010 1 movs.l @as,ds (as) ? ds 111101aadddd0110 1 movs.l @as+,ds (as) ? ds , as + 4 ? as 111101aadddd1010 1 movs.l @as+is,ds (as) ? ds , as + is ? as 111101aadddd1110 1 movs.l ds,@-as as C 4 ? as , ds ? (as) * 111101aadddd0011 1 movs.l ds,@as ds ? (as) * 111101aadddd0111 1 movs.l ds,@as+ ds ? (as) * , as + 4 ? as 111101aadddd1011 1 movs.l ds,@as+is ds ? (as) * , as + is ? as 111101aadddd1111 1 note: * when guard bit register a0g or a1g is specified as source operand ds, the data is sign- extended before being transferred. the correspondence between dsp data transfer operands and registers is shown in table 2.22. cpu core registers are used as a pointer address that indicates a memory address. rev. 1.0, 08/99, page 82 of 875 table 2.31 correspondence between dsp data transfer operands and registers sh (cpu core) register operand r0 r1 r2 (as2) r3 (as3) r4 (ax0, as0) r5 (ax1, as1) r6 (ay0) r7 (ay1) r8 (ix,is) r9 (iy) ax yes yes ix, ( is ) yes dx ay yes yes iy yes dy da as yes yes yes yes ds dsp register x0 x1 y0 y1 m0 m1 a0 a1 a0g a1g ax ix, ( is ) dx yes yes ay iy dy yes yes da yes yes as ds yes yes yes yes yes yes yes yes yes yes note: yes: settable register rev. 1.0, 08/99, page 83 of 875 2.5.3 dsp operation instruction set dsp operation instructions are instructions for digital signal processing performed by the dsp unit. these instructions have a 32-bit instruction code, and multiple instructions can be executed in parallel. the instruction code is divided into an a field and b field; a parallel data transfer instruction is specified in the a field, and a single or double data transfer operation instruction in the b field. instructions can be specified independently, and are also executed independently. the parallel data transfer instruction specified in the a field is exactly the same as a double data transfer instruction. b field data operation instructions are divided into three: double data operation instructions, conditional single data operation instructions, and unconditional single data operation instructions. the formats of the dsp operation instructions are shown in table 2.32. the respective operands are selected independently from the dsp registers. the correspondence between dsp operation instruction operands and registers is shown in table 2.33. table 2.32 dsp operation instruction formats type instruction formats instructions double data operation instructions (6 operands) aluop. sx, sy, du mltop. se, sf, dg padd pmuls, psub pmuls 3 operands aluop. sx, sy, dz dct aluop. sx, sy, dz dcf aluop. sx, sy, dz padd, pand, por, psha, pshl, psub, pxor 2 operands aluop. sx, dz dct aluop. sx, dz dcf aluop. sx, dz aluop. sy, dz dct aluop. sy, dz dcf aluop. sy, dz pcopy, pdec, pdmsb, pinc, plds, psts, pneg conditional single data operation instructions 1 operand aluop. dz dct aluop. dz dcf aluop. dz pclr 3 operands aluop. sx, sy, du mltop. se, sf, dg paddc, psubc, pmuls 2 operands aluop. sx, dz aluop. sy, dz pcmp, pabs, prnd unconditional single data operation instructions 1 operand aluop. dz psha #imm, pshl #imm rev. 1.0, 08/99, page 84 of 875 table 2.33 correspondence between dsp instruction operands and registers alu/bpu instructions multiply instructions register sxsydzdu sesf dg a0 yes yes yes yes a1 yes yes yes yes yes yes m0 yes yes yes m1 yes yes yes x0 yes yes yes yes yes x1 yes yes yes y0 yes yes yes yes yes y1 yes yes yes when writing parallel instructions, the b field instruction is written first, followed by the a field instruction. a sample parallel processing program is shown in figure 2.13. padd a0, m0, a0 pmuls x0, y0, m0 movx.w @r4+, x0 movy.w @r6+, y0 [;] pinc x1, a1 movx.w a0, @r5+r8 movy.w @r7+, y0 [;] pcmp x1, m0 movx.w @r4 [nopy] [;] dcf figure 2.13 sample parallel processing program square brackets mean that the contents can be omitted. the no operation instructions nopx and nopy can be omitted. a semicolon is the instruction line delimiter, but this can also be omitted. if the semicolon delimiter is used, the area to the right of the semicolon can be used as a comment field. the dsr register status codes (dc, n, z, v, and gt) are always updated by unconditional alu operation instructions and shift operation instructions. conditional instructions do not update the status codes even if the condition is satisfied. multiply instructions, too, do not update the status codes. the definition of the dc bit is determined by the specification of the cs bit in the dsr register. the dsp operation instructions are listed by type in table 2.34. rev. 1.0, 08/99, page 85 of 875 table 2.34 dsp operation instruction types type kinds of instruction op code function number of instructions pabs absolute value operation 28 padd addition padd pmuls addition and signed multiplication paddc addition with carry pclr clear pcmp comparison pcopy copy pneg signed inversion psub subtraction psub pmuls subtraction and signed multiplication alu fixed-point operation instructions 11 psubc subtraction with borrow pdec decrement 12 alu integer operation instructions 2 pinc increment alu arithmetic operation instructions msb detection instructions 1 pdmsb msb detection 6 rounding operation instructions 1 prnd rounding operation 2 pand logical and operation 9 por logical or operation alu logic operation instructions 3 pxor exclusive logical or operation fixed-point multiply instruction 1 pmuls signed multiplication 1 arithmetic shift operation instructions 1 psha arithmetic shift 4 shift logical shift operation instructions 1 pshl logical shift 4 2 plds system register load 12 system control instructions psts store from system register total: 23 total: 78 rev. 1.0, 08/99, page 86 of 875 alu arithmetic operation instructions table 2.35 alu fixed-point operation instructions instruction operation instruction code execution states dc bit pabs sx,dz if sx 3 0, sx ? dz if sx < 0, 0 C sx ? dz 111110********** 10001000xx00zzzz 1 updated pabs sy,dz if sy 3 0, sy ? dz if sy< 0, 0 C sy ? dz 111110********** 1010100000yyzzzz 1 updated padd sx,sy,dz sx + sy ? dz 111110********** 10110001xxyyzzzz 1 updated dct padd sx,sy,dz if dc = 1, sx + sy ? dz if dc = 0, nop 111110********** 10110010xxyyzzzz 1 dcf padd sx,sy,dz if dc = 0, sx + sy ? dz if dc = 1 , nop 111110********** 10110011xxyyzzzz 1 padd sx,sy,du pmuls se,sf,dg sx + sy ? du se upper word sf upper word ? dg 111110********** 0111eeffxxyygguu 1 updated paddc sx,sy,dz sx + sy + dc ? dz 111110********** 10110000xxyyzzzz 1 updated pclr dz h'00000000 ? dz 111110********** 100011010000zzzz 1 updated dct pclr dz if dc = 1, h'00000000 ? dz if dc = 0, nop 111110********** 100011100000zzzz 1 dcf pclr dz if dc = 0, h'00000000 ? dz if dc = 1, nop 111110********** 100011110000zzzz 1 pcmp sx,sy sx C sy 111110********** 10000100xxyy0000 1 updated pcopy sx,dz sx ? dz 111110********** 11011001xx00zzzz 1 updated pcopy sy,dz sy ? dz 111110********** 1111100100yyzzzz 1 updated dct pcopy sx,dz if dc = 1, sx ? dz if dc = 0, nop 111110********** 11011010xx00zzzz 1 dct pcopy sy,dz if dc = 1, sy ? dz if dc = 0, nop 111110********** 1111101000yyzzzz 1 rev. 1.0, 08/99, page 87 of 875 table 2.35 alu fixed-point operation instructions (cont) instruction operation instruction code execution states dc bit dcf pcopy sx,dz if dc = 0, sx ? dz if dc = 1, nop 111110********** 11011011xx00zzzz 1 dcf pcopy sy,dz if dc = 0, sy ? dz if dc = 1, nop 111110********** 1111101100yyzzzz 1 pneg sx,dz 0 C sx ? dz 111110********** 11001001xx00zzzz 1 updated pneg sy,dz 0 C sy ? dz 111110********** 1110100100yyzzzz 1 updated dct pneg sx,dz if dc = 1, 0 C sx ? dz if dc = 0, nop 111110********** 11001010xx00zzzz 1 dct pneg sy,dz if dc = 1, 0 C sy ? dz if dc = 0, nop 111110********** 1110101000yyzzzz 1 dcf pneg sx,dz if dc = 0, 0 C sx ? dz if dc = 1, nop 111110********** 11001011xx00zzzz 1 dcf pneg sy,dz if dc = 0, 0 C sy ? dz if dc = 1, nop 111110********** 1110101100yyzzzz 1 psub sx,sy,dz sx C sy ? dz 111110********** 10100001xxyyzzzz 1 updated dct psub sx,sy,dz if dc = 1, sx C sy ? dz if dc = 0, nop 111110********** 10100010xxyyzzzz 1 dcf psub sx,sy,dz if dc = 0, sx C sy ? dz if dc = 1, nop 111110********** 10100011xxyyzzzz 1 psub sx,sy,du pmuls se,sf,dg sx C sy ? du se upper word sf upper word ? dg 111110********** 0110eeffxxyygguu 1 updated psubc sx,sy,dz sx C sy C dc ? dz 111110********** 10100000xxyyzzzz 1 updated rev. 1.0, 08/99, page 88 of 875 table 2.36 alu integer operation instructions instruction operation instruction code execution states dc bit pdec sx,dz sx upper word C 1 ? dz upper word dz lower word is cleared 111110********** 10001001xx00zzzz 1 updated pdec sy,dz sy upper word C 1 ? dz upper word dz lower word is cleared 111110********** 1010100100yyzzzz 1 updated dct pdec sx,dz if dc = 1, sx upper word C 1 ? dz upper word, dz lower word is cleared if dc = 0, nop 111110********** 10001010xx00zzzz 1 dct pdec sy,dz if dc = 1, sy upper word C 1 ? dz upper word, dz lower word is cleared if dc = 0, nop 111110********** 1010101000yyzzzz 1 dcf pdec sx,dz if dc = 0, sx upper word C 1 ? dz upper word, dz lower word is cleared if dc = 1, nop 111110********** 10001011xx00zzzz 1 dcf pdec sy,dz if dc = 0, sy upper word C 1 ? dz upper word, dz lower word is cleared if dc = 1, nop 111110********** 1010101100yyzzzz 1 pinc sx,dz sx upper word + 1 ? dz upper word dz lower word is cleared 111110********** 10011001xx00zzzz 1 updated pinc sy,dz sy upper word + 1 ? dz upper word dz lower word is cleared 111110********** 1011100100yyzzzz 1 updated dct pinc sx,dz if dc = 1, sx upper word + 1 ? dz upper word, dz lower word is cleared if dc = 0, nop 111110********** 10011010xx00zzzz 1 rev. 1.0, 08/99, page 89 of 875 table 2.36 alu integer operation instructions (cont) instruction operation instruction code execution states dc bit dct pinc sy,dz if dc = 1, sy upper word + 1 ? dz upper word, dz lower word is cleared if dc = 0, nop 111110********** 1011101000yyzzzz 1 dcf pinc sx,dz if dc = 0, sx upper word + 1 ? dz upper word, dz lower word is cleared if dc = 1, nop 111110********** 10011011xx00zzzz 1 dcf pinc sy,dz if dc = 0, sy upper word + 1 ? dz upper word, dz lower word is cleared if dc = 1, nop 111110********** 1011101100yyzzzz 1 rev. 1.0, 08/99, page 90 of 875 table 2.37 msb detection instructions instruction operation instruction code execution states dc bit pdmsb sx,dz msb position of sx data ? dz upper word, dz lower word is cleared 111110********** 10011101xx00zzzz 1 updated pdmsb sy,dz msb position of sy data ? dz upper word, dz lower word is cleared 111110********** 1011110100yyzzzz 1 updated dct pdmsb sx,dz if dc = 1, msb position of sx data ? dz upper word, dz lower word is cleared if dc = 0, nop 111110********** 10011110xx00zzzz 1 dct pdmsb sy,dz if dc = 1, msb position of sy data ? dz upper word, dz lower word is cleared if dc = 0, nop 111110********** 1011111000yyzzzz 1 dcf pdmsb sx,dz if dc = 0, msb position of sx data ? dz upper word, dz lower word is cleared if dc = 1, nop 111110********** 10011111xx00zzzz 1 dcf pdmsb sy,dz if dc = 0, msb position of sy data ? dz upper word, dz lower word is cleared if dc = 1, nop 111110********** 1011111100yyzzzz 1 table 2.38 rounding operation instructions instruction operation instruction code execution states dc bit prnd sx,dz sx + h'00008000 ? dz dz lower word is cleared 111110********** 10011000xx00zzzz 1 updated prnd sy,dz sy + h'00008000 ? dz dz lower word is cleared 111110********** 1011100000yyzzzz 1 updated rev. 1.0, 08/99, page 91 of 875 alu logic operation instructions table 2.39 alu logic operation instructions instruction operation instruction code execution states dc bit pand sx,sy,dz sx & sy ? dz dz lower word is cleared 111110********** 10010101xxyyzzzz 1 updated dct pand sx,sy,dz if dc = 1, sx&sy ? dz, dz lower word is cleared if dc = 0, nop 111110********** 10010110xxyyzzzz 1 dcf pand sx,sy,dz if dc = 0, sx&sy ? dz, dz lower word is cleared if dc = 1, nop 111110********** 10010111xxyyzzzz 1 por sx,sy,dz sx | sy ? dz dz lower word is cleared 111110********** 10110101xxyyzzzz 1 updated dct por sx,sy,dz if dc = 1, sx|sy ? dz, dz lower word is cleared if dc = 0, nop 111110********** 10110110xxyyzzzz 1 dcf por sx,sy,dz if dc = 0, sx|sy ? dz, dz lower word is cleared if dc = 1, nop 111110********** 10110111xxyyzzzz 1 pxor sx,sy,dz sx ^ sy ? dz dz lower word is cleared 111110********** 10100101xxyyzzzz 1 updated dct pxor sx,sy,dz if dc = 1, sx^sy ? dz, dz lower word is cleared if dc = 0, nop 111110********** 10100110xxyyzzzz 1 dcf pxor sx,sy,dz if dc = 0, sx^sy ? dz, dz lower word is cleared if dc = 1, nop 111110********** 10100111xxyyzzzz 1 fixed-point multiply instruction table 2.40 fixed-point multiply instruction instruction operation instruction code execution states dc bit pmuls se,sf,dg se upper word sf ? upper word ? dg 111110********** 0100eeff0000gg00 1 rev. 1.0, 08/99, page 92 of 875 shift operation instructions table 2.41 arithmetic shift operation instructions instruction operation instruction code execution states dc bit psha sx,sy,dz if sy 3 0, sx< rev. 1.0, 08/99, page 93 of 875 table 2.42 logical shift operation instructions instruction operation instruction code execution states dc bit pshl sx,sy,dz if sy 3 0, sx< rev. 1.0, 08/99, page 94 of 875 system control instructions table 2.43 system control instructions instruction operation instruction code execution states dc bit plds dz,mach dz ? mach 111110********** 111011010000zzzz 1 plds dz,macl dz ? macl 111110********** 111111010000zzzz 1 dct plds dz,mach if dc = 1, dz ? mach if dc = 0, nop 111110********** 111011100000zzzz 1 dct plds dz,macl if dc = 1, dz ? macl if dc = 0, nop 111110********** 111111100000zzzz 1 dcf plds dz,mach if dc = 0, dz ? mach if dc = 1, nop 111110********** 111011110000zzzz 1 dcf plds dz,macl if dc = 0, dz ? macl if dc = 1, nop 111110********** 111111110000zzzz 1 psts mach,dz mach ? dz 111110********** 110011010000zzzz 1 psts macl,dz macl ? dz 111110********** 110111010000zzzz 1 dct psts mach,dz if dc = 1, mach ? dz if dc = 0, nop 111110********** 110011100000zzzz 1 dct psts macl,dz if dc = 1, macl ? dz if dc = 0, nop 111110********** 110111100000zzzz 1 dcf psts mach,dz if dc = 0, mach ? dz if dc = 1, nop 111110********** 110011110000zzzz 1 dcf psts macl,dz if dc = 0, macl ? dz if dc = 1, nop 111110********** 110111110000zzzz 1 rev. 1.0, 08/99, page 95 of 875 nopx and nopy instruction codes: when there is no data transfer instruction to be parallel- processed simultaneously with a dsp operation instruction, an nopx or nopy instruction can be written as the data transfer instruction, or the instruction can be omitted. the instruction code is the same whether an nopx or nopy instruction is written or the instruction is omitted. examples of nopx and nopy instruction codes are shown in table 2.44. table 2.44 sample nopx and nopy instruction codes instruction code padd x0, y0, a0 movx. w @r4+, x0 movy.w @r6+r9, y0 1111100000001011 1011000100000111 padd x0, y0, a0 nopx movy.w @r6+r9, y0 1111100000000011 1011000100000111 padd x0, y0, a0 nopx nopy 1111100000000000 1011000100000111 padd x0, y0, a0 nopx 1111100000000000 1011000100000111 padd x0, y0, a0 1111100000000000 1011000100000111 movx. w @r4+, x0 movy.w @r6+r9, y0 1111000000001011 movx. w @r4+, x0 nopy 1111000000001000 movs. w @r4+, x0 1111010010001000 nopx movy.w @r6+r9, y0 1111000000000011 movy.w @r6+r9, y0 1111000000000011 nopx nopy 1111000000000000 nop 0000000000001001 rev. 1.0, 08/99, page 97 of 875 section 3 operating modes 3.1 operating mode selection the sh7065 has ten operating modes. the settings of the mode pins (md5 to md0) determine the mode in which the chip operates. the mode pin settings must not be changed while the chip is operating (while power is being supplied). the method of selecting the operating mode is shown in table 3.1 table 3.1 operating mode selection pin settings operating mode no. mode name fwe md5 md4 md3 md2 md1 * 1 md0 on-chip rom cs0 bus width (bits) 0 single-chip mode 0 used for clock mode selection 0 0 0 enabled 1 mcu mode 1 0 0 0 1 enabled 8/16/32 2 mcu mode 2 0 0 1 0 disabled 32 3 mcu mode 3 0 0 1 1 disabled 16 4 mcu mode 4 0 1 0 0 disabled 8 f0 * 3 user program mode (single- chip) 1 0 0 0 enabled f1 * 3 user program mode 1 0 0 1 enabled 8/16/32 f2 * 3 boot mode (single-chip) 1 0 1 0 enabled f3 * 3 boot mode 1 0 1 1 enabled 8/16/32 f7 * 3 prom mode (programmer mode) * 2 1 1 1 enabled other than the above reserved (do not set) notes: 1. in the f-ztat version, it is possible to change md1 during a power-on reset. 2. 0 or 1 3. f0 to f7 can only be used in the f-ztat version. rev. 1.0, 08/99, page 98 of 875 table 3.2 shows the correspondence between the settings of mode pins md5 to md3 and the clock operating mode. table 3.2 clock operating mode selection mode no. md4 supply source output pll circuit 1 pll circuit 2 initial state of ckio pin initial state of ck pin ckm ckp cke ckio ck initial value of frqcr register 0 1 2 3 4 5 6 7 md5 md3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 extal or crystal resonator ckio, ck on ( 2) on ( 2) on ( 1) on ( 4) off on ( 4) on ( 2) on ( 1) off ckio ck output output hi-z input output output output output 1 4 1 4 1 4 2 1 1 2 1 2 1 2 1 1 1 2 1 4 1 2 1 1 2 2 4 4 4 4 1 1 1 2 1 2 1 2 1 1 h'c0aa h'c045 h'c0aa h'c044 h'40aa h'4045 h'4045 h'4000 pin settings clock i/o initial clock ratio (input clock = 1) rev. 1.0, 08/99, page 99 of 875 3.1.1 operating modes mode 0 (single-chip mode): in single-chip mode any port can be used, but external addresses cannot be used. mode 1 (mcu mode 1): in mode 1, on-chip rom is enabled. the bus width for on-chip rom space is 32 bits. mode 2 (mcu mode 2): in mode 2, external memory space with a 32-bit cs0 space bus width is used. mode 3 (mcu mode 3): in mode 3, external memory space with a 16-bit cs0 space bus width is used. mode 4 (mcu mode 4): in mode 4, external memory space with an 8-bit cs0 space bus width is used. modes f0 and f1 (user program modes): in the user program modes, on-chip flash memory can be programmed, erased, and verified on-board. for details, see section 19, 256 kb flash memory (f-ztat). modes f2 and f3 (boot modes): in the boot modes, on-chip flash memory can be programmed, erased, and verified on-board. for details, see section 19, 256 kb flash memory (f-ztat). mode f7 (prom (programmer) mode): in prom (programmer) mode, on-chip flash memory can be programmed using a prom programmer recommended by hitachi. for details, see section 19, 256 kb flash memory (f-ztat). rev. 1.0, 08/99, page 100 of 875 3.1.2 pin configuration the functions of pins relating to the operating modes are shown in table 3.3. table 3.3 pin functions pin name i/o function md0 input the level at this pin is used in the operating mode specification. md1 input the level at this pin is used in the operating mode specification. md2 input the level at this pin is used in the operating mode specification. md3 input the level at this pin is used in the clock mode specification. md4 input the level at this pin is used in the clock mode specification. md5 input the level at this pin is used in the clock mode specification. fwe input used for hardware protection against on-chip flash memory programming/erasing. in the mask rom version this pin is v ss . 3.1.3 register configuration table 3.4 summarizes the registers relating to the operating modes. table 3.4 registers name abbreviation r/w initial value address access size mode status register msr r h'ffff1020 8, 16, 32 mode control register modecr r/w h'001c h'ffff102a 8, 16, 32 rev. 1.0, 08/99, page 101 of 875 3.2 register descriptions 3.2.1 mode status register (msr) the mode status register (msr) is a 16-bit read-only register used to monitor the operating mode status. bit: 15 14 13 12 11 10 9 8 initial value: undefined undefined undefined undefined undefined undefined undefined undefined r/w:rrrrrrrr bit:76543210 md5 md4 md3 md2 md1 md0 initial value: undefined undefined r/w:rrrrrrrr bits 15 to 6reserved: these bits always return an undefined value when read. bits 5 to 0mode (md5 to md0): these bits indicate the mode pin states in a power-on reset. bits 5 to 0: md5 to md0 description 0 or 1 indicates the mode pin state rev. 1.0, 08/99, page 102 of 875 3.2.2 mode control register (modecr) the mode control register (modecr) is a 16-bit readable/writable register that selects the on- chip rom access mode. modecr is initialized to h'001c by a power-on reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 rommd initial value:00011100 r/w:rrrr/wrrrr bits 15 to 5reserved: these bits are always read as 0 and should only be written with 0. bit 4rom access mode (rommd): selects the on-chip rom access mode. normally, high- speed mode should be used. bit 4: rommd description 0 on-chip rom is accessed in high-speed mode 1 on-chip rom is accessed in low-speed mode (initial value) bits 3 and 2reserved: these bits are always read as 1 and should only be written with 1. bits 1 and 0reserved: these bits are always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 103 of 875 section 4 clock pulse generator (cpg) and power-down modes 4.1 overview the sh7065 has an on-chip clock pulse generator (cpg) which is used to generate the clocks supplied internally and control the power-down modes. in the power-down modes, the operation of the on-chip peripheral modules and cpu, or of all functions, is halted. it is also possible to select a division ratio for the clock supplied to individual modules, even during operation. these features enable power consumption to be reduced. 4.1.1 features the cpg has the following features: eight clock modes any of eight clock operating modes can be selected, differentiated by frequency range, power consumption, and use of a crystal resonator or external clock input. three clocks the cpg can generate independently a master clock (ckm) used by the cpu, etc., a peripheral clock (ckp) used by the peripheral modules, and an external bus clock (cke) used by the external bus interface. frequency modification function pll (phase-locked loop) circuits and frequency dividers in the cpg enable the frequencies of the master clock, peripheral clock, and external bus clock to be changed independently. frequency changes are performed by software in accordance with the settings in the frequency control register (frqcr). the power-down modes include the following modes and functions: power-down mode control it is possible to stop the clock in sleep mode, software standby mode, and hardware standby mode, to stop the clock supply to specific modules with the module standby function, and to divide the frequency of clocks supplied to specific modules with the module clock division function. rev. 1.0, 08/99, page 104 of 875 4.1.2 block diagram of cpg figure 4.1 shows a block diagram of the cpg. master clock (ckm) (max. 60 mhz) peripheral clock (ckp) * (max. 60 mhz) external bus clock (cke) (max. 30 mhz) standby control frequency divider 1 1 1/2 1/4 standby control circuit clock mode/ clock output control circuit standby control register bus interface internal bus frequency control register pll circuit 1 ( 1, 2) pll circuit 2 ( 2, 4) crystal oscillator cpg control unit oscillator circuit ck (max. 60 mhz) ckio (max. 60 mhz) cap2 xtal extal md5 md4 md3 cap1 frequency divider 2 1 1/2 1/4 frequency divider 3 1 1/2 1/4 frequency divider 4 1 1/2 1/4 note: * peripheral clock ckp is divided by the module clock division function before being input to individual modules. the maximum operating frequency of the peripheral modules is 30 mhz. for details, see section 4.14, module clock division function. figure 4.1 block diagram of cpg rev. 1.0, 08/99, page 105 of 875 the function of each of the cpg blocks is described below. pll circuit 1: pll circuit 1 has the function of multiplying the frequency of the clock from the ckio pin or pll circuit 2 by a factor of 1 or 2. the phase of the rising edge of the external bus clock (cke) is controlled so that it matches the phase of the rising edge at the ckio pin. the multiplication factor is determined by the clock operating mode. pll circuit 2: pll circuit 2 has the function of multiplying the frequency of the input clock from the crystal oscillator or extal pin by a factor of 2 or 4. the multiplication factor is determined by the clock operating mode. crystal oscillator: this is the oscillator circuit used when a crystal resonator is connected to the xtal and extal pins. use of the crystal oscillator can be selected by a clock operating mode setting, frequency divider 1: frequency divider 1 has the function of generating the master clock (ckm). the master clock (ckm) operating frequency can be selected from 4, 2, 1, 1/2, or 1/4 times the input clock frequency according to the clock mode. the division ratio is set in the frequency control register. frequency divider 2: frequency divider 2 has the function of generating the peripheral clock (ckp). the peripheral clock (ckp) operating frequency can be selected from 4, 2, 1, 1/2, or 1/4 times the input clock frequency according to the clock mode. the division ratio is set in the frequency control register. frequency divider 3: frequency divider 3 has the function of generating the external bus clock (cke). the external bus clock (cke) operating frequency can be selected from 4, 2, 1, 1/2, or 1/4 times the input clock frequency according to the clock mode. the division ratio is set in the frequency control register. frequency divider 4: frequency divider 4 has the function of generating external clock output (ck). the external clock output (ck) operating frequency can be selected from 4, 2, 1, 1/2, or 1/4 times the input clock frequency according to the clock mode. the division ratio is set in the frequency control register. clock mode/clock output control circuit: the clock mode/clock output control circuit controls the clock mode and the clock output from the ck/ckio pin by means of the frequency control register. standby control circuit: the standby control circuit controls the state of the on-chip oscillator circuit and other modules when the clock is switched and in sleep and standby modes. frequency control register: the frequency control register contains control bits for on/off control of the clock output from the ck/ckio pin, and the frequency division ratios for the master clock, peripheral clock, external bus clock, and clock output. rev. 1.0, 08/99, page 106 of 875 standby control register: the standby control register contains power-down mode control bits. 4.1.3 cpg pin configuration table 4.1 shows the cpg pins and their functions. table 4.1 cpg pins pin name abbreviation i/o function mode control pins md5Cmd3 input set clock operating mode. xtal output connects crystal resonator. crystal input/output pins (clock input pins) extal input connects crystal resonator, or used as external clock input pin. ckio i/o used as external clock input or external clock output pin. in output mode, can be fixed in high-impedance state. clock input/output pin ck output used as external clock output pin. can be fixed in high-impedance state. cap1 input connects capacitance (recommended value: 470 pf) for pll circuit 1 operation. pll capacitance connection pins cap2 input connects capacitance (recommended value: 470 pf) for pll circuit 2 operation. 4.1.4 cpg register configuration table 4.2 shows the cpg register configuration. table 4.2 cpg register name abbreviation r/w initial value address access size frequency control register frqcr r/w depends on clock mode h'ffff 1028 8, 16, 32 rev. 1.0, 08/99, page 107 of 875 4.2 clock operating modes table 4.3 shows the clock operating modes corresponding to various combinations of mode control pin (md5 to md3) settings. table 4.3 clock operating mode settings mode no. md4 supply source output pll circuit 1 pll circuit 2 ckio pin initial state ck pin initial state ckm * 1 ckp * 2 cke * 3 ckio ck frqcr register initial value 0 1 2 3 4 5 6 7 notes: 1. master clock 2. peripheral clock 3. external bus clock md5 md3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 extal or crystal resonator ckio, ck on ( 2) on ( 2) on ( 1) on ( 4) off on ( 4) on ( 2) on ( 1) off ckio ck output output hi-z input output output output output 1 4 1 4 1 4 2 1 1 2 1 2 1 2 1 1 1 2 1 4 1 2 1 1 2 2 4 4 4 4 1 1 1 2 1 2 1 2 1 1 h'c0aa h'c045 h'c0aa h'c044 h'40aa h'4045 h'4045 h'4000 pin settings clock input/output clock ratio initial value (input clock = 1) rev. 1.0, 08/99, page 108 of 875 modes 0 and 1: an external clock is input from the extal pin, or a crystal resonator is connected, and pll circuits 1 and 2 operate. the frequency multiplication factor is fixed at 2 for both pll circuit 1 and pll circuit 2. when the cke clock is multiplied by 2 by means of a setting in the frequency control register (frqcr), a clock in phase with the cke clock is output from the ckio pin. when the cke clock is multiplied by 4, switching of ckio output coincides with the rise of the cke clock. when the cke clock is multiplied by 1, the rise of the ckio output coincides with switching of the cke clock. a clock with the frequency set by frqcr (without phase coordination) is output from the ck pin. the ck pin can be set to the high-impedance state by means of a setting in frqcr. modes 2 and 3: an external clock is input from the extal pin, or a crystal resonator is connected, and pll circuits 1 and 2 operate. the frequency multiplication factor is fixed at 1 for pll circuit 1 and 4 for pll circuit 2. when the cke clock is multiplied by 4 by means of a setting in the frequency control register (frqcr), a clock in phase with the cke clock is output from the ckio pin. when the cke clock is multiplied by 1 or 2, the rise of the ckio output coincides with switching of the cke clock. a clock with the frequency set by frqcr (without phase coordination) is output from the ck pin. the ck pin can be set to the high-impedance state by means of a setting in frqcr. modes 4 and 5: an external clock is input from the extal pin, or a crystal resonator is connected, and pll circuit 2 operates. the frequency multiplication factor is fixed at 4. the ckio pin is in the high-impedance state. pll circuit 1 is off, and phase coordination is not performed. a clock with the frequency set by frqcr (without phase coordination) is output from the ck pin. the ck pin can be set to the high-impedance state and a clock output from the ckio pin by means of settings in frqcr. mode 6: an external clock is input from the ckio pin, and pll circuit 1 operates. the frequency multiplication factor is fixed at 2. pll circuit 2 is off. when the cke clock is multiplied by 1 by means of a setting in frqcr, a cke clock in phase with the ckio pin is output. when the cke clock is multiplied by 1/2, the rise of the ckio output coincides with switching of the cke clock. when the cke clock is multiplied by 2, switching of ckio output coincides with the rise of the cke clock. rev. 1.0, 08/99, page 109 of 875 a clock with the frequency set by frqcr (without phase coordination) is output from the ck pin. the ck pin can be set to the high-impedance state by means of a setting in frqcr. mode 7: an external clock is input from the ckio pin, and pll circuit 1 operates. the frequency multiplication factor is fixed at 1. pll circuit 2 is off. when the cke clock is multiplied by 1 by means of a setting in frqcr, a cke clock in phase with the ckio pin is output. when the cke clock is multiplied by 1/2 or 1/4, the rise of the ckio output coincides with switching of the cke clock. a clock with the frequency set by frqcr (without phase coordination) is output from the ck pin. the ck pin can be set to the high-impedance state by means of a setting in frqcr. 4.3 cpg register description 4.3.1 frequency control register (frqcr) the frequency control register (frqcr) is a 16-bit readable/writable register used for on/off control of clock output from the ckio/ck pin, and specification of the frequency division ratios for the master clock, peripheral clock, external bus clock, and clock output. frqcr is initialized to a value determined by the clock mode in a power-on reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 ckiooeckoe initial value:1000000 r/w:r/wr/wrrrrrr bit:76543210 fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 15ckio output enable (ckiooe): specifies whether the ckio pin outputs a clock or goes to the high-impedance state. the initial value is determined by the clock operating mode. in clock modes 6 and 7, ckio is an input pin, and the initial value of this bit is 0. do not write 0 to this bit in clock operating mode 0, 1, 2, or 3, and do not write 1 in clock operating mode 6 or 7. rev. 1.0, 08/99, page 110 of 875 bit 15: ckiooe description 0 ckio pin goes to high-impedance state (initial value in clock operating modes 4, 5, 6, and 7) 1 ckio pin outputs a clock (initial value in clock operating modes 0, 1, 2, and 3) bit 14ck output enable (ckoe): specifies whether the ck pin outputs a clock or goes to the high-impedance state. bit 14: ckoe description 0 ck pin goes to high-impedance state 1 ck pin outputs a clock (initial value) bits 13 to 8reserved: these bits are always read as 0, and should only be written with 0. bits 7 to 0frequency setting (fr7 to fr0): these bits set the frequency of the master clock (ckm), peripheral clock (ckp), external bus clock (cke), and clock output (ck). the initial value is determined by the clock operating mode. table 4.8 shows settings of fr7 to fr0 and the corresponding frequency ratios of the master clock (ckm), peripheral clock (ckp), external bus clock (cke), clock output (ck), and ckio pin, taking the external input clock frequency as 1. table 4.4 frequency divider 1 control (ckm) fr5 fr4 frequency divider 1 control 00 1 1 1/2 10 1/4 1 do not set table 4.5 frequency divider 2 control (ckp) fr3 fr2 frequency divider 2 control 00 1 1 1/2 10 1/4 1 do not set rev. 1.0, 08/99, page 111 of 875 table 4.6 frequency divider 3 control (cke) fr1 fr0 frequency divider 3 control 00 1 1 1/2 10 1/4 1 do not set table 4.7 frequency divider 4 control (ck pin) fr7 fr6 frequency divider 4 control 00 1 1 1/2 10 1/4 1 do not set rev. 1.0, 08/99, page 112 of 875 table 4.8 (1) fr register values and frequency ratios (input clock = 1) clock modes 0 and 1 fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 00000000 2 2 4 4 4 2 4 4C15 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 0100 2 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 1000 1 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 rev. 1.0, 08/99, page 113 of 875 table 4.8 (1) fr register values and frequency ratios (input clock = 1) (cont) clock modes 0 and 1 (cont) fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 00010000 2 2 2 4 4 2 4 4C15 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 0100 2 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 1000 1 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 rev. 1.0, 08/99, page 114 of 875 table 4.8 (1) fr register values and frequency ratios (input clock = 1) clock modes 0 and 1 (cont) fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 001000002 2 1 4 4 2 4 4C15 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 0100 2 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 1000 1 44 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 rev. 1.0, 08/99, page 115 of 875 table 4.8 (2) fr register values and frequency ratios (input clock = 1) clock modes 2 and 3 fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 000000001 4 4 4 4 4 4 2C15 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 0100 2 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 1000 1 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 rev. 1.0, 08/99, page 116 of 875 table 4.8 (2) fr register values and frequency ratios (input clock = 1) clock modes 2 and 3 (cont) fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 000100001 4 2 4 4 4 4 2C15 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 0100 2 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 1000 1 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 rev. 1.0, 08/99, page 117 of 875 table 4.8 (2) fr register values and frequency ratios (input clock = 1) clock modes 2 and 3 (cont) fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 00100000 1 4 1 4 4 4 4 2C15 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 0100 2 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 1000 1 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 rev. 1.0, 08/99, page 118 of 875 table 4.8 (3) fr register values and frequency ratios (input clock = 1) clock modes 4 and 5 fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 00000000 4 4 4 4 4 4 2C15 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 0100 2 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 1000 1 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 rev. 1.0, 08/99, page 119 of 875 table 4.8 (3) fr register values and frequency ratios (input clock = 1) clock modes 4 and 5 (cont) fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 00010000 4 2 4 4 4 4 2C15 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 0100 2 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 1000 1 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 rev. 1.0, 08/99, page 120 of 875 table 4.8 (3) fr register values and frequency ratios (input clock = 1) clock modes 4 and 5 (cont) fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 00100000 4 1 4 4 4 4 2C15 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 0100 2 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 00 1000 1 4 4 01 2 10 1 00 01 2 4 01 2 10 1 00 10 1 4 01 2 10 1 rev. 1.0, 08/99, page 121 of 875 table 4.8 (4) fr register values and frequency ratios (input clock = 1) clock mode 6 fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 000000002 2 2 2 1 2 4C30 01 1 10 1/2 00 01 1 2 01 1 10 1/2 00 10 1/2 2 01 1 10 1/2 00 0100 1 2 2 01 1 10 1/2 00 01 1 2 01 1 10 1/2 00 10 1/2 2 01 1 10 1/2 00 1000 1/22 2 01 1 10 1/2 00 01 1 2 01 1 10 1/2 00 10 1/2 2 01 1 10 1/2 rev. 1.0, 08/99, page 122 of 875 table 4.8 (4) fr register values and frequency ratios (input clock = 1) clock mode 6 (cont) fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 000100002 1 2 2 1 2 4C30 01 1 10 1/2 00 01 1 2 01 1 10 1/2 00 10 1/2 2 01 1 10 1/2 00 0100 1 2 2 01 1 10 1/2 00 01 1 2 01 1 10 1/2 00 10 1/2 2 01 1 10 1/2 00 1000 1/22 2 01 1 10 1/2 00 01 1 2 01 1 10 1/2 00 10 1/2 2 01 1 10 1/2 rev. 1.0, 08/99, page 123 of 875 table 4.8 (4) fr register values and frequency ratios (input clock = 1) clock mode 6 (cont) fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 001000002 1/22 2 1 2 4C30 01 1 10 1/2 00 01 1 2 01 1 10 1/2 00 10 1/2 2 01 1 10 1/2 00 0100 1 2 2 01 1 10 1/2 00 01 1 2 01 1 10 1/2 00 10 1/2 2 01 1 10 1/2 00 1000 1/22 2 01 1 10 1/2 00 01 1 2 01 1 10 1/2 00 10 1/2 2 01 1 10 1/2 rev. 1.0, 08/99, page 124 of 875 table 4.8 (5) fr register values and frequency ratios (input clock = 1) clock mode 7 fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 000000001 1 1 1 1 1 8C60 01 1/2 10 1/4 00 01 1/2 1 01 1/2 10 1/4 00 10 1/4 1 01 1/2 10 1/4 00 0100 1/21 1 01 1/2 10 1/4 00 01 1/2 1 01 1/2 10 1/4 00 10 1/4 1 01 1/2 10 1/4 00 1000 1/41 1 01 1/2 10 1/4 00 01 1/2 1 01 1/2 10 1/4 00 10 1/4 1 01 1/2 10 1/4 rev. 1.0, 08/99, page 125 of 875 table 4.8 (5) fr register values and frequency ratios (input clock = 1) clock mode 7 (cont) fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 000100001 1/21 1 1 1 8C60 01 1/2 10 1/4 00 01 1/2 1 01 1/2 10 1/4 00 10 1/4 1 01 1/2 10 1/4 00 0100 1/21 1 01 1/2 10 1/4 00 01 1/2 1 01 1/2 10 1/4 00 10 1/4 1 01 1/2 10 1/4 00 1000 1/41 1 01 1/2 10 1/4 00 01 1/2 1 01 1/2 10 1/4 00 10 1/4 1 01 1/2 10 1/4 rev. 1.0, 08/99, page 126 of 875 table 4.8 (5) fr register values and frequency ratios (input clock = 1) clock mode 7 (cont) fr register values clock ratio fr 7 fr 6 fr 5 fr 4 fr 3 fr 2 fr 1 fr 0 pll circuit 1 multipli- cation factor pll circuit 2 multipli- cation factor ckm ckp cke ckio ck clock input frequency range (mhz) 001000001 1/41 1 1 1 8C60 01 1/2 10 1/4 00 01 1/2 1 01 1/2 10 1/4 00 10 1/4 1 01 1/2 10 1/4 00 0100 1/21 1 01 1/2 10 1/4 00 01 1/2 1 01 1/2 10 1/4 00 10 1/4 1 01 1/2 10 1/4 00 1000 1/41 1 01 1/2 10 1/4 00 01 1/2 1 01 1/2 10 1/4 00 10 1/4 1 01 1/2 10 1/4 rev. 1.0, 08/99, page 127 of 875 4.4 changing the frequency changes in the master clock, peripheral clock, external bus clock, and clock output frequencies are controlled by software by means of the frequency control register. the method of changing the frequencies is described below. a frequency change is carried out by writing the required value in bits fr7 to fr0 in the frqcr register. the write to frqcr must be executed by a program in on-chip ram or on-chip rom. also note that the dmac must not be used to access frqcr. if the frequency ratio of m f (the clock resulting from master clock (ckm) division) to cke (the external bus clock) changes as a result of the frequency change, after the change frqcr must be read before making an external cs space access. (the frqcr value read at this time will be undefined.) rev. 1.0, 08/99, page 128 of 875 4.5 output clock control the ckio and ck pins can be switched between clock output and the high-impedance state by means of the ckiooe and ckoe bits in the frqcr register. the initial values depend on the clock mode. table 4.9 shows the correspondence between the clock mode, the state of the ckio and ck pins, and the initial value of the ckiooe and ckoe bits. when the ckiooe and ckoe bits are modified, the ckio or ck output is changed immediately. table 4.9 clock modes, ckio and ck pin states, and initial value of ckiooe and ckoe bits initial pin state * initial value bit value modification clock mode ckio ck ckiooe ckoe ckiooe ckoe 0 external clock output external clock output 1 1 not possible possible 1 external clock output external clock output 1 1 not possible possible 2 external clock output external clock output 1 1 not possible possible 3 external clock output external clock output 1 1 not possible possible 4 high impedance external clock output 0 1 possible possible 5 high impedance external clock output 0 1 possible possible 6 clock input external clock output 0 1 not possible possible 7 clock input external clock output 0 1 not possible possible note: * if hardware standby mode is entered after power is applied without executing a power-on reset, the pin states will be undefined. in this case, the res pin must be driven low in hardware standby mode in order to fix the initial pin states according to the clock mode. when hardware standby mode is entered after a power-on reset, the prior pin states are retained. rev. 1.0, 08/99, page 129 of 875 4.6 oscillator there are two ways of supplying a clock: by connecting a crystal resonator and by inputting an external clock. 4.6.1 connecting a crystal resonator figure 4.2 shows an example of crystal resonator connection. the values of damping resistance rd and load capacitances cl1 and cl2 should be decided after investigating the components in collaboration with the manufacturer of the crystal resonator to be used. the crystal resonator should be an at-cut parallel-resonance type. place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. cl1 cl2 ckio extal xtal rd output or high impedance 4 tbd 10 tbd 15 tbd reference values: cl1 = cl2 = 22pf damping resistance frequency (mhz) rd ( w ) notes: 1. the ckio pin is an output in clock modes 0, 1, 2, and 3, and is high-impedance in clock modes 4 and 5. 2. the values of cl1 and cl2 and damping resistance rd should be decided after consultation with the manufacturer of the crystal resonator to be used. figure 4.2 example of crystal resonator connection rev. 1.0, 08/99, page 130 of 875 4.6.2 external clock input methods an external clock is input from the extal pin or the ckio pin, depending on the clock mode. clock input from extal pin: this method can be used in clock modes 0, 1, 2, 3, 4, and 5. ckio extal xtal output or high-impedance the ckio pin is an output in clock modes 0, 1, 2, and 3, and is high-impedance in clock modes 4 and 5. open external clock input figure 4.3 external clock input method clock input from ckio pin: this method can be used in clock modes 6 and 7. ckio extal xtal open external clock input open figure 4.4 external clock input method rev. 1.0, 08/99, page 131 of 875 4.6.3 notes on board design when using a crystal resonator: place the crystal resonator, capacitors cl1 and cl2, and damping resistance rd as close as possible to the extal and xtal pins. to prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern near these components. extal cl1 cl2 rd xtal avoid crossing signal lines note: the values for cl1, cl2, and the damping resistance should be determined after consultation with the crystal resonator manufacturer. figure 4.5 points for attention when using crystal resonator bypass capacitors: as far as possible, insert a laminated ceramic capacitor of 0.01 to 0.1 f as a bypass capacitor for each v ss /v cc pair. mount the bypass capacitors as close as possible to the sh7065s power supply pins, and use components with a frequency characteristic suitable for the sh7065 operating frequency, as well as a suitable capacitance value. when using pll oscillator circuits: keep the wiring from the pll v cc and v ss connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. ground the oscillation stabilization capacitors c1 and c2 to v ss (pll). place c1 and c2 close to the cap1 and cap2 pins and do not locate a wiring pattern in the vicinity. rev. 1.0, 08/99, page 132 of 875 pllv ss c 2 c 1 pllcap2 pllcap1 pllv cc v ss v cc power supply avoid crossing signal lines bypass capacitor reference values: c1 = (470) pf c2 = (470) pf figure 4.6 points for attention when using pll oscillator circuits table 4.10 capacitance values (for reference) capacitance value mode 0 mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 c1 = 470 pf required required required required not required not required required required c2 = 470 pf required required required required required required not required not required rev. 1.0, 08/99, page 133 of 875 4.7 oscillation stoppage detection function this cpg is provided with a function that automatically places the timer pins in the high- impedance state when it detects clock stoppage to provide for cases where the oscillator halts due to a system error of some kind. if the cpg detects that extal or ckio has not changed due to an oscillator fault, stoppage of the external clock, or a transition to the standby state, it places the 12 mmt (motor management timer) pins pd26/d26/pwob/rxd3, pd25/d25/pvob/txd3, pd24/d24/puob/sck3, pd22/d22/pwoa/sck0, pd21/d21/pvoa/ irq7 , pd20/d20/puoa/ irq6 , pe23/ irq7 /pwob, pe22/ irq6 /pvob, pe21/ irq5 /puob, pe19/ irq3 /pwoa, pe18/ irq2 /pvoa, and pe17/ irq1 /puoa/sck0 in the high-impedance state. (however, pd26/d26/pwob/rxd3, pd25/d25/pvob/txd3, pd24/d24/puob/sck3, pd22/d22/pwoa/sck0, pd21/d21/pvoa/ irq7 , and pd20/d20/puoa/ irq6 go to the high- impedance state only when set as mmt 6-phase output pins by the pfc.) when oscillation stops other than in the standby state, however, other chip operations are undefined. also, when oscillation is restarted after stopping other than in the standby state, chip operations, including those of the above 12 pins, are undefined. a power-on reset must therefore be executed when resuming chip operation. rev. 1.0, 08/99, page 134 of 875 4.8 power-down modes 4.8.1 states in power-down modes table 4.11 shows the conditions for entering the power-down modes from the program execution state, the state of the cpu and peripheral modules in each mode, and the method of exiting each mode. table 4.11 state of cpu and peripheral modules in power-down modes state power- down mode entering conditions cpg cpu cpu registers on-chip memory on-chip peripheral modules pins refresh operations exiting conditions sleep sleep instruction executed while sby bit is 0 in sbycr operating halted held held operating operating refreshing 1. interrupt 2. dma address error 3. power-on reset software standby sleep instruction executed while sby bit is 1 in sbycr halted halted held held halted halted or high impedance self- refreshing 1. nmi interrupt 2. power-on reset hardware standby low-level input to hstby pin halted halted undefined held halted high impedance refreshing not possible high-level input to hstby pin during low-level input to res pin module standby function setting mstp bit to 1 in mstpcr operating operating held held specified modules halted * held or initialized refreshing 1. clearing mstp bit to 0 2. power-on reset module clock division setting mclk bit to 1 in mclkcr clock to module corresponding to mclk bit is further divided from master clock (ckm) or peripheral clock (ckp) set in cpg before being supplied 1. setting mclk bit to initial value 2. power-on reset rev. 1.0, 08/99, page 135 of 875 register configuration: table 4.12 shows the registers used for power-down mode control. table 4.12 power-down mode registers name abbreviation r/w initial value address access size standby control register sbycr r/w h'1f h'ffff 1004 8, 16, 32 module stop control register 1 mstpcr1 r/w h'0000 h'ffff 1030 8, 16, 32 module stop control register 2 mstpcr2 r/w h'0000 h'ffff 1032 8, 16, 32 module clock control register 1 mclkcr1 r/w h'8888 (clock modes 1, 3, 5, 6) h'ffff (clock modes 0, 2, 4, 7) h'ffff 1034 8, 16, 32 module clock control register 2 mclkcr2 r/w h'8888 (clock modes 1, 3, 5, 6) h'ffff (clock modes 0, 2, 4, 7) h'ffff 1036 8, 16, 32 module clock control register 3 mclkcr3 r/w h'8888 (clock modes 1, 3, 5, 6) h'ffff (clock modes 0, 2, 4, 7) h'ffff 1038 8, 16, 32 module clock control register 4 mclkcr4 r/w h'8888 (clock modes 1, 3, 5, 6) h'ffff (clock modes 0, 2, 4, 7) h'ffff 103a 8, 16, 32 module clock control register 5 mclkcr5 r/w h'cccc (clock modes 1, 3, 5, 6) h'ffff (clock modes 0, 2, 4, 7) h'ffff 103c 8, 16, 32 4.8.2 pin configuration table 4.13 shows the pin used for power-down mode control. table 4.13 power-down mode pin pin name abbreviation i/o function hardware standby pin hstby input low-level input to this pin places the chip in the hardware standby state. rev. 1.0, 08/99, page 136 of 875 4.9 register descriptions 4.9.1 standby control register (sbycr) the standby control register (sbycr) is an 8-bit readable/writable register that specifies the power-down mode status. sbycr is initialized to h'1f by a power-on reset, but is not initialized in software standby mode. bit:76543210 sbyhiz initial value:00011111 r/w:r/wr/wrrrrrr bit 7software standby (sby): specifies a transition to software standby mode. the sby bit cannot be set to 1 while the watchdog timer (wdt) is operating (while the timer enable bit (tme) is set to 1 in the watchdog timers timer control/status register (tcsr)). when making a transition to software standby mode, the watchdog timer must be stopped by clearing the tme bit to 0 before the sby bit is set. bit 7: sby description 0 transition to sleep mode on execution of sleep instruction (initial value) 1 transition to software standby mode on execution of sleep instruction bit 6port high impedance (hiz): selects whether specific output pins retain their state or become high-impedance in software standby mode. see appendix b, pin states, for the pins that are controlled. the hiz bit cannot be set to 1 when the tme bit is set to 1 in the watchdog timers tcsr register. to set output pins to the high-impedance state, the tme bit must be cleared to 0 before the hiz bit is set. bit 6: hiz description 0 pin state retained in software standby mode (initial value) 1 pins go to high-impedance state in software standby mode bit 5reserved: this bit is always read as 0 and should only be written with 0. bits 4 to 0reserved: these bits are always read as 1 and should only be written with 1. rev. 1.0, 08/99, page 137 of 875 4.9.2 module stop control registers 1 and 2 (mstpcr1, mstpcr2) module stop control registers 1 and 2 (mstpcr1, mstpcr2) are 16-bit readable/writable registers that specify the module stop mode status. mstpcr1 and mstpcr2 are initialized to h'0000 by a power-on reset, but are not initialized in software standby mode. mstpcr1 bit: 15 14 13 12 11 10 9 8 mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w mstpcr2 bit: 15 14 13 12 11 10 9 8 mstp31 mstp30 mstp29 mstp28 mstp27 mstp26 mstp25 mstp24 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 mstp23 mstp22 mstp21 mstp20 mstp19 mstp18 mstp17 mstp16 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 to 0module stop 31 to 0 (mstp31 to mstp0): these bits specify stoppage of the clock supply to the corresponding modules. see table 4.15 for the correspondence between the register bits and modules. bits 15 to 0: mstp31 to mstp0 description 0 clock is supplied to corresponding module (initial value) 1 clock supply to corresponding module is stopped rev. 1.0, 08/99, page 138 of 875 4.9.3 module clock control registers 1 to 5 (mclkcr1 to mclkcr5) module clock control registers 1 to 5 (mclkcr1 to mclkcr5) are 16-bit readable/writable registers that specify the division ratio for the clocks supplied to the modules. registers mclkcr1 to mclkcr5 are initialized to a value determined by the clock mode in a power-on reset, but are not initialized in software standby mode. mclkcr1 bit: 15 14 13 12 11 10 9 8 mclk 032 mclk 031 mclk 030 mclk 022 mclk 021 mclk 020 initial value:1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit:76543210 mclk 012 mclk 011 mclk 010 mclk 002 mclk 001 mclk 000 initial value:1 1 r/w: r r/w r/w r/w r r/w r/w r/w mclkcr2 bit: 15 14 13 12 11 10 9 8 mclk 072 mclk 071 mclk 070 mclk 062 mclk 061 mclk 060 initial value:1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit:76543210 mclk 052 mclk 051 mclk 050 mclk 042 mclk 041 mclk 040 initial value:1 1 r/w: r r/w r/w r/w r r/w r/w r/w rev. 1.0, 08/99, page 139 of 875 mclkcr3 bit: 15 14 13 12 11 10 9 8 mclk 112 mclk 111 mclk 110 mclk 102 mclk 101 mclk 100 initial value:1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit:76543210 mclk 092 mclk 091 mclk 090 mclk 082 mclk 081 mclk 080 initial value:1 1 r/w: r r/w r/w r/w r r/w r/w r/w mclkcr4 bit: 15 14 13 12 11 10 9 8 mclk 152 mclk 151 mclk 150 mclk 142 mclk 141 mclk 140 initial value:1 1 r/w: r r/w r/w r/w r r/w r/w r/w bit:76543210 mclk 132 mclk 131 mclk 130 mclk 122 mclk 121 mclk 120 initial value:1 1 r/w: r r/w r/w r/w r r/w r/w r/w rev. 1.0, 08/99, page 140 of 875 mclkcr5 bit: 15 14 13 12 11 10 9 8 mclk 191 mclk 190 mclk 181 mclk 180 initial value: 1 1 1 1 r/w: r r r/w r/w r r r/w r/w bit:76543210 mclk 171 mclk 170 mclk 161 mclk 160 initial value: 1 1 1 1 r/w: r r r/w r/w r r r/w r/w bits 15, 11, 7, and 3reserved: these bits are always read as 1 and should only be written with 1. bits 14, 10, 6, and 2reserved (mclkck5 only): these bits are always read as 1 and should only be written with 1. other bitsmodule clock 191 to 000 (mclk191 to mclk000): these bits specify the clock division ratio for the corresponding modules. a clock further divided from the master clock (ckm) or peripheral clock (ckp) set in the frequency control register (frqcr) of the clock pulse generator (cpg) is supplied to the corresponding modules. the initial values depend on the clock mode. see table 4.18 for the correspondence between the register bits and modules. mclk191 to mclk160 bit nn1: mclknn1 bit nn0: mclknn0 description 0 0 clock supplied to module is not divided (initial value in clock modes 1, 3, 5, 6) 1 reserved (do not set) 1 0 clock supplied to module is further divided by 8 1 clock supplied to module is further divided by 64 (initial value in clock modes 0, 2, 4, 7) rev. 1.0, 08/99, page 141 of 875 mclk152 to mclk000 bit nn2: mclknn2 bit nn1: mclknn1 bit nn0: mclknn0 description 000clock supplied to module is not divided (initial value in clock modes 1, 3, 5, 6) 1 clock supplied to module is further divided by 2 1 0 clock supplied to module is further divided by 3 1 clock supplied to module is further divided by 5 100reserved (do not set) 1 reserved (do not set) 1 0 clock supplied to module is further divided by 8 1 clock supplied to module is further divided by 64 (initial value in clock modes 0, 2, 4, 7) 4.10 sleep mode 4.10.1 transition to sleep mode if a sleep instruction is executed when the sby bit in sbycr is cleared to 0, the chip switches from the program execution state to sleep mode. after execution of the sleep instruction, the cpu halts but its register contents are retained. the on-chip peripheral modules continue to operate, and clocks continue to be output from the ckio and ck pins. in sleep mode, external bus release requests are not accepted. the cpu regards the sbycr write as being executed in one cycle, and performs the next processing. however, the write actually takes the number of cycles shown in table 8.12 in section 8, bus state controller (bsc). to ensure that the value written from the cpu to sbycr is reliably reflected in the sleep instruction, either read sbycr or else wait for the number of cycles shown in table 8.12, before executing the sleep instruction. rev. 1.0, 08/99, page 142 of 875 4.10.2 exit from sleep mode sleep mode is exited by means of an interrupt (nmi, irq, irl, or on-chip peripheral module), a dmac address error, a power-on reset, or the hstby pin. exit by interrupt: when an nmi, irq, irl, or on-chip peripheral module interrupt is generated, sleep mode is exited and interrupt exception handling is executed. the interrupt request is not accepted and sleep mode is not exited when the priority level of the generated interrupt is not higher than the interrupt mask level set in the cpus status register (sr), or when an interrupt from an on-chip peripheral module is disabled on the module side. exit by dmac address error: when a dmac address error occurs, sleep mode is exited and dmac address error exception handling is executed. exit by power-on reset: when the res pin is driven low, the sh7065 enters the power-on reset state and exits sleep mode. exit by hstby hstby hstby hstby pin: when the hstby pin is driven low, the sh7065 enters the hardware standby mode state and exits sleep mode. 4.11 software standby mode 4.11.1 transition to software standby mode if a sleep instruction is executed when the sby bit in sbycr is set to 1, the chip switches from the program execution state to software standby mode. in software standby mode, the clock and on-chip peripheral modules halt as well as the cpu, reducing power consumption to an extremely low level. clock output from the ckio and ck pins is also stopped. cpu register contents and data in on-chip ram are retained. some on-chip peripheral module registers are initialized. the state of the peripheral module registers in software standby mode is shown in table 4.14. see appendix b, pin states, for the pin states. the cpu regards the sbycr write as being executed in one cycle, and performs the next processing. however, the write actually takes the number of cycles shown in table 8.12 in section 8, bus state controller (bsc). to ensure that the value written from the cpu to sbycr is reliably reflected in the sleep instruction, either read sbycr or else wait for the number of cycles shown in table 8.12, before executing the sleep instruction. rev. 1.0, 08/99, page 143 of 875 table 4.14 state of registers in software standby mode module initialized registers registers retaining contents interrupt controller (intc) all registers user break controller (ubc) all registers bus state controller (bsc) all registers clock pulse generator (cpg) all registers direct memory access controller (dmac) all registers timer pulse unit (tpu) all registers motor management timer (mmt) all registers watchdog timer (wdt) ovf, wt/it, and tme bits in tcsr register rstcsr register bits cks2 to cks0 in tcsr register tcnt registers serial communication interface (sci) all registers a/d converter (a/d) all registers d/a converter (d/a) all registers compare match timer (cmt) all registers pin function controller (pfc) all registers i/o ports (i/o) all registers power-down mode related modules all registers rev. 1.0, 08/99, page 144 of 875 4.11.2 exit from software standby mode software standby mode is exited by means of a power-on reset or the hstby pin. exit by nmi interrupt: when a falling edge or rising edge (as selected with the nmi edge select bit (nmie) in interrupt control register 1 (icr1) of the interrupt controller (intc)) is detected in the nmi signal, clock oscillation is started. this clock is supplied only to the watchdog timer (wdt). when the time set in the clock select bits (cks2 to cks0) in the wdts timer control/status register (tcsr) before entering software standby mode has elapsed, wdt overflow occurs. this overflow is taken as an indication that the clock has settled, and the clock is then supplied to the entire chip. software standby mode is thus exited and nmi exception handling is begun. when exiting software standby mode by means of an nmi interrupt, set bit cks2 to cks0 so that the wdt overflow period is at least as long as the oscillation settling time. when exiting software standby mode with the nmi pin designated for falling edge detection, ensure that the nmi pin level goes high when software standby mode is entered (when the clock is stopped) and low when recovering from software standby mode (when the clock is restarted after the oscillation settling time). when exiting software standby mode with the nmi pin designated for rising edge detection, ensure that the nmi pin level goes low when software standby mode is entered (when the clock is stopped) and high when recovering from software standby mode (when the clock is restarted after the oscillation settling time). exit by power-on reset: when the res pin is driven low, the sh7065 enters the power-on reset state and exits software standby mode. the res pin must be held low until clock oscillation settles. exit by hstby hstby hstby hstby pin: when the hstby pin is driven low, the sh7065 enters the hardware standby mode state and exits software standby mode. rev. 1.0, 08/99, page 145 of 875 4.11.3 software standby mode application example in the following example, software standby mode is entered at a falling edge on the nmi pin, and exited at a rising edge. the timing for this example is shown in figure 4.7. when the nmi pin level changes from high to low while the nmi edge select bit (nmie) is cleared to 0 (falling edge detection) in the interrupt control register 1 (icr1), an nmi interrupt is accepted. when the nmie bit is set to 1 (rising edge detection), the standby bit (sby) in the standby control register is set to 1, and a sleep instruction is executed in the nmi exception service routine, a transition is made to standby mode. when the nmi pin level is subsequently changed from low to high, software standby mode is exited. oscillator ck nmi nmie sby nmi exception handling exception service routine sby = 1 sleep instruction standby mode oscillation start time wdt set time nmi exception handling oscillation settling time figure 4.7 nmi timing in standby mode (application example) rev. 1.0, 08/99, page 146 of 875 4.12 hardware standby mode 4.12.1 transition to hardware standby mode regardless of its current state, the chip enters hardware standby mode whenever the hstby pin is driven low. hardware standby mode reduces power consumption drastically by resetting and halting all functions. as long as the specified voltage is supplied, on-chip ram data is retained. however, on-chip ram contents may be lost if an access to on-chip ram has been initiated when the hardware standby state is entered. to retain ram contents, the clock supply to ram should be halted with the module standby function before entering the hardware standby state. i/o ports are placed in the high-impedance state. the level of the mode pins (md5 to md0) should not be changed during hardware standby mode. 4.12.2 exit from hardware standby mode hardware standby mode is exited by means of the hstby and res pins. when hstby is driven high while res is low, the power-on reset state is entered and hardware standby mode is exited. the res pin must be held low until clock oscillation settles. 4.12.3 hardware standby mode timing figure 4.8 shows the timing relationships for hardware standby mode. to enter hardware standby mode, first drive res low, then drive hstby low. to exit hardware standby mode, first drive hstby high, wait for the clock to settle, then bring res from low to high. rev. 1.0, 08/99, page 147 of 875 oscillator oscillation settling time reset exception handling figure 4.8 hardware standby mode timing 4.13 module standby function 4.13.1 transition to module standby function setting an mstp bit to 1 in module stop mode control register 1 or 2 (mstpcr1, mstpcr2) enables the clock supply to the corresponding on-chip peripheral module to be halted. use of this function allows power consumption to be reduced in normal operation and in sleep mode. the correspondence between the mstp bits and on-chip peripheral modules is shown in table 4.15. in the module standby state, the sci and a/d registers are initialized. other registers retain their states prior to halting of the module. registers of modules set to the module standby state cannot be read or written to. rev. 1.0, 08/99, page 148 of 875 table 4.15 mstp bits and corresponding on-chip peripheral modules bit description mstp31 x-ram and y-ram mstp30 on-chip rom mstp29 mstp28 user break controller (ubc) mstp27 direct memory access controller (dmac) mstp26 mstp25 mstp24 mstp23 mstp22 mstp21 mstp20 mstp19 mstp18 mstp17 mstp16 mstp15 serial communication interface (sci) channel 0 mstp14 serial communication interface (sci) channel 1 mstp13 serial communication interface (sci) channel 2 mstp12 mstp11 compare match timer (cmt) mstp10 mstp9 motor management timer (mmt) mstp8 port output enable (poe) mstp7 timer pulse unit (tpu) mstp6 a/d converter (a/d) mstp5 d/a converter (d/a) mstp4 mstp3 mstp2 mstp1 mstp0 note: bits to which an on-chip peripheral module is not assigned must be written with 0. rev. 1.0, 08/99, page 149 of 875 4.13.2 exit from module standby function the module standby function is exited by clearing the mstp bits to 0, or by a power-on reset. when the x-ram/y-ram or on-chip rom module standby function is exited by modification of the module stop control register (mstpcr2), following the register modification at least one mstpcr2 register read must be performed before the above memory is accessed. 4.14 module clock division function 4.14.1 clock definitions definitions of the clocks used by the sh7065 are given in tables 4.16 and 4.17, and figure 4.9. table 4.16 definitions of internal clocks abbreviation name ckm master clock ckp peripheral clock cke external bus clock table 4.17 definitions of divided clocks abbreviation name m f clock supplied to modules after division of master clock (ckm) p f clock supplied to modules after division of peripheral clock (ckp) rev. 1.0, 08/99, page 150 of 875 1 1/8 1/64 1 1/2 1/3 1/5 1/8 1/64 m f (cpu) (wdt) (dmac) (rom) (x-ram) (y-ram) (ubc) ckp ckm p f (sci0) (sci1) (sci2) (cmt) (mmt) (poe) (tpu) (a/d) (d/a) figure 4.9 divided clocks and corresponding modules 4.14.2 transition to module clock division function setting mclk bits in module clock control registers 1 to 5 (mclkcr1 to mclkcr5) supplies a clock obtained by further division of the master clock (ckm) or peripheral clock (ckp) set in the frequency control register (frqcr) of the clock pulse generator (cpg) to the corresponding module. use of this function allows power consumption to be reduced during normal operation. the correspondence between the mclk bits and on-chip peripheral modules is shown in table 4.18. rev. 1.0, 08/99, page 151 of 875 table 4.18 mclk bits and corresponding on-chip peripheral modules bit * 1 description maximum operating frequency mclk191C190 cpu * 2 60 mhz mclk181C180 mclk171C170 mclk161C160 mclk152C150 serial communication interface (sci) channel 0 30 mhz mclk142C140 serial communication interface (sci) channel 1 30 mhz mclk132C130 serial communication interface (sci) channel 2 30 mhz mclk122C120 mclk112C110 compare match timer (cmt) 30 mhz mclk102C100 mclk092C090 motor management timer (mmt) 30 mhz mclk082C080 port output enable (poe) 30 mhz mclk072C070 timer pulse unit (tpu) 30 mhz mclk062C060 a/d converter (a/d) 30 mhz (high-speed mode) 20 mhz (low-speed mode) mclk052C050 d/a converter (d/a) 30 mhz mclk042C040 mclk032C030 mclk022C020 mclk012C010 mclk002C000 notes: 1. including the dmac, rom, x-ram, y-ram, ubc, and wdt. 2. bits to which a module is not assigned must be written with their initial value. rev. 1.0, 08/99, page 152 of 875 4.14.3 exit from module clock division function the module clock division function is exited by setting the mclk bits. 4.14.4 notes on use of module clock division function 1. the module clock division ratio is changed by writing the required value in the mclk bits in the mclkcr register. the write to mclkcr must be executed by a program in on-chip ram or on-chip rom. also note that the dmac must not be used to access mclkcr. if the frequency ratio of m f (the clock resulting from master clock (ckm) division) to cke (the external bus clock) changes as a result of the frequency change, after the change the mclkcr5 register must be read before ? an external space access, or ? a transition to sleep mode. (the mclkcr5 register value read at this time will be undefined.) when changing p f (the clock resulting from peripheral clock (ckp) division), after the change a register in the module corresponding to the changed p f must be read before ? accessing a register in the module corresponding to the changed p f , ? entering the module standby state for the module corresponding to the changed p f , ? changing the changed p f again, or ? entering software standby mode. (the register value read at this time will be undefined.) 2. ensure that ckm, ckp, cke, and m f and p f supplied to the modules, do not exceed their maximum frequency while the setting is being made. 3. immediately after the value of the mclk bits is changed, the module corresponding to the changed m f or p f will temporarily enter the module standby state. therefore, when an mclk bit value corresponding to the sci or a/d converter is changed, the sci or a/d converter registers are initialized. however, there is no temporary transition to the module standby state if the same value is written to the mclk bits. 4. do not set a combination that gives a division ratio of m f :cke = 1/8:1/4 (taking the clock input to dividers 1 to 4 in the cpg as 1); that is, a combination giving a cpg division setting of ckm:cke = 1:1/4, and a module clock division setting of ckm:m f = 1:1/8. rev. 1.0, 08/99, page 153 of 875 section 5 exception handling 5.1 overview 5.1.1 exception handling types and priority as table 5.1 indicates, exception handling may be caused by a reset, address error, interrupt, or instruction. exception handling is prioritized as shown in table 5.1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. table 5.1 exception types and priority exception handling priority reset power-on reset cpu address error address errors dmac address error nmi user break external interrupt (irq/irl) direct memory access controller (dmac) bus state controller (bsc) watchdog timer (wdt) timer pulse unit (tpu) serial communication interface (sci) compare match timer (cmt) a/d converter (a/d) interrupts on-chip peripheral modules motor management timer (mmt) trap instruction (trapa instruction) general illegal instruction (undefined code) instructions slot illegal instruction (undefined code or instruction that modifies pc * 1 located immediately after delayed branch instruction * 2 ) high - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? low notes: 1. instructions that modify pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf 2. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf rev. 1.0, 08/99, page 154 of 875 5.1.2 timing of exception source detection and start of exception handling table 5.2 shows the timing of detection and the start of exception handling for each exception source. table 5.2 exception source detection and exception handling start timing exception type source detection and start of exception handling reset power-on reset started immediately after low-to-high transition at res pin address error interrupt detected when instruction is decoded; exception handling is started after completion of currently executing instruction trap instruction started by execution of trapa instruction general illegal instruction started when undefined code not in a delayed branch instruction (delay slot) is decoded instruction slot illegal instruction started when undefined code or instruction that modifies pc located in a delayed branch instruction (delay slot) is decoded when exception handling is initiated, the cpu operates as follows. power-on reset exception handling: the initial values of the program counter (pc) and stack pointer (sp) are fetched from exception vector table addresses h'00000000 and h'00000004, respectively. see section 5.1.3, exception vector table, for details of the exception vector table. next, the vector base register (vbr) is cleared to 0 and the interrupt mask bits (i3 to i0) in the status register (sr) are set to 1111. program execution starts from the pc address fetched from the exception vector table. address error, interrupt, or instruction exception handling: sr and pc are saved on the stack indicated by r15. in the case of interrupt exception handling, the interrupt priority level is written to the interrupt mask bits (i3 to i0) in sr. in address error and instruction exception handling, bits i3 to i0 are not affected. next, the start address is fetched from the exception vector table and program execution starts from that address. 5.1.3 exception vector table before exception handling is executed, the exception vector table must have been set up in memory. the exception vector table holds the start addresses of the exception service routines (the reset exception handling table holds the initial values of pc and sp. a different vector number and vector table address offset are assigned to each exception source. the vector table address is calculated from the corresponding vector number and vector table address offset. in exception handling, the start address of the exception service routine is fetched from the exception vector table entry indicated by this vector table address. rev. 1.0, 08/99, page 155 of 875 the vector numbers and vector table address offsets are shown in table 5.3, and the method of calculating the vector table address in table 5.4. table 5.3 exception vector table exception source vector number vector table address offset power-on reset pc 0 h'00000000Ch'00000003 sp 1 h'00000004Ch'00000007 (reserved for system) pc 2 h'00000008Ch'0000000b sp 3 h'0000000cCh'0000000f general illegal instruction 4 h'00000010Ch'00000013 (reserved for system) 5 h'00000014Ch'00000017 slot illegal instruction 6 h'00000018Ch'0000001b (reserved for system) 7 h'0000001cCh'0000001f 8 h'00000020Ch'00000023 cpu address error 9 h'00000024Ch'00000027 dmac address error 10 h'00000028Ch'0000002b interrupt (reserved for system) 11 h'0000002cCh'0000002f nmi 12 h'00000030Ch'00000033 user break 13 h'00000034Ch'00000037 (reserved for system) 14 to 31 h'00000038Ch'0000003b to h'0000007cCh'0000007f trap instruction (user vector) 32 to 63 h'00000080Ch'00000083 to h'000000fcCh'000000ff interrupt irq0 64 h'00000100Ch'00000103 irq1, irl1 65 h'00000104Ch'00000107 irq2, irl2 66 h'00000108Ch'0000010b irq3, irl3 67 h'0000010cCh'0000010f irq4 80 h'00000140Ch'00000143 irq5 81 h'00000144Ch'00000147 irq6 82 h'00000148Ch'0000014b irq7 83 h'0000014cCh'0000014f rev. 1.0, 08/99, page 156 of 875 table 5.3 exception vector table (cont) exception source vector number vector table address offset interrupt (reserved for system) 84 h'00000150Ch'00000153 85 h'00000154Ch'00000157 86 h'00000158Ch'0000015b 87 h'0000015cCh'0000015f 88 h'00000160Ch'00000163 89 h'00000164Ch'00000167 90 h'00000168Ch'0000016b 91 h'0000016cCh'0000016f irl4 to irl15 * 1 68 to 79 h'00000110Ch'00000113 to h'0000013cCh'0000013f (reserved for system) 92 to 127 h'00000170Ch'00000173 to h'000001fcCh'000001ff on-chip peripheral module * 2 128 to 255 h'00000200Ch'00000203 to h'000003fcCh'000003ff notes: 1. for the vector numbers and vector table offsets of external interrupts irl4 and irl5, see table 6.3, irl interrupt priority levels and auto vector numbers, in section 6, interrupt controller. 2. for the vector numbers and vector table offsets of on-chip peripheral module interrupts, see table 6.6, internal module interrupt exception handling vectors and priority order, in section 6, interrupt controller (intc). table 5.4 exception vector table address calculation exception source vector table address calculation reset vector table address = (vector table address offset) = (vector number) 4 address error, interrupt, instruction vector table address = vbr + (vector table address offset) = vbr + (vector number) 4 note: vbr: vector base register vector table address offset: see table 5.3. vector number: see table 5.3. rev. 1.0, 08/99, page 157 of 875 5.2 power-on reset when the res pin is driven low, the sh7065 enters the power-on reset state. to ensure that the sh7065 is properly reset, the res pin must be held low for at least the oscillation settling time when powering on or when in standby mode (when the clock is stopped), or at least 40 tcyc (of the slowest module clock) when the clock is running. in the power-on reset state, the internal state of the cpu and all on-chip peripheral module registers are initialized. see appendix b, pin states, for the pin states in the power-on reset state. when the res pin is driven high after being held low for the necessary time in the power-on reset state, power-on reset exception handling is started. cpu operations are as follows. 1. the initial value of the program counter (pc) (i.e. the execution start address) is fetched from the exception vector table. 2. the initial value of the stack pointer (sp) is fetched from the exception vector table. 3. the vector base register (vbr) is cleared to h'00000000, and the interrupt mask bits (i3 to i0) in the status register (sr) are set to h'f (1111). 4. the values fetched from the exception vector table are set in the program counter (pc) and stack pointer (sp), and program execution is started. power-on reset processing must always be executed when the system is powered on. rev. 1.0, 08/99, page 158 of 875 5.3 address errors 5.3.1 address error sources address errors occur in instruction fetches and data read/write accesses, as shown in table 5.5. table 5.5 bus cycles and address errors bus cycle type bus master bus cycle operation address error occurrence instruction fetched from even address no error (normal) instruction fetched from odd address address error instruction fetched from other than on-chip peripheral module space * no error (normal) instruction fetched from on-chip peripheral module space * address error instruction fetch cpu instruction fetched from external memory space in single-chip mode address error word data accessed from even address no error (normal) word data accessed from odd address address error longword data accessed from longword boundary no error (normal) longword data accessed from other than longword boundary address error word data or byte data accessed in on-chip peripheral module space * no error (normal) longword data accessed in 16-bit on-chip peripheral module space * no error (normal) longword data accessed in 8-bit on-chip peripheral module space * no error (normal) data read/write cpu or dmac external memory space accessed in single- chip mode address error note: * for details of the on-chip peripheral module space, see section 8, bus state controller (bsc). rev. 1.0, 08/99, page 159 of 875 5.3.2 address error exception handling when an address error occurs, the cpu starts address error exception handling as shown below after the end of the bus cycle in which the error occurred and completion of the currently executing instruction. 1. the status register (sr) is saved on the stack. 2. the program counter (pc) is saved on the stack. the pc value saved is the start address of the instruction following the last instruction executed. 3. the exception service routine start address is fetched from the exception vector table entry corresponding to the address error, and program execution starts from that address. the jump in this case is not a delayed branch. 5.4 interrupts 5.4.1 interrupt sources interrupt exception handling can be initiated by nmi, a user break, irq, or an on-chip peripheral module, as shown in table 5.6. table 5.6 interrupt sources type request source nmi nmi pin (external input) user break user break controller irq, irl pins irq0 to irq7 (external input) on-chip peripheral module direct memory access controller timer pulse unit compare match timer a/d converter serial communication interface watchdog timer bus state controller motor management timer each interrupt source is assigned a different vector number and vector table offset. for details of vector numbers and vector table address offsets, see section 6.2.5, interrupt exception vectors and priority. rev. 1.0, 08/99, page 160 of 875 5.4.2 interrupt priority interrupt sources are assigned priority levels. if a number of interrupts occur simultaneously (multiple interruption), the priority order is determined by the interrupt controller (intc) and exception handling is initiated accordingly. interrupt source priority levels are expressed as values from 0 to 16, with 0 representing the lowest priority level and 16 as the highest. the nmi interrupt is the highest-priority interrupt at level 16; it cannot be masked and is always accepted. the user break interrupt is assigned priority level 15. the priority level of irq interrupts and on-chip peripheral module interrupts can be set as desired in the intcs interrupt priority registers a to l (ipra to iprl) (see table 5.7). priority levels 0 to 15, but not 16, can be set. for details of ipra to iprl, see section 6.3.1, interrupt priority registers a to l (ipra to iprl). table 5.7 interrupt priority levels type priority level notes nmi 16 fixed priority level, not maskable user break 15 fixed priority level irq, irl on-chip peripheral module 0 to 15 can be set in interrupt priority registers a to l (ipra to iprl) 5.4.3 interrupt exception handling when an interrupt occurs, its priority is determined by the interrupt controller (intc). nmi is always accepted, but other interrupts are only accepted if their priority level is higher than the priority level set in the interrupt mask bits (i3 to i0) in the status register (sr). when an interrupt is accepted, interrupt exception handling is started. in interrupt exception handling, the cpu saves sr and the program counter (pc) on the stack and writes the priority level of the accepted interrupt to bits i3 to i0 in sr. in the case of nmi, however, although its priority level is 16, h'f (level 15) is written to bits i3 to i0. next, the cpu fetches the exception service routine start address from the exception vector table entry corresponding to the accepted interrupt, jumps to that address, and starts executing the exception service routine. for details of interrupt exception handling, see section 6.4, operation. rev. 1.0, 08/99, page 161 of 875 5.5 instruction exceptions 5.5.1 types of instruction exception there are three kinds of instruction that can initiate exception handling: the trap instruction, slot illegal instructions, and general illegal instructions, these are summarized in table 5.8. table 5.8 instruction exception types type source instructions notes trap instruction trapa slot illegal instruction undefined code or instruction that modifies pc located immediately after delayed branch instruction (in delay slot) delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf instructions that modify pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf general illegal instruction undefined code other than in delay slot 5.5.2 trap instruction when a trapa instruction is executed, trap instruction exception handling is started. the cpu operates as follows. 1. the status register (sr) is saved on the stack. 2. the program counter (pc) is saved on the stack. the pc value saved is the start address of the instruction following the trap instruction. 3. the exception service routine start address is fetched from the exception vector table entry corresponding to the vector number specified by the trapa instruction, a jump is made to that address, and program execution starts from that point. the jump in this case is not a delayed branch. rev. 1.0, 08/99, page 162 of 875 5.5.3 slot illegal instructions an instruction located immediately after a delayed branch instruction is said to be located in the delay slot. if the instruction in the delay slot is undefined code, slot illegal instruction exception handling is started when that undefined code is decoded. also, if the instruction in the delay slot is one that modifies the program counter (pc), slot illegal instruction exception handling is started when that instruction is decoded. cpu operations in slot illegal instruction exception handling are as follows. 1. the status register (sr) is saved on the stack. 2. the program counter (pc) is saved on the stack. the pc value saved is the jump destination address of the delayed branch instruction immediately preceding the undefined code or pc- modifying instruction. 3. the exception service routine start address is fetched from the exception vector table entry corresponding to the generated exception, a jump is made to that address, and program execution starts from that point. the jump in this case is not a delayed branch. 5.5.4 general illegal instructions when undefined code located other than immediately after a delayed branch instruction (in a delay slot) is decoded, general illegal instruction exception handling is started. the cpu follows the same procedure as in the case of slot illegal instruction exception handling, except that the program counter (pc) value saved is the start address of the undefined code. rev. 1.0, 08/99, page 163 of 875 5.6 cases in which exceptions are not accepted there are cases, as shown in table 5.9, in which, if an address error or interrupt occurs after a delayed branch instruction or an interrupt for which interruption is prohibited, the exception is not accepted immediately, but is held pending. in such cases, the address error or interrupt will be accepted when an instruction for which exception acceptance is permitted is decoded. table 5.9 exception occurrence: special cases exception source point of occurrence address error interrupt immediately after a delayed branch instruction * 1 not accepted not accepted immediately after an instruction for which interruption is prohibited * 2 accepted not accepted repeat loop comprising up to three instructions (instruction fetch cycle not generated) first instruction or last three instructions in a repeat loop containing four or more instructions not accepted not accepted fourth from last instruction in a repeat loop containing four or more instructions accepted not accepted notes: 1. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf 2. instructions for which interruption is prohibited: ldc, ldc.l, stc, stc.l, lds, lds.l, sts, sts.l 5.6.1 after a delayed branch instruction when an instruction located immediately after a delayed branch instruction (i.e. in the delay slot) is decoded, neither an address error nor an interrupt is accepted. as a delayed branch instruction and the instruction located immediately after it (in the delay slot) are always executed consecutively, exception handling is not initiated during this period. 5.6.2 after an instruction for which interruption is prohibited when the instruction immediately following an instruction for which interruption is prohibited is decoded, an interrupt is not accepted. however, an address error exception is accepted. rev. 1.0, 08/99, page 164 of 875 5.6.3 instructions in repeat loops if a repeat loop comprises up to three instructions, neither exceptions nor interrupts are accepted. if a repeat loop contains four or more instructions, neither exceptions nor interrupts are accepted during the execution cycle of the first instruction or the last three instructions. if a repeat loop contains four or more instructions, address errors only are accepted during the execution cycle of the fourth from last instruction. for more information, see the sh-1/sh-2/sh-dsp programming manual. a. all interrupts and address errors are accepted. b. address errors only are accepted. c. no interrupts or address errors are accepted. when rc > = 1 ; operation depends on the number of instructions in the repeat loop, as follows. when rc = 0 ; all interrupts and address errors are accepted. 1. one instruction ? a ? b ? c ? a instr0 instr1 instr2 start (end): 4. four or more instructions ? a ? a or c (on return from instr n) ? a : ? a ? b ? c ? c ? c ? a instr0 instr1 : : instr n-3 instr n-2 instr n-1 instr n instr n+1 start: end: 2. two instructions ? a ? b ? c ? c ? a instr0 instr1 instr2 instr3 start: end: 3. three instructions ? a ? b ? c ? c ? c ? a instr0 instr1 instr2 instr3 instr4 start: end: figure 5.1 restrictions on interrupt acceptance in repeat mode rev. 1.0, 08/99, page 165 of 875 5.7 stack status after exception handling table 5.10 shows the stack after completion of exception handling. table 5.10 stack status after exception handling type stack status address error 32 bits 32 bits sr address of instruction following executed instruction sp trap instruction 32 bits 32 bits sr address of instruction following trapa instruction sp general illegal instruction 32 bits 32 bits sr start address of illegal instruction sp interrupt 32 bits 32 bits sr address of instruction following executed instruction sp slot illegal instruction 32 bits 32 bits sr jump destination address of delayed branch instruction sp rev. 1.0, 08/99, page 166 of 875 5.8 usage notes 5.8.1 stack pointer (sp) value ensure that the stack pointer (sp) value is a multiple of 4. if it is not, an address error will be caused when the stack is accessed in exception handling. 5.8.2 vector base register (vbr) value ensure that the vector base register (vbr) value is a multiple of 4. if it is not, an address error will be caused when the stack is accessed in exception handling. 5.8.3 address errors occurring in address error exception handling stacking if the stack pointer (sp) value is not a multiple of 4, an address error will occur in exception handling (interrupt, etc.) stacking, and after the exception handling is completed, address error exception handling will be started. an address error will also occur in stacking in the address error exception handling, but this address error will not be accepted in order to prevent endless stacking due to address errors. this enables program control to be switched to the address error exception service routine, and error handling to be carried out. when an address error occurs in exception handling stacking, the stacking bus cycle (write) is executed. in status register (sr) and program counter (pc) stacking, sp is decremented by 4 in each case, and therefore the sp value is not a multiple of 4 after stacking is completed. also, the address value output in stacking is the sp value, and the actual address at which the error occurred is output. in this case, the stacked write data is undefined. rev. 1.0, 08/99, page 167 of 875 section 6 interrupt controller (intc) 6.1 overview the interrupt controller (intc) ascertains the priority of interrupt sources and controls interrupt requests to the cpu. the intc registers set the order of priority of each interrupt, allowing the user to handle interrupt requests according to a user-set priority order. 6.1.1 features the intc has the following features. two external interrupt modes ? irq mode eight external signals comprise independent interrupt sources ( irq7 to irq0 ). each interrupt source has an interrupt vector, and can be assigned a priority level. ? irl mode four external interrupt signals ( irq3 to irq0 ) can be assigned a priority level from 1 to 15. external interrupt signals irq4 to irq7 function as independent interrupt sources. 16 interrupt priority levels using 12 interrupt priority registers, one of 15 priority levels can be assigned to each irq interrupt and on-chip peripheral module interrupt source. priority level 16 is automatically assigned to the nmi interrupt. nmi noise canceler function an nmi input level bit is provided to indicate the nmi pin state. the pin state can be checked by reading this bit in the interrupt exception service routine, enabling it to be used as a noise canceler. interrupt occurrence can be reported externally ( irqout pin) when the sh7065 has released the bus, for example, this function can be used to report interrupt generation to an external bus master, and request the bus. rev. 1.0, 08/99, page 168 of 875 6.1.2 block diagram figure 6.1 shows a block diagram of the intc. irqout nmi irq7Cirq0 ubc dmac tpu cmt sci wdt bsc a/d mmt poe (i/o) i/o control priority determination com- parator ipraCiprl cpu sr isr ipr bus interface interrupt request intc i3 i2 i1 i0 peripheral bus module bus ubc: user break controller dmac: direct memory access controller tpu: timer pulse unit cmt: compare match timer sci: serial communication interface wdt: watchdog timer bsc: bus state controller (dram refresh control unit) a/d: a/d converter mmt: motor management timer icr1, icr2: interrupt control registers 1 and 2 isr: irq status register ipra to iprl: interrupt priority registers a to l sr: status register poe (i/o): port output enable icr1, 2 figure 6.1 block diagram of intc rev. 1.0, 08/99, page 169 of 875 6.1.3 pin configuration table 6.1 shows the intc pin configuration. table 6.1 intc pins pin name i/o function nmi input input of nonmaskable interrupt request signal irq7 C irq0 input input of maskable interrupt request signals irqout output output of signal indicating interrupt source occurrence 6.1.4 register configuration the intc has the 15 registers shown in table 6.2. the functions of these registers include interrupt priority level setting and control of external interrupt input signal detection. table 6.2 intc registers name abbreviation r/w initial value address access size interrupt priority register a ipra r/w h'0000 h'ffff 1050 8, 16, 32 interrupt priority register b iprb r/w h'0000 h'ffff 1052 8, 16, 32 interrupt priority register c iprc r/w h'0000 h'ffff 1054 8, 16, 32 interrupt priority register d iprd r/w h'0000 h'ffff 1056 8, 16, 32 interrupt priority register e ipre r/w h'0000 h'ffff 1058 8, 16, 32 interrupt priority register f iprf r/w h'0000 h'ffff 105a 8, 16, 32 interrupt priority register g iprg r/w h'0000 h'ffff 105c 8, 16, 32 interrupt priority register h iprh r/w h'0000 h'ffff 105e 8, 16, 32 interrupt priority register i ipri r/w h'0000 h'ffff 1060 8, 16, 32 interrupt priority register j iprj r/w h'0000 h'ffff 1062 8, 16, 32 interrupt priority register k iprk r/w h'0000 h'ffff 1064 8, 16, 32 interrupt priority register l iprl r/w h'0000 h'ffff 1066 8, 16, 32 interrupt control register 1 icr1 r/w * 1 h'ffff 106e 8, 16, 32 interrupt control register 2 icr2 r/w h'0000 h'ffff 1070 8, 16, 32 irq status register isr r/(w) * 2 h'0000 h'ffff 1072 8, 16, 32 notes: 1. bit 15 (nmil) indicates the level of the signal being input to the nmi pin. for details, see section 6.3.2, interrupt control register 1 (icr1). 2. see section 6.3.4, irq status register (isr), for details. rev. 1.0, 08/99, page 170 of 875 6.2 interrupt sources there are four types of interrupt sources: nmi, user break, irq/irl, and on-chip peripheral modules. each interrupt has a priority level (0 to 16), with level 0 as the lowest and level 16 as the highest. if level 0 is set, the interrupt is masked. 6.2.1 nmi interrupt the nmi interrupt has the highest priority level of 16, and is always accepted. input from the nmi pin is edge-detected. the nmi edge select bit (nmie) in the interrupt control register 1 (icr1) is used to select either rising or falling edge detection. nmi interrupt exception handling sets the interrupt mask bits (i3 to i0) in the status register (sr) to 15. the nmi pin level is set in the nmil bit in the interrupt control register (icr). interrupt requests resulting from erroneous edge detection due to noise can be avoided by referencing the nmil bit in the interrupt exception service routine. 6.2.2 user break interrupt the user break interrupt is requested when a break condition set in the user break controller (ubc) occurs. its priority level is 15. a user break interrupt is edge-detected, and is retained until acknowledged. user break exception handling sets the interrupt mask bits (i3 to i0) in the status register (sr) to 15. for details of user breaks, see section 7, user break controller (ubc). 6.2.3 external interrupts irq interrupts: irq interrupts correspond to pins irl7 to irl0 . low-level detection or falling edge detection can be selected independently for each pin with the irq sense select bits (irq7s to irq0s) in the interrupt control register 2 (icr2), and a priority level of 0 to 15 can be selected independently for each pin by means of interrupt priority registers a and b. irq interrupt exception handling sets the interrupt mask bits (i3 to i0) in sr to the priority level of the accepted irq interrupt. irl interrupts: irl interrupts are requested by input at external pins irq3 to irq0 . fifteen interrupts, irl15 to irl1, can be input from an external source by means of pins irq3 to irq0 . interrupts irl15 to irl1 have priority levels of 15 to 1, respectively, and are assigned vector numbers 79 to 64. in irl interrupt mode, external interrupts irq4 to irq7 are independent interrupt sources. the priority levels of irq4 to irq7 can be set in interrupt priority register b (iprb), as in irq interrupt mode. (an example of interrupt connection is shown in figure 6.2.) rev. 1.0, 08/99, page 171 of 875 table 6.3 irl interrupt priority levels and vector numbers signals interrupt irq3 irq3 irq3 irq3 irq2 irq2 irq2 irq2 irq1 irq1 irq1 irq1 irq0 irq0 irq0 irq0 priority level vector number irl15000015 79 irl14000114 78 irl13001013 77 irl12001112 76 irl11010011 75 irl10010110 74 irl901109 73 irl801118 72 irl710007 71 irl610016 70 irl510105 69 irl410114 68 irl311003 67 irl211012 66 irl111101 65 11110 (no interrupt)64 . . . interrupt requests priority encoder sh7065 4 C figure 6.2 example of irl mode interrupt connection rev. 1.0, 08/99, page 172 of 875 6.2.4 on-chip peripheral module interrupts on-chip peripheral module interrupts are generated by the following modules: direct memory access controller (dmac) watchdog timer (wdt) bus state controller (bsc) timer pulse unit (tpu) serial communication interface (sci) compare match timer (cmt) motor management timer (mmt) a/d converter port output enable (poe (i/o)) as a different vector number is assigned to each source, it is not necessary to determine the source in the exception service routine. a priority level in the range 0 to 15 can be set for each module with interrupt priority registers e to l (ipre to iprl). in on-chip peripheral module interrupt exception handling, the interrupt mask bits (i3 to i0) in the status register (sr) are set to the priority level of the accepted on-chip peripheral module interrupt. 6.2.5 interrupt exception vectors and priority order tables 6.4 to 6.6 show interrupt sources, vector numbers, vector table addresses, and default interrupt priorities. each interrupt source is assigned a different vector number and vector table address offset. the vector table address is calculated from the vector number and vector table address offset. in interrupt exception handling, the start address of the exception service routine is fetched from the vector table entry indicated by this vector table address. for the method of calculating the vector table address, see table 5.4, exception vector table address calculation, in section 5, exception handling. in irq mode, an interrupt priority level of 0 to 15 can be assigned to the irq interrupts using interrupt priority registers a and b (ipra, iprb). in irl mode, irl interrupts irl15 to irl1 are assigned interrupt priority levels 15 to 1, respectively. the vectors shown in tables 6.3 to 6.5 can be used for the vector numbers of irq and irl interrupts. the priority of on-chip peripheral module interrupts can be set to any level from 0 to 15 for each module using interrupt priority registers e to l (ipre to iprl). the priority within ipr setting column in table 6.6 shows the relative priority of interrupts sharing the same ipr field. this priority order cannot be changed. in a power-on reset, irq interrupts and on-chip peripheral rev. 1.0, 08/99, page 173 of 875 module interrupts are set to priority level 0. if two or more interrupt sources assigned the same priority level occur simultaneously, they are handled according to the default priority order shown in tables 6.4 to 6.6. table 6.4 irq mode interrupt exception vectors and priority order vector interrupt source interrupt priority (initial value) ipr (bit numbers) vector number vector table offset default priority nmi 16 12 h'0000 0030 user break 15 13 h'0000 0034 irq0 0C15 (0) * ipra (15C12) 64 h'0000 0100 irq1 0C15 (0) ipra (11C8) 65 h'0000 0104 irq2 0C15 (0) ipra (7C4) 66 h'0000 0108 irq3 0C15 (0) ipra (3C0) 67 h'0000 010c irq4 0C15 (0) iprb (15C12) 80 h'0000 0140 irq5 0C15 (0) iprb (11C8) 81 h'0000 0144 irq6 0C15 (0) iprb (7C4) 82 h'0000 0148 irq7 0C15 (0) iprb (3C0) 83 h'0000 014c high - ? ? ? ? ? ? ? ? ? ? ? ? ? ? low note: * the figure in parentheses is the initial value. rev. 1.0, 08/99, page 174 of 875 table 6.5 irl mode interrupt exception vectors and priority order vector interrupt source interrupt priority (initial value) ipr (bit numbers) vector number vector table offset default priority nmi 16 12 h'0000 0030 user break 15 13 h'0000 0034 irl15 15 79 h'0000 013c irl14 14 78 h'0000 0138 irl13 13 77 h'0000 0134 irl12 12 76 h'0000 0130 irl11 11 75 h'0000 012c irl10 10 74 h'0000 0128 irl9 9 73 h'0000 0124 irl8 8 72 h'0000 0120 irl7 7 71 h'0000 011c irl6 6 70 h'0000 0118 irl5 5 69 h'0000 0114 irl4 4 68 h'0000 0110 irl3 3 67 h'0000 010c irl2 2 66 h'0000 0108 irl1 1 65 h'0000 0104 high - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? low rev. 1.0, 08/99, page 175 of 875 table 6.6 on-chip peripheral module interrupt exception vectors and priority order interrupt source interrupt priority (initial value) ipr (bit numbers) priority within ipr setting vector number vector table offset default priority dmac0 dei0 0C15 (0) ipre (15C12) 128 h'0000 0200 dmac1 dei1 0C15 (0) ipre (11C8) 129 h'0000 0204 dmac2 dei2 0C15 (0) ipre (7C4) 130 h'0000 0208 dmac3 dei3 0C15 (0) ipre (3C0) 131 h'0000 020c reserved 0C15 (0) iprf (15C12) 132 h'0000 0210 0C15 (0) iprf (11C8) 133 h'0000 0214 0C15 (0) iprf (7C4) 134 h'0000 0218 0C15 (0) iprf (3C0) 135 h'0000 021c bsc cmi 0C15 (0) iprg (15C12) 136 h'0000 0220 ovi 0C15 (0) iprg (11C8) 137 h'0000 0224 wdt iti 0C15 (0) iprg (7C4) 138 h'0000 0228 reserved 0C15 (0) iprg (3C0) 139 h'0000 022c tpu0 tgi0a 0C15 (0) iprh (15C12) 140 h'0000 0230 tgi0b 141 h'0000 0234 tgi0c 142 h'0000 0238 tgi0d high - ? ? low 143 h'0000 023c tci0v 0C15 (0) iprh (11C8) 144 h'0000 0240 reserved 145 h'0000 0244 reserved 146 h'0000 0248 reserved high - ? ? low 147 h'0000 024c tpu1 tgi1a 0C15 (0) iprh (7C4) 148 h'0000 0250 tgi1b 149 h'0000 0254 reserved 150 h'0000 0258 reserved high - ? ? low 151 h'0000 025c tci1v 0C15 (0) iprh (3C0) 152 h'0000 0260 tci1u 153 h'0000 0264 reserved 154 h'0000 0268 reserved high - ? ? low 155 h'0000 026c high - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? low rev. 1.0, 08/99, page 176 of 875 table 6.6 on-chip peripheral module interrupt exception vectors and priority order (cont) interrupt source interrupt priority (initial value) ipr (bit numbers) priority within ipr setting vector number vector table offset default priority tpu2 tgi2a 0C15 (0) ipri (15C12) 156 h'0000 0270 tgi2b 157 h'0000 0274 reserved 158 h'0000 0278 reserved high - ? ? low 159 h'0000 027c tci2v 0C15 (0) ipri (11C8) 160 h'0000 0280 tci2u 161 h'0000 0284 reserved 162 h'0000 0288 reserved high - ? ? low 163 h'0000 028c tpu3 tgi3a 0C15 (0) ipri (7C4) 164 h'0000 0290 tgi3b 165 h'0000 0294 tgi3c 166 h'0000 0298 tgi3d high - ? ? low 167 h'0000 029c tci3v 0C15 (0) ipri (3C0) 168 h'0000 02a0 reserved 169 h'0000 02a4 reserved 170 h'0000 02a8 reserved high - ? ? low 171 h'0000 02ac tpu4 tgi4a 0C15 (0) iprj(15C12) 172 h'0000 02b0 tgi4b 173 h'0000 02b4 reserved 174 h'0000 02b8 reserved high - ? ? low 175 h'0000 02bc tci4v 0C15 (0) iprj(11C8) 176 h'0000 02c0 tci4u 177 h'0000 02c4 reserved 178 h'0000 02c8 reserved high - ? ? low 179 h'0000 02cc high - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? low rev. 1.0, 08/99, page 177 of 875 table 6.6 on-chip peripheral module interrupt exception vectors and priority order (cont) interrupt source interrupt priority (initial value) ipr (bit numbers) priority within ipr setting vector number vector table offset default priority tpu5 tgi5a 0C15 (0) iprj (7C4) 180 h'0000 02d0 tgi5b 181 h'0000 02d4 reserved 182 h'0000 02d8 reserved high - ? ? low 183 h'0000 02dc tci5v 0C15 (0) iprj (3C0) 184 h'0000 02e0 tci5u 185 h'0000 02e4 reserved 186 h'0000 02e8 reserved high - ? ? low 187 h'0000 02ec sci0 eri0 0C15 (0) iprk (15C12) 188 h'0000 02f0 rxi0 189 h'0000 02f4 txi0 190 h'0000 02f8 tei0 high - ? ? low 191 h'0000 02fc sci1 eri1 0C15 (0) iprk (11C8) 192 h'0000 0300 rxi1 193 h'0000 0304 txi1 194 h'0000 0308 tei1 high - ? ? low 195 h'0000 030c sci2 eri2 0C15 (0) iprk (7C4) 196 h'0000 0310 rxi2 197 h'0000 0314 txi2 198 h'0000 0318 tei2 high - ? ? low 199 h'0000 031c reserved reserved 0C15 (0) iprk (3C0) 200 h'0000 0320 reserved 201 h'0000 0324 reserved 202 h'0000 0328 reserved high - ? ? low 203 h'0000 032c cmt cmi0 0C15 (0) iprl (15C12) 204 h'0000 0330 cmi1 205 h'0000 0334 reserved 206 h'0000 0338 reserved high - ? ? low 207 h'0000 033c high - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? low rev. 1.0, 08/99, page 178 of 875 table 6.6 on-chip peripheral module interrupt exception vectors and priority order (cont) interrupt source interrupt priority (initial value) ipr (bit numbers) priority within ipr setting vector number vector table offset default priority a/d adi0 0C15 (0) iprl (11C8) 208 h'0000 0340 adi1 209 h'0000 0344 reserved 210 h'0000 0348 reserved high - ? ? low 211 h'0000 034c mmt tgim 0C15 (0) iprl (7C4) 212 h'0000 0350 tgin 213 h'0000 0354 reserved 214 h'0000 0358 reserved high - ? ? low 215 h'0000 035c poe (i/o) oei 0C15 (0) iprl (3C0) 216 h'0000 0360 reserved 217 h'0000 0364 reserved 218 h'0000 0368 reserved high - ? ? low 219 h'0000 036c high - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? low rev. 1.0, 08/99, page 179 of 875 6.3 register descriptions 6.3.1 interrupt priority registers a to l (ipra to iprl) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w interrupt priority registers a to l (ipra to iprl) are 16-bit readable/writable registers that set priority levels from 0 to 15 for irq interrupts and on-chip peripheral module interrupts. table 6.7 shows the relationship between the interrupt request sources and bits in registers ipra to iprl. table 6.7 interrupt request sources and registers ipra to iprl bits register 15C12 11C8 7C4 3C0 interrupt priority register a irq0 irq1 irq2 irq3 interrupt priority register b irq4 irq5 irq6 irq7 interrupt priority register c reserved reserved reserved reserved interrupt priority register d reserved reserved reserved reserved interrupt priority register e dmac0 dmac1 dmac2 dmac3 interrupt priority register f reserved reserved reserved reserved interrupt priority register g bsc bsc wdt reserved interrupt priority register h tpu0 tpu0 tpu1 tpu1 interrupt priority register i tpu2 tpu2 tpu3 tpu3 interrupt priority register j tpu4 tpu4 tpu5 tpu5 interrupt priority register k sci0 sci1 sci2 reserved interrupt priority register l cmt a/d mmt poe (i/o) four irq pins or four on-chip peripheral modules are assigned to one register. interrupt priority levels are established by setting a value from h'0 (0000) to h'f (1111) in each of the four-bit groups: 15 to 12, 11 to 8, 7 to 4, and 3 to 0. setting h'0 designates priority level 0 (the lowest level), and setting h'f designates priority level 15 (the highest level). rev. 1.0, 08/99, page 180 of 875 registers ipra to iprl are initialized to h'0000 by a power-on reset. they are not initialized in standby mode. reserved bits are always read as 0, and should only be written with 0. 6.3.2 interrupt control register 1 (icr1) bit: 15 14 13 12 11 10 9 8 nmil * eximdnmie initial value:0000000 r/w:r r/wr/w bit:76543210 initial value:00000000 r/w: note: * 1 when nmi pin input is high, 0 when low. interrupt control register 1 (icr1) is a 16-bit register that sets the input signal detection mode for external interrupt input pins nmi and irq7 to irq0 , and indicates the input level at the nmi pin. icr1 is initialized to h'0000 or h'8000 by a power-on reset. it is not initialized in standby mode. bit 15nmi input level (nmil): the level of the signal input to the nmi pin is set in this bit. this bit can be read to determine the nmi pin level. it cannot be modified. bit 15: nmil description 0 nmi pin input level is low 1 nmi pin input level is high bits 14 to 11reserved: these bits are always read as 0 and cannot be modified. bit 10external interrupt vector mode select (eximd): this bit selects irq mode or irl mode. in irq mode, each of signals irq7 to irq0 functions as a separate interrupt source. in irl mode, signals irq3 to irq0 specify an interrupt priority level from 1 to 15, and each of signals irq7 to irq4 functions as a separate interrupt source. bit 10: eximd description 0 irq mode (initial value) 1 irl mode rev. 1.0, 08/99, page 181 of 875 bit 9reserved: this bit is always read as 0 and cannot be modified. bit 8nmi edge select (nmie): specifies whether an interrupt request is detected at the falling or rising edge of nmi input. bit 8: nmie description 0 interrupt request detected at falling edge of nmi input (initial value) 1 interrupt request detected at rising edge of nmi input bits 7 to 0reserved: these bits are always read as 0 and cannot be modified. 6.3.3 interrupt control register 2 (icr2) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w: bit:76543210 irq7s irq6s irq5s irq4s irq3s irq2s irq1s irq0s initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w interrupt control register 2 (icr2) is a 16-bit register that sets the input signal detection mode for irq7 to irq0 . icr2 is initialized to h'0000 by a power-on reset. it is not initialized in standby mode. bits 15 to 8reserved: these bits are always read as 0 and cannot be modified. bits 7 to 0irq7 to irq0 sense select (irq7s to irq0s): these bits set the irq detection mode for irq7 to irq0 interrupt requests. bits 7 to 0: irq7s to irq0s description 0 interrupt request detected at low level of irq input (initial value) 1 interrupt request detected at falling edge of irq input rev. 1.0, 08/99, page 182 of 875 6.3.4 irq status register (isr) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w: bit:76543210 irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the irq status register (isr) is a 16-bit register that indicates the interrupt request status of external interrupt input pins irq7 to irq0 . when edge detection is set for an irq interrupt, an interrupt request being retained can be cleared by reading irqnf while set to 1 and then writing 0 to irqnf. isr is initialized to h'0000 by a power-on reset. it is not initialized in standby mode. bits 15 to 8reserved: these bits are always read as 0 and cannot be modified. bits 7 to 0irq0 to irq7 flags (irq0f to irq7f): these bits indicate the irq7 to irq0 interrupt request status. bits 7 to 0: irq0f to irq7f detection setting description 0 level detection there is no irqn interrupt request [clearing condition] when irqn input is high edge detection an irqn interrupt request has not been detected [clearing conditions] when 0 is written to irqnf after reading irqnf = 1 when irqn interrupt exception handling is executed 1 level detection there is no irqn interrupt request [setting condition] when irqn input is low edge detection an irqn interrupt request has been detected [setting condition] when a falling edge occurs in irqn input rev. 1.0, 08/99, page 183 of 875 irq pin edge detection selection cpu interrupt request (irqn interrupt acceptance/irqnf = 0 write after irqnf = 1 read) s r resirqn q irqns (0: level, 1: edge) isr.irqnf level detection figure 6.3 external interrupt process rev. 1.0, 08/99, page 184 of 875 6.4 operation 6.4.1 interrupt operation sequence the sequence of operations when an interrupt is requested is described below. figure 6.4 shows a flowchart of the operations. 1. interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest-priority interrupt from the interrupt requests sent, according to the priority levels set in interrupt priority registers a to l (ipra to iprl). lower-priority interrupts are ignored*. if two of these interrupts have the same priority level, or if multiple interrupts occur within the same module, the interrupt with the highest priority according to the default priority and priority within ipr setting entries in table 6.6 is selected. an ignored interrupt is accepted after completion of the higher-level interrupt handling, or can be cleared before the end of the higher-level interrupt handling. 3. the priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (i3 to i0) in the cpus status register (sr). an interrupt with a priority level equal to or lower than that set in bits i3 to i0 will be ignored. if the interrupt priority level is higher that the level in bits i3 to i0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the cpu. 4. when the interrupt controller accepts an interrupt, a low-level signal is output from the irqout pin. 5. the interrupt request sent from the interrupt controller is detected when the instruction about to be executed by the cpu is decoded, and execution of that instruction is replaced by interrupt exception handling (see figure 6.5). 6. the status register (sr) and program counter (pc) are saved to the stack. 7. the priority level of the accepted interrupt is written to bits i3 to i0 in sr. 8. if the accepted interrupt is level-detected, or is from an on-chip peripheral module, a high-level signal is output from the irqout pin. if the accepted interrupt is edge-detected, a high-level signal is output from the irqout pin at the point at which the instruction about to be executed by the cpu is replaced by interrupt exception handling in (5). however, if the interrupt controller accepts another interrupt of a higher level than the interrupt in the process of being accepted, the irqout pin remains low. 9. the start address of the exception service routine is fetched form the exception vector table entry corresponding to the accepted interrupt, a jump is made to that address, and program execution starts from that point. the jump in this case is not a delayed branch. note: * an interrupt request for which edge detection has been set will be held pending until it can be acknowledged. however, an irq interrupt can be cleared by accessing the irq status register (isr). for details, see section 6.2.3, external interrupts. rev. 1.0, 08/99, page 185 of 875 program execution state irqout = low save sr to stack save pc to stack irqout = high copy interrupt level to i3 to i0 read exception vector table branch to exception service routine read vector number interrupt generated? no no no no yes yes yes yes yes yes yes no no no no user break? level 15 interrupt? i3 to i0 = level 14 or lower? level 1 interrupt? i3 to i0 = level 0? nmi? * 1 * 2 notes: i3 to i0: interrupt mask bits in the cpus status register (sr). 1. irqout is the same signal as the interrupt request signal sent to the cpu (see figure 6.1), and so is output in the event of an interrupt request with a higher priority level than that set in bits i3 to i0 in sr. 2. if the accepted interrupt is edge-detected, irqout goes high at the point at which the instruction about to be executed by the cpu is replaced by interrupt exception handling (before sr is saved to the stack). if the interrupt controller is accepting another interrupt with a higher priority level and an interrupt request is being output to the cpu, the irqout pin remains low. figure 6.4 interrupt operation flowchart rev. 1.0, 08/99, page 186 of 875 6.4.2 interrupt response time the time from generation of an interrupt request until interrupt exception handling is performed and fetching of the first instruction of the exception service routine is started (the interrupt response time) is shown in table 6.8. figure 6.5 shows an example of pipeline operation when an irq interrupt is accepted. table 6.8 interrupt response time number of states item nmi, peripheral modules irq notes time for priority decision and sr mask bit comparison 23 wait time until end of sequence being executed by cpu x ( 3 0) x ( 3 0) the longest sequence is for interrupt or address error exception handling (x = 4 + m1 + m2 + m3 + m4). however, the sequence may be even longer if an interrupt-masking instruction follows. time from interrupt exception handling until fetch of first instruction of exception service routine is started 5 + m1 + m2 + m3 5 + m1 + m2 + m3 sr and pc save and vector address fetch are performed. total 7 + m1 + m2 + m3 8 + m1 + m2 + m3 minimum case 10 11 at 60 mhz operation: 0.17 to 0.18 s response time maximum case 11 + 2 (m1 + m2 + m3) + m4 12 + 2 (m1 + m2 + m3) + m4 at 60 mhz operation: 0.30 to 0.32 s * notes: m1 to m4 are the number of states required for the following memory accesses. m1: sr save (longword write) m2: pc save (longword write) m3: vector address read (longword read) m4: fetch of first instruction of interrupt service routine * : when m1 = m2 = m3 = m4 = 1 rev. 1.0, 08/99, page 187 of 875 fdeemmemee fde f 33 5 + m1 + m2 + m3 m1 m2 1 1 m3 interrupt acceptance irq instruction (instruction replaced by interrupt exception handling) first instruction of interrupt service routine overrun fetch f: instruction fetch d: instruction decode e: instruction execution m: memory access instruction is fetched from memory in which program is stored. fetched instruction is decoded. data operation and address calculation are performed in accordance with result of decoding. memory data access is performed. ... ... ... ... figure 6.5 example of pipeline operations when irq interrupt is accepted rev. 1.0, 08/99, page 188 of 875 6.4.3 stack status after interrupt exception handling figure 6.6 shows the stack after completion of interrupt exception handling. pc * 1 sp * 2 32 bits 32 bits sr address 4n C 8 4n C 4 4n notes: 1. pc: start address of instruction following executed instruction (i.e. return destination instruction) 2. ensure that the sp value is a multiple of 4. figure 6.6 stack status after interrupt exception handling rev. 1.0, 08/99, page 189 of 875 6.5 sampling of signals irq3 to irq0 in irl mode in irl mode, interrupt request signals irq3 to irq0 pass through a noise canceler before being sent by the interrupt controller to the cpu as an interrupt request. the noise canceler eliminates minute width variations in the signals. the cpu samples interrupts between executing instructions. during this period, the noise canceler varies its output according to the signal level after noise cancellation, so the signal level must be held until the cpu completes its sampling operation. therefore, interrupt source clearing should normally be carried out after making the transition to the interrupt routine. figure 6.7 shows a block diagram of the interrupt response mechanism, and figure 6.8 shows the interrupt response timing. irq0 irq1 irq2 irq3 noise canceler interrupt controller cpu interrupt request accepted interrupt figure 6.7 interrupt response block diagram irq3 to irq0 signal levels 1011 for one clock due to noise level 2 interrupt cleared when interrupt is accepted level 6 interrupt 1111 1111 1101 1001 1101 1001 1011 noise canceler output interrupt request to cpu interrupt acknowledge signal from cpu 1111 figure 6.8 interrupt response timing chart rev. 1.0, 08/99, page 190 of 875 6.6 data transfer by means of interrupt request signal the dmac can be activated, and data transfer performed, by means of an interrupt request signal. interrupt sources designated as dmac activation sources are masked, and not input to the intc. the mask condition is as follows: mask condition = dme (de0 source selection 0 + de1 source selection 1 + de2 source selection 2 + de3 source selection 3) a control block diagram is shown in figure 6.8. dme is bit 0 of the dmacs dmaor register, and den (n = 0 to 3) is bit 0 of dmac registers chr0 to chr3. for details see section 9, direct memory access controller (dmac). interrupt source interrupt source flag clearing (by dmac) cpu interrupt request interrupt source (not designated as dmac activation source) dmac intc figure 6.9 interrupt control block diagram 6.6.1 to designate a source as a dmac activation source, not a cpu interrupt source 1. select the source in the dmac, and set de = 1, dme = 1. the cpu interrupt source is masked regardless of the interrupt priority register settings. 2. when the interrupt is generated, the activation source is sent to the dmac. 3. the dmac clears the activation source when it performs transfer. 6.6.2 to designate a source as a cpu interrupt source, not a dmac activation source 1. do not select the source in the dmac, or clear the dme bit to 0. if the source has been selected in the dmac, clear the de bit for the relevant dmac channel to 0. 2. when the interrupt is generated, an interrupt request is sent to the cpu. 3. the cpu clears the interrupt source and performs the necessary processing in the interrupt service routine. rev. 1.0, 08/99, page 191 of 875 6.7 usage notes 6.7.1 irq3 to irq0 sampling and interrupt source determination in irl interrupt mode low level sensing or falling edge sensing can be set as the sampling method for each of pins irq3 to irq0 by means of irq sense select bits 3 to 0 in interrupt control register 2 (icr2). in irl interrupt mode, the same sampling method must be set for all four pins, irq3 to irq0. when low level sensing is set for irq3 to irq0, on acceptance of an interrupt request the interrupt source (irl1 to irl15) is determined by the levels of irq3 to irq0. when falling edge sensing is set for irq3 to irq0, the falling edge detection results for irq3 to irq0 are retained. when an interrupt request is accepted, the interrupt source (irl1 to irl15) is determined by the retained detection results. for example, if level 3 (irq[3:0] = h'1100) input is not accepted, and this is followed by level 4 (irq[3:0] = h'1011) input without clearing the retained detection results, a level 7 (irq[3:0] = h'1000) interrupt request will be judged to have been issued on the basis of the detection results retained up to that point. in this example, in order to end up with a level 4 interrupt request, the level 3 detection results must be cleared before the level 4 interrupt signal is input. detection results can be cleared by reading 1 from bits irq3f to irq0f in the irq status register (isr), then writing 0 to these bits. 6.7.2 irq pin noise cancellation function signals irq7 to irq0 are sent to the interrupt controller via a noise canceler that eliminates noise of one state or less in duration. therefore, when edge detection is set for the irq pins, the irq input must be at least two states in duration. rev. 1.0, 08/99, page 193 of 875 section 7 user break controller (ubc) 7.1 overview the user break controller (ubc) provides functions that simplify program debugging. when break conditions are set in the ubc, a user break interrupt is generated according to the conditions of the bus cycle generated by the cpu or on-chip dmac. this function makes it easy to design an effective self-monitoring debugger, enabling programs to be debugged with the chip alone, without using a large-scale in-circuit emulator. 7.1.1 features the ubc has the following features: the following break conditions can be set: ? address (bit masking possible) internal address bus (cab)/internal address bus (iab)/x memory address bus (xab)/y memory address bus (yab) ? bus master cpu cycle/dma cycle ? bus cycle instruction fetch/data access ? read/write ? operand size byte/word/longword user break interrupt generation on occurrence of break condition a user-written user break interrupt exception routine can be executed. when a user break is set for a cpu instruction fetch, the break is effected before execution of the next instruction (post-execution break). rev. 1.0, 08/99, page 194 of 875 7.1.2 block diagram figure 7.1 shows a block diagram of the ubc. module bus ubbr ubamrh ubamrl ubarh ubarl break condition comparator user break interrupt generator interrupt request interrupt controller ubarh, ubarl: user break address registers h and l ubamrh, ubamrl: user break address mask registers h and l ubbr: user break bus cycle register internal bus (cab) internal bus (iab) x/y memory bus figure 7.1 block diagram of ubc rev. 1.0, 08/99, page 195 of 875 7.1.3 register configuration the ubc has the five registers shown in table 7.1. these registers are used to set the break conditions. table 7.1 ubc registers name abbre- viation r/w initial value address access size user break address register h ubarh r/w h'0000 h'ffff0c80 16, 32 user break address register l ubarl r/w h'0000 h'ffff0c82 16, 32 user break address mask register h ubamrh r/w h'0000 h'ffff0c84 16, 32 user break address mask register l ubamrl r/w h'0000 h'ffff0c86 16, 32 user break bus cycle register ubbr r/w h'0000 h'ffff0c88 16, 32 7.2 register descriptions 7.2.1 user break address register (ubar) ubarh bit: 15 14 13 12 11 10 9 8 uba31 uba30 uba29 uba28 uba27 uba26 uba25 uba24 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 uba23 uba22 uba21 uba20 uba19 uba18 uba17 uba16 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w rev. 1.0, 08/99, page 196 of 875 ubarl bit: 15 14 13 12 11 10 9 8 uba15 uba14 uba13 uba12 uba11 uba10 uba9 uba8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 uba7 uba6 uba5 uba4 uba3 uba2 uba1 uba0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the user break address register (ubar) consists of two 16-bit readable/writable registers: user break address register h (ubarh) and user break address register l (ubarl). control bits xye and xys in the user break bus cycle register (ubbr) select the break condition address bus. when xye is 0, the break address is specified on the cab internal address bus or iab internal address bus. in this case, ubarh specifies the upper half (bits 31 to 16) of the address used as the break condition, and ubarl specifies the lower half (bits 15 to 0). when xye is 1, ubarh specifies the break address on x memory address bus xab (bits 15 to 1), and ubarl specifies the break address on y memory address bus yab (bits 15 to 1). as xab and yab have only 15 bits, 0 must be set as the least significant bit. when xye is 1, either xab or yab must be selected with the xys bit in ubbr. ubarh and ubarl are initialized to h'0000 by a power-on reset and in hardware standby mode. they are not initialized by the module standby function or in software standby mode. xye ubarh ubarl 0 cab31C16/iab31Ciab16 cab15C0/iab15C0 1 xab15C1 (xys = 0) yab15C1 (xys = 1) rev. 1.0, 08/99, page 197 of 875 7.2.2 user break address mask register (ubamr) ubamrh bit: 15 14 13 12 11 10 9 8 ubm31 ubm30 ubm29 ubm28 ubm27 ubm26 ubm25 ubm24 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 ubm23 ubm22 ubm21 ubm20 ubm19 ubm18 ubm17 ubm16 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w ubamrl bit: 15 14 13 12 11 10 9 8 ubm15 ubm14 ubm13 ubm12 ubm11 ubm10 ubm9 ubm8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 ubm7 ubm6 ubm5 ubm4 ubm3 ubm2 ubm1 ubm0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the user break address mask register (ubamr) consists of two 16-bit readable/writable registers: user break address mask register h (ubamrh) and user break mask address register l (ubamrl). control bits xye and xys in the user break bus cycle register (ubbr) select the break condition address bus. when xye is 0, ubar specifies a break address on the cab internal address bus or iab internal address bus. in this case, ubamrh specifies which bits of the break address set in ubarh are to be masked, and ubamrl specifies which bits of the break address set in ubarl are to be masked. when xye is 1, ubamrh specifies which bits of the break address on xab (bits 15 to 1) set in ubarh are to be masked, and ubamrl specifies which bits of the break address on yab (bits 15 to 1) set in ubarl are to be masked. as xab and yab have only 15 bits, the setting of the least significant bit of ubamrh and ubamrl is invalid. when xye is 1, either xab or yab must be selected with the xys bit in ubbr. rev. 1.0, 08/99, page 198 of 875 ubamrh and ubamrl are initialized to h'0000 by a power-on reset and in hardware standby mode. they are not initialized by the module standby function or in software standby mode. xye ubamrh ubamrl 0 cab31C16/iab31C16 masked cab15C0/iab15C0 masked 1 xab15C1 masked (xys = 0) yab15C1 masked (xys = 1) bits 15 to 0: ubmn description 0 user break address uban is included in break conditions (initial value) 1 user break address uban is not included in break conditions note: n = 31 to 0 7.2.3 user break bus cycle register (ubbr) bit: 15 14 13 12 11 10 9 8 ubiexyexys initial value:00000000 r/w:r/wrrrrrr/wr/w bit:76543210 cp1 cp0 id1 id0 rw1 rw0 sz1 sz0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the user break bus cycle register (ubbr) is a 16-bit readable/writable register that sets five conditions(1) internal bus (c-bus) or internal bus (i-bus)/x memory bus or y memory bus, (2) cpu cycle/dma cycle, (3) instruction fetch/data access, (4) read/write, and (5) operand size (byte/word/longword)and selects whether or not a user break interrupt is to generated when a condition is matched. ubbr is initialized to h'0000 by a power-on reset and in hardware standby mode. it is not initialized by the module standby function or in software standby mode. bit 15user break interrupt enable (ubie): specifies whether or not a user break interrupt is to be generated when the set break condition occurs. bit 15: ubie description 0 user break interrupt is not generated when break condition occurs (initial value) 1 user break interrupt is generated when break condition occurs rev. 1.0, 08/99, page 199 of 875 bits 14 to 10reserved: these bits are always read as 0, and should only be written with 0. bit 9x/y memory bus enable (xye): selects the c-bus/i-bus or the x/y memory bus as the break condition bus. bit 9: xye description 0 c-bus or i-bus is selected as break condition (initial value) 1 x memory bus or y memory bus is selected as break condition bit 8x memory bus/y memory bus select (xys): selects the x memory bus or y memory bus as the break condition bus. bit 8: xys description 0 x memory bus is selected as break condition (initial value) 1 y memory bus is selected as break condition note: when xye = 0, the setting of bit 8 is ignored. bits 7 and 6cpu cycle/dma cycle select (cp1, cp0): these bits select the cpu or dma as the break condition bus master. bit 7: cp1 bit 6: cp0 description 0 0 user break interrupt is not generated (initial value) 1 cpu cycle is selected as break condition 1 0 dma cycle is selected as break condition 1 both cpu cycle and dma cycle are selected as break conditions bits 5 and 4instruction fetch/data access select (id1, id0): these bits select an instruction fetch cycle or data access cycle as the break condition bus cycle. bit 5: id1 bit 4: id0 description 0 0 user break interrupt is not generated (initial value) 1 instruction fetch cycle is selected as break condition 1 0 data access cycle is selected as break condition 1 both instruction fetch cycle and data access cycle are selected as break conditions rev. 1.0, 08/99, page 200 of 875 bits 3 and 2read/write select (rw1, rw0): these bits select a read cycle or write cycle as the break condition access. bit 3: rw1 bit 2: rw0 description 0 0 user break interrupt is not generated (initial value) 1 read cycle is selected as break condition 1 0 write cycle is selected as break condition 1 both read cycle and write cycle are selected as break conditions bits 1 and 0operand size select (sz1, sz0): these bits select the operand size of the break condition bus cycle. bit 1: sz1 bit 0: sz0 description 0 0 operand size is not included in break conditions (initial value) 1 byte access is selected as break condition 1 0 word access is selected as break condition 1 longword access is selected as break condition rev. 1.0, 08/99, page 201 of 875 7.3 operation 7.3.1 user break operation sequence the sequence of operations from setting of break conditions to user break interrupt exception handling is described below. 1. as break conditions, set the user break address in the user break address register (ubar), the address bits to be masked in the user break address mask register (ubamr), and the type of bus cycle on which a break is to be executed in the user break bus cycle register (ubbr). if any pair of bits from among the cpu cycle/dma cycle select bits (cp1, cp0), instruction fetch/data access select bits (id1, id0), or read/write select bits (rw1, rw0) in ubbr is set to 00 (user break interrupt not generated), a user break interrupt will not be generated even if other conditions are satisfied. if the user break interrupt is to be used, a condition must be set in all of these bit pairs. 2. if the user break interrupt enable bit (ubie) in the user break bus cycle register (ubbr) is set to 1 when a break condition occurs, the ubc sends a user break interrupt request signal to the interrupt controller (intc). 3. when the intc receives the user break interrupt request signal, it determines its priority. as the priority level of the user break interrupt is 15, it is accepted if the level set in the interrupt mask bits (i3 to i0) in the status register (sr) is 14 or less. if the level set in bits i3 to i0 is 15, the user break interrupt is not accepted, but is held pending until it can be. as the setting of bits i3 to i0 is 15 during nmi exception handling, a user break interrupt is not accepted during execution of the nmi exception service routine. however, changing the setting of bits i3 to i0 to level 14 or below at the start of the nmi exception service routine will enable subsequent user break interrupts to be accepted. for details of priority determination, see section 6, interrupt controller (intc). 4. the intc sends a user break interrupt request signal to the cpu. on receiving this signal, the cpu begins user break interrupt exception handling. for details of interrupt exception handling, see section 5, exception handling, and section 6.4, operation. rev. 1.0, 08/99, page 202 of 875 7.3.2 instruction fetch cycle break when an internal bus (c-bus)/cpu/instruction fetch/read setting is made in the user break bus cycle register (ubbr), a cpu instruction fetch cycle can be selected as a user break condition. in this case, an operand size setting is not necessary. when a user break condition occurs, the instruction set in the user break conditions is executed, and an interrupt is generated before execution of the next instruction. therefore, a user break cannot be specified for an instruction that is fetched but not executed, such as an overrun fetch instruction. however, if a user break condition is set for a delayed branch instruction or an interrupt-disabled instruction such as ldc, an interrupt will be generated before execution of the next instruction at which the interrupt can be accepted. when an instruction fetch cycle is set as a user break condition, the start address at which that instruction is located should be set as the user break address. a user break will not occur if a different address is set. therefore, if the address of the lower word of a 32-bit instruction is set as a user break condition, a user break will not occur. 7.3.3 data access cycle break memory cycles subject to a cpu data access break are memory cycles due to instructions and stack operations and vector reads when exception handling is executed. table 7.2 shows the bits of the user break address register and the address bus that are compared for each operand size to determine whether a break condition has been matched. table 7.2 data access cycle address and operand size comparison conditions access size compared address bits longword bits 31C2 of break address register compared with bits 31C2 of address bus word bits 31C1 of break address register compared with bits 31C1 of address bus byte bits 31C0 of break address register compared with bits 31C0 of address bus this means, for example, that if address h'00001003 is set without specifying an operand size condition (i.e. the operand size select bits in the user break bus cycle register are set to 00), bus cycles that satisfy the break conditions include the following(assuming that all other conditions are satisfied): longword access at h'00001000 word access at h'00001002 byte access at h'00001003 rev. 1.0, 08/99, page 203 of 875 7.3.4 x memory bus or y memory bus cycle break when xye is set to 1 in ubbr, break addresses on the x memory bus or y memory bus are selected. either the x memory bus or the y memory bus must be selected with the xys bit in ubbr; the x and y memory buses cannot both be included in the break conditions at the same time. the break conditions are applied to x memory bus cycles or y memory bus cycles by specifying the cpu bus master, data access cycle, read or write access, and word operand size or operand size not included. when the x memory address bus is selected as a break condition, specify the x memory address in ubarh and ubamrh; when the y memory address bus is selected, specify the y memory address in ubarl and ubamrl. 7.3.5 program counter (pc) value saved when instruction fetch is set as user break condition: the program counter (pc) value saved in user break interrupt exception handling is the address of the instruction to be executed after the instruction at which the user break condition was satisfied. the instruction at which the break condition was satisfied is executed, and a user break interrupt is generated before execution of the next instruction. however, when a user break condition is set for a delayed branch instruction, the delay slot instruction is executed, and the user break interrupt is generated before execution of the branch instruction. in this case, the pc value is the address of the branch destination instruction. when data access (cpu/dma) is set as user break condition: the address saved is the start address of the instruction following the instruction for which execution has been completed at the point at which user break exception handling starts. when a data access (cpu/dma) is set as a user break condition, it is not possible to specify where the break will occur. the break will be effected at an instruction about to be fetched close to where the break data access occurred. rev. 1.0, 08/99, page 204 of 875 7.4 examples of use cpu instruction fetch cycle break condition settings example of valid settings ? register settings ubarh = h'0000, ubarl = h'0404 ubamrh = h'0000, ubamrl = h'0000 ubbr = h'8054 ? set conditions address: h'00000404; address mask: h'00000000 bus cycle: cpu, instruction fetch, read (operand size not included) ? a user break interrupt is generated after execution of the instruction at address h'00000404. example of invalid settings ? register settings ubarh = h'0015, ubarl = h'389c ubamrh = h'0000, ubamrl = h'0000 ubbr = h'8058 ? set conditions address: h'0015389c; address mask: h'00000000 bus cycle: cpu, instruction fetch, write (operand size not included) ? as an instruction fetch cycle is not a write cycle, a user break interrupt is not generated. cpu data access cycle (internal bus (c-bus) cycle) break condition settings example of valid settings (1) ? register settings ubarh = h'0012, ubarl = h'3456 ubamrh = h'0000, ubamrl = h'0000 ubbr = h'806a ? set conditions address: h'00123456; address mask: h'00000000 bus cycle: cpu, data access, write, word ? a user break interrupt is generated when word data is written to address h'00123456. example of valid settings (2) ? register settings ubarh = h'00a8, ubarl = h'3901 ubamrh = h'0000, ubamrl = h'0000 rev. 1.0, 08/99, page 205 of 875 ubbr = h'8066 ? set conditions address: h'00a80391; address mask: h'00000000 bus cycle: cpu, data access, read, word ? as a word access is performed on an even address, user break interrupt exception handling is performed after address error exception handling. example of invalid settings ? register settings ubarh = h'0034, ubarl = h'5024 ubamrh = h'0000, ubamrl = h'0000 ubbr = h'8062 ? set conditions address: h'00345024; address mask: h'00000000 bus cycle: cpu, data access, , word ? as the access type has not been set as either read or write, a user break interrupt is not generated. dma cycle break condition settings example of valid settings ? register settings ubarh = h'0076, ubarl = h'bcdc ubamrh = h'0000, ubamrl = h'0000 ubbr = h'80a7 ? set conditions address: h'0076bcdc; address mask: h'00000000 bus cycle: dma, data access, longword ? a user break interrupt is generated when longword data is read from address h'0076bcdc. example of invalid settings ? register settings ubarh = h'0023, ubarl = h'45c8 ubamrh = h'0000, ubamrl = h'0000 ubbr = h'8094 ? set conditions address: h'002345c8; address mask: h'00000000 bus cycle: dma, instruction fetch, write (operand size not included) rev. 1.0, 08/99, page 206 of 875 ? as an instruction fetch is not performed in a dma cycle, a user break interrupt is not generated. cpu data access cycle (x/y memory bus cycle) break condition settings example of valid settings ? register settings ubarh = h'8000, ubarl = h'0000 ubamrh = h'0000, ubamrl = h'0000 ubbr = h'826a ? set conditions address: h'ffff8000; address mask: h'00000000 bus cycle: cpu, data access (x memory access using x memory bus), write, word ? a user break access is generated when word data is written to address h'ffff8000 in x memory space using the x memory bus. example of invalid settings ? register settings ubarh = h'a000, ubarl = h'0000 ubamrh = h'0000, ubamrl = h'0000 ubbr = h'826b ? set conditions address: h'ffffa000; address mask: h'00000000 bus cycle: cpu, data access (y memory access using y memory bus), write, byte ? as byte access cannot be performed in a data access cycle using the x/y memory bus, a user break interrupt is not generated. rev. 1.0, 08/99, page 207 of 875 7.5 usage notes 7.5.1 changes to ubc register settings ubc register reads and writes are executed in the ma (memory access) stage of the instruction pipeline, and checks are not carried out based on new user break conditions until register changes have been completed. a user break based on new break conditions will not occur until register setting changes have been completed. thus, if the check stage of the succeeding instruction occurs before new user break conditions are written to the ubc registers, a user break will not occur even if the checked address matches the user break condition. 7.5.2 repeat condition breaks if repeated execution of a repeat instruction is included as a break condition, note that a user break will not occur if a user break condition is set for an instruction being executed repeatedly during execution of a repeat loop consisting of no more than three instructions. rev. 1.0, 08/99, page 209 of 875 section 8 bus state controller (bsc) 8.1 overview the functions of the bus state controller (bsc) include division of the address space and output of control signals for various types of memory. the bsc functions allow dram, edo dram, sram, rom, etc., to be connected directly to the sh7065 without the use of external circuitry. 8.1.1 features the bsc has the following features: address space is managed as six independent areas ? cs0 space: maximum linear 48 mbytes in on-chip rom enabled modes, and maximum 64 mbytes in on-chip rom disabled modes ? cs1 to cs3 spaces: maximum linear 64 mbytes for each ? cs4, cs5 spaces: dedicated dram spaces, maximum linear 64 mbytes ? memory types (dram, edo dram, sram, rom, etc.) can be specified individually for each space ? bus width (8, 16, or 32 bits) can be selected for each space (settable by external pin for cs0 space only) ? wait states can be inserted by software for each space ? wait states can be inserted by the wait pin when accessing external memory space ? output of appropriate control signals for memory connected to each space ? automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different cs spaces, or a read access followed by a write access to the same area ? big-endian or little-endian mode can be set for each space direct dram interface ? row address/column address multiplexed output according to dram capacity ? burst operation supported (fast page mode, edo mode, ras down mode) ? precharge cycle generated to secure ras precharge interval access control for various kinds of memory and peripheral chips ? address/data multiplexing refresh functions ? supports cas-before-ras refreshing and self-refreshing ? supports refresh operation immediately after self-refresh operation in low-power dram by means of refresh counter overflow interrupt function ? up to 8 consecutive cas-before-ras refreshes rev. 1.0, 08/99, page 210 of 875 refresh counter can be used as interval timer ? interrupt request generated by compare match ? interrupt request generated by refresh counter overflow rev. 1.0, 08/99, page 211 of 875 8.1.2 block diagram figure 8.1 shows a block diagram of the bsc. wcr: wait control register acr: area control register bcr: bus control register dcr: dram control register bus interface wcr wait wait control unit rfcr rtcnt comparator rtcor rtcsr refresh control unit acr csn area control unit interrupt controller bcr dcr bs, rd, wr, rdwr, wrxx, rasn, casxxn, xxbs, oen, ah memory control unit module bus internal bus peripheral bus bsc rfcr: refresh count register rtcnt: refresh timer count register rtcor: refresh time constant register rtcsr: refresh timer control/status register figure 8.1 block diagram of bsc rev. 1.0, 08/99, page 212 of 875 8.1.3 pin configuration table 8.1 shows the bsc pin configuration. table 8.1 bsc pins name signals i/o function address bus a25Ca0 output address output data bus d31Cd0 i/o data input/output bus cycle start bs output signal that indicates the start of a bus cycle. in burst transfer, asserted each data cycle. chip select cs5 C cs0 output chip select signals indicating the area being accessed read rd output strobe signal indicating a read cycle write ll wrll output strobe signal indicating a d7Cd0 write cycle write lh wrlh output strobe signal indicating a d15Cd8 write cycle write hl wrhl output strobe signal indicating a d23Cd16 write cycle write hh wrhh output strobe signal indicating a d31Cd24 write cycle write strobe ll llbs output strobe signal indicating access to d7Cd0 write strobe lh lhbs output strobe signal indicating access to d15Cd8 write strobe hl hlbs output strobe signal indicating access to d23Cd16 write strobe hh hhbs output strobe signal indicating access to d31Cd24 write wr output data bus input/output direction designation signal. used as write designation signal for byte-strobe memory. read/write rdwr output dram/edo dram write designation signal row address strobe ras1 , ras0 output ras signals for dram connected to areas 5 and 4 column address strobe ll casll1 , casll0 output d7Cd0 cas signals for dram connected to areas 5 and 4 column address strobe lh caslh1 , caslh0 output d15Cd8 cas signals for dram connected to areas 5 and 4 column address strobe hl cashl1 , cashl0 output d23Cd16 cas signals for dram connected to areas 5 and 4 column address strobe hh cashh1 , cashh0 output d31Cd24 cas signals for dram connected to areas 5 and 4 output enable oe1 , oe0 output output enable signals for edo dram connected to areas 5 and 4. used for access in ras down mode. rev. 1.0, 08/99, page 213 of 875 table 8.1 bsc pins (cont) name signals i/o function address hold ah output signal for holding address in address/data multiplexing wait wait input wait state request signal bus release request breq input bus release request signal bus request acknowledge back output signal granting use of the bus 8.1.4 register configuration the bsc has the 18 registers shown in table 8.2. the functions of these registers include control of direct interfaces to various types of memory, wait states, and refreshing. table 8.2 bsc registers name abbre- viation r/w initial value address access size bus control register bcr r/w h'0000 h'ffff 0c00 8, 16, 32 area control register 1 (for area 0) acr1_0 r/w h'07ff h'ffff 0c10 8, 16, 32 area control register 1 (for area 1) acr1_1 r/w h'07ff h'ffff 0c12 8, 16, 32 area control register 1 (for area 2) acr1_2 r/w h'07ff h'ffff 0c14 8, 16, 32 area control register 1 (for area 3) acr1_3 r/w h'07ff h'ffff 0c16 8, 16, 32 area control register 1 (for area 4) acr1_4 r/w h'0000 h'ffff 0c20 8, 16, 32 area control register 1 (for area 5) acr1_5 r/w h'0000 h'ffff 0c22 8, 16, 32 wait control register (for area 0) wcr_0 r/w h'fffe h'ffff 0c30 8, 16, 32 wait control register (for area 1) wcr_1 r/w h'fffe h'ffff 0c32 8, 16, 32 wait control register (for area 2) wcr_2 r/w h'fffe h'ffff 0c34 8, 16, 32 wait control register (for area 3) wcr_3 r/w h'fffe h'ffff 0c36 8, 16, 32 dram control register 1 dcr1 r/w h'0000 h'ffff 0c40 8, 16, 32 dram control register 2 dcr2 r/w h'1fe0 h'ffff 0c42 8, 16, 32 dram control register 3 dcr3 r/w h'1800 h'ffff 0c44 8, 16, 32 refresh timer control/status register rtcsr r/w h'0000 h'ffff 0c68 8, 16, 32 refresh timer counter rtcnt r/w h'0000 h'ffff 0c6a 8, 16, 32 refresh time constant counter rtcor r/w h'0000 h'ffff 0c6c 8, 16, 32 refresh count register rfcr r/w h'0000 h'ffff 0c6e 8, 16, 32 rev. 1.0, 08/99, page 214 of 875 8.1.5 address format figure 8.2 shows the address format used in the sh7065. a31 a30Ca26 a25 cs space selection: decoded, outputs to space selection: not output externally; used for space type selection 0: cs space 1: xram/yram space, on-chip peripheral module space output address: output from address pins a0 figure 8.2 address format the sh7065 uses 32-bit addresses. bit a31 is used to select the type of space. this signal is not output externally. bits a30 to a26 are decoded to provide the chip select signal ( cs0 to cs5 ) for the area, which is output. bits a25 to a0 are output externally. table 8.3 shows the address maps when the maximum range is set for each space. rev. 1.0, 08/99, page 215 of 875 table 8.3 address maps ? in on-chip rom disabled modes addresses type of space type of memory size bus width h'0000 0000 to h'03ff ffff cs0 space normal space 64 mb 8/16/32 bits h'0400 0000 to h'07ff ffff cs1 space 64 mb 8/16/32 bits h'0800 0000 to h'0bff ffff cs2 space 64 mb 8/16/32 bits h'0c00 0000 to h'0fff ffff cs3 space normal space/ multiplexed i/o space 64 mb 8/16/32 bits h'1000 0000 to h'3fff ffff reserved reserved h'4000 0000 to h'43ff ffff cs4 space dram 64 mb 8/16/32 bits h'4400 0000 to h'47ff ffff cs5 space 64 mb 8/16/32 bits h'4800 0000 to h'57ff ffff reserved reserved h'5800 0000 to h'5803 ffff on-chip rom * on-chip rom * 256 kb 32 bits h'5804 0000 to h'fffe ffff reserved reserved h'ffff 0000 to h'ffff 13ff on-chip peripheral module on-chip peripheral module 5 kb 8/16 bits h'ffff 1400 to h'ffff 7fff reserved reserved h'ffff 8000 to h'ffff 8fff xram xram 4 kb 32 bits h'ffff 9000 to h'ffff 9fff reserved reserved h'ffff a000 to h'ffff afff yram yram 4 kb 32 bits h'ffff b000 to h'ffff ffff reserved reserved note: * in this mode, the power-on reset vector table is located in the cs0 space (external space). also, addresses h'5800 0000 to h'5803 ffff can be used as on-chip rom. rev. 1.0, 08/99, page 216 of 875 ? in on-chip rom enabled modes addresses type of space type of memory size bus width h'0000 0000 to h'0003 ffff on-chip rom on-chip rom 256 kb 32 bits h'0004 0000 to h'00ff ffff reserved reserved h'0100 0000 to h'03ff ffff cs0 space normal space 48 mb 8/16/32 bits h'0400 0000 to h'07ff ffff cs1 space 64 mb 8/16/32 bits h'0800 0000 to h'0bff ffff cs2 space 64 mb 8/16/32 bits h'0c00 0000 to h'0fff ffff cs3 space normal space/ multiplexed i/o space 64 mb 8/16/32 bits h'1000 0000 to h'3fff ffff reserved reserved h'4000 0000 to h'43ff ffff cs4 space dram 64 mb 8/16/32 bits h'4400 0000 to h'47ff ffff cs5 space 64 mb 8/16/32 bits h'4800 0000 to h'57ff ffff reserved reserved h'5800 0000 to h'5803 ffff on-chip rom * on-chip rom * 256 kb 32 bits h'5804 0000 to h'fffe ffff reserved reserved h'ffff 0000 to h'ffff 13ff on-chip peripheral module on-chip peripheral module 5 kb 8/16 bits h'ffff 1400 to h'ffff 7fff reserved reserved h'ffff 8000 to h'ffff 8fff xram xram 4 kb 32 bits h'ffff 9000 to h'ffff 9fff reserved reserved h'ffff a000 to h'ffff afff yram yram 4 kb 32 bits h'ffff b000 to h'ffff ffff reserved reserved note: * the same data as in on-chip rom addresses h'0000 0000 to h'0003 ffff can be read. rev. 1.0, 08/99, page 217 of 875 8.2 register descriptions 8.2.1 bus control register (bcr) the bus control register (bcr) is a 16-bit readable/writable register that specifies bus settings common to all areas. bcr is initialized to h'0000 by a power-on reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 brqebashizcnt initial value:00000000 r/w:r/wr/wr/wrrrrr bit:76543210 initial value:00000000 r/w:rrrrrrrr bit 15breq enable (brqe): enables or disables acceptance of the bus release request (breq). bit 15: brqe description 0 bus release request (breq) is not accepted (initial value) 1 bus release request (breq) is accepted bit 14byte access specification (bas): specifies the byte access control signals. bit 14: bas description 0 access by wrhh , wrhl , wrlh , and wrll signals (initial value) 1 access by wr , hhbs , hlbs , lhbs , and llbs signals rev. 1.0, 08/99, page 218 of 875 bit 13high-impedance control (hizcnt): specifies the state of the ras and cas signals (which control the dram self-refresh status) in standby mode and when the bus is released. this enables the dram to be kept in the self-refresh state. bit 13: hizcnt description 0 the ras and cas signals go to the high-impedance (hi-z) state in standby mode and when the bus is released (initial value) 1 the ras and cas signals drive in standby mode and when the bus is released bits 12 to 0reserved: these bits are always read as 0 and should only be written with 0. 8.2.2 area control registers 1 (acr1_0 to acr1_5) the acr1 registers are 16-bit readable/writable registers that specify the type of memory to be connected to each area, acceptance of external waits, bus width, number of idle cycles, and number of cs expansion cycles. the acr1 registers are initialized to h'07ff (acr1_0 to acr1_3 for areas 0 to 3) or h'0000 (acr1_4 and acr1_5 for areas 4 and 5) by a power-on reset, but are not initialized in standby mode. registers acr1_0 to acr1_3 (forareas 0 to 3) bit: 15 14 13 12 11 10 9 8 endian tp1 tp0 exwe sz1 sz0 iw2 initial value:00000111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 iw1 iw0 swh2 swh1 shw0 swt2 swt1 swt0 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit 15endian specification (endian): specifies the endian mode for each area. bit 15: endian description 0 big-endian mode (initial value) 1 little-endian mode rev. 1.0, 08/99, page 219 of 875 bits 14 and 13memory specification (tp1, tp0): these bits specify the type of memory or i/o connected to each area. bit 14: tp1 bit 13: tp0 description 0 0 access as normal space (initial value) 1 reserved (do not set) 1 0 access as multiplexed address/data i/o space 1 reserved (do not set) note: area 0 is always normal space. for this space, these bits are always read as 0 and should only be written with 0. bit 12external wait enable (exwe): specifies for each area whether or not wait requests via the external wait pin are to be accepted. bit 12: exwe description 0 external wait requests are accepted (initial value) 1 external wait requests are not accepted bit 11reserved: this bit is always read as 0 and should only be written with 0. bits 10 and 9bus width specification (sz1, sz0): these bits specify the bus width of each area. bit 10: sz1 bit 9: sz0 description 0 0 reserved (do not set) 18 bits 1 0 16 bits 1 32 bits (initial value) note: in romless expanded mode, the bus width of the cs0 space is set by pins md0 and md1. for details, see section 8.3.2, areas. rev. 1.0, 08/99, page 220 of 875 bits 8 to 6inter-cycle idle specification (iw2 to iw0): these bits specify the number of idle cycles between bus cycles to be inserted for each area when switching to a different space, or from read access to write access in the same space. the idle cycle specification for the area accessed immediately before is valid. when switching to access to a different space, one idle cycle is inserted automatically in the case of a read cycle, and two idle cycles in the case of a write cycle, even if no idle cycles is set. when switching from read cycle to write cycle in the same space, two idle cycles are inserted automatically even if no idle cycles is set. bit 8: iw2 bit 7: iw1 bit 6: iw0 description 000no idle cycles 1 1 idle cycle inserted 10 2 idle cycles inserted :::: 1106 idle cycles inserted 1 7 idle cycles inserted (initial value) bits 5 to 3extension cycles after cs cs cs cs assertion (swh2 to swh0): these bits specify, for each area, the number of cycles to be inserted between assertion of the cs signal and assertion of the rd signal or wr signal. bit 5: swh2 bit 4: swh1 bit 3: swh0 description 000no extension cycles 1 1 extension cycle inserted 10 2 extension cycles inserted :::: 1106 extension cycles inserted 1 7 extension cycles inserted (initial value) bits 2 to 0extension cycles before cs cs cs cs negation (swh2 to swh0): these bits specify, for each area, the number of cycles to be inserted between negation of the rd signal or wr signal and negation of the cs signal. rev. 1.0, 08/99, page 221 of 875 bit 2: swt2 bit 1: swt1 bit 0: swt0 description 000no extension cycles 1 1 extension cycle inserted 10 2 extension cycles inserted :::: 1106 extension cycles inserted 1 7 extension cycles inserted (initial value) registers acr1_4 and acr1_5 (for areas 4 and 5) bit: 15 14 13 12 11 10 9 8 endianexwe initial value:00000000 r/w: r/w r r r/w r/w r r r bit:76543210 initial value:00000000 r/w:rrrrrrrr bit 15endian specification (endian): specifies the endian mode for each area. bit 15: endian description 0 big-endian mode (initial value) 1 little-endian mode bits 14 and 13reserved: these bits are always read as 0 and should only be written with 0. bit 12external wait enable (exwe): specifies for each area whether or not wait requests via the external wait pin are to be accepted. bit 12: exwe description 0 external wait requests are accepted (initial value) 1 external wait requests are not accepted bits 11 to 0reserved: these bits are always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 222 of 875 8.2.3 wait control registers (wcr_0 to wcr_3) the wait control registers (wcr) are 16-bit readable/writable registers that specify the number of wait state cycles to be inserted in areas 0 to 3. the wcr registers are initialized to h'fffe by a power-on reset, but are not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 w3 w2 w1 w0 dsww3 dsww2 dsww1 dsww0 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 dswr3 dswr2 dswr1 dswr0 hww2 hww1 hww0 initial value:11111110 r/w: r/w r/w r/w r/w r/w r/w r/w r bits 15 to 12wait state insertion cycle specification (w3 to w0): these bits specify the number of wait states to be inserted in areas 0 to 3. bit 15: w3 bit 14: w2 bit 13: w1 bit 12: w0 description 0000no waits 11 wait 102 waits ::::: 111014 waits 1 15 waits (initial value) bits 11 to 8cs0 to cs3 space dma single address mode write access wait state insertion cycle specification (dsww3 to dsww0): these bits specify the number of wait states to be inserted in writes to spaces cs0 to cs3 in dma single address mode. rev. 1.0, 08/99, page 223 of 875 bit 11: dsww3 bit 10: dsww2 bit 9: dsww1 bit 8: dsww0 description 0000no waits 11 wait 102 waits ::::: 111014 waits 1 15 waits (initial value) bits 7 to 4cs0 to cs3 space dma single address mode read access wait state insertion cycle specification (dswr3 to dswr0): these bits specify the number of wait states to be inserted in reads from spaces cs0 to cs3 in dma single address mode. bit 7: dswr3 bit 6: dswr2 bit 5: dswr1 bit 4: dswr0 description 0000no waits 11 wait 102 waits ::::: 111014 waits 1 15 waits (initial value) bits 3 to 1wait state insertion cycles after external wait wait wait wait pin negation (hww2 to hww0): these bits specify the number of wait states to be inserted after external wait pin negation in areas 0 to 3. this specification is valid only when a hard wait is inserted by means of the external wait pin. if a hard wait is not inserted, the wait states specified by these bits will not be inserted. bit 3: hww2 bit 2: hww1 bit 1: hww0 description 000no waits 11 wait 102 waits :::: 1106 waits 1 7 waits (initial value) bit 0reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 224 of 875 8.2.4 dram control register 1 (dcr1) dram control register 1 (dcr1) is a 16-bit readable/writable register that specifies dram control. control is the same for cs4 and cs5 space accesses. dcr1 is initialized to h'0000 by a power-on reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 tpc1 tpc0 tpcs2 tpcs1 tpcs0 rcd2 rcd1 rcd0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 dww1 dww0 dwr1 dwr0 initial value:00000000 r/w: r r r/w r/w r/w r/w r r bits 15 and 14ras precharge interval specification (tpc1, tpc0): these bits specify, for dram, the minimum number of cycles before ras is asserted again after being negated. bit 15: tpc1 bit 14: tpc0 description 0 0 1 cycle (initial value) 1 2 cycles 1 0 3 cycles 1 4 cycles bits 13 to 11ras precharge interval immediately after self-refreshing (tpcs2 to tpcs0): these bits specify, for dram, the ras precharge interval immediately after self- refreshing. bit 13: tpcs2 bit 12: tpcs1 bit 11: tpcs0 description 0 0 0 cycles specified by tpc + 0 cycles (initial value) 1 cycles specified by tpc + 1 cycle 1 0 cycles specified by tpc + 2 cycles :::: 1 1 0 cycles specified by tpc + 6 cycles 1 cycles specified by tpc + 7 cycles rev. 1.0, 08/99, page 225 of 875 bits 10 to 8ras-cas delay specification (rcd2 to rcd0): these bits specify the dram ras-cas delay time. description bit 10: rcd2 bit 9: rcd1 bit 8: rcd0 normal access edo access 0 0 0 1 cycle (initial value) 1 cycle (initial value) 1 2 cycles do not set :::: : 1 1 0 7 cycles do not set 1 8 cycles do not set note: use the one cycle setting for edo dram. bits 7 and 6reserved: these bits are always read as 0 and should only be written with 0. bits 5 and 4write cycle column address output cycle interval specification (dww1, dww0): these bits specify the column address output cycle interval in a dram write cycle. description bit 5: dww1 bit 4: dww0 in normal write cycle in edo write cycle in edo burst write cycle 0 0 2 cycles (no waits) * 2 cycles (no waits) * 1 cycle (no waits) * 1 3 cycles (1 wait) do not set do not set 1 0 4 cycles (2 waits) do not set do not set 1 5 cycles (3 waits) do not set do not set note: * initial value use the no wait setting for edo dram. bits 3 and 2read cycle column address output cycle interval specification (dwr1, dwr0): these bits specify the column address output cycle interval in a dram read cycle. description bit 3: dwr1 bit 2: dwr0 in normal read cycle in edo read cycle in edo burst read cycle 0 0 2 cycles (no waits) * 2 cycles (no waits) * 1 cycle (no waits) * 1 3 cycles (1 wait) do not set do not set 1 0 4 cycles (2 waits) do not set do not set 1 5 cycles (3 waits) do not set do not set note: * initial value use the no wait setting for edo dram. rev. 1.0, 08/99, page 226 of 875 bits 1 and 0reserved: these bits are always read as 0 and should only be written with 0. 8.2.5 dram control register 2 (dcr2) dram control register 2 (dcr2) is a 16-bit readable/writable register that specifies dram control. control is the same for cs4 and cs5 space accesses. dcr2 is initialized to h'1fe0 by a power-on reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 diw2 diw1 diw0 ddww3 ddww2 ddww1 ddww0 ddwr3 initial value:00011111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 ddwr2 ddwr1 ddwr0 rdw tcas initial value:11100000 r/w: r/w r/w r/w r/w r/w r r r bits 15 to 13idle cycles after dram access (diw2 to diw0): these bits specify the number of idle cycles to be inserted between bus cycles when access is switched from the cs4 or cs5 space to another space, or from read access to write access within the same cs4 or cs5 space. when switching to access to a different space, one idle cycle is inserted automatically in the case of a read cycle, and two idle cycles in the case of a write cycle, even if no idle cycles is set. when switching from a read cycle to a write cycle within the same space, two idle cycles are inserted automatically. bit 15: diw2 bit 14: diw1 bit 13: diw0 description 0 0 0 no idle cycles (initial value) 1 1 idle cycle inserted 1 0 2 idle cycles inserted :::: 1106 idle cycles inserted 1 7 idle cycles inserted rev. 1.0, 08/99, page 227 of 875 bits 12 to 9dma single address mode write access wait state insertion cycle specification (ddww3 to ddww0): these bits specify the number of wait states to be inserted in writes to dram in dma single address mode. description bit 12: ddww3 bit 11: ddww2 bit 10: ddww1 bit 9: ddww0 normal access edo access 0000no waits no waits 1 1 wait do not set 1 0 2 waits do not set ::::: : 1 1 1 0 14 waits do not set 1 15 waits (initial value) do not set (initial value) note: use the no wait setting for edo dram. bits 8 to 5dma single address mode read access wait state insertion cycle specification (ddwr3 to ddwr0): these bits specify the number of wait states to be inserted in reads from dram in dma single address mode. description bit 8: ddwr3 bit 7: ddwr2 bit 6: ddwr1 bit 5: ddwr0 normal access edo access 0000no waits no waits 1 1 wait do not set 1 0 2 waits do not set ::::: : 1 1 1 0 14 waits do not set 1 15 waits (initial value) do not set (initial value) note: use the no wait setting for edo dram. bit 4idle cycle insertion before continuous burst operation in dma single transfer in ras down mode (rdw): specifies whether one idle cycle is to be inserted before burst operation when the same dram row address is accessed in dma single mode during ras down mode. this cycle is inserted only when access is switched from another space to the cs4 space or cs5 space, or from read access to write access within the same cs4 or cs5 space. bit 4: rdw description 0 no idle cycle (initial value) 1 1 idle cycle inserted rev. 1.0, 08/99, page 228 of 875 bit 3write cycle cas assertion width with software wait setting (tcas): specifies the cas assertion width in a dram write cycle. description bit 3: tcas normal access edo access 0 1 cycle (initial value) 1 cycle (initial value) 1 2 cycles do not set note: use the no wait setting for edo dram. bits 2 to 0reserved: these bits are always read as 0 and should only be written with 0. 8.2.6 dram control register 3 (dcr3) dram control register 3 (dcr3) is a 16-bit readable/writable register that specifies dram control. control is the same for cs4 and cs5 space accesses. dcr3 is initialized to h'1800 by a power-on reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 be rsd edo dsz1 dsz0 amx2 amx1 amx0 initial value:00011000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 rfshrmd initial value:00000000 r/w:r/wr/wrrrrrr bit 15burst enable (be): specifies whether or not burst access is performed on dram. bit 15: be description 0 burst disabled (initial value) 1 access in fast page mode rev. 1.0, 08/99, page 229 of 875 bit 14ras down mode (rsd): specifies whether or not ras down mode access is performed on dram. bit 14: rsd description 0 dram accessed in ras up mode (initial value) 1 dram accessed in ras down mode bit 13edo mode (edo): specifies whether or not edo mode access is performed on dram. bit 13: edo description 0 dram accessed in normal mode (initial value) 1 dram accessed in edo mode bits 12 and 11bus width specification (dsz1, dsz0): these bits specify the bus width for dram. bit 12: dsz1 bit 11: dsz0 description 0 0 reserved (do not set) 18 bits 1 0 16 bits 1 32 bits (initial value) bits 10 to 8address multiplexing specification (amx2 to amx0): these bits specify dram address multiplexing. bit 10: amx2 bit 9: amx1 bit 8: amx0 description 0 0 0 9 bits (initial value) 1 10 bits 1 0 11 bits 1 12 bits 1 0 0 13 bits 1 14 bits 1 0 15 bits 1 16 bits rev. 1.0, 08/99, page 230 of 875 bit 7refresh control (rfsh): specifies whether or not refreshing is performed for dram. when the refresh function is not used, the refresh request cycle generation timer can be used as an interval timer. bit 7: rfsh description 0 refreshing is not performed (initial value) 1 refreshing is performed bit 6refresh mode (rmd): specifies whether normal refreshing or self-refreshing is performed for dram when the rfsh bit is set to 1. when the rfsh bit is 1 and this bit is cleared to 0, cas-before-ras refreshing is performed using the cycle set with refresh-related registers rtcnt, rtcor, and rtcsr. if a refresh request is issued during execution of an external bus cycle, the refresh cycle is executed when the bus cycle ends. when the rfsh bit is 1 and this bit is set to 1, the self-refresh state is set after waiting for the end of any currently executing external bus cycle. all refresh requests for memory in the self-refresh state are ignored. bit 6: rmd description 0 cas-before-ras refreshing is performed (initial value) 1 self-refreshing is performed bits 5 to 0reserved: these bits are always read as 0 and should only be written with 0. 8.2.7 refresh timer control/status register (rtcsr) the refresh timer control/status register (rtcsr) is a 16-bit readable/writable register that specifies the refresh cycle, whether interrupts are to be generated, and if so the interrupt cycle. rtcsr is initialized to h'0000 by a power-on reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 cmf cmie cks2 cks1 cks0 ovf ovie lmts1 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 lmts0 bref2 bref1 bref0 tras2 tras1 tras0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r rev. 1.0, 08/99, page 231 of 875 bit 15compare match flag (cmf): status flag that indicates a match between the refresh timer counter (rtcnt) and refresh time constant register (rtcor) values. bit 15: cmf description 0 rtcnt and rtcor values do not match (initial value) [clearing conditions] when 0 is written to cmf after reading rtcsr when cmf = 1, or when refreshing is performed with rfsh = 1 and rmd = 0 (cbr refreshing performed) 1 rtcnt and rtcor values match [setting condition] when rtcnt = rtcor bit 14compare match interrupt enable (cmie): controls generation or suppression of an interrupt request when the cmf flag is set to 1 in rtcsr. do not set this bit to 1 when cas- before-ras refreshing is used. bit 14: cmie description 0 interrupts initiated by cmf are disabled (initial value) 1 interrupts initiated by cmf are enabled bits 13 to 11clock select bits (cks2 to cks0): these bits select the rtcnt input clock. the base clock is the external bus clock (cke). the rtcnt count clock is obtained by scaling cke by the specified factor. to change the division ratio (scaling factor), first clear bits cks0 to cks2 to 0, then write the required value in these bits. bit 13: cks2 bit 12: cks1 bit 11: cks0 description 0 0 0 clock input disabled (initial value) 1 external bus clock (cke) /4 1 0 external bus clock (cke) /16 1 external bus clock (cke) /64 1 0 0 external bus clock (cke) /256 1 external bus clock (cke) /1024 1 0 external bus clock (cke) /2048 1 external bus clock (cke) /4096 rev. 1.0, 08/99, page 232 of 875 bit 10refresh count overflow flag (ovf): status flag that indicates that the number of refresh requests indicated by the refresh count register (rfcr) has exceeded the number specified by the lmts bits in rtcsr. bit 10: ovf description 0 rfcr has not overflowed the count limit indicated by the lmts bits [clearing condition] when rtcsr is read while ovf = 1, then 0 is written to ovf (initial value) 1 rfcr has overflowed the count limit indicated by the lmts bits [setting condition] when rfcr overflows the count limit indicated by the lmts bits bit 9refresh count overflow interrupt enable (ovie): controls generation or suppression of an interrupt request when the ovf flag is set to 1 in rtcsr. bit 9: ovie description 0 interrupts initiated by ovf are disabled (initial value) 1 interrupts initiated by ovf are enabled bits 8 and 7refresh count overflow limit select (lmts1, lmts0): these bits specify the count limit to be compared with the refresh count indicated by the refresh count register (rfcr). if the rfcr register value exceeds the value specified by the lmts bits, the ovf flag is set to 1. bit 8: lmts1 bit 7: lmts0 description 0 0 refresh count limit is 4096 (initial value) 1 refresh count limit is 2048 1 0 refresh count limit is 1024 1 refresh count limit is 512 rev. 1.0, 08/99, page 233 of 875 bits 6 to 4refresh request number select (bref2 to bref0): these bits specify the number of consecutive refresh requests requested by a single compare match. the number of cas-before-ras refreshes specified by these bits are performed consecutively. bit 6: bref2 bit 5: bref1 bit 4: bref0 description 0 0 0 1 cas-before-ras refresh is performed (initial value) 1 2 consecutive cas-before-ras refreshes are performed 1 0 3 consecutive cas-before-ras refreshes are performed 1 4 consecutive cas-before-ras refreshes are performed 1 0 0 5 consecutive cas-before-ras refreshes are performed 1 6 consecutive cas-before-ras refreshes are performed 1 0 7 consecutive cas-before-ras refreshes are performed 1 8 consecutive cas-before-ras refreshes are performed bits 3 to 1refresh ras assertion interval specification (tras2 to tras0): these bits specify the refresh interval of the dram connected to areas 4 and 5. with dram, this is the ras assertion interval in cas-before-ras refreshing. bit 3: tras2 bit 2: tras1 bit 1: tras0 description 0 0 0 2 cycles (initial value) 1 3 cycles 1 0 4 cycles 1 5 cycles 1006 cycles 1 7 cycles 1 0 8 cycles 1 9 cycles bit 0reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 234 of 875 8.2.8 refresh timer counter (rtcnt) the refresh timer counter (rtcnt) is an 8-bit readable/writable counter that is incremented by the input clock selected by bits cks2 to cks0 in the rtcsr register. when the rtcnt counter value matches the rtcor register value, the cmf bit is set in the rtcsr register and the rtcnt counter is cleared. rtcnt bits 15 to 8 are reserved; they are always read as 0 and should only be written with 0. rtcnt is initialized to h'0000 by a power-on reset. in standby mode, rtcnt is not initialized, and retains its contents. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 rtcnt7 rtcnt6 rtcnt5 rtcnt4 rtcnt3 rtcnt2 rtcnt1 rtcnt0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w rev. 1.0, 08/99, page 235 of 875 8.2.9 refresh time constant register (rtcor) the refresh time constant register (rtcor) is a 16-bit readable/writable register that specifies the upper limit of the rtcnt counter. the rtcor register and rtcnt counter values (lower 8 bits) are constantly compared, and when they match the cmf bit is set in the rtcsr register and the rtcnt counter is cleared to 0. if rfsh has been set to 1 and rmd has been cleared to 0 in dram control register 3 (dcr3), cas-before-ras refreshing is performed. if the cmie bit has been set to 1 in rtcsr, a compare match interrupt (cmi) is generated. rtcor bits 15 to 8 are reserved; they are always read as 0 and should only be written with 0. rtcor is initialized to h'0000 by a power-on reset, but is not initialized in standby mode. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 rtcor7 rtcor6 rtcor5 rtcor4 rtcor3 rtcor2 rtcor1 rtcor0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w rev. 1.0, 08/99, page 236 of 875 8.2.10 refresh count register (rfcr) the refresh count register (rfcr) is a 12-bit readable/writable counter that counts the number of refreshes by being incremented each time the rtcor register and rtcnt counter values match. if the rfcr register value exceeds the count limit specified by bits lmts1 and lmts0 in the rtcsr register, the ovf flag is set in the rtcsr register and the rfcr register is cleared. rfcr bits 15 to 12 are reserved; they are always read as 0 and should only be written with 0. rfcr is initialized to h'0000 by a power-on reset. in standby mode, rfcr is not initialized, and retains its contents. bit: 15 14 13 12 11 10 9 8 rfcr11rfcr10rfcr9rfcr8 initial value:00000000 r/w:rrrrr/wr/wr/wr/w bit:76543210 rfcr7 rfcr6 rfcr5 rfcr4 rfcr3 rfcr2 rfcr1 rfcr0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w rev. 1.0, 08/99, page 237 of 875 8.3 operation 8.3.1 endian/access size and data alignment the sh7065 supports both big-endian mode, in which the most significant byte (msbyte) is at the 0 address end in a string of byte data, and little-endian mode, in which the least significant byte (lsbyte) is at the 0 address end. the mode is set by means of the endian bit in area control register 1 (acr1_0 to acr1_5). a data bus width of 8, 16, or 32 bits can be selected for normal memory and dram. for multiplexed i/o there is a choice of 8 or 16 bits. data alignment is carried out according to the data bus width and endian mode of each device. thus, four read operations are needed to read longword data from an 8-bit device. in the sh7065, data alignment and data length conversion between the different interfaces is performed automatically. the relationship between the endian mode, device data width, and access unit, is shown in tables 8.4 to 8.9. instruction codes should be handled as word data. similarly, with a 32-bit instruction code, handle the a-field and b-field instruction codes as word data. table 8.4 32-bit external device/big-endian access and data alignment data bus strobe signals operation d31C d24 d23C d16 d15C d8 d7C d0 wrhh, hhbs, cashh wrhl, hlbs, cashl wrlh, lhbs, caslh wrll, llbs, casll address 0 byte access data 7C0 asserted address 1 byte access data 7C0 asserted address 2 byte access data 7C0 asserted address 3 byte accessdata 7C0 asserted address 0 word access data 15C8 data 7C0 asserted asserted address 2 word access data 15C8 data 7C0 asserted asserted address 0 longword access data 31C24 data 23C16 data 15C8 data 7C0 asserted asserted asserted asserted rev. 1.0, 08/99, page 238 of 875 table 8.5 16-bit external device/big-endian access and data alignment data bus strobe signals operation d31C d24 d23C d16 d15C d8 d7C d0 wrhh, hhbs, cashh wrhl, hlbs, cashl wrlh, lhbs, caslh wrll, llbs, casll address 0 byte access data 7C0 asserted address 1 byte accessdata 7C0 asserted address 2 byte access data 7C0 asserted address 3 byte accessdata 7C0 asserted address 0 word access data 15C8 data 7C0 asserted asserted address 2 word access data 15C8 data 7C0 asserted asserted 1st access (address 0) data 31C24 data 23C16 asserted asserted address 0 longword access 2nd access (address 2) data 15C8 data 7C0 asserted asserted rev. 1.0, 08/99, page 239 of 875 table 8.6 8-bit external device/big-endian access and data alignment data bus strobe signals operation d31C d24 d23C d16 d15C d8 d7C d0 wrhh, hhbs, cashh wrhl, hlbs, cashl wrlh, lhbs, caslh wrll, llbs, casll address 0 byte accessdata 7C0 asserted address 1 byte accessdata 7C0 asserted address 2 byte accessdata 7C0 asserted address 3 byte accessdata 7C0 asserted 1st access (address 0) data 15C8 asserted address 0 word access 2nd access (address 1) data 7C0 asserted 1st access (address 2) data 15C8 asserted address 2 word access 2nd access (address 3) data 7C0 asserted 1st access (address 0) data 31C24 asserted 2nd access (address 1) data 23C16 asserted 3rd access (address 2) data 15C8 asserted address 0 longword access 4th access (address 3) data 7C0 asserted rev. 1.0, 08/99, page 240 of 875 table 8.7 32-bit external device/little-endian access and data alignment data bus strobe signals operation d31C d24 d23C d16 d15C d8 d7C d0 wrhh, hhbs, cashh wrhl, hlbs, cashl wrlh, lhbs, caslh wrll, llbs, casll address 0 byte accessdata 7C0 asserted address 1 byte access data 7C0 asserted address 2 byte access data 7C0 asserted address 3 byte access data 7C0 asserted address 0 word access data 15C8 data 7C0 asserted asserted address 2 word access data 15C8 data 7C0 asserted asserted address 0 longword access data 31C24 data 23C16 data 15C8 data 7C0 asserted asserted asserted asserted rev. 1.0, 08/99, page 241 of 875 table 8.8 16-bit external device/little-endian access and data alignment data bus strobe signals operation d31C d24 d23C d16 d15C d8 d7C d0 wrhh, hhbs, cashh wrhl, hlbs, cashl wrlh, lhbs, caslh wrll, llbs, casll address 0 byte accessdata 7C0 asserted address 1 byte access data 7C0 asserted address 2 byte accessdata 7C0 asserted address 3 byte access data 7C0 asserted address 0 word access data 15C8 data 7C0 asserted asserted address 2 word access data 15C8 data 7C0 asserted asserted 1st access (address 0) data 15C8 data 7C0 asserted asserted address 0 longword access 2nd access (address 2) data 31C24 data 23C16 asserted asserted rev. 1.0, 08/99, page 242 of 875 table 8.9 8-bit external device/little-endian access and data alignment data bus strobe signals operation d31C d24 d23C d16 d15C d8 d7C d0 wrhh, hhbs, cashh wrhl, hlbs, cashl wrlh, lhbs, caslh wrll, llbs, casll address 0 byte accessdata 7C0 asserted address 1 byte accessdata 7C0 asserted address 2 byte accessdata 7C0 asserted address 3 byte accessdata 7C0 asserted 1st access (address 0) data 7C0 asserted address 0 word access 2nd access (address 1) data 15C8 asserted 1st access (address 2) data 7C0 asserted address 2 word access 2nd access (address 3) data 15C8 asserted 1st access (address 0) data 7C0 asserted 2nd access (address 1) data 15C8 asserted 3rd access (address 2) data 23C16 asserted address 0 longword access 4th access (address 3) data 31C24 asserted rev. 1.0, 08/99, page 243 of 875 8.3.2 areas area 0: for area 0, address bits a31 to a26 are 000000. however, in the on-chip rom enabled modes, the space from h'0000 0000 to h'0003 ffff is allocated to on-chip rom. enabling or disabling of on-chip rom is selected in a power-on reset by means of external pins md2, md1, and md0. normal memory such as sram and rom can be connected to this space. a value of 0 must always be written to bits tp1 and tp0 in the acr1 register. these bits are always read as 0. a bus width of 8, 16, or 32 bits can be selected in a power-on reset by means of external pins md1 and md0. when area 0 space is accessed, the cs0 signal is asserted. in addition, the rd signal, which can be used as the sram and rom oe signal, and write control signals wrhh to wrll , are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected with bits w3 to w0 in the wcr register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). areas 1 to 3: for areas 1 to 3, address bits a31 to a26 are 000001 to 000011. normal memory such as sram and rom, and address/data multiplexed i/o devices, can be connected to this space. the kind of memory control to be performed is set with bits tp1 and tp0 in the acr1 register provided for each area. a bus width of 8, 16, or 32 bits can be selected in a power-on reset with bits sz1 and sz0 in the acr1 register provided for each area. however, when a multiplexed address/data i/o device is connected, bits sz1 and sz0 in the acr1 register are ignored, and the bus width is 8 bits when address bit a14 is 0, and 16 bits when 1. when area 1, 2, or 3 space is accessed, the cs1 , cs2 , or cs3 signal is asserted, respectively. in addition, the rd signal, which can be used as the sram and rom oe signal, and write control signals wrhh to wrll , are asserted. as regards the number of bus cycles, from 0 to 15 waits can be selected with bits w3 to w0 in the wcr register provided for each area. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). areas 4 and 5: for areas 4 and 5, address bits a31 to a26 are 010000 and 010001, respectively. a bus width of 8, 16, or 32 bits can be selected in a power-on reset with bits dsz1 and dsz0 in the dcr3 register. rev. 1.0, 08/99, page 244 of 875 when area 4 or 5 space is accessed, the cs4 or cs5 signal is asserted, respectively. the ras signal, the cashh , cashl , caslh , and casll signals, and the rdwr signal are asserted, and address multiplexing is performed. ras , cas , and data timing control, and address multiplexing control, can be set with registers dcr1 to dcr3. as regards the number of bus cycles, from 0 to 3 waits can be selected with a setting in the dcr1 register. in addition, any number of waits can be inserted in each bus cycle by means of the external wait pin ( wait ). however, a wait setting should not be made for edo dram. 8.3.3 normal space access basic timing: the sh7065 uses strobe signal output for normal space access in consideration of the fact that mainly static ram will be directly connected. figure 8.3 shows the basic timing of normal space accesses. a no-wait normal access is completed in two cycles. the bs signal is asserted for one cycle to indicate the start of a bus cycle. there is no access size specification when reading. the correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in the case of a 32-bit device, and 16 bits in the case of a 16-bit device, using the necessary byte value. when writing, only the wrll to wrhh signal for the byte to be written, or the wr signal and llbs to hhbs are asserted, according to the setting of the bas bit in the bcr register. for details, see section 8.3.1, endian/access size and data alignment. rev. 1.0, 08/99, page 245 of 875 t1 t2 cke * a25Ca0 C d31Cd0 C d31Cd0 read write note: * when the setting cke = ckio is made in clock mode 0 to 3, 6, or 7, cke is identical to ckio on the timing chart. in clock modes 4 and 5, the phases of cke and ckio do not coincide, but the relative relationship of the ac specifications is the same as in the other clock modes. figure 8.3 basic timing of normal space access rev. 1.0, 08/99, page 246 of 875 figures 8.4, 8.5, and 8.6 show examples of connection to 32-, 16-, and 8-bit data width sram. figures 8.7 and 8.8 show examples of connection to 32- and 16-bit data width byte-strobe sram. a18 a2 d31 sh7065 d24 d23 d16 d15 d8 d7 d0 128k 8-bit sram a16 a0 i/o7 i/o0 a16 a0 i/o7 i/o0 a16 a0 i/o7 i/o0 a16 a0 i/o7 i/o0 figure 8.4 example of 32-bit data width sram connection rev. 1.0, 08/99, page 247 of 875 a17 a1 d15 sh7065 d8 d7 d0 128k 8-bit sram a16 a0 i/o7 i/o0 a16 a0 i/o7 i/o0 figure 8.5 example of 16-bit data width sram connection a16 a0 d7 sh7065 d0 128k 8-bit sram a16 a0 i/o7 i/o0 figure 8.6 example of 8-bit data width sram connection rev. 1.0, 08/99, page 248 of 875 a18 a2 d31 sh7065 d16 d15 d0 128k 16-bit sram a16 a0 i/o15 i/o0 a16 a0 i/o15 i/o0 figure 8.7 example of 32-bit data width byte-strobe sram connection a17 a1 d15 sh7065 d0 128k 16-bit sram a16 a0 i/o15 i/o0 figure 8.8 example of 16-bit data width byte-strobe sram connection rev. 1.0, 08/99, page 249 of 875 wait state control: wait state insertion in normal space access can be controlled by means of wcr settings. if the wcr wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. for details, see section 8.2.3, wait control register (wcr_0 to wcr_3). the number of tw cycles specified in wcr are inserted as wait cycles using the basic interface wait timing shown in figure 8.9. t1 tw t2 cke * a25Ca0 C d31Cd0 C d31Cd0 read write note: * when the setting cke = ckio is made in clock mode 0 to 3, 6, or 7, cke is identical to ckio on the timing chart. in clock modes 4 and 5, the phases of cke and ckio do not coincide, but the relative relationship of the ac specifications is the same as in the other clock modes. figure 8.9 wait state timing for normal space access (one software wait state inserted) rev. 1.0, 08/99, page 250 of 875 the wait input wait signal from an external source can be sampled by making the appropriate setting for the exwe bit in acr1. wait signal sampling is shown in figure 8.10. the signal is sampled at the rise of the clock in the t2 cycle. by making a setting in bits hww2 to hww0 in wcr, additional software wait states can be inserted after the wait signal is negated. the specified number of thww cycles (see figure 8.10) are inserted as wait cycles after negation of the wait signal. t1 wait state due to wait signal input two thww t2 cke* a25Ca0 csn wr hhbsCllbs rd d31Cd0 wrhhCwrll d31Cd0 bs wait dackn read write note: * when the setting cke = ckio is made in clock mode 0 to 3, 6, or 7, cke is identical to ckio on the timing chart. in clock modes 4 and 5, the phases of cke and ckio do not coincide, but the relative relationship of the ac specifications is the same as in the other clock modes. figure 8.10 wait state timing for normal space access (one wait inserted by wait signal, and one software wait inserted after negation of wait signal) rev. 1.0, 08/99, page 251 of 875 extension of cs cs cs cs assertion interval: by making settings in bits swh2 to swh0 and swt2 to swt0 in acr1, idle cycles can be inserted to prevent the rd or wr assertion interval from extending beyond the csn assertion interval. this allows flexible interfacing to external circuitry. the timing is shown in figure 8.11. the th and tt cycles are added before and after the normal cycles, respectively. the number of th cycles is set in bits swh2 to swh0, and the number of tt cycles in bits swt2 to swt0. in these cycles, only csn is asserted; rd and wr are not. also, since data is extended up to the tt cycle, this feature is useful for devices with slow write operations, for example. th t1 t2 tt cke * a25Ca0 C d31Cd0 C d31Cd0 read write note: * when the setting cke = ckio is made in clock mode 0 to 3, 6, or 7, cke is identical to ckio on the timing chart. in clock modes 4 and 5, the phases of cke and ckio do not coincide, but the relative relationship of the ac specifications is the same as in the other clock modes. figure 8.11 cs cs cs cs assertion interval extension (swh = 1, swt = 1) rev. 1.0, 08/99, page 252 of 875 byte access control: making the appropriate setting for the bas bit in bcr enables byte-strobe type 16-bit-width sram to be connected directly. when the bas bit is cleared to 0, access is performed using the wrhh , wrhl , wrlh , and wrll signals. when the bas bit is set to 1, access is performed using the wr , hhbs , hlbs , lhbs , and llbs signals. also, since the hhbs , hlbs , lhbs , and llbs signals are also asserted in read accesses, it is always possible to know which byte position is being accessed. figure 8.12 shows the timing for a 32-bit-bus-width, big-endian, no-wait write cycle, and figure 8.13 shows the timing for a read cycle. rev. 1.0, 08/99, page 253 of 875 t1 a25Ca0 d31Cd24 d23Cd16 d15Cd8 d7Cd0 address 0 byte access t2 t1 address 1 byte access t2 t1 address 2 byte access t2 t1 address 3 byte access t2 cke * when bas = 0 when bas = 1 note: * when the setting cke = ckio is made in clock mode 0 to 3, 6, or 7, cke is identical to ckio on the timing chart. in clock modes 4 and 5, the phases of cke and ckio do not coincide, but the relative relationship of the ac specifications is the same as in the other clock modes. figure 8.12 byte access control timing (32-bit bus width, big-endian mode, no waits, write cycle) rev. 1.0, 08/99, page 254 of 875 t1 a25Ca0 d31Cd24 d23Cd16 d15Cd8 d7Cd0 address 0 byte access t2 t1 address 1 byte access t2 t1 address 2 byte access t2 t1 address 3 byte access t2 cke * asserted only when bas = 1 note: * when the setting cke = ckio is made in clock mode 0 to 3, 6, or 7, cke is identical to ckio on the timing chart. in clock modes 4 and 5, the phases of cke and ckio do not coincide, but the relative relationship of the ac specifications is the same as in the other clock modes. figure 8.13 byte access control timing (32-bit bus width, big-endian mode, no waits, read cycle) rev. 1.0, 08/99, page 255 of 875 8.3.4 dram interface direct connection of dram: when area 4 or area 5 space is accessed, the target space is 64- mbyte dram space, and the dram interface function can then be used to connect dram directly to the sh7065. as cas is used to control byte access, 2- cas type 16-bit-width drams can be connected. in addition to normal read and write access modes, fast page mode is supported for burst access. edo mode is similarly supported, enabling one-cycle access in burst mode, in particular. address multiplexing: address multiplexing is always performed in accesses to dram. this enables dram, which requires row and column address multiplexing, to be connected directly to the sh7065 without using an external address multiplexer circuit. any of the eight multiplexing methods shown below can be selected, by setting bits amx2 to amx0 in dcr3. the relationship between bits amx2 to amx0 and address multiplexing is shown in table 8.10. the address output pins subject to address multiplexing are a15 to a0. the original address signals are output to pins a25 to a16. table 8.10 relationship between bits amx2 to amx0 and address multiplexing external address pins amx2 amx1 amx0 number of column address bits output timing a0Ca9 a10 a11 a12 a13 a14 a15 0 0 0 9 bits column address a0Ca9 a10 a11 a12 a13 a14 a15 row address a9Ca18 a19 a20 a21 a22 a23 a24 1 10 bits column address a0Ca9 a10 a11 a12 a13 a14 a15 row address a10Ca19 a20 a21 a22 a23 a24 a25 1 0 11 bits column address a0Ca9 a10 a11 a12 a13 a14 a15 row address a11Ca20 a21 a22 a23 a24 a25 a15 1 12 bits column address a0Ca9 a10 a11 a12 a13 a14 a15 row address a12Ca21 a22 a23 a24 a25 a14 a15 1 0 0 13 bits column address a0Ca9 a10 a11 a12 a13 a14 a15 row address a13Ca22 a23 a24 a25 a13 a14 a15 1 14 bits column address a0Ca9 a10 a11 a12 a13 a14 a15 row address a14Ca23 a24 a25 a12 a13 a14 a15 1 0 15 bits column address a0Ca9 a10 a11 a12 a13 a14 a15 row address a15Ca24 a25 a11 a12 a13 a14 a15 1 16 bits column address a0Ca9 a10 a11 a12 a13 a14 a15 row address a16Ca25 a10 a11 a12 a13 a14 a15 rev. 1.0, 08/99, page 256 of 875 basic timing: the basic timing for dram access is 3 cycles. this basic timing is shown in figure 8.14. tr is the ras assert cycle, tc1 the cas assert cycle, and tc2 the read data latch cycle. tr tc1 tc2 cke d31Cd0 (read) d31Cd0 (write) row column a25Ca0 rdwr figure 8.14 dram basic access timing figures 8.15, 8.16, and 8.17 show examples of connection to 32-, 16-, and 8-bit data width dram. rev. 1.0, 08/99, page 257 of 875 a14 a2 rdwr d31 sh7065 d16 d15 d0 64m 16-bit dram a12 a0 i/o15 i/o0 a8 a0 i/o15 i/o0 figure 8.15 example of 32-bit data width dram connection a13 a1 rdwr d15 sh7065 d0 64m 16-bit dram a12 a0 i/o15 i/o0 figure 8.16 example of 16-bit data width dram connection rev. 1.0, 08/99, page 258 of 875 a12 a0 rdwr d7 sh7065 d0 64m 8-bit dram a12 a0 i/o7 i/o0 figure 8.17 example of 8-bit data width dram connection wait state control: as the clock frequency increases, it becomes impossible to complete all states in one cycle as in the basic cycle. therefore, provision is made for state extension by using setting bits in the dcr1 and dcr2 registers. the timing with state extension using these settings is shown in figure 8.18. additional tpc cycles (used to secure the ras precharge time) can be inserted by means of the tpc bits in the dcr1 register; from 1 to 4 cycles can be selected. the number of cycles from ras assertion to cas assertion can be set to between 1 and 8 by inserting trw cycles by means of the rcd bits in the dcr1 register. the number of cycles from cas assertion to the end of the access can be varied, when reading, between 2 and 5 (1 cycle only in edo mode) with the dwr bits in the dcr1 register, enabling cas negation to be extended, and when writing, between 2 and 5 (1 cycle only in edo mode) with the dww bits in the dcr1 register, enabling cas assertion to be extended. in a write, a cas assertion width of 1 or 2 cycles can be set with the tcas bit in the dcr2 register. also, when tcas = 1, the end of the write is extended by 1 cycle. as with normal space, the wait input wait signal from an external source can be sampled by making the appropriate setting for the exwe bit in acr1. wait signal sampling is shown in figure 8.19. the signal is sampled at the rise of the clock in the tc1 cycle. rev. 1.0, 08/99, page 259 of 875 tr trw tc1 tcw tcw (tcas) tc2 (tpc) row column cke d31Cd0 (read) d31Cd0 (write) (read) (write) a25Ca0 rdwr figure 8.18 dram wait state timing (normal mode, rcd = 1, tpc = 1, dwr = 2, dww/tcas = 1) rev. 1.0, 08/99, page 260 of 875 tr wait state due to signal input two tc1 tc2 row column cke a25Ca0 rdwr d31Cd0 (read) d31Cd0 (write) (read) (write) figure 8.19 dram basic access timing (wait state inserted by wait wait wait wait signal) rev. 1.0, 08/99, page 261 of 875 burst access: in addition to the normal dram access mode in which a row address is output in each data access, a fast page mode is also provided for the case where consecutive accesses are made to the same row. this mode allows fast access to data by outputting the row address only once, then changing only the column address for each subsequent access. normal access or burst access using fast page mode can be selected by means of the be bit in dcr3. the timing for burst access using fast page mode is shown in figure 8.20. burst transfer is performed when the access width exceeds the bus width, or in single address transfer in burst mode by the dmac. tr tc1 tc2 tc1 cke a25Ca0 rdwr tc2 tc1 tc2 tc1 tc2 d31Cd0 (read) d31Cd0 (write) row column column column column figure 8.20 basic timing of dram burst access edo mode: with dram, in addition to the mode in which data is output to the data bus only while the cas signal is asserted in a data read cycle, an edo mode is also provided in which, once the cas signal is asserted while the ras signal is asserted, even if the cas signal is negated, rev. 1.0, 08/99, page 262 of 875 data is output to the data bus until the cas signal is next asserted. either normal access/burst access using fast page mode, or edo mode normal access/burst access, can be selected for dram with the edo bit in dcr3. edo mode normal access is shown in figure 8.21, and burst access in figure 8.22. in burst access, only one-cycle access is possible only when column addresses are consecutive. no-wait access must be used for edo dram. no-wait access must be used for edo dram, and wait state insertion by means of the wait pin must not be used. tr tc1 tc2 cke a25Ca0 rdwr ( ) d31Cd0 (read) d31Cd0 (write) row column figure 8.21 dram basic access timing in edo mode rev. 1.0, 08/99, page 263 of 875 tr tce1 tce2 tce2 tce2 tce3 cke a25Ca0 rdwr ( ) d31Cd0 (read) d31Cd0 (write) row column column column column figure 8.22 dram burst access basic timing in edo mode ras down mode: even if burst operation is selected, it may happen that dram accesses are not consecutive, but are interrupted by an access to a different space. with the normal setting, the ras signal is temporarily negated while a different space is being accessed, and must be reasserted to restart burst operation when dram is next accessed. this is known as ras up mode. however, it is possible to keep the ras signal asserted while a different space is being accessed, enabling burst operation to be continued when the same dram row address is next accessed. this is known as ras down mode. to use ras down mode, set both be and rasd to 1 in dcr3. when using ras down mode to access dram in edo mode, the oe signal must be connected to the sh7065. figure 8.23 shows the timing in ras up mode, and figure 8.24 the timing in ras down mode setting the rdw bit in the dcr2 register enables an idle cycle to be inserted before burst operation when the same dram row address is accessed in dma single address mode. the rev. 1.0, 08/99, page 264 of 875 dack signal is asserted during this idle cycle, facilitating dma single transfer. figure 8.25 shows an example of idle cycle insertion in ras down mode when using edo mode. tr tc1 tc2 t1 cke a25Ca0 rdwr d31Cd0 t2 tr tc1 tc2 area 4 dram access area 1 sram access area 4 dram access row row column column figure 8.23 ras up mode basic timing (read cycle) rev. 1.0, 08/99, page 265 of 875 tr tc1 tc2 t1 cke a25Ca0 rdwr d31Cd0 t2 tc1 tc2 area 4 dram access area 1 sram access area 4 dram access row column column figure 8.24 ras down mode basic timing (read cycle) rev. 1.0, 08/99, page 266 of 875 tr tc1 tc2 t1 cke a25Ca0 rdwr d31Cd0 t2 trdw tc1 tc2 area 4 dram access area 1 sram access area 4 dram access row column column figure 8.25 example of ras down mode wait timing (edo mode, read cycle, rdw = 1) rev. 1.0, 08/99, page 267 of 875 refresh timing: the bus state controller includes a function for controlling dram refreshing. distributed refreshing using cas-before-ras refresh cycles can be performed for dram by clearing the rmd bit to 0 and setting the rfsh bit to 1 in dcr3. self-refresh mode is also supported. cas-before-ras refreshing when cas-before-ras refresh cycles are executed, refreshing is performed at intervals determined by the input clock selected by bits cks2 to cks0 in rtcsr, and the value set in rtcor. the value of bits cks2 to cks0 in rtcor should be set so as to satisfy the specification for the dram refresh interval. to change the input clock, first clear bits cks0 to cks2 to 0, then write the required value in these bits. when the clock is selected by bits cks2 to cks0, rtcnt starts counting up from the value at that time. the rtcnt value is constantly compared with the rtcor value, and if the two values are the same, a refresh request is generated. at the same time, rtcnt is cleared to zero and the count-up is restarted. after generation of the reference request, if the sh7065s external bus can be used, cas- before-ras refreshing is performed. a setting can be made in bits bref2 to bref0 in rtcsr to specify execution of from 1 to 8 consecutive cas-before-ras refreshes in response to a single refresh request. figure 8.26 shows the operation of cas-before-ras refreshing, and figure 8.27 shows the timing of cmf bit setting. = 000 rtcsr.cks (2C0) cmf cmf flag cleared by start of refresh cycle external bus 1 000 rtcnt rtcor value rtcnt cleared to 0 when rtcnt = rtcor h'0000 time cas-before-ras refresh cycles figure 8.26 cas-before-ras refresh operation rev. 1.0, 08/99, page 268 of 875 rtcnt value rtcnt input clock cke n n 0 m f rtcor value cmf cmi refresh request figure 8.27 timing of cmf bit setting (when m0: cke = 1:1/2) figure 8.28 shows the timing of the cas-before-ras refresh cycle. the number of ras assert cycles in the refresh cycle is specified by the tras bits in rtcsr. the specification of the ras precharge time in the refresh cycle is determined by the setting of the tpc bits in dcr1. cas-before-ras refreshing is performed in normal operation, in sleep mode. rev. 1.0, 08/99, page 269 of 875 trc trr1 trrw trr2 cke rdwr figure 8.28 basic timing of dram cas-before-ras refresh cycle self-refreshing the self-refreshing supported by the sh7065 is shown in figure 8.29. a transition to self-refresh mode is made by setting the rfsh bit and rmd bit to 1 in dcr. self-refresh mode is exited by clearing the rmd bit to 0 in dcr, than performing cas- before-ras refreshing on all row addresses within the time specified for the dram. the ras precharge time immediately after the end of self-refreshing can be set with the tpcs bits in dcr. if there is a delay between clearing self-refreshing and the start of cas-before-ras refreshing, this must be taken into consideration when setting the initial rtcnt value. when the rtcnt value is set to the same value as rtcor, a refresh request is issued immediately. to protect dram data, the dram should not be accessed during self-refreshing. if dram is to be accessed during self-refreshing, first clear self-refreshing, then perform refreshing of all row addresses before making the access. drams include low-power products (l versions) with a long refresh cycle time (for example, the hm51w4160al l version has a refresh cycle of 1024 cycles/128 ms compared with 1024 cycles/16 ms for the normal version). with these drams, however, the same refresh cycle as for the normal version is requested only in the case of refreshing immediately following self- refreshing. to ensure efficient dram refreshing, therefore, processing is needed to generate an overflow interrupt and restore the refresh cycle to the proper value, after the necessary cas-before-ras refreshing has been performed following self-refreshing of an l-version dram, using the ovf, ovie, and lmts bits in rtcsr, and the refresh controllers refresh count register (rfcr). the necessary procedure is as follows. rev. 1.0, 08/99, page 270 of 875 1. normally, set the refresh counter count cycle to the optimum value for the l version (e.g. 1024 cycles/128 ms). 2. when a transition is made to self-refreshing: a. provide an interrupt handler to restore the refresh counter count value to the optimum value for the l version (e.g. 1024 cycles/128 ms) when a refresh counter overflow interrupt is generated. b. re-set the refresh counter count cycle to the requested short cycle (e.g. 1024 cycles/16 ms), set refresh controller overflow interruption, and clear the refresh controllers refresh count register (rfcr) to 0. c. set self-refresh mode. by using this procedure, the refreshing immediately following a self-refresh will be performed in a short cycle, and when refreshing ends, an interrupt is generated and the setting can be restored to the original refresh cycle. self-refreshing is performed in normal operation, in sleep mode, and in standby mode. when the bus has been released in response to a bus arbitration request, or when a transition is made to standby mode, signals generally become high-impedance, but whether the ras and cas signals for dram in the self-refresh state become high-impedance or continue to be output can be controlled by the hizcnt bit in bcr. the dram can be kept in the self- refresh state when the bus is released and in standby mode by setting the hizcnt bit to 1. however, in this case, too, the dram should not be accessed during self-refreshing. also, after self-refreshing is set, a bus request, self-refresh clearing, or execution of a sleep instruction involving a transition to software standby mode, should only be performed after another cs space has first been accessed. trc trr1 trrw tsr1 cke csn rdwr rasn casxxn tsr1 tsr2 (tpc) (tpc) figure 8.29 dram self-refresh cycle timing rev. 1.0, 08/99, page 271 of 875 relationship between refresh requests and bus cycle requests if a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. if a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. if a match between rtcnt and rtcor occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. in order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. when a refresh request is generated, the irqout pin is asserted (driven low). therefore, normal refreshing can be performed by having the irqout pin monitored by a bus master other than the sh7065 requesting the bus, or the bus arbiter, and returning the bus to the sh7065. when refreshing is started, and if no other interrupt request has been generated, the irqout pin is negated (driven high). for details, see section 17.3.27, function control register (fcr). power-on sequence: regarding use of dram after powering on, it is requested that a wait time (at least 100 s or 200 s) during which no access can be performed be provided, followed by the prescribed number (usually 8) or more dummy cas-before-ras refresh cycles. as the bus state controller does not perform any special operations for a power-on reset, the necessary power-on sequence must be carried out by the initialization program executed after a power-on reset. 8.3.5 multiplexed address/data i/o interface basic timing: a function is provided that performs multiplexed input/output of an address and data on pins d15 to d0 when the appropriate setting is made in bits tp1 and tp0 of the acr1 registers for areas 1 to 3. this allows a peripheral lsi that requires address/data multiplexing to be connected to the sh7065. the bus width of multiplexed address/data i/o space is selected by the a14 bit. when a14 = 0, the data bus width is 8 bits; the address is output at pins d15 to d0 and data is input/output at pins d7 to d0. when a14 = 1, the address and data are both 16 bits, and address output and data input/output is performed at pins d15 to d0. in multiplexed address/data i/o space access, normal space type access is carried out after address output has been performed for three cycles (fixed). the basic timing for multiplexed address/data i/o space is shown in figure 8.30. rev. 1.0, 08/99, page 272 of 875 ta1 ta2 ta3 ta4 cke a25Ca0 d15Cd0 C d15Cd0 read write t1 t2 address data address data figure 8.30 basic access timing for multiplexed address/data i/o space rev. 1.0, 08/99, page 273 of 875 wait state control: wait control for multiplexed address/data i/o space access is carried out by making the appropriate setting for the exwe bit in acr1. software wait and external wait insertion timing is the same as for normal space access. figure 8.31 the timing for two software wait insertion, and figure 8.32 shows the timing when one external wait is inserted, and then an additional software wait state is inserted after negation of the wait signal. figure 8.33 shows the timing when extension of cs assertion has been set. ta1 ta2 ta3 ta4 cke a25Ca0 d15Cd0 C d15Cd0 read write t1 tw tw t2 address data address data figure 8.31 wait state timing for multiplexed address/data i/o space (two software waits) rev. 1.0, 08/99, page 274 of 875 ta1 ta2 ta3 ta4 cke a25Ca0 csn wr rd d15Cd0 wrhhCwrll d15Cd0 wait ah bs dackn rread write t1 two thww t2 address data address data figure 8.32 wait state timing for multiplexed address/data i/o space (insertion of one external wait + one software wait after wait pin negation) rev. 1.0, 08/99, page 275 of 875 ta1 ta2 ta3 ta4 cke a25Ca0 d15Cd0 C d15Cd0 rread write th t1 t2 tt address data address data figure 8.33 timing when extension of cs cs cs cs assertion is set (swh = 1, swt = 1) rev. 1.0, 08/99, page 276 of 875 8.3.6 waits between access cycles a problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with the data in the next access, and so resulting in lower reliability or incorrect operation. to avoid this problem, a data collision prevention feature has been provided. this memorizes the preceding access area and the kind of read/write, and if there is a possibility of a bus collision when the next access is started, inserts a wait cycle before the access cycle to prevent a data collision. there are two cases in which wait cycles are inserted: (1) when an access is immediately followed by an access to a different area, and (2) when a read cycle access is immediately followed by a write access from the sh7065. when the sh7065 performs consecutive write cycles, the data transfer direction is fixed (from the sh7065 to other memory) and there is no problem. with read access to the same area, also, in principle data is assumed to be output from the same data buffer, and the set wait cycle insertion is not performed. figure 8.34 shows the timing of waits between access cycles. the number of idle cycles to be inserted between access cycles is specified by bits iw2 to iw0 in acr1 and bits diw2 to diw0 in dcr2. if there is space between accesses to begin with, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. when a write cycle is executed immediately after a read cycle, two wait cycles are inserted automatically between the cycles even if the inter-cycle wait specification is 0. when switching to access to a different space, also, one wait cycle is inserted automatically in the case of a read cycle, and two wait cycles in the case of a write cycle, even if no idle cycles is set. in the case of consecutive accesses to the same space, one wait cycle is inserted automatically in the case of a read cycle, and two wait cycles in the case of a write cycle, regardless of the inter-cycle wait setting. when bus arbitration is performed, empty cycles are inserted for arbitration purposes, and so waits are not inserted between cycles. rev. 1.0, 08/99, page 277 of 875 t1 area 1 sram read area 1 sram read area 2 sram read specification of idle cycle insertion after area 1 access specification of idle cycle insertion after area 2 access idle cycle in read access idle cycle in write access area 2 sram write area 2 sram write a25Ca0 d31Cd0 t2 t1 twait t2 t1 t2 t1 twait twait twait twait t2 twait twait t1 t2 cke figure 8.34 example of timing of waits between access cycles (no wait) rev. 1.0, 08/99, page 278 of 875 8.3.7 bus arbitration when the bus release request signal ( breq ) is asserted in accordance with the setting of the brqe bit in bcr, the sh7065 releases the bus as soon as the currently executing bus cycle ends, and outputs the bus request acknowledge signal ( back ). however, bus release is not performed between a read cycle and write cycle during execution of a tas instruction (unless the destination of tas instruction execution is on-chip ram). also, bus arbitration is not performed between bus cycles generated due to the fact that the data bus width is smaller than the access size, such as when a longword access is made to 8-bit memory. when breq is negated, back is negated and use of the bus is resumed. see appendix b.1, pin states, for the pin states when the bus is released. sometimes, the sh7065 may want to take back the bus while in the process of releasing it. this happens if a memory refresh request is generated internally, or an interrupt is requested, and the relevant processing must be executed. for this reason, the sh7065 is provided with an irqout pin to output a bus request signal. if the sh7065 needs to take back the bus, it asserts the irqout signal. on receiving this irqout signal assertion, the device that asserted the external bus request negates the breq signal in order to release the bus. the bus is thereby returned to the sh7065, which then carries out the necessary processing. note that if the device that asserted the external bus request does not return the bus within the time specified as the dram refresh interval, the sh7065 will not be able to carry out refreshing, and ram contents may be lost. there are two cases in which the irqout pin is asserted: (1) when a memory refresh request has been issued and the refresh cycle has not yet begun, and (2) when an interrupt source occurs and the interrupt request level is higher than that set in the interrupt mask bits (i3 to i0) in the status register (sr). the sh7065 has two internal bus masters: the cpu and the dmac. when dram is connected and refresh control is performed, refresh requests constitute a third bus master. in addition to these are bus requests from external devices. if requests occur simultaneously, priority is given, in high- to-low order, to a refresh request, a bus request from an external device, the dmac, and the cpu. if an external space access request by the cpu or dmac and a bus request by an external device occur, in that order, during execution of a refresh cycle, acceptance of the bus request by the external device will be delayed until the refresh cycle and external space access have been executed. similarly, if an external space access request by the cpu or dmac and a refresh request occur, in that order, execution of the refresh cycle after the sh7065 acquires the bus will be delayed until the external space access has been executed. bus requests from off-chip are not accepted in sleep mode. if breq is asserted in sleep mode and the dmac is subsequently activated, external access by the dmac is delayed until breq is negated. rev. 1.0, 08/99, page 279 of 875 8.4 number of access cycles external memory and external i/o: table 8.11 shows the number of external access cycles for m f :cke division ratios of 1:1, 1:1/2, and 1:1/4. the cpu regards an external space write as being executed in one cycle, and performs the next processing. however, the write actually takes the number of cycles shown in table 8.11. therefore, execution of an on-chip register or external access following an external space write by the cpu is delayed until the end of the external space write. table 8.11 number of external access cycles bus master m f f f f :cke division ratio read/write cycles in access from cpu cycles in access from dmac read number of external bus cycles + 3 number of external bus cycles + 1 1:1 write number of external bus cycles + 4 number of external bus cycles + 2 read (number of external bus cycles) 2 + (4 or 5) * (number of external bus cycles) 2 + (2 or 3) * 1:1/2 write (number of external bus cycles) 2 + (6 or 7) * (number of external bus cycles) 2 + (4 or 5) * 1:1/4 read (number of external bus cycles) 4 + (5 to 8) * (number of external bus cycles) 4 + (3 to 6) * write (number of external bus cycles) 4 + (9 to 12) * (number of external bus cycles) 4 + (7 to 10) * note: * depends on the phase difference between m f and cke due to frequency division. rev. 1.0, 08/99, page 280 of 875 on-chip registers in bsc, ubc, wdt, intc, cpg, dmac, pfc, i/o, flash memory related, and power-down related register access table 8.12 shows the number of access cycles. the cpu regards an on-chip register write as being executed in one cycle, and performs the next processing. however, the write actually takes the number of cycles shown in table 8.12. when a value written to an on-chip register is to be used by a later instruction, either read the written value or else wait for the number of cycles shown in table 8.12, before executing that later instruction. execution of an on-chip register or external access following an on-chip register write by the cpu is delayed until the end of the on-chip register write. table 8.12 number of access cycles in bsc, ubc, wdt, intc, cpg, dma, pfc, i/o, flash memory related, and power-down related register access bus master operand size read/write cycles in access from cpu cycles in access from dmac read 5 3 word/byte * write 6 4 longword * read 8 6 write 9 7 note: * only byte access in the case of flash memory related registers. rev. 1.0, 08/99, page 281 of 875 a/d, d/a, tpu, mmt, cmt, poe, and sci internal register access table 8.13 shows the number of access cycles for m f :p f division ratios of 1:1, 1:1/2, and 1:1/3. the cpu regards an on-chip register write as being executed in one cycle, and performs the next processing. however, the write actually takes the number of cycles shown in table 8.13. when a value written to an on-chip register is to be used by a later instruction, either read the written value or else wait for the number of cycles shown in table 8.13, before executing that later instruction. execution of an on-chip register or external access following an on-chip register write by the cpu is delayed until the end of the on-chip register write. table 8.13 number of access cycles in a/d, d/a, tpu, mmt, cmt, poe, and sci internal register access bus master m f f f f :p f f f f division ratio operand size read/ write cycles in access from cpu cycles in access from dmac read 7 5 word/byte * 1 write 7 5 read 9 7 1:1 longword * 2 write 9 7 read 9C10 * 3 7C8 * 3 word/byte * 1 write 9C10 * 3 7C8 * 3 read 13C14 * 3 11C12 * 3 1:1/2 longword * 2 write 13C14 * 3 11C12 * 3 read 12C14 * 3 10C12 * 3 word/byte * 1 write 12C14 * 3 10C12 * 3 read 18C20 * 3 16C18 * 3 1:1/3 longword * 2 write 18C20 * 3 16C18 * 3 notes: 1. only byte access applies in the case of a/d and d/a registers. 2. only word access applies in the case of a/d and d/a registers. 3. depends on the phase difference between m f and p f due to frequency division. rev. 1.0, 08/99, page 282 of 875 on-chip rom in low-speed mode all 2 cycles in high-speed mode ? consecutive instruction fetch cycles 1 cycle (however, in a branch to address 8n+4 or 8n+6, consecutive instruction fetch cycles immediately after the branch instruction fetch cycle comprise two cycles.) ? branch instruction fetch cycle 2 to 3 cycles* ? data read cycle 2 to 3 cycles* note: * the number of cycles depends on the state of the cpu pipeline, and buffering between the internal 32-bit data bus (cdb) and the 64-bit internal data rom bus. figures 8.35 to 8.42 show the cpu pipeline state and the number of on-chip rom access cycles when no on-chip rom data read cycles are generated. fetch 2 2 C 3 fetch 2 1 fetch 2 1 nop 1 1 fetch 2 1 nop 1 1 fetch 2 1 nop 1 1 fetch 2 1 nop 1 1 ex id ex id id ex id ex id ex id if ex id ex id rev. 1.0, 08/99, page 288 of 875 ? one idle cycle when switching from a read cycle to a read cycle in a different space ? two idle cycles when switching from a read cycle or write cycle to a write cycle in a different space 6. while the write signal ( wr ) is low, the signal may contain noise with a peak value of 1.5 v max. deatils of the schedule for lifting the above restrictions will be given separately by hitachi sales. rev. 1.0, 08/99, page 289 of 875 section 9 direct memory access controller (dmac) 9.1 overview the sh7065 includes an on-chip four-channel direct memory access controller (dmac). the dmac can be used in place of the cpu to perform high-speed data transfers among external devices equipped with dack (transfer request acknowledge signal), external memories, memory- mapped external devices, and on-chip peripheral modules (except the dmac, bsc, and ubc). using the dmac reduces the burden on the cpu and increases the operating efficiency of the entire chip. 9.1.1 features the dmac has the following features. four channels four gbytes of address space in the architecture choice of 8-bit, 16-bit, or 32-bit transfer data length maximum of 4g (4,294,967,296) transfers choice of single or dual address mode ? single address mode: either the transfer source or the transfer destination (peripheral device) is accessed by a dack signal while the other is accessed by address. one data transfer is completed in one bus cycle. ? dual address mode: both the transfer source and transfer destination are accessed by address. values set in dmac internal registers indicate the accessed address for both the transfer source and the transfer destination. two bus cycles are required for one data transfer. channel functions: the transfer mode can be set independently for each channel. transfer requests: the following dmac transfer activation requests are supported. ? external request: from two dreq pins. either low level detection or falling edge detection can be specified. when low level detection is selected, the sampled dreq signal is stored in a fifo. either a 1-stage or 16-stage fifo can be selected. ? internal requests: transfer requests from on-chip modules such as the tpu and sci. choice of bus mode: cycle steal mode or burst mode two types of dmac channel priority ranking: ? fixed priority mode: channel priorities are permanently fixed. ? round robin mode: sets the lowest priority for the channel that last received an execution request. rev. 1.0, 08/99, page 290 of 875 an interrupt request can be sent to the cpu on completion of the specified number of transfers. chain transfer allows a specified block of data to be transferred consecutively without cpu processing after the end of the current data transfer. a transfer end signal ( tend ) can be output for each channel at the end of dma transfer. rev. 1.0, 08/99, page 291 of 875 9.1.2 block diagram figure 9.1 shows a block diagram of the dmac. x, yram on-chip rom tpu sci0, sci1, sci2 a/d converter mmt dein n: 0, 1 peripheral bus internal bus on-chip peripheral module external rom external ram external i/o (memory- mapped) external i/o (with acknowledge) external bus bus state controller bus interface request priority control activation control register control count control sarn darn dmatcrn chncntn chcrn dmaor nsarn chain transfer registers dmac module ndarn ndmatcrn dmaor: dmac operation register sarn: dmac source address register darn: dmac destination address register dmatcrn: dmac transfer count register chcrn: dmac channel control register nsarn: next source address register ndarn: next destination address register ndmatcrn: next transfer count register chncntn: chain transfer count register mmt: motor management timer (n: 0 to 3) figure 9.1 block diagram of dmac rev. 1.0, 08/99, page 292 of 875 9.1.3 pin configuration table 9.1 shows the pins provided for each dmac channel. table 9.1 dmac pins pin name abbreviation i/o function dma transfer request dreqn input dma transfer request input from external device to channel 0 or 1 dma transfer request acceptance drakn output output of sampling acceptance signal for dma transfer request input to channel 0 or 1 from external device dma transfer strobe dackn output strobe output to external i/o in case of dma transfer request from external device to channel 0 or 1 dma transfer end tendn output output at end of dma transfer on relevant channel 0 or 1 rev. 1.0, 08/99, page 293 of 875 9.1.4 register configuration table 9.2 summarizes the dmac registers. the dmac has a total of 33 registers. eight registers are allocated to each channel, and an additional control register is shared by all four channels. table 9.2 dmac registers abbreviation name chan- nel read/ write initial value address register size access size sar0 dma source address register 0 0 r/w undefined h'ffff1100 32 bits 16, 32 dar0 dma destination address register 0 0 r/w undefined h'ffff1104 32 bits 16, 32 dmatcr0 dma transfer count register 0 0 r/w undefined h'ffff1108 32 bits 16, 32 chcr0 dma channel control register 0 0r/w * 1 00000000 h'ffff110c 32 bits 16, 32 nsar0 next source address register 0 0 r/w undefined h'ffff1110 32 bits 16, 32 ndar0 next destination address register 0 0 r/w undefined h'ffff1114 32 bits 16, 32 ndmatcr0 next transfer count register 0 0 r/w undefined h'ffff1118 32 bits 16, 32 chncnt0 chain transfer count register 0 0 r/w undefined h'ffff111c 32 bits 16, 32 sar1 dma source address register 1 1 r/w undefined h'ffff1120 32 bits 16, 32 dar1 dma destination address register 1 1 r/w undefined h'ffff1124 32 bits 16, 32 dmatcr1 dma transfer count register 1 1 r/w undefined h'ffff1128 32 bits 16, 32 chcr1 dma channel control register 1 1r/w * 1 00000000 h'ffff112c 32 bits 16, 32 nsar1 next source address register 1 1 r/w undefined h'ffff1130 32 bits 16, 32 ndar1 next destination address register 1 1 r/w undefined h'ffff1134 32 bits 16, 32 ndmatcr1 next transfer count register 1 1 r/w undefined h'ffff1138 32 bits 16, 32 chncnt1 chain transfer count register 1 1 r/w undefined h'ffff113c 32 bits 16, 32 rev. 1.0, 08/99, page 294 of 875 table 9.2 dmac registers (cont) abbreviation name chan- nel read/ write initial value address register size access size sar2 dma source address register 2 2 r/w undefined h'ffff1140 32 bits 16, 32 dar2 dma destination address register 2 2 r/w undefined h'ffff1144 32 bits 16, 32 dmatcr2 dma transfer count register 2 2 r/w undefined h'ffff1148 32 bits 16, 32 chcr2 dma channel control register 2 2r/w * 1 00000000 h'ffff114c 32 bits 16, 32 nsar2 next source address register 2 2 r/w undefined h'ffff1150 32 bits 16, 32 ndar2 next destination address register 2 2 r/w undefined h'ffff1154 32 bits 16, 32 ndmatcr2 next transfer count register 2 2 r/w undefined h'ffff1158 32 bits 16, 32 chncnt2 chain transfer count register 2 2 r/w undefined h'ffff115c 32 bits 16, 32 sar3 dma source address register 3 3 r/w undefined h'ffff1160 32 bits 16, 32 dar3 dma destination address register 3 3 r/w undefined h'ffff1164 32 bits 16, 32 dmatcr3 dma transfer count register 3 3 r/w undefined h'ffff1168 32 bits 16, 32 chcr3 dma channel control register 3 3r/w * 1 00000000 h'ffff116c 32 bits 16, 32 nsar3 next source address register 3 3 r/w undefined h'ffff1170 32 bits 16, 32 ndar3 next destination address register 3 3 r/w undefined h'ffff1174 32 bits 16, 32 ndmatcr3 next transfer count register 3 3 r/w undefined h'ffff1178 32 bits 16, 32 chncnt3 chain transfer count register 3 3 r/w undefined h'ffff117c 32 bits 16, 32 dmaor dma operation register all r/w * 1 0000 h'ffff10f0 16 bits 16 notes: 1. bit 1 of chcr0 to chcr3 and bits 1 and 2 of dmaor can only be written with 0 after being read as 1, to clear the flags. 2. when 16-bit access is used on sar0 to sar3, dar0 to dar3, or chcr0 to chcr3, the 16 bits that are not accessed retain their value. rev. 1.0, 08/99, page 295 of 875 9.2 register descriptions 9.2.1 dma source address registers 0 to 3 (sar0 to sar3) bit: 31 30 29 28 27 26 25 24 23 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . initial value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . r/w dma source address registers 0 to 3 (sar0 to sar3) are 32-bit readable/writable registers that specify the source address of a dma transfer. these registers have a count function, and during a dma transfer they indicate the next source address. in single address mode, the sar value is ignored when a device with dack has been specified as the transfer source. specify a 16-bit boundary address in a 16-bit transfer, and a 32-bit boundary address in a 32-bit transfer. operation cannot be guaranteed if a different address is set. the value of these registers is undefined after a power-on reset, and in hardware standby mode and software standby mode. 9.2.2 dma destination address registers 0 to 3 (dar0 to dar3) bit: 31 30 29 28 27 26 25 24 23 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . initial value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . r/w dma destination address registers 0 to 3 (dar0 to dar3) are 32-bit readable/writable registers that specify the destination address of a dma transfer. these registers have a count function, and during a dma transfer they indicate the next destination address. in single address mode, the dar value is ignored when a device with dack has been specified as the transfer destination. specify a 16-bit boundary address in a 16-bit transfer, and a 32-bit boundary address in a 32-bit transfer. operation cannot be guaranteed if a different address is set. the value of these registers is undefined after a power-on reset, and in hardware standby mode and software standby mode. rev. 1.0, 08/99, page 296 of 875 9.2.3 dma transfer count registers 0 to 3 (dmatcr0 to dmatcr3) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w dma transfer count registers 0 to 3 (dmatcr0 to dmatcr3) are 32-bit readable/writable registers that specify the transfer count for the channel (number of bytes, words, or longwords). setting h'00000001 gives a transfer count of 1, while h'00000000 gives the maximum setting of 4,294,967,296 (4g) transfers. during dmac operation, the remaining number of transfers is shown. the value of these registers is undefined after a power-on reset, and in hardware standby mode and software standby mode. rev. 1.0, 08/99, page 297 of 875 9.2.4 dma channel control registers 0 to 3 (chcr0 to chcr3) bit: 31 30 29 28 27 26 25 24 rs4 rs3 rs2 rs1 rs0 initial value:00000000 r/w: r r r r/w r/w r/w r/w r/w bit: 23 22 21 20 19 18 17 16 fifos ndare nsare fcs tes initial value:00000000 r/w: r r/w r r r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 dm1 dm0 sm1 sm0 chne rl am al initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 tend ds tm ts1 ts0 ie te * de initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * the te bit can only be cleared by writing 0 after it is read as 1. dma channel control registers 0 to 3 (chcr0 to chcr3) are 32-bit readable/writable registers that specify the operating mode, transfer method, etc., for each channel. all bits in these registers are initialized to 0 after a power-on reset, and in hardware standby mode and software standby mode. bits 31 to 29reserved: these bits are always read as 0 and cannot be modified. rev. 1.0, 08/99, page 298 of 875 bits 28 to 24resource select 4 to 0 (rs4 to rs0): these bits specify the transfer request source. bit 28: rs4 bit 27: rs3 bit 26: rs2 bit 25: rs1 bit 24: rs0 description 00000external request, dual address mode (initial value) 1 (reserved) 1 0 external request, single address mode external address space ? external device 1 external request, single address mode external device ? external address space 100auto-request 1 (reserved) 10(reserved) 1 (reserved) 1000tputgi0a 1tgi1a 1 0 tgi2a 1tgi3a 1 0 0 tgi4a 1tgi5a 1 0 a/d adi 0 1adi 1 10000sci0txi0 1 rxi0 10sci1txi1 1 rxi1 100sci2txi2 1 rxi2 10(reserved) 1 (reserved) 1000mmttgm 1 mmt tgn 10(reserved) 1 (reserved) 100(reserved) 1 (reserved) 10(reserved) 1 (reserved) rev. 1.0, 08/99, page 299 of 875 bit 23reserved: this bit is always read as 0 and cannot be modified. bit 22fifo select (fifos): selects the fifo to be used for dreq level detection. this bit is invalid when dreq falling edge detection is used. bit 22: fifos description 0 1-stage fifo is used for dreq level detection (initial value) 1 16-stage fifo is used for dreq level detection bits 21 and 20reserved: these bits are always read as 0 and cannot be modified. bit 19next destination address register enable (ndare): selects whether or not the next destination address register value is to be transferred to the destination address register to update the destination address during chain transfer. bit 19: ndare description 0 in chain transfer, next destination address register value is not copied to destination address register (initial value) 1 in chain transfer, next destination address register value is copied to destination address register bit 18next source address register enable (nsare): selects whether or not the next source address register value is to be transferred to the source address register to update the source address during chain transfer. bit 18: nsare description 0 in chain transfer, next source address register value is not copied to source address register (initial value) 1 in chain transfer, next source address register value is copied to source address register rev. 1.0, 08/99, page 300 of 875 bit 17flag clear timing select (fcs): when a transfer request by an on-chip module is accepted, the dmac outputs a signal to clear the transfer request flag of the on-chip module that made the transfer request. this bit selects whether this output is to be performed in the bus cycle in which the transfer count register (dmatcrn) value becomes 0, or in every bus cycle. when this bit is set to 1, the edge detection setting should be made in bit 6 (dreq select: ds). bit 17: fcs description 0 when an on-chip module is the transfer request source, the dmac outputs the flag clearing signal in the bus cycle in which the transfer count register (dmatcrn) value becomes 0 (initial value) 1 when an on-chip module is the transfer request source, the dmac outputs the flag clearing signal in every last bus cycle note: when dreq is edge-detected, fcs can be used to select the edge clearing timing. bit 16transfer end setting select (tes): specifies whether the transfer end bit (te) is to be set at the end of all the chain transfers specified in the chain count register (chncnt), or at the end of the number of data transfers specified by dmatcrn. this bit is valid regardless of the setting of bit 11 (chain transfer enable: chne). therefore, when not performing chain transfer, either set this bit to 1 or else set a value of 0 in the chncnt. when bit 2 (interrupt enable: ie) is set to 1, a transfer end interrupt (dei) is requested when the transfer end bit is set at the timing specified by this bit. bit 16: tes description 0 transfer end bit (te) is set to 1 when chncntn = 0 and dmatcrn = 0 (initial value) 1 transfer end bit (te) is set to 1 when dmatcrn = 0 note: with auto-request, this bit is invalid and an interrupt is requested when dmatcrn = 0. when auto-request is selected, tes = 1 operation is used. bits 15 and 14destination address mode 1 and 0 (dm1, dm0): these bits specify incrementing/decrementing of the dma transfer destination address. the specification of these bits is ignored when data is transferred from address space to an external device in single address mode. bit 15: dm1 bit 14: dm0 description 0 0 destination address fixed (initial value) 1 destination address incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer) 1 0 destination address decremented (C1 in 8-bit transfer, C2 in 16-bit transfer, C4 in 32-bit transfer) 1 (use prohibited) rev. 1.0, 08/99, page 301 of 875 bits 13 and 12source address mode 1 and 0 (sm1, sm0): these bits specify incrementing/ decrementing of the dma transfer source address. the specification of these bits is ignored when data is transferred from an external device to address space in single address mode. bit 13: sm1 bit 12: sm0 description 0 0 source address fixed (initial value) 1 source address incremented (+1 in 8-bit transfer, +2 in 16- bit transfer, +4 in 32-bit transfer) 1 0 source address decremented (C1 in 8-bit transfer, C2 in 16-bit transfer, C4 in 32-bit transfer) 1 (use prohibited) bit 11chain transfer enable (chne): selects whether or not chain transfer is performed in dmac transfer. bit 11: chne description 0 chain transfer is not performed (initial value) 1 chain transfer is performed bit 10request check level (rl): selects whether the drak signal (that notifies an external device of the acceptance of dreq ) is an active-high or active-low output. note that the initial value of this bit is the active-high setting. bit 10: rl description 0 drak is an active-high output (initial value) 1 drak is an active-low output bit 9acknowledge mode (am): in dual address mode, selects whether dack is output in the data read cycle or write cycle. in single address mode, dack is always output regardless of the setting of this bit. bit 9: am description 0 dack is output in read cycle (initial value) 1 dack is output in write cycle rev. 1.0, 08/99, page 302 of 875 bit 8acknowledge level (al): specifies the dack (acknowledge) signal as active-high or active-low. note that the initial value of this bit is the active-high setting. bit 8: al description 0 active-high output (initial value) 1 active-low output bit 7tend select (tend): selects whether or not the tend signal (notifying an external device that transfer has ended) is to be output at the end of dma transfer. when output is selected, tend is output in synchronization with dack assertion at the end of transfer. bit 7: tend description 0 tend is not output at end of dma transfer (initial value) 1 tend is output at end of dma transfer bit 6dreq select (ds): specifies either low level detection or falling edge detection as the sampling method for the dreq pin and on-chip peripheral module transfer requests used in external request mode. if auto-request is specified, the specification of this bit is ignored. edge detection is not used with auto-request. bit 6: ds description 0 low level detection (initial value) 1 falling edge detection bit 5transmit mode (tm): specifies the bus mode for transfer. bit 5: tm description 0 cycle steal mode (initial value) 1burst mode bits 4 and 3transmit size 1 and 0 (ts1, ts0): these bits specify the transfer data size. bit 4: ts1 bit 3: ts0 description 0 0 byte size (8 bits) (initial value) 1 word size (16 bits) 1 0 longword size (32 bits) 1 (use prohibited) rev. 1.0, 08/99, page 303 of 875 bit 2interrupt enable (ie): when this bit is set to 1, an interrupt request is generated after the number of data transfers specified in dmatcr, or after all chain transfers are completed. bit 2: ie description 0 interrupt request not generated after number of transfers specified in dmatcr (initial value) 1 interrupt request generated after number of transfers specified in dmatcr bit 1transfer end (te): this bit is set to 1 on completion of the number of transfers specified in dmatcr, or on completion of all the chain transfers specified in chncnt. the timing of te bit setting is specified by bit 16 (tes). if the ie bit is set to 1 at this time, an interrupt request is generated. if data transfer ends before te is set to 1 (for example, due to an nmi interrupt, address error, or clearing of the de bit or the dme bit in dmaor), the te bit is not set to 1. when this bit is 1, data transfer is not enabled even if the de bit is set to 1. bit 1: te description 0 number of transfers specified in dmatcr not completed (initial value) [clearing conditions] when 0 is written to te after reading te = 1 in a power-on reset, and in standby mode 1 number of transfers specified in dmatcr completed, or all chain transfers specified in chncnt completed note: not initialized in module standby mode. bit 0dmac enable (de): enables operation of the corresponding channel. bit 0: de description 0 operation of corresponding channel is disabled (initial value) 1 operation of corresponding channel is enabled when auto-request is specified (with rs5 to rs0), transfer is begun when this bit is set to 1. in the case of an external request or on-chip module request, transfer is begun when a transfer request is issued after this bit is set to 1. transfer can be suspended midway by clearing this bit to 0. even if the de bit has been set, transfer is not enabled when te is 1, when dme in dmaor is 0, or when the nmif or ae bit in dmaor is 1. rev. 1.0, 08/99, page 304 of 875 9.2.5 next source address registers 0 to 3 (nsar0 to nsar3) bit: 31 30 29 28 27 26 25 24 23 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . initial value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . r/w next source address registers 0 to 3 (nsar0 to nsar3) are 32-bit readable/writable registers that specify the source address for the next transfer when chain transfer is set. in single address mode, the nsar value is ignored when a device with dack has been specified as the transfer destination. specify a 16-bit boundary address in a 16-bit transfer, and a 32-bit boundary address in a 32-bit transfer. operation cannot be guaranteed if a different address is set. the value of these registers is undefined after a power-on reset, and in hardware standby mode and software standby mode. 9.2.6 next destination address registers 0 to 3 (ndar0 to ndar3) bit: 31 30 29 28 27 26 25 24 23 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . initial value: . . . . . . . . . . . . . . . . . . . . . . . . . . . . r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . r/w next destination address registers 0 to 3 (ndar0 to ndar3) are 32-bit readable/writable registers that specify the destination address for the next transfer when chain transfer is set. in single address mode, the ndar value is ignored when a device with dack has been specified as the transfer destination. specify a 16-bit boundary address in a 16-bit transfer, and a 32-bit boundary address in a 32-bit transfer. operation cannot be guaranteed if a different address is set. the value of these registers is undefined after a power-on reset, and in hardware standby mode and software standby mode. rev. 1.0, 08/99, page 305 of 875 9.2.7 next transfer count registers 0 to 3 (ndmatcr0 to ndmatcr3) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w next transfer count registers 0 to 3 (ndmatcr0 to ndmatcr3) are 32-bit readable/writable registers that specify the transfer count for the next transfer on the channel (number of bytes, words, or longwords) in chain transfer. the value of these registers is undefined after a power-on reset, and in hardware standby mode and software standby mode. 9.2.8 chain transfer count registers 0 to 3 (chncnt0 to chncnt3) bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value: r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w chain transfer count registers 0 to 3 (chncnt0 to chncnt3) are 32-bit readable/writable registers that specify the chain transfer count when chain transfer is set. the value of these registers is undefined after a power-on reset, and in hardware standby mode and software standby mode. if chain transfer is not to be enabled, either initialize these registers to 0 or set bit 16 (tes) in chcrn to 1 before enabling transfer. rev. 1.0, 08/99, page 306 of 875 9.2.9 dma operation register (dmaor) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rc3 rc2 rc1 rc0 ae nmif dme initial value:0000000000000000 r/w: r/w r/w r/w r/w r r r r r r/(w) r/(w) r/w note: the ae and nmif bits can only be cleared to 0 after being read as 1. the dma operation register (dmaor) is a 16-bit readable/writable register that specifies the dmac transfer mode. dmaor bits are initialized to 0 after a power-on reset, and in hardware standby mode and software standby mode. bits 15 to 12reserved: these bits are always read as 0 and cannot be modified. bits 11 to 8round robin channel select 3 to 0 (rc3 to rc0): when there are simultaneous transfer requests for a number of channels, these bits determine the channel priority order for executing the transfers. bits rc3 to rc0 correspond to channels ch3 to ch0. when a bit is set to 1, the priority of the corresponding channel is determined according to the round robin method. bits 11 to 8: rcn description 0 the priority order of corresponding channel chn (n = 0 to 3) is fixed. when all rc bits are 0, the channel priority order is ch0 > ch1 > ch2 > ch3. (initial value) 1 the priority order of corresponding channel chn (n = 0 to 3) is determined according to the round robin method. note: when the round robin method is set for the priority order, at least two rc bits should be set to 1. if only one rc bit is set to 1, the inter-channel priority order will be ch0 > ch1 > ch2 > ch3. when the priority order of two or more channels is determined by the round robin method, channels with consecutive channel numbers must be set (e.g. ch2 and ch3, or ch1, ch2, and ch3). operation cannot be guaranteed if channels with non-consecutive channel numbers (such as ch0 and ch2) are designated as having their priority order determined by the round robin method. if round robin priority is specified for ch1, ch2, and ch3, the channel priority relationship with the other channel will be as follows: ch0 > ch1, ch2, ch3. round robin bits 7 to 3reserved: these bits are always read as 0 and cannot be modified. rev. 1.0, 08/99, page 307 of 875 bit 2address error flag (ae): flag that indicates the occurrence of an address error during dma transfer. if this bit is set during data transfer, transfers on all channels are suspended. the cpu cannot write a 1 to ae. this bit can only be cleared by writing 0 after reading 1. bit 2: ae description 0 no address error, dma transfer enabled (initial value) [clearing condition] when 0 is written to ae after reading ae = 1 1 address error, dma transfer disabled [setting condition] when an address error is caused by the dmac bit 1nmi flag (nmif): flag that indicates nmi input. setting of this bit can be performed regardless of whether the dmac is operating or halted. if this bit is set during data transfer, transfers on all channels are suspended. the cpu cannot write a 1 to nmif. this bit can only be cleared by writing 0 after reading 1. bit 1: nmif description 0 no nmi input, dma transfer enabled (initial value) [clearing condition] when 0 is written to nmif after reading nmif = 1 1 nmi input, dma transfer disabled [setting condition] when an nmi interrupt is generated bit 0dmac master enable (dme): enables activation of the entire dmac. when the dme bit and the de bit of the chcr register for the corresponding channel are set to 1, that channel is enabled for transfer. if this bit is cleared during data transfer, transfers on all channels are suspended. even if the dme bit has been set, transfer is not enabled when te is 1 or de is 0 in chcr, or when the nmif or ae bit in dmaor is 1. bit 0: dme description 0 operation disabled on all channels (initial value) 1 operation enabled on all channels rev. 1.0, 08/99, page 308 of 875 9.3 operation when there is a dma transfer request, the dmac starts the transfer according to the predetermined channel priority order. it ends the transfer when the transfer end conditions are satisfied. transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. there are two modes for dma transfer: single address mode and dual address mode. either burst mode or cycle steal mode can be selected as the bus mode. 9.3.1 dma transfer procedure after the desired transfer conditions have been set in the dma source address register (sar), dma destination address register (dar), dma transfer count register (dmatcr), dma channel control register (chcr), dma operation register (dmaor), next source address register (nsar), next destination address register (ndar), next transfer count register (ndmatcr), and chain transfer count register (chncnt), the dmac executes data transfer according to the following procedure: 1. the dmac checks to see if transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0). 2. when a transfer request is issued while transfer is enabled, the dmac transfers one transfer unit of data (determined by the setting of ts0 and ts1). in auto-request mode, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value is decremented by 1 for each transfer. the actual transfer flow depends on the address mode and bus mode. 3. when the specified number of transfers have been completed (when the dmatcr value reaches 0), the transfer ends normally. if the ie bit in chcr is set to 1 at this time, a dei interrupt request is sent to the cpu.* 4. when a dmac address error or nmi interrupt occurs, the transfer is suspended. transfer is also suspended when the de bit in chcr or the dme bit in dmaor is cleared to 0. 5. in the case of auto-request, or when chne = 0 and tes = 1, transfer ends when dmatcrn = 0. when the chain transfer enable bit (chne) is set to 1, the values in the next source address register (nsar), next destination address register (ndar), and next transfer count register (ndmatcr) are copied, respectively, to the dma source address register (sar), dma destination address register (dar), and dma transfer count register (dmatcr), and chain transfer is started. chain transfer ends when the value in the chain transfer count register (chncnt) reaches 0. note: * if the tes bit in chcrn is cleared to 0, a dei interrupt is generated when the chncntn and dmatcrn values both become 0. figure 9.2 shows a flowchart of this procedure. rev. 1.0, 08/99, page 309 of 875 start initial settings (sar, dar, dmatcr, chcr, dmaor, nsar, ndar, ndmatcr, chncnt) de, dme = 1 & nmif, ae, te = 0? transfer request issued? * 1 dmatcr = 0? dei interrupt request * 5 (when ie = 1) nmif or ae = 1 or de = 0 or dme = 0 ? end of transfer end of transfer auto-request or tes = 1? transfer (1 transfer unit) dmatcr-1 ? dmatcr, sar, dar update yes yes yes yes yes end of transfer chne = 0 & tes = 1? yes transfer suspended nmif or ae = 1 or de = 0 or dme = 0? bus mode, transfer request mode, dreq detection method yes end of transfer tes = 0 & chncnt = 0? yes no no no no no * 6 no * 3 * 2 no no nsar ndar ndmatcr chncnt-1 sar * 4 dar dmatcr chncnt notes: 1. in auto-request mode, transfer begins when the nmif, ae, and te bits are all 0, and the de and dme bits are set to 1. 2. dreq level detection (external request) in burst mode, or cycle steal mode. when edge detection and edge clearing every cycle are set. 3. when transfer requests are edge-detected, and edge clearing is performed at the end of all transfers. 4. whether or not nsar ? sar and ndar ? dar transfer is required can be set with the corresponding bits in chcr. 5. when the tes bit in chcr is cleared to 0, the condition for interrupt generation is {chncntn = 0 and dmatcrn = 0}. when the tes bit in chcr is set to 1, the condition for interrupt generation is {dmatcrn = 0}, and the value of chncntn is immaterial. 6. when clearing chne to 0, either set tes to 1 or clear chncnt to 0. figure 9.2 dmac transfer flowchart rev. 1.0, 08/99, page 310 of 875 9.3.2 dma transfer requests transfer requests are basically generated at either the data transfer source or destination, but they can also be issued by external devices or on-chip peripheral modules that are neither the source nor the destination. transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. the transfer request mode is selected by means of bits rs4 to rs0 in dma channel control registers 0 to 3 (chcr0 to chcr3). auto request mode: when there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the rs bit in chcr0 to chcr3 is set to auto-request mode, the de bit is set to 1, and the dme bit in the dma operation register (dmaor) is set to 1, the transfer begins (so long as the te bit in chcr0 to chcr3 and the nmif and ae bits in dmaor are all 0). external request mode: in this mode a transfer is performed in response to a transfer request signal ( dreq ) from an external device. one of the modes shown in table 9.3 should be chosen according to the application system. if dma transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), transfer starts when dreq is input. the ds bit in chcr0 to chcr3 is used to select either falling edge detection or low level detection for the dreq signal (level detection when ds = 0, edge detection when ds = 1). when low level detection is used, the fifo to be used can be selected with the fifos bit. when edge detection is used, the edge clearing timing can be selected with the fcs bit. the source of the transfer request does not have to be the data transfer source or destination. table 9.3 selecting external request mode with rs bits rs4 rs3 rs2 rs1 rs0 address mode transfer source transfer destination 0 0 0 0 0 dual address mode any * any * 0 0 0 1 0 single address mode external memory or memory-mapped external device external device with dack 0 0 0 1 1 single address mode external device with dack external memory or memory-mapped external device note: * external memory, memory-mapped external device, on-chip memory, on-c hip peri pheral module (except dmac, ubc, and bsc) rev. 1.0, 08/99, page 311 of 875 on-chip peripheral module request mode: in this mode a transfer is performed in response to a transfer request signal (interrupt request signal) from one of the sh7065s on-chip peripheral modules. as shown in table 9.4, there are a total of 16 transfer request signals: six compare match interrupts or input capture interrupts from the timer pulse unit (tpu), receive-data-full interrupts (rxi) and transmit-data-empty interrupts (txi) from the three serial communication interface (sci) channels, a/d conversion end interrupts (adi) from the two a/d converter channels, and two interrupts from the motor management timer (mmt). if dma transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), dma transfer starts when a transfer request signal is input. the source of the transfer request does not have to be the data transfer source or destination. however, when the transfer request is set to rxi (transfer request by sci receive-data-full interrupt), the transfer source must be the scis receive fifo data register (scfrdr). when the transfer request is set to txi (transfer request by sci transmit-data-empty interrupt), the transfer destination must be the scis transmit fifo data register (scftdr). when the transfer request is set to adin, the transfer source must be the a/d data register (addrn). to output a transfer request from an on-chip peripheral module, set the interrupt enable bit for the module and output an interrupt signal. when an on-chip peripheral module interrupt request signal is used as a dma transfer request signal, an interrupt is not issued to the cpu. the transfer request signals shown in table 9.4 are cleared automatically when the corresponding dma transfer is performed. in cycle steal mode the signal is cleared for a single transfer; in burst mode, there is a choice of clearance each time a transfer is executed or on execution of the last transfer. the flag clear timing select bit (fcs) in the channel control register (chcr) is used to select the transfer request signal clearing mode. rev. 1.0, 08/99, page 312 of 875 table 9.4 selecting on-chip peripheral module request mode with rs bits rs4 rs3 rs2 rs1 rs0 dmac transfer request source dmac transfer request signal transfer source transfer destina- tion bus mode 01000tpu tgi0a interrupt any * any * burst/cycle steal mode 1 tpu tgi1a interrupt any * any * burst/cycle steal mode 1 0 tpu tgi2a interrupt any * any * burst/cycle steal mode 1 tpu tgi3a interrupt any * any * burst/cycle steal mode 100tpu tgi4a interrupt any * any * burst/cycle steal mode 1 tpu tgi5a interrupt any * any * burst/cycle steal mode 10a/d converter adi0 (a/d conversion end interrupt) addr0 any * burst/cycle steal mode 1a/d converter adi1 (a/d conversion end interrupt) addr1 any * burst/cycle steal mode 10000sci0 transmitter txi0 (sci0 transmit- data-empty transfer request) any * tdr0 burst/cycle steal mode 1sci0 receiver rxi0 (sci0 receive- data-full transfer request) rdr0 any * burst/cycle steal mode 10sci1 transmitter txi1 (sci1 transmit- data-empty transfer request) any * tdr1 burst/cycle steal mode 1sci1 receiver rxi1 (sci1 receive- data-full transfer request) rdr1 any * burst/cycle steal mode 100sci2 transmitter txi2 (sci2 transmit- data-empty transfer request) any * tdr2 burst/cycle steal mode 1sci2 receiver rxi2 (sci2 receive- data-full transfer request) rdr2 any * burst/cycle steal mode 10 0mmt tgm any * any * burst/cycle steal mode 1 mmt tgn any * any * burst/cycle steal mode tpu: timer pulse unit sci0, sci1, sci2: serial communication interface channels 0 to 2 addr0, addr1: a/d data registers for a/d converters 0 and 1 rev. 1.0, 08/99, page 313 of 875 tdrn, rdrn: scftdrn and scfrdrn for sci channel n (n = 0 to 2) mmt: motor management timer note: * external memory, memory-mapped external device, on-chip memory, on-c hip peri pheral module (except dmac, bsc, and ubc) 9.3.3 channel priorities if the dmac receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority system, either in a fixed mode or round robin mode. the mode is selected with the round robin channel select bits (rc0 to rc3) in the dma operation register (dmaor). the fixed mode is selected for the channel priority order by clearing the round robin channel select bits for all channels to 0. when using round robin mode, the round robin bits for the channels to be used are set to 1. the channels specified in this case must have consecutive channel numbers. fixed mode: in the fixed mode, the channel priority order does not change. in this mode, the following initial channel priority order is used. ch0 > ch1 > ch2 > ch3 to perform fixed mode transfer, the round robin channel select bits (rc0 to rc3) in the dma operation register (dmaor) must all be cleared to 0. round robin mode: in round robin mode, each time the transfer of one transfer unit (byte, word, or longword) ends on a given channel, that channel is assigned the lowest priority level. the channels specified by the round robin channel select bits (rc0 to rc3) in the dma operation register (dmaor) are subject to round robin control. only channels with consecutive channel numbers can be specified; operation cannot be guaranteed if non-consecutive channels are specified for round robin priority control. if only one channel is specified, the channel priority order is the same as in the fixed mode. figure 9.3 illustrates round robin operation for ch0 to ch3. the order of priority in round robin mode immediately after a reset is the initial priority order: ch0 > ch1 > ch2 > ch3. rev. 1.0, 08/99, page 314 of 875 ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 ch1 > ch2 > ch3 > ch0 ch2 > ch3 > ch0 > ch1 ch3 > ch0 > ch1 > ch2 ch2 > ch3 > ch0 > ch1 1. transfer on channel 0 initial priority order channel 0 is given the lowest priority. no change in priority order priority order after transfer 2. transfer on channel 1 initial priority order priority order after transfer 3. transfer on channel 2 initial priority order priority order after transfer 4. transfer on channel 3 initial priority order priority order after transfer priority after transfer due to issuance of a transfer request for channel 1 only ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 when channel 2 is given the lowest priority, the priorities of channels 0 and 1, which were higher than channel 2, are also shifted simultaneously. if there is a transfer request for channel 1 only immediately afterward, channel 1 is given the lowest priority and the priorities of channels 3 and 0 are simultaneously shifted down. when channel 1 is given the lowest priority, the priority of channel 0, which was higher than channel 1, is also shifted simultaneously. figure 9.3 round robin mode rev. 1.0, 08/99, page 315 of 875 figure 9.4 shows the changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. the operation of the dmac in this case is as follows. 1. transfer requests are issued simultaneously for channels 0 and 3. 2. since channel 0 has a higher priority level than channel 3, the channel 0 transfer is executed first (channel 3 is on transfer standby). 3. a transfer request is issued for channel 1 during the channel 0 transfer (channels 1 and 3 are on transfer standby). 4. at the end of the channel 0 transfer, channel 0 shifts to the lowest priority level. 5. at this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer is started (channel 3 is on transfer standby). 6. at the end of the channel 1 transfer, channel 1 shifts to the lowest priority level. 7. the channel 3 transfer is started. 8. at the end of the channel 3 transfer, the channel 3 and channel 2 priority levels are lowered, giving channel 3 the lowest priority. rev. 1.0, 08/99, page 316 of 875 1. issued for channels 0 and 3 channel waiting dmac operation channel priority order 2. start of channel 0 transfer 0 > 1 > 2 > 3 3 1, 3 3 none 1 > 2 > 3 > 0 2 > 3 > 0 > 1 0 > 1 > 2 > 3 4. end of channel 0 transfer change of priority order 5. start of channel 1 transfer 6. end of channel 1 transfer 7. start of channel 3 transfer 8. end of channel 3 transfer transfer request 3. issued for channel 1 change of priority order change of priority order figure 9.4 example of changes in channel priority order in round robin mode rev. 1.0, 08/99, page 317 of 875 9.3.4 types of dma transfer the dmac supports the transfers shown in table 9.5. it can operate in single address mode, in which either the transfer source or the transfer destination is accessed using the acknowledge signal, or in dual address mode, in which both the transfer source and transfer destination addresses are output. the actual transfer operation timing depends on the bus mode, which can be either burst mode or cycle steal mode. table 9.5 supported dma transfers transfer destination transfer source external device with dack external memory memory- mapped external device on-chip memory on-chip peripheral module external device with dack not available single address mode single address mode not available not available external memory single address mode dual address mode dual address mode dual address mode dual address mode memory-mapped external device single address mode dual address mode dual address mode dual address mode dual address mode on-chip memory not available dual address mode dual address mode dual address mode dual address mode on-chip peripheral module not available dual address mode dual address mode dual address mode dual address mode rev. 1.0, 08/99, page 318 of 875 address modes single address mode in single address mode, both the transfer source and the transfer destination are external; one is accessed by the dack signal and the other by an address. in this mode, the dmac performs a dma transfer in one bus cycle by simultaneously outputting the external i/o strobe signal ( dack ) to either the transfer source or transfer destination external device to access it, while outputting an address to the other side of the transfer. figure 9.5 shows an example of a transfer between external memory and an external device with dack in which the external device outputs data to the data bus while that data is written to external memory in the same bus cycle. external address bus sh7065 data flow dmac external memory external device with external data bus figure 9.5 data flow in single address mode two types of transfer are possible in single address mode: (1) transfer between an external device with dack and a memory-mapped external device, and (2) transfer between an external device with dack and external memory. only the external request signal ( dreq ) is used in both these cases. figure 9.6 shows the dma transfer timing in single address mode. rev. 1.0, 08/99, page 319 of 875 cke a25Ca0 d31Cd0 address output to external memory space data output from external device with signal (active-low) to external device with signal to external memory space output (a) from external device with to external memory space cke a25Ca0 d31Cd0 address output to external memory space data output from external memory space signal to external memory space signal (active-low) to external device with output (b) from external memory space to external device with figure 9.6 dma transfer timing in single address mode dual address mode dual address mode is used to access both the transfer source and the transfer destination by address. the transfer source and destination can be accessed either internally or externally. in dual address mode, data is read from the transfer source in the data read cycle, and written to the transfer destination in the data write cycle, so that the transfer is executed in two bus cycles. the transfer data is temporarily stored in the dmac. in a transfer between external memories such as that shown in figure 9.7, data is read from external memory into the dmac rev. 1.0, 08/99, page 320 of 875 in the read cycle, then written to the other external memory in the write cycle. figure 9.8 shows the timing for this operation. sar memory transfer source module transfer destination module dmac dar taking the sar value as the address, data is read from the transfer source module and stored temporarily in the data buffer in the dmac. first bus cycle address bus data bus data buffer sar memory transfer source module transfer destination module dar taking the dar value as the address, the data stored in the dmac is written to the transfer destination module. second bus cycle address bus data bus data buffer dmac figure 9.7 direct address operation in dual address mode rev. 1.0, 08/99, page 321 of 875 cke a25Ca0 d31Cd0 data read cycle transfer from external memory space to external memory space, tend output enabled, output in read cycle (1st) transfer source address data write cycle (2nd) transfer destination address figure 9.8 example of dual address mode transfer timing rev. 1.0, 08/99, page 322 of 875 bus modes: there are two bus modes, cycle steal mode and burst mode, selected with the tm bit in chcr0 to chcr3. cycle steal mode in cycle steal mode, the dmac gives the bus to another bus master at the end of each transfer- unit (8-bit, 16-bit, or 32-bit) transfer. when the next transfer request is issued, the dmac reacquires the bus from the other bus master and carries out another transfer-unit transfer. at the end of this transfer, the bus is again given to another bus master. this is repeated until the transfer end condition is satisfied. cycle steal mode can be used with all categories of transfer request source, transfer source, and transfer destination. figure 9.9 shows an example of dma transfer timing in cycle steal mode. the transfer conditions in this example are dual address mode and dreq level detection (using the 16- stage fifo). cpu cpu cpu cpu bus temporarily returned to cpu read, write bus cycle read, write dmac dmac cpu cpu dmac dmac figure 9.9 example of dma transfer in cycle steal mode burst mode in burst mode, once the dmac has acquired the bus it transfers data continuously until the transfer end condition is satisfied. with dreq low level detection in external request mode, however, when dreq is driven high the bus passes to another bus master after the end of the dmac transfer request that has already been accepted, even if the transfer end condition has not been satisfied. figure 9.10 shows an example of dma transfer timing in burst mode. the transfer conditions in this example are single address mode and dreq level detection (using the 16-stage fifo). cpu cpu cpu dmac bus cycle dmac dmac dmac cpu dmac dmac figure 9.10 example of dma transfer in burst mode rev. 1.0, 08/99, page 323 of 875 relationship between dma transfer type, request mode, and bus mode: table 9.6 shows the relationship between the type of dma transfer, the request mode, and the bus mode. table 9.6 relationship between dma transfer type, request mode, and bus mode address mode type of transfer request mode bus mode transfer size (bits) usable channels single external device with dack and external memory external b/c 8/16/32 0, 1 external device with dack and memory-mapped external device external b/c 8/16/32 0, 1 dual external memory and external memory any * 1 b/c 8/16/32 3 external memory and memory-mapped external device any * 1 b/c 8/16/32 3 memory-mapped external device and memory-mapped external device any * 1 b/c 8/16/32 3 external memory and on-chip memory any * 1 b/c 8/16/32 3 external memory and on-chip peripheral module any * 2 b/c 8/16/32 * 3 3 memory-mapped external device and on-chip memory any * 1 b/c 8/16/32 3 memory-mapped external device and on-chip peripheral module any * 2 b/c 8/16/32 * 3 3 on-chip memory and on-chip memory any * 1 b/c 8/16/32 3 on-chip memory and on-chip peripheral module any * 2 b/c 8/16/32 * 3 3 on-chip peripheral module and on-chip peripheral module any * 2 b/c 8/16/32 * 3 3 notes: b: burst c: cycle steal 1. external request, auto-request, or on-chip peripheral module request possible. the sci or a/d converter cannot be specified as the transfer request source in on-chip peripheral module request mode. 2. external request, auto-request, or on-chip peripheral module request possible. if the transfer request source is also the sci or a/d converter, the transfer source or transfer destination must be the sci or a/d converter. 3. access size permitted for register of on-chip peripheral module that is the transfer source or transfer destination. rev. 1.0, 08/99, page 324 of 875 bus mode and channel priority order: when, for example, channel 1 is transferring data in burst mode, and a transfer request is issued to channel 0, which has a higher priority, the channel 0 transfer is started immediately. if fixed mode has been set for the priority order (ch0 > ch1), or if burst mode is set for channel 0, transfer on channel 1 is continued after transfer on channel 0 is completely finished. if round robin mode has been set for the priority order, transfer on channel 1 is restarted after one transfer unit of data is transferred on channel 0, regardless of whether cycle steal mode or burst mode is set for channel 0. bus mastership then alternates in the order: channel 1 ? channel 0 ? channel 1 ? channel 0. since channel 1 is in burst mode, the bus is not given to the cpu during this period, regardless of whether fixed mode or round robin mode is set for the priority order. an example of round robin mode operation is shown in figure 9.11. cpu dmac ch1 dmac ch1 dmac ch1 dmac ch1 dmac ch1 cpu cpu dmac ch1 burst mode dmac ch0 and ch1 round robin mode dmac ch1 burst mode priority system: round robin mode channel 0: cycle steal mode channel 1: burst mode cpu dmac ch0 dmac ch0 figure 9.11 bus handling with two dmac channels operating 9.3.5 number of bus cycle states and dreq dreq dreq dreq pin sampling timing number of bus cycle states: when the dmac is the bus master, the number of bus cycle states is controlled by the bus state controller (bsc) in the same way as when the cpu is the bus master. for details, see section 8, bus state controller (bsc). dreq dreq dreq dreq pin sampling and drak drak drak drak signal: in external request mode, the dreq pin for each channel is sampled using falling edge or low level detection. the dreq sampling circuit for each channel comprises a noise canceler and edge detection circuit, a 16-stage fifo, and a 1-stage fifo. regardless of whether dreq pin falling edge detection or low level detection is used, the signal is sampled via a noise canceler circuit. the noise canceler eliminates noise of one clock cycle or less in duration by ignoring the first clock cycle of dreq input. rev. 1.0, 08/99, page 325 of 875 after passing through the noise canceler, an external request signal is sampled by one of three dreq sampling methods, as selected by the relevant register settings: falling edge detection, low level detection using the 16-stage fifo, or low level detection using the 1-stage fifo. whichever dreq sampling method is selected, the drak signal is output for one cke state each time dreq is sampled. regardless of whether cycle steal or burst mode is selected, and of the dreq sampling method, the drak signal is output when generation of a dma transfer cycle in response to the sampled dreq signal is confirmed. drak signal output is synchronized with cke, but it is not possible to stipulate the output timing relative to the external bus cycle. dreq falling edge detection when dreq falling edge detection is used, dreq samples are not stored in a fifo, and dma transfer is carried out in response to a single falling edge. since the noise canceler function ignores the first state of dreq input, the dreq signal must be input for at least two states. dreq sampling is performed in the same way regardless of whether single or dual address mode, or cycle steal or burst mode, is selected. with dreq falling edge detection, the number of transfers to be initiated by detection of a single falling edge can be set, regardless of whether single or dual address mode, or cycle steal or burst mode, is selected. the following settings can be made with the flag clear timing select (fcs) bit in the channel control register (chcr) for each channel. ? execution of one transfer in response to one falling edge ? execution of the number of transfers set in the dma transfer count register (dmatcr) in response to one falling edge regardless of the setting of the flag clear timing select (fcs) bit, while the transfer initiated by the previously detected falling edge is in progress, there is a period during which the next dreq falling edge is ignored. therefore, the next falling edge should not be input until the final drak signal has been output for the currently executing transfer. the drak signal is output once only for one falling edge. regardless of the setting of the flag clear timing select (fcs) bit, it is output at the same time as, or earlier than, address output in the first dma transfer cycle. figure 9.12 shows an example of the operation when one dma transfer is performed in response to one falling edge. the example in figure 9.12 is for cycle steal mode, but even if burst mode is selected, the operation still ends after one transfer in response to one falling edge. figure 9.13 shows an example of the operation when the number of dma transfers set in the dma transfer count register (dmatcr) are performed in response to one falling edge. rev. 1.0, 08/99, page 326 of 875 dreq low level detection using 16-stage fifo when dreq low level detection is selected, dreq is sampled in every cycle at the rise of cke (figure 9.14). the noise canceler function prevents sampling of dreq input at the first rise of cke. the sampled dreq signal is stored in the 16-stage fifo. one dma transfer is performed for one stored sampling result, and a number of transfers corresponding to the number of stored samples are always carried out. if dreq is input continuously, samples are taken until the fifo is full; once the fifo is full, the dreq input is no longer sampled (figure 9.15). the fifo is incremented each time dreq is sampled, and is decremented when generation of the next dma transfer cycle is confirmed. it is not always possible to stipulate the fifo decrement timing relative to the external bus cycle, but in the case of a cke:ckm frequency division ratio of 1:1, it will be at the start of the bus cycle before the dma transfer cycle (timings (a), (b), (c), (d), and (e) in figure 9.14). with the 16-stage fifo, in the event of contention between fifo incrementing and decrementing, both are performed simultaneously. the fifo operation in this case is as shown at (a), (b), (c), (d), and (e) in figure 9.14. the drak signal is output one state after the fifo is decremented, and at the same time as, or earlier than, address output in the corresponding dma transfer cycle. the drak signal is output once for each dreq sample. with this dreq sampling method, sampling is carried out in the same way regardless of whether single or dual address mode, or cycle steal or burst mode, is selected (figures 9.16 to 9.18). dreq low level detection using 1-stage fifo dreq low level sampling using the 1-stage fifo should be selected when external bus cycles are two cke states or longer in maximum-speed operation. if external bus cycles are two cke states or longer in maximum-speed operation, when dreq input is halted upon drak signal output, one subsequent dma transfer will always be performed after the dma transfer cycle corresponding to this drak signal output before transfer is halted (figure 9.19). if low level detection using the 1-stage fifo is selected when the external bus cycle is one cke state in maximum-speed operation, the amount of dma cycle overrun cannot be guaranteed. with the 1-stage fifo, as with the 16-stage fifo, dreq sampling is performed at the rise of cke. the noise canceler function prevents sampling of dreq input at the first rise of cke. the sampled dreq signal is stored in the 1-stage fifo, and the fifo is full after one sample is taken. the drak signal is output at the same time as, or earlier than, address output in the corresponding dma transfer cycle, and is output once for each dreq sample. the sampling conditions for the 1-stage fifo are different from those for the 16-stage fifo. with the 16-stage fifo, fifo incrementing and decrementing are performed simultaneously (see figure 9.19), but with the 1-stage fifo, after the fifo is cleared by decrementing, the next sampling operation is performed. the fifo decrement timing is the same as the drak signal output timing. figure 9.19 shows an example of the operation when single/burst mode dma transfer is carried out with dreq sampling by low level detection using the 1-stage rev. 1.0, 08/99, page 327 of 875 fifo. in figure 9.19, when dreq input is halted (b in the figure) at the point at which drak is output (a in the figure), transfer is terminated after execution of the dma transfer cycle following the corresponding dma cycle. with this dreq sampling method, sampling is carried out in the same way regardless of whether single or dual address mode, or cycle steal or burst mode, is selected (figures 9.20 to 9.22). cke fifo bus cpu dmac read cpu dmac write dmac read dmac write notes: 1. cke:ckm = 1:1 2. cycle steal mode/dual address transfer 3. one transfer is performed for one edge. 4. and are active-low. figure 9.12 operation example: cke = ckm, edge detection, one transfer for one edge rev. 1.0, 08/99, page 328 of 875 cke fifo bus cpu dmac read cpu dmac write dmac read dmac write notes: 1. cke:ckm = 1:1 2. cycle steal mode/dual address transfer 3. number of transfers set in dmatcr are performed for one edge. 4. and are active-low. figure 9.13 operation example: cke = ckm, edge detection, set number of transfers for one edge rev. 1.0, 08/99, page 329 of 875 cke fifo bus dma (r) dma (w) dma (r) dma (w) cpu cpu dma (r) dma (w) dma (r) dma (w) cpu cpu cpu 233 11 4 6778 055 (e) (d) (c) (b) (a) notes: 1. cke:ckm = 1:1 2. cycle steal mode/dual address transfer 3. low level detection using 16-stage fifo 4. and are active-low. figure 9.14 operation example: cke = ckm, low level detection, 16-stage fifo used (1) (maximum-speed operation in dual address/cycle steal mode) rev. 1.0, 08/99, page 330 of 875 cke fifo bus cpu cpu dma (r) dma (w) dma (r) dma (w) cpu cpu cpu cpu cpu cpu cpu cpu 16 16 15 16 16 15 14 16 15 14 14 13 13 15 14 dma (r) dma (w) notes: 1. cke:ckm = 1:1 2. cycle steal mode/dual address transfer 3. low level detection using 16-stage fifo 4. and are active-low. figure 9.15 operation example: cke = ckm, low level detection, 16-stage fifo used (2) sampling operation when fifo = full (dual address/cycle steal mode) rev. 1.0, 08/99, page 331 of 875 cke fifo bus dma (r) dma (w) dma (r) dma (w) cpu cpu dma (r) dma (r) dma (w) dma (r) dma (w) dma (r) dma (w) dma (w) cpu 223 11 3 5566 044 notes: 1. cke:ckm = 1:1 2. burst mode/dual address transfer 3. low level detection using 16-stage fifo 4. and are active-low. figure 9.16 operation example: cke = ckm, low level detection, 16-stage fifo used (3) (dual address/burst mode) rev. 1.0, 08/99, page 332 of 875 cke fifo bus dma dma cpu cpu cpu cpu cpu dma dma cpu cpu dma cpu cpu dma 223 11 3 5566 044 notes: 1. cke:ckm = 1:1 2. cycle steal mode/single address transfer 3. low level detection using 16-stage fifo 4. and are active-low. figure 9.17 operation example: cke = ckm, low level detection, 16-stage fifo used (4) (single address/cycle steal mode) rev. 1.0, 08/99, page 333 of 875 cke fifo bus dma dma cpu cpu cpu dma dma dma dma dma dma dma dma dma 111 11 1 1111 011 notes: 1. cke:ckm = 1:1 2. burst mode/single address transfer 3. low level detection using 16-stage fifo 4. and are active-low. figure 9.18 operation example: cke = ckm, low level detection, 16-stage fifo used (5) (single address/burst mode) rev. 1.0, 08/99, page 334 of 875 cke fifo bus dma dma dma cpu cpu cpu dma 010 11 1 0000 001 a b notes: 1. cke:ckm = 1:1 2. burst mode/single address transfer 3. low level detection using 1-stage fifo 4. and are active-low. figure 9.19 operation example: cke = ckm, low level detection, 1-stage fifo used (1) (single address/burst mode/maximum-speed operation) rev. 1.0, 08/99, page 335 of 875 cke fifo bus dma dma cpu cpu cpu cpu dma 011 11 0 0000 011 a b notes: 1. cke:ckm = 1:1 2. cycle steal mode/single address transfer 3. low level detection using 1-stage fifo 4. and are active-low. figure 9.20 operation example: cke = ckm, low level detection, 1-stage fifo used (2) (single address/cycle steal mode) rev. 1.0, 08/99, page 336 of 875 cke fifo bus dma(r) dma(w) dma(r) dma(w) cpu cpu cpu 011 11 0 0000 000 a b notes: 1. cke:ckm = 1:1 2. burst mode/dual address transfer 3. low level detection using 1-stage fifo 4. and are active-low. figure 9.21 operation example: cke = ckm, low level detection, 1-stage fifo used (3) (dual address/burst mode) rev. 1.0, 08/99, page 337 of 875 cke fifo bus dma(r) dma(w) dma(r) dma(w) cpu cpu cpu 011 11 1 0000 010 a b notes: 1. cke:ckm = 1:1 2. cycle steal mode/dual address transfer 3. low level detection using 1-stage fifo 4. and are active-low. figure 9.22 operation example: cke = ckm, low level detection, 1-stage fifo used (4) (dual address/cycle steal mode) clock frequency division restrictions relating to dreq dreq dreq dreq sampling: in the sh7065, the frequency of the master clock (ckm) and the external bus clock (cke) can be set independently by means of settings in the frequency control register (frqcr) in the clock pulse generator (cpg). when the dmac is activated by an external request, the frequency of the master clock (ckm) must be set as equal to or higher than that of the external bus clock (cke). if the master clock (ckm) frequency is set to a value lower than the external bus clock (cke) frequency, sampling will not be performed correctly with either falling edge detection or low level detection, and it will not be possible to stipulate the number of dma transfers performed in response to an external request. for details of clock frequency settings, see section 4, clock pulse generator (cpg) and power-down modes. rev. 1.0, 08/99, page 338 of 875 9.3.6 parallel operation of dma and cpu the sh7065 has two 32-bit internal buses, the c-bus and i-bus. dma is never the master on the c-bus, so the cpu can access mask rom and on-chip flash memory from the c-bus during dma transfer. however, when the dma controller is accessing x-ram or y-ram, the cpu cannot simultaneously access the same ram. the combinations of access spaces for which parallel dma and cpu operation is possible are shown in table 9.7. 9.3.7 dma transfer when external bus is released if the dma transfer source and transfer destination are both on-chip memory or on-chip peripheral modules, dma transfer cannot be performed while the external bus is released. the combinations of transfer source and transfer destination for which dma transfer is possible while the external bus is released are shpown in table 9.8. rev. 1.0, 08/99, page 339 of 875 table 9.7 contention between dma and cpu mode dma transfer external on-chip rom/flash on-chip memory on-chip peripheral module single external device with dack and external memory xo ox external device with dack and memory-mapped external device xo ox dual external memory and external memory xo ox external memory and memory- mapped external device xo ox external memory and on-chip memory xo d x external memory and on-chip peripheral module xo ox memory-mapped external device and memory-mapped external device xo ox memory-mapped external device and on-chip memory xo ox memory-mapped external device and on-chip peripheral module xo ox on-chip memory and on-chip memory xo d x on-chip memory and on-chip peripheral module xo d x on-chip peripheral module and on- chip peripheral module xo ox note: o: parallel dma and cpu operation possible x: parallel dma and cpu operation not possible because of bus contention d : on-chip memory consists of x-ram and y-ram. as x-ram and y-ram can be accessed independently, parallel operation is possible when different ram is accessed by dma and by the cpu. rev. 1.0, 08/99, page 340 of 875 table 9.8 contention between dma and external bus release transfer destination external device with dack external memory memory- mapped external device on-chip memory on-chip peripheral module external device with dack dma transfer not possible x x dma transfer not possible dma transfer not possible external memory x xxx x memory- mapped external device x xxx x on-chip memory dma transfer not possible xxo o transfer source on-chip peripheral module dma transfer not possible xxo o note: o: dma transfer possible while external bus is released x: dma transfer not possible while external bus is released 9.3.8 chain transfer use of chain transfer allows a specified block of data to be transferred consecutively without cpu processing after the end of the current data transfer. to perform chain transfer, it is necessary to set the registers used for chain transferthe next source address register (nsar), next destination address register (ndar), next transfer count register (ndmatcr), and chain transfer count register (chncnt)and to set the chain transfer enable bit (chne) to 1 in the channel control register (chcr). when the number of chain transfers set in the transfer count register (dmatcr) are completed while chain transfer is enabled, in the state following the end of transfer the set values are copied from nsar into sar, from ndar into dar, and from ndmatcr into dmatcr, and the dmac waits for the next transfer request (figure 9.2). however, whether or not copying of nsar and ndar is necessary can be specified by means of the next source address register enable bit (nsare) and next destination address register enable bit (ndare) in chcr. register copying is performed the number of times set in the chain transfer count register (chncnt), and chain transfer ends when the value in chncnt reaches 0. there is no auto-request chain transfer, and transfer always ends on completion of the first transfer. rev. 1.0, 08/99, page 341 of 875 as an example of chain transfer, table 9.9 shows the settings when the data stored in external memory addresses h'04000000 to h'04001000 is transferred in eight 512-byte transfers to the same address space in xram. in this example, dmac channel 0 is used and the transfer request source is dreq0 falling edge detection. table 9.9 sample chain transfer settings transfer conditions register set value transfer source: external memory sar0 h'04000000 transfer destination: xram dar0 h'ffff8000 number of transfers: 128 dmatcr0 h'00000080 transfer source and destination addresses: incremented transfer request source: dreq0 (dual address) dreq0 detection mode: falling edge detection edge clear timing: end of transfer bus mode: burst transfer unit: longword chain transfer enabled transfer source address copying in chain transfer disabled transfer destination address copying in chain transfer enabled interrupt request generated at end of chain transfer chcr0 h'000858f5 transfer source address in chain transfer: setting unnecessary nsar0 setting unnecessary transfer destination address in chain transfer: xram ndar0 h'ffff8000 number of transfers in chain transfer: 128 ndmatcr0 h'00000080 number of chain transfers: 7 chncnt0 h'00000007 channel priority order: 0 > 1 > 2 > 3 dma0r h'0001 rev. 1.0, 08/99, page 342 of 875 9.4 example of use 9.4.1 example of dma transfer between on-chip sci and external memory in the example considered here, on-chip serial communication interface channel 2 (sci2) receive data is transferred to external memory using dmac channel 3. dmac settings must be completed and transfer enabled before inputting a transfer request from the serial communication interface. table 9.10 shows the transfer conditions and register set values in this case. table 9.10 example of use transfer conditions register set value transfer source: rdr0 of on-chip sci0 sar3 h'ffff0546 transfer destination: external memory dar3 h'04000000 number of transfers: 8 dmatcr3 h'00000008 transfer source address: fixed chcr3 h'13024045 transfer destination address: incremented transfer request source: sci0 (rx0) bus mode: cycle steal transfer unit: byte interrupt requested at end of transfer channel priority order: 0 > 1 > 2 > 3 dmaor h'0001 rev. 1.0, 08/99, page 343 of 875 9.5 usage notes 1. only word (16-bit) access can be used on the dma operation register (dmaor). word (16- bit) or longword (32-bit) access can be used on all other registers. 2. when modifying bits rs0 to rs4 in chcr0 to chcr3, first clear the de bit to 0 (when modifying chcr, clear the de bit to 0 beforehand). 3. the nmif bit in dmaor is set when an nmi interrupt is input even if the dmac is not operating. 4. when setting standby mode, first clear the dme bit in dmaor to 0 and wait until the dmac has completed processing of all accepted transfer requests. 5. do not access the dmac, bsc, or ubc on-chip peripheral modules. 6. when activating the dmac, make the chcr setting as the final step. the dmac may not operate normally if any other register setting is made last. 7. after the dmatcr count reaches 0 and dma transfer ends normally, always write 0 to dmatcr even when executing the maximum number of transfers on the same channel. the dmac may not operate normally if this is not done. 8. when using the round robin method to determine the priority order, more than one channel must be specified, and consecutive channel numbers must be specified (e.g. ch1, ch2, ch3). operation cannot be guaranteed if non-consecutive channel numbers are specified. to change the specified channel, change the dma operation register (dmaor) setting when the channel priority order is the initial priority order. 9. when falling edge detection is used for external requests, keep the external request pin high when making dmac settings. 10. when using the dmac in single address mode, set an external address as the address. the dmac may not operate normally if an internal address is set. 11. on-chip rom space cannot be accessed. 12. the same internal request cannot be set for more than one channel. if it is, the request will only be valid for the channel with the highest default priority. 13. when a transfer request is accepted from an on-chip peripheral module, the relevant interrupt request signal is masked and not input to the intc. for details of the masking conditions, see section 6, interrupt controller (intc). 14. with the exception of dmaor and chcrn, dmac internal registers cannot be accessed while the dmac is operating. 15. when performing chain transfer initiated by an on-chip module, the ds bit in chcrn must be set to 1. 16. when chain transfer is disabled by means of the chne bit in chcrn, either clear chncntn to 0 or set the tes bit to 1 in chcrn. 17. a transfer request should not be made until the dmac register settings are completed (figure 9.2). rev. 1.0, 08/99, page 345 of 875 section 10 16-bit timer pulse unit (tpu) 10.1 overview the sh7065 has an on-chip 16-bit timer pulse unit (tpu) that comprises six 16-bit timer channels. 10.1.1 features the tpu has the following features: maximum 16-pulse input/output ? a total of 16 timer general registers (tgrs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register ? tgrc and tgrd for channels 0 and 3 can also be used as buffer registers selection of 8 counter input clocks for each channel the following operations can be set for each channel: ? waveform output at compare match: selection of 0, 1, or toggle output ? input capture function: selection of rising edge, falling edge, or both edge detection ? counter clear operation: counter clearing possible by compare match or input capture ? synchronous operation: multiple timer counters (tcnt) can be written to simultaneously simultaneous clearing by compare match and input capture possible register simultaneous input/output possible by counter synchronous operation ? pwm mode: any pwm output duty can be set ? maximum of 15-phase pwm output possible by combination with synchronous operation buffer operation settable for channels 0 and 3 ? input capture register double-buffering possible ? automatic rewriting of output compare register possible phase counting mode settable independently for each of channels 1, 2, 4, and 5 ? two-phase encoder pulse up/down-count possible cascaded operation ? channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow fast access via internal 16-bit bus ? fast access is possible via a 16-bit bus interface 26 interrupt sources ? for channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently rev. 1.0, 08/99, page 346 of 875 ? for channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently automatic transfer of register data ? block transfer, 1-word transfer, and 1-byte transfer possible by dma controller (dmac) activation a/d converter conversion start trigger can be generated ? channel 0 to 5 compare match a/input capture a signal can be used as a/d converter conversion start trigger rev. 1.0, 08/99, page 347 of 875 table 10.1 lists the functions of the tpu. table 10.1 tpu functions item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 count clock p f /1 p f /4 p f /16 p f /64 tclka tclkb tclkc tclkd p f /1 p f /4 p f /16 p f /64 p f /256 tclka tclkb p f /1 p f /4 p f /16 p f /64 p f /1024 tclka tclkb tclkc p f /1 p f /4 p f /16 p f /64 p f /256 p f /1024 p f /4096 tclka p f /1 p f /4 p f /16 p f /64 p f /1024 tclka tclkc p f /1 p f /4 p f /16 p f /64 p f /256 tclka tclkc tclkd general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b tgr3a tgr3b tgr4a tgr4b tgr5a tgr5b general registers/ buffer registers tgr0c tgr0d tgr3c tgr3d i/o pins tioc0a tioc0b tioc0c tioc0d tioc1a tioc1b tioc2a tioc2b tioc3a tioc3b tioc3c tioc3d tioc4a tioc4b tioc5a tioc5b counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output o o o o o o 1 output o o o o o o compare match output toggle output oooooo input capture function o o o o o o synchronous operation oooooo pwm mode oooooo phase counting mode o o o o buffer operation o o rev. 1.0, 08/99, page 348 of 875 table 10.1 tpu functions (cont) item channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 dmac activation tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture tgr3a compare match or input capture tgr4a compare match or input capture tgr5a compare match or input capture a/d conversion start trigger tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture tgr3a compare match or input capture tgr4a compare match or input capture tgr5a compare match or input capture interrupt sources 5 sources compare match/ input capture 0a compare match/ input capture 0b compare match/ input capture 0c compare match/ input capture 0d overflow 4 sources compare match/ input capture 1a compare match/ input capture 1b overflow underflow 4 sources compare match/ input capture 2a compare match/ input capture 2b overflow underflow 5 sources compare match/ input capture 3a compare match/ input capture 3b compare match/ input capture 3c compare match/ input capture 3d overflow 4 sources compare match/ input capture 4a compare match/ input capture 4b overflow underflow 4 sources compare match/ input capture 5a compare match/ input capture 5b overflow underflow legend o: possible : not possible rev. 1.0, 08/99, page 349 of 875 10.1.2 block diagram figure 10.1 shows a block diagram of the tpu. channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb channel 5 tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 3 to 5 channel 2 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 tmdr tsr tcr tiorh tier control logic for channels 0 to 2 tgra tcnt tgrb tgrd bus interface common tsyr control logic tstr [i/o pins] tioc3a tioc3b tioc3c tioc3d tioc4a tioc4b tioc5a tioc5b [clock input] p f /1 p f /4 p f /16 p f /64 p f /256 p f /1024 p f /4096 tclka tclkb tclkc tclkd [i/o pins] tioc0a tioc0b tioc0c tioc0d tioc1a tioc1b tioc2a tioc2b [interrupt request signals] channel 3: channel 4: channel 5: [interrupt request signals] channel 0: channel 1: channel 2: internal data bus a/d conversion start request signal tiorl module data bus tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u channel 3: channel 4: channel 5: internal clock: external clock: channel 0: channel 1: channel 2: figure 10.1 block diagram of tpu rev. 1.0, 08/99, page 350 of 875 10.1.3 pin configuration table 10.2 shows the pin configuration of the tpu. table 10.2 tpu pins channel name abbre- viation i/o function all clock input a tclka input external clock a input pin (channel 1 and 5 phase counting mode a phase input) clock input b tclkb input external clock b input pin (channel 1 and 5 phase counting mode b phase input) clock input c tclkc input external clock c input pin (channel 2 and 4 phase counting mode a phase input) clock input d tclkd input external clock d input pin (channel 2 and 4 phase counting mode b phase input) 0 input capture/out compare match 0a tioc0a i/o tgr0a input capture input/output compare output/pwm output pin input capture/out compare match 0b tioc0b i/o tgr0b input capture input/output compare output/pwm output pin input capture/out compare match 0c tioc0c i/o tgr0c input capture input/output compare output/pwm output pin input capture/out compare match 0d tioc0d i/o tgr0d input capture input/output compare output/pwm output pin 1 input capture/out compare match 1a tioc1a i/o tgr1a input capture input/output compare output/pwm output pin input capture/out compare match 1b tioc1b i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/out compare match 2a tioc2a i/o tgr2a input capture input/output compare output/pwm output pin input capture/out compare match 2b tioc2b i/o tgr2b input capture input/output compare output/pwm output pin 3 input capture/out compare match 3a tioca3 i/o tgr3a input capture input/output compare output/pwm output pin input capture/out compare match 3b tioc3b i/o tgr3b input capture input/output compare output/pwm output pin input capture/out compare match 3c tioc3c i/o tgr3c input capture input/output compare output/pwm output pin input capture/out compare match 3d tioc3d i/o tgr3d input capture input/output compare output/pwm output pin rev. 1.0, 08/99, page 351 of 875 table 10.2 tpu pins (cont) channel name abbre- viation i/o function 4 input capture/out compare match 4a tioc4a i/o tgr4a input capture input/output compare output/pwm output pin input capture/out compare match 4b tioc4b i/o tgr4b input capture input/output compare output/pwm output pin 5 input capture/out compare match 5a tioc5a i/o tgr5a input capture input/output compare output/pwm output pin input capture/out compare match 5b tioc5b i/o tgr5b input capture input/output compare output/pwm output pin rev. 1.0, 08/99, page 352 of 875 10.1.4 register configuration table 10.3 summarizes the tpu registers. table 10.3 tpu registers channel name abbre- viation r/w initial value address access size 0 timer control register 0 tcr0 r/w h'00 h'ffff0410 8, 16, 32 timer mode register 0 tmdr0 r/w h'c0 h'ffff0411 8, 16, 32 timer i/o control register 0h tior0h r/w h'00 h'ffff0412 8, 16, 32 timer i/o control register 0l tior0l r/w h'00 h'ffff0413 8, 16, 32 timer interrupt enable register 0 tier0 r/w h'40 h'ffff0414 8, 16, 32 timer status register 0 tsr0 r/(w) * h'c0 h'ffff0415 8, 16, 32 timer counter 0 tcnt0 r/w h'0000 h'ffff0416 16, 32 timer general register 0a tgr0a r/w h'ffff h'ffff0418 16, 32 timer general register 0b tgr0b r/w h'ffff h'ffff041a 16, 32 timer general register 0c tgr0c r/w h'ffff h'ffff041c 16, 32 timer general register 0d tgr0d r/w h'ffff h'ffff041e 16, 32 1 timer control register 1 tcr1 r/w h'00 h'ffff0420 8, 16, 32 timer mode register 1 tmdr1 r/w h'c0 h'ffff0421 8, 16, 32 timer i/o control register 1 tior1 r/w h'00 h'ffff0422 8, 16, 32 timer interrupt enable register 1 tier1 r/w h'40 h'ffff0424 8, 16, 32 timer status register 1 tsr1 r/(w) * h'c0 h'ffff0425 8, 16, 32 timer counter 1 tcnt1 r/w h'0000 h'ffff0426 16, 32 timer general register 1a tgr1a r/w h'ffff h'ffff0428 16, 32 timer general register 1b tgr1b r/w h'ffff h'ffff042a 16, 32 2 timer control register 2 tcr2 r/w h'00 h'ffff0430 8, 16, 32 timer mode register 2 tmdr2 r/w h'c0 h'ffff0431 8, 16, 32 timer i/o control register 2 tior2 r/w h'00 h'ffff0432 8, 16, 32 timer interrupt enable register 2 tier2 r/w h'40 h'ffff0434 8, 16, 32 timer status register 2 tsr2 r/(w) * h'c0 h'ffff0435 8, 16, 32 timer counter 2 tcnt2 r/w h'0000 h'ffff0436 16, 32 timer general register 2a tgr2a r/w h'ffff h'ffff0438 16, 32 timer general register 2b tgr2b r/w h'ffff h'ffff043a 16, 32 rev. 1.0, 08/99, page 353 of 875 table 10.3 tpu registers (cont) channel name abbre- viation r/w initial value address access size 3 timer control register 3 tcr3 r/w h'00 h'ffff0440 8, 16, 32 timer mode register 3 tmdr3 r/w h'c0 h'ffff0441 8, 16, 32 timer i/o control register 3h tior3h r/w h'00 h'ffff0442 8, 16, 32 timer i/o control register 3l tior3l r/w h'00 h'ffff0443 8, 16, 32 timer interrupt enable register 3 tier3 r/w h'40 h'ffff0444 8, 16, 32 timer status register 3 tsr3 r/(w) * h'c0 h'ffff0445 8, 16, 32 timer counter 3 tcnt3 r/w h'0000 h'ffff0446 16, 32 timer general register 3a tgr3a r/w h'ffff h'ffff0448 16, 32 timer general register 3b tgr3b r/w h'ffff h'ffff044a 16, 32 timer general register 3c tgr3c r/w h'ffff h'ffff044c 16, 32 timer general register 3d tgr3d r/w h'ffff h'ffff044e 16, 32 4 timer control register 4 tcr4 r/w h'00 h'ffff0450 8, 16, 32 timer mode register 4 tmdr4 r/w h'c0 h'ffff0451 8, 16, 32 timer i/o control register 4 tior4 r/w h'00 h'ffff0452 8, 16, 32 timer interrupt enable register 4 tier4 r/w h'40 h'ffff0454 8, 16, 32 timer status register 4 tsr4 r/(w) * h'c0 h'ffff0455 8, 16, 32 timer counter 4 tcnt4 r/w h'0000 h'ffff0456 16, 32 timer general register 4a tgr4a r/w h'ffff h'ffff0458 16, 32 timer general register 4b tgr4b r/w h'ffff h'ffff045a 16, 32 5 timer control register 5 tcr5 r/w h'00 h'ffff0460 8, 16, 32 timer mode register 5 tmdr5 r/w h'c0 h'ffff0461 8, 16, 32 timer i/o control register 5 tior5 r/w h'00 h'ffff0462 8, 16, 32 timer interrupt enable register 5 tier5 r/w h'40 h'ffff0464 8, 16, 32 timer status register 5 tsr5 r/(w) * h'c0 h'ffff0465 8, 16, 32 timer counter 5 tcnt5 r/w h'0000 h'ffff0466 16, 32 timer general register 5a tgr5a r/w h'ffff h'ffff0468 16, 32 timer general register 5b tgr5b r/w h'ffff h'ffff046a 16, 32 all timer start register tstr r/w h'00 h'ffff0400 8, 16, 32 timer sync register tsyr r/w h'00 h'ffff0401 8, 16, 32 note: * can only be written with 0 for flag clearing. rev. 1.0, 08/99, page 354 of 875 10.2 register descriptions 10.2.1 timer control registers (tcr) channel 0: tcr0 channel 3: tcr3 bit:76543210 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w channel 1: tcr1 channel 2: tcr2 channel 4: tcr4 channel 5: tcr5 bit:76543210 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w the tcr registers are 8-bit registers that control the tcnt channels. the tpu has six tcr registers, one for each of channels 0 to 5. the tcr registers are initialized to h'00 by a reset, and in hardware standby mode and software standby mode. they are not initialized by the module standby function. tcr settings should only be made when tcnt operation is halted. rev. 1.0, 08/99, page 355 of 875 bits 7, 6, 5counter clear 2, 1, 0 (cclr2, cclr1, cclr0): these bits select the tcnt counter clearing source. channel bit 7: cclr2 bit 6: cclr1 bit 5: cclr0 description 0, 3 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture * 2 1 0 tcnt cleared by tgrd compare match/input capture * 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 channel bit 7: reserved * 3 bit 6: cclr1 bit 5: cclr0 description 1, 2, 4, 5 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/ input capture 1 0 tcnt cleared by tgrb compare match/ input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 notes: 1. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. bit 7 is reserved in channels 1, 2, 4, and 5. it is always read as 0 and cannot be modified. rev. 1.0, 08/99, page 356 of 875 bits 4 and 3clock edge 1 and 0 (ckeg1, ckeg0): these bits select the input clock edge. when the internal clock is counted using both edges, the input clock period is halved (e.g. p f /4 both edges = p f /2 rising edge). if phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. bit 4: ckeg1 bit 3: ckeg0 description 0 0 count at rising edge (initial value) 1 count at falling edge 1 count at both edges note: internal clock edge selection is valid when the input clock is p f /4 or slower. this setting is ignored if the input clock is p f /1, or when overflow/underflow of another channel is selected. bits 2, 1, 0time prescaler 2, 1, 0 (tpsc2 to tpsc0): these bits select the tcnt counter clock. the clock source can be selected independently for each channel. table 10.4 shows the clock sources that can be set for each channel. table 10.4 tpu clock sources internal clock external clock chan- nel p f f f f /1 p f f f f /4 p f f f f / 16 p f f f f / 64 p f f f f / 256 p f f f f / 1024 p f f f f / 4096 tclka tclkb tclkc tclkd overflow/ underflow on another channel 0oooo o o o o 1ooooo o o o 2oooo o o o o 3 ooooooo o 4oooo o o o o 5ooooo o o o legend o: setting available blank: no setting rev. 1.0, 08/99, page 357 of 875 channel bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 0 0 0 0 internal clock: counts on p f /1 (initial value) 1 internal clock: counts on p f /4 10 internal clock: counts on p f /16 1 internal clock: counts on p f /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input channel bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 1 0 0 0 internal clock: counts on p f /1 (initial value) 1 internal clock: counts on p f /4 10 internal clock: counts on p f /16 1 internal clock: counts on p f /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on p f /256 1 counts on tcnt2 overflow/underflow note: this setting is invalid when channel 1 is in phase counting mode. channel bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 2 0 0 0 internal clock: counts on p f /1 (initial value) 1 internal clock: counts on p f /4 10 internal clock: counts on p f /16 1 internal clock: counts on p f /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on p f /1024 note: this setting is invalid when channel 2 is in phase counting mode. rev. 1.0, 08/99, page 358 of 875 channel bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 3 0 0 0 internal clock: counts on p f /1 (initial value) 1 internal clock: counts on p f /4 1 0 internal clock: counts on p f /16 1 internal clock: counts on p f /64 1 0 0 external clock: counts on tclka pin input 1 internal clock: counts on p f /1024 1 0 internal clock: counts on p f /256 1 internal clock: counts on p f /4096 channel bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 4 0 0 0 internal clock: counts on p f /1 (initial value) 1 internal clock: counts on p f /4 1 0 internal clock: counts on p f /16 1 internal clock: counts on p f /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on p f /1024 1 counts on tcnt5 overflow/underflow note: this setting is invalid when channel 4 is in phase counting mode. channel bit 2: tpsc2 bit 1: tpsc1 bit 0: tpsc0 description 5 0 0 0 internal clock: counts on p f /1 (initial value) 1 internal clock: counts on p f /4 1 0 internal clock: counts on p f /16 1 internal clock: counts on p f /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on p f /256 1 external clock: counts on tclkd pin input note: this setting is invalid when channel 5 is in phase counting mode. rev. 1.0, 08/99, page 359 of 875 10.2.2 timer mode registers (tmdr) channel 0: tmdr0 channel 3: tmdr3 bit:76543210 bfb bfa md3 md2 md1 md0 initial value:11000000 r/w: r/w r/w r/w r/w r/w r/w channel 1: tmdr1 channel 2: tmdr2 channel 4: tmdr4 channel 5: tmdr5 bit:76543210 md3md2md1md0 initial value:11000000 r/w:r/wr/wr/wr/w the tmdr registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. the tpu has six tmdr registers, one for each channel. the tmdr registers are initialized to h'c0 by a reset, and in hardware standby mode and software standby mode. they are not initialized by the module standby function. tmdr settings should only be made when tcnt operation is halted. bits 7 and 6reserved: these bits are always read as 1 and cannot be modified. bit 5buffer operation b (bfb): specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5: bfb description 0 tgrb operates normally (initial value) 1 tgrb and tgrd are used together for buffer operation rev. 1.0, 08/99, page 360 of 875 bit 4buffer operation a (bfa): specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. bit 4: bfa description 0 tgra operates normally (initial value) 1 tgra and tgrc are used together for buffer operation bit 3 to 0mode 3 to 0 (md3 to md0): these bits are used to set the timer operating mode. bit 3: md3 * 1 bit 2: md2 * 2 bit 1: md1 bit 0: md0 description 0000normal operation (initial value) 1 reserved 10 pwm mode 1 1 pwm mode 2 100phase counting mode 1 1 phase counting mode 2 1 0 phase counting mode 3 1 phase counting mode 4 1 *** notes: * dont care 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in these channels, 0 should always be written to md2. rev. 1.0, 08/99, page 361 of 875 10.2.3 timer i/o control registers (tior) channel 0: tior0h channel 1: tior1 channel 2: tior2 channel 3: tior3h channel 4: tior4 channel 5: tior5 bit:76543210 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w channel 0: tior0l channel 3: tior3l bit:76543210 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. the tior registers are 8-bit registers that control the tgr registers. the tpu has eight tior registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. the tior registers are initialized to h'00 by a reset, and in hardware standby mode and software standby mode. they are not initialized by the module standby function. note that the tior registers are affected by the tmdr settings. the initial output specified by tior becomes valid when the counter is halted (the cst bit is cleared to 0 in tstr). in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified. rev. 1.0, 08/99, page 362 of 875 bits 7 to 4 i/o control b3 to b0 (iob3 to iob0) i/o control d3 to d0 (iod3 to iod0): iob3 to iob0 specify the function of tgrb. iod3 to iod0 specify the function of tgrd. channel bit 7: iob3 bit 6: iob2 bit 5: iob1 bit 4: iob0 description 0 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr0b is output compare register initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc0b pin input capture at both edges 1 ** tgr0b is input capture register capture input source is channel 1/count clock input capture at tcnt1 count- up/count-down note: * dont care rev. 1.0, 08/99, page 363 of 875 channel bit 7: iod3 bit 6: iod2 bit 5: iod1 bit 4: iod0 description 0 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr0d is output compare register * 2 initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc0d pin input capture at both edges 1 ** tgr0d is input capture register * 2 capture input source is channel 1/count clock input capture at tcnt1 count- up/count-down * 1 notes: * dont care 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and p f /1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. rev. 1.0, 08/99, page 364 of 875 channel bit 7: iob3 bit 6: iob2 bit 5: iob1 bit 4: iob0 description 1 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr1b is output compare register initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc1b pin input capture at both edges 1 ** tgr1b is input capture register capture input source is tgr0c compare match/input capture input capture at tgr0c compare match/input capture note: * dont care rev. 1.0, 08/99, page 365 of 875 channel bit 7: iob3 bit 6: iob2 bit 5: iob1 bit 4: iob0 description 2 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr2b is output compare register initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr2b is input capture register capture input source is tioc2b pin input capture at both edges note: * dont care rev. 1.0, 08/99, page 366 of 875 channel bit 7: iob3 bit 6: iob2 bit 5: iob1 bit 4: iob0 description 3 0000 output disabled(initial value) 1 initial output is 0 output 0 output at compare match 1 0 1 output at compare match 1 toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr3b is output compare register initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc3b pin input capture at both edges 1 ** tgr3b is input capture register capture input source is channel 4/count clock input capture at tcnt4 count- up/count-down note: * dont care rev. 1.0, 08/99, page 367 of 875 channel bit 7: iod3 bit 6: iod2 bit 5: iod1 bit 4: iod0 description 3 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr3d is output compare register * 2 initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc3d pin input capture at both edges 1 ** tgr3d is input capture register * 2 capture input source is channel 4/count clock input capture at tcnt4 count- up/count-down * 1 notes: * dont care 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and p f /1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. rev. 1.0, 08/99, page 368 of 875 channel bit 7: iob3 bit 6: iob2 bit 5: iob1 bit 4: iob0 description 4 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr4b is output compare register initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc4b pin input capture at both edges 1 ** tgr4b is input capture register capture input source is tgr3c compare match/input capture input capture at generation of tgr3c compare match/input capture note: * dont care rev. 1.0, 08/99, page 369 of 875 channel bit 7: iob3 bit 6: iob2 bit 5: iob1 bit 4: iob0 description 5 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr5b is output compare register initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr5b is input capture register capture input source is tioc5b pin input capture at both edges note: * dont care rev. 1.0, 08/99, page 370 of 875 bits 3 to 0 i/o control a3 to a0 (ioa3 to ioa0) i/o control c3 to c0 (ioc3 to ioc0): ioa3 to ioa0 specify the function of tgra. ioc3 to ioc0 specify the function of tgrc. channel bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 0 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr0a is output compare register initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc0a pin input capture at both edges 1 ** tgr0a is input capture register capture input source is channel 1/count clock input capture at tcnt1 count- up/count-down note: * dont care rev. 1.0, 08/99, page 371 of 875 channel bit 3: ioc3 bit 2: ioc2 bit 1: ioc1 bit 0: ioc0 description 0 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr0c is output compare register * 1 initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc0c pin input capture at both edges 1 ** tgr0c is input capture register * 1 capture input source is channel 1/count clock input capture at tcnt1 count- up/count-down notes: * dont care 1. when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. rev. 1.0, 08/99, page 372 of 875 channel bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 1 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr1a is output compare register initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc1a pin input capture at both edges 1 ** tgr1a is input capture register capture input source is tgr0a compare match/input capture input capture at generation of channel 0/tgr0a compare match/input capture note: * dont care rev. 1.0, 08/99, page 373 of 875 channel bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 2 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr2a is output compare register initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr2a is input capture register capture input source is tioc2a pin input capture at both edges note: * dont care rev. 1.0, 08/99, page 374 of 875 channel bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 3 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr3a is output compare register initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc3a pin input capture at both edges 1 ** tgr3a is input capture register capture input source is channel 4/count clock input capture at tcnt4 count- up/count-down note: * dont care rev. 1.0, 08/99, page 375 of 875 channel bit 3: ioc3 bit 2: ioc2 bit 1: ioc1 bit 0: ioc0 description 3 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr3c is output compare register * 1 initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at falling edge 1 * capture input source is tioc3c pin input capture at both edges 1 ** tgr3c is input capture register * 1 capture input source is channel 4/count clock input capture at tcnt4 count- up/count-down notes: * dont care 1. when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. rev. 1.0, 08/99, page 376 of 875 channel bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 4 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr4a is output compare register initial output is 1 output toggle output at compare match 1000 i nput capture at rising edge 1 input capture at rising edge 1 * capture input source is tioc4a pin input capture at both edges 1 ** tgr4a is input capture register capture input source is tgr3a compare match/input capture input capture at generation of tgr3a compare match/input capture note: * dont care rev. 1.0, 08/99, page 377 of 875 channel bit 3: ioa3 bit 2: ioa2 bit 1: ioa1 bit 0: ioa0 description 5 0000 output disabled(initial value) 1 0 output at compare match 1 0 1 output at compare match 1 initial output is 0 output toggle output at compare match 1 0 0 output disabled 1 0 output at compare match 1 0 1 output at compare match 1 tgr5a is output compare register initial output is 1 output toggle output at compare match 1 * 0 0 input capture at rising edge 1 input capture at falling edge 1 * tgr5a is input capture register capture input source is tioc5a pin input capture at both edges note: * dont care rev. 1.0, 08/99, page 378 of 875 10.2.4 timer interrupt enable registers (tier) channel 0: tier0 channel 3: tier3 bit:76543210 ttge tciev tgied tgiec tgieb tgiea initial value:01000000 r/w: r/w r/w r/w r/w r/w r/w channel 1: tier1 channel 2: tier2 channel 4: tier4 channel 5: tier5 bit:76543210 ttge tcieu tciev tgieb tgiea initial value:01000000 r/w: r/w r/w r/w r/w r/w the tier registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. the tpu has six tier registers, one for each channel. the tier registers are initialized to h'40 by a reset, and in hardware standby mode and software standby mode. they are not initialized by the module standby function. bit 7a/d conversion start request enable (ttge): enables or disables generation of a/d conversion start requests by tgra input capture/compare match. bit 7: ttge description 0 a/d conversion start request generation disabled (initial value) 1 a/d conversion start request generation enabled bit 6reserved: this bit is always read as 1 and cannot be modified. bit 5underflow interrupt enable (tcieu): enables or disables interrupt requests (tciu) by the tcfu flag in tsr when tcfu is set to 1 in channels 1, 2, 4, and 5. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. rev. 1.0, 08/99, page 379 of 875 bit 5: tcieu description 0 interrupt requests (tciu) by tcfu disabled (initial value) 1 interrupt requests (tciu) by tcfu enabled bit 4overflow interrupt enable (tciev): enables or disables interrupt requests (tciv) by the tcfv flag in tsr when tcfv is set to 1. bit 4: tciev description 0 interrupt requests (tciv) by tcfv disabled (initial value) 1 interrupt requests (tciv) by tcfv enabled bit 3tgr interrupt enable d (tgied): enables or disables interrupt requests (tgid) by the tgfd bit in tsr when tgfd is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3: tgied description 0 interrupt requests (tgid) by tgfd bit disabled (initial value) 1 interrupt requests (tgid) by tgfd bit enabled bit 2tgr interrupt enable c (tgiec): enables or disables interrupt requests (tgic) by the tgfc bit in tsr when tgfc is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2: tgiec description 0 interrupt requests (tgic) by tgfc bit disabled (initial value) 1 interrupt requests (tgic) by tgfc bit enabled bit 1tgr interrupt enable b (tgieb): enables or disables interrupt requests (tgib) by the tgfb bit in tsr when tgfb is set to 1. bit 1: tgieb description 0 interrupt requests (tgib) by tgfb bit disabled (initial value) 1 interrupt requests (tgib) by tgfb bit enabled rev. 1.0, 08/99, page 380 of 875 bit 0tgr interrupt enable a (tgiea): enables or disables interrupt requests (tgia) by the tgfa bit in tsr when tgfa is set to 1. bit 0: tgiea description 0 interrupt requests (tgia) by tgfa bit disabled (initial value) 1 interrupt requests (tgia) by tgfa bit enabled 10.2.5 timer status registers (tsr) channel 0: tsr0 channel 3: tsr3 bit:76543210 tcfv tgfd tgfc tgfb tgfa initial value:11000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * note: * can only be written with 0 for flag clearing. channel 1: tsr1 channel 2: tsr2 channel 4: tsr4 channel 5: tsr5 bit:76543210 tcfd tcfu tcfv tgfb tgfa initial value:11000000 r/w: r r/(w) * r/(w) * r/(w) * r/(w) * note: * can only be written with 0 for flag clearing. the tsr registers are 8-bit registers that indicate the status of each channel. the tpu has six tsr registers, one for each channel. the tsr registers are initialized to h'c0 by a reset, and in hardware standby mode and software standby mode. they are not initialized by the module standby function. bit 7count direction flag (tcfd): status flag that shows the direction in which tcnt counts in channels 1, 2, 4, and 5. in channels 0 and 3, bit 7 is reserved. it is always read as 1 and cannot be modified. rev. 1.0, 08/99, page 381 of 875 bit 7: tcfd description 0 tcnt counts down 1 tcnt counts up (initial value) bit 6reserved: this bit is always read as 1 and cannot be modified. bit 5underflow flag (tcfu): status flag that indicates that tcnt underflow has occurred in channels 1, 2, 4, and 5. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5: tcfu description 0 [clearing condition] (initial value) when 0 is written to tcfu after reading tcfu = 1 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) bit 4overflow flag (tcfv): status flag that indicates that tcnt overflow has occurred. bit 4: tcfv description 0 [clearing condition] (initial value) when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) bit 3input capture/output compare flag d (tgfd): status flag that indicates the occurrence of tgrd input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3: tgfd description 0 [clearing condition] (initial value) when 0 is written to tgfd after reading tgfd = 1 1 [setting conditions] when tcnt = tgrd while tgrd is functioning as output compare register when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register rev. 1.0, 08/99, page 382 of 875 bit 2input capture/output compare flag c (tgfc): status flag that indicates the occurrence of tgrc input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2: tgfc description 0 [clearing condition] (initial value) when 0 is written to tgfc after reading tgfc = 1 1 [setting conditions] when tcnt = tgrc while tgrc is functioning as output compare register when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register bit 1input capture/output compare flag b (tgfb): status flag that indicates the occurrence of tgrb input capture or compare match. bit 1: tgfb description 0 [clearing condition] (initial value) when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register bit 0input capture/output compare flag a (tgfa): status flag that indicates the occurrence of tgra input capture or compare match. bit 0: tgfa description 0 [clearing condition] (initial value) when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register note: cleared by dmac transfer initiated by tgfa. rev. 1.0, 08/99, page 383 of 875 10.2.6 timer counters (tcnt) channel 0: tcnt0 (up-counter) channel 1: tcnt1 (up/down-counter*) channel 2: tcnt2 (up/down-counter*) channel 3: tcnt3 (up-counter) channel 4: tcnt4 (up/down-counter*) channel 5: tcnt5 (up/down-counter*) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value:0000000000000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w note: * these counters can be used as up/down-counters only in phase counting mode (or when counting overflows/underflows on another channel in phase counting mode). in other cases they function as up-counters. the tcnt registers are 16-bit counters. the tpu has six tcnt counters, one for each channel. the tcnt counters are initialized to h'0000 by a reset, and in hardware standby mode and software standby mode. they are not initialized by the module standby function. the tcnt counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. rev. 1.0, 08/99, page 384 of 875 10.2.7 timer general registers (tgr) bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value:1111111111111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w the tgr registers are 16-bit registers with a dual function as output compare and input capture registers. the tpu has 16 general registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. tgrc and tgrd for channels 0 and 3 can also be designated for operation as buffer registers*. the tgr registers are initialized to h'ffff by a reset, and in hardware standby mode and software standby mode. they are not initialized by the module standby function. the tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. note: * tgr buffer register combinations are tgraCtgrc and tgrbCtgrd. 10.2.8 timer start register (tstr) bit:76543210 cst5 cst4 cst3 cst2 cst1 cst0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w tstr is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. tstr is initialized to h'00 by a reset, and in hardware standby mode and software standby mode. it is not initialized by the module standby function. bits 7 and 6reserved: these bits are always read as 0 and cannot be modified. bits 5 to 0counter start 5 to 0 (cst5 to cst0): these bits select operation or stoppage of the tcnt counters. rev. 1.0, 08/99, page 385 of 875 bit n: cstn description 0 tcntn count operation is stopped (initial value) 1 tcntn performs count operation notes: n = 0 to 5 if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 10.2.9 timer sync register (tsyr) bit:76543210 sync5 sync4 sync3 sync2 sync1 sync0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w tsyr is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 tcnt counters. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. tsyr is initialized to h'00 by a reset, and in hardware standby mode and software standby mode. it is not initialized by the module standby function. bits 7 and 6reserved: these bits must always be written with 0. bits 5 to 0timer sync 5 to 0 (sync5 to sync0): these bits select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, synchronous presetting * 1 of multiple tcnt counters or synchronous clearing * 2 by counter clearing on another channel is possible. notes: 1. to set synchronous operation, the sync bits for at least two channels must be set to 1. 2. to set synchronous clearing, in addition to the sync bit, the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr. bit n: syncn description 0 tcntn operates independently (tcnt presetting/clearing is unrelated to other channels) (initial value) 1 tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible note: n = 5 to 0 rev. 1.0, 08/99, page 386 of 875 10.3 interface to bus master 10.3.1 16-bit registers tcnt and tgr are 16-bit registers. as the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. these registers cannot be read or written to in 8-bit units; 16-bit access must always be used. an example of 16-bit register access operation is shown in figure 10.2. bus interface h internal data bus l bus master module data bus tcnth tcntl figure 10.2 16-bit register access operation (bus master ? ? ? ? tcnt (16 bits)) 10.3.2 8-bit registers registers other than tcnt and tgr are 8-bit registers. as the data bus to the cpu is 16 bits wide, these registers can be read and written to in 16-bit units. they can also be written to in 8-bit units. examples of 8-bit register access operation are shown in figures 10.3, 10.4, and 10.5. bus interface h internal data bus l bus master module data bus tcr figure 10.3 8-bit register access operation (bus master ? ? ? ? tcr (upper 8 bits)) rev. 1.0, 08/99, page 387 of 875 h l tmdr bus interface internal data bus bus master module data bus figure 10.4 8-bit register access operation (bus master ? ? ? ? tmdr (lower 8 bits)) h l tcr tmdr bus interface internal data bus bus master module data bus figure 10.5 8-bit register access operation (bus master ? ? ? ? tcr and tmdr (16 bits)) rev. 1.0, 08/99, page 388 of 875 10.4 operation 10.4.1 overview operation in each mode is outlined below. normal operation: each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. synchronous operation: when synchronous operation is designated for a channel, tcnt for that channel performs synchronous presetting. that is, when tcnt for a channel designated for synchronous operation is rewritten, the tcnt counters for the other channels are also rewritten at the same time. synchronous clearing of the tcnt counters is also possible by setting the timer synchronization bits in tsyr for channels designated for synchronous operation. buffer operation: when tgr is an output compare register when a compare match occurs, the value in the buffer register for the relevant channel is transferred to tgr. when tgr is an input capture register when input capture occurs, the value in tcnt is transfer to tgr and the value previously held in tgr is transferred to the buffer register. cascaded operation: the channel 1 counter (tcnt1) and channel 2 counter (tcnt2), or the channel 4 counter (tcnt4) and channel 5 counter (tcnt5), can be connected together to operate as a 32-bit counter. pwm mode: in this mode, a pwm waveform is output. the output level can be set in tior. a pwm waveform with a duty of between 0% and 100% can be output, according to the setting of each tgr register. phase counting mode: in this mode, tcnt is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. when phase counting mode is set, the corresponding tclk pin functions as the clock pin, and tcnt performs up- or down-counting. this mode can be used for two-phase encoder pulse input. rev. 1.0, 08/99, page 389 of 875 10.4.2 basic functions counter operation: when one of bits cst0 to cst5 is set to 1 in tstr, the tcnt counter for the corresponding channel starts counting. tcnt can operate as a free-running counter, a cyclic counter, and so on. example of count operation setting procedure figure 10.6 shows an example of the count operation setting procedure. select counter clock operation selection cyclic counter set cycle select output compare register start count operation rev. 1.0, 08/99, page 390 of 875 tcnt value h'ffff h'0000 cst bit tcfv time figure 10.7 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs cyclic count operation. the tgr register for setting the cycle is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr2 to cclr0 in tcr. after the settings have been made, tcnt starts up-count operation as a cyclic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000. figure 10.8 illustrates cyclic counter operation. tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match flag cleared by software or dmac activation figure 10.8 cyclic counter operation rev. 1.0, 08/99, page 391 of 875 waveform output by compare match: the tpu can perform 0, 1, or toggle output from the corresponding output pin using compare matches. example of setting procedure for waveform output by compare match figure 10.9 shows an example of the setting procedure for waveform output by compare match. select waveform output mode output selection rev. 1.0, 08/99, page 392 of 875 examples of waveform output operation figure 10.10 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, and settings have been made so that 0 is output by compare match a, and 1 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb does not change does not change does not change does not change 1 output 0 output figure 10.10 example of 0 output/1 output operation figure 10.11 shows an example of toggle output. in this example tcnt has been designated as a cyclic counter (with counter clearing performed by compare match b), and settings have been made so that output is toggled by both by compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle output toggle output counter cleared by tgrb compare match figure 10.11 example of toggle output operation rev. 1.0, 08/99, page 393 of 875 input capture function: the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detected edge. for channels 0, 1, 3, and 4, it is also possible to specify another channels counter input clock or compare match signal as the input capture source. note: when another channels counter input clock is specified as the input capture source in channel 0 or 3, p f /1 must not be selected as the counter input clock used for input capture input. input capture will not occur if p f /1 is selected. example of input capture operation setting procedure figure 10.12 shows an example of the input capture operation setting procedure. select input capture input input selection 1 start count operation 3 set external pin function 2 1. designate tgr as an input capture register by means of tior, and select the input signal rising edge, falling edge, or both edges as the input capture source. 2. set the external pin function with the pin function controller (pfc). 3. set the cst bit in tstr to 1 to start the count operation. figure 10.12 example of input capture operation setting procedure rev. 1.0, 08/99, page 394 of 875 example of input capture operation figure 10.13 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin input capture input edge, falling edge has been selected as the tiocb pin input capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra time h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb figure 10.13 example of input capture operation 10.4.3 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incremented with respect to a single time base. channels 0 to 5 can all be designated for synchronous operation. rev. 1.0, 08/99, page 395 of 875 example of synchronous operation setting procedure: figure 10.14 shows an example of the synchronous operation setting procedure. set synchronous operation synchronous operation selection set tcnt synchronous presetting rev. 1.0, 08/99, page 396 of 875 example of synchronous operation: figure 10.15 shows an example of synchronous operation. in this example, synchronous operation and pwm mode 1 have been designated for channels 0 to 2, tgr0b compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioc0a, tioc1a, and tioc2a. synchronous presetting and synchronous clearing by tgr0b compare match is performed for the channel 0 to 2 tcnt counters, and the data set in tgr0b is the pwm cycle. for details of pwm modes, see section 10.4.6, pwm modes. tcnt0 to tcnt2 values h'0000 tioc0a tioc1a time tgr0b synchronous clearing by tgr0b compare match tgr2a tgr1a tgr2b tgr0a tgr1b tioc2a figure 10.15 example of synchronous operation rev. 1.0, 08/99, page 397 of 875 10.4.4 buffer operation buffer operation, provided for channels 0 and 3, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 10.5 shows the register combinations used in buffer operation. table 10.5 register combinations in buffer operation channel timer general register buffer register 0tgr0a tgr0c tgr0b tgr0d 3tgr3a tgr3c tgr3b tgr3d when tgr is an output compare register when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 10.16. buffer register timer general register tcnt comparator compare match signal figure 10.16 compare match buffer operation rev. 1.0, 08/99, page 398 of 875 when tgr is an input capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 10.17. buffer register timer general register tcnt input capture signal figure 10.17 input capture buffer operation example of buffer operation setting procedure: figure 10.18 shows an example of the buffer operation setting procedure. select tgr function buffer operation rev. 1.0, 08/99, page 399 of 875 examples of buffer operation: when tgr is an output compare register figure 10.19 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been designated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been set, when compare match a occurs the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each time compare match a occurs. for details of pwm modes, see section 10.4.6, pwm modes. tcnt value tgr0b h'0000 tgr0c time tgr0a h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgr0a h'0450 h'0200 transfer figure 10.19 example of buffer operation (1) rev. 1.0, 08/99, page 400 of 875 when tgr is an input capture register figure 10.20 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 10.20 example of buffer operation (2) rev. 1.0, 08/99, page 401 of 875 10.4.5 cascaded operation in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of tcnt2 (tcnt5) as set in bits tpsc2 to tpsc0 in tcr. underflow occurs only when the lower-16-bit tcnt is in phase counting mode. table 10.6 shows the register combinations used in cascaded operation. note: when phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. table 10.6 cascading combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt1 tcnt2 channels 4 and 5 tcnt4 tcnt5 example of cascaded operation setting procedure: figure 10.21 shows an example of the setting procedure for cascaded operation. cascaded operation rev. 1.0, 08/99, page 402 of 875 examples of cascaded operation: figure 10.22 illustrates the operation when counting upon tcnt2 overflow/underflow has been set for tcnt1, and phase counting mode has been designated for channel 2. tcnt1 is incremented by tcnt2 overflow and decremented by tcnt2 underflow. tclka tcnt2 fffd tcnt1 0001 tclkb fffe ffff 0000 0001 0002 0001 0000 ffff 0000 0000 figure 10.22 example of cascaded operation 10.4.6 pwm modes in pwm mode, pwm waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each tgr. designating tgr compare match as the counter clearing source enables the cycle to be set in that register. all channels can be designated for pwm mode independently. synchronous operation is also possible. there are two pwm modes, as described below. pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by tior bits ioa3 to ioa0 or ioc3 to ioc0 is performed from the tioca or tiocc pin upon compare match a or c. the initial output value is the value set in tgra or tgrc. if the set values of the paired tgr registers are identical, the output value does not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible. pwm mode 2 pwm output is generated using one tgr register as the cycle register and the others as duty registers. the output specified by tior is performed upon compare match. upon counter clearing by a cycle register compare match, the output value of each pin is the initial value set in tior. if the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. rev. 1.0, 08/99, page 403 of 875 in pwm mode 2, a maximum 15-phase pwm output is possible by combined use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 10.7. table 10.7 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 0 tgr0a tioc0a tioc0a tgr0b tioc0b tgr0c tioc0c tioc0c tgr0d tioc0d 1 tgr1a tioc1a tioc1a tgr1b tioc1b 2 tgr2a tioc2a tioc2a tgr2b tioc2b 3 tgr3a tioc3a tioc3a tgr3b tioc3b tgr3c tioc3c tioc3c tgr3d tioc3d 4 tgr4a tioc4a tioc4a tgr4b tioc4b 5 tgr5a tioc5a tioc5a tgr5b tioc5b note: in pwm mode 2, pwm output is not possible for the tgr register in which the cycle is set. rev. 1.0, 08/99, page 404 of 875 example of pwm mode setting procedure: figure 10.23 shows an example of the pwm mode setting procedure. select counter clock pwm mode select counter clearing source select waveform output level rev. 1.0, 08/99, page 405 of 875 examples of pwm mode operation: figure 10.24 shows an example of pwm mode 1 operation. in this example, tgra compare match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 output is set as the tgrb output value. in this case, the value set in tgra is used as the cycle, and the value set in tgrb as the duty. tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 10.24 example of pwm mode operation (1) figure 10.25 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgr1b compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers, to output a 5-phase pwm waveform. in this case, the value set in tgr1b is used as the cycle, and the values set in the other tgr registers as the duty. rev. 1.0, 08/99, page 406 of 875 tcnt value tgr1b h'0000 tioc0a counter cleared by tgr1b compare match time tgr1a tgr0d tgr0c tgr0b tgr0a tioc0b tioc0c tioc0d tioc1a figure 10.25 example of pwm mode operation (2) rev. 1.0, 08/99, page 407 of 875 figure 10.26 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously 0% duty tgrb rewritten figure 10.26 example of pwm mode operation (3) rev. 1.0, 08/99, page 408 of 875 10.4.7 phase counting mode in phase counting mode, the phase difference between two external clock inputs is detected and tcnt is incremented/decremented accordingly. this mode can be set for channels 1, 2, 4, and 5. when phase counting mode is set, an external clock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc2 to tpsc0 and bits ckeg1 and ckeg0 in tcr. however, the functions of bits cclr1 and cclr0 in tcr, and of tior, tier, and tgr are valid, and input capture/compare match and interrupt functions can be used. when overflow occurs while tcnt is counting up, the tcfv flag in tsr is set; when underflow occurs while tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. by reading the tcfd flag it is possible to check whether tcnt is counting up or down. table 10.8 shows the correspondence between external clock pins and channels. table 10.8 phase counting mode clock input pins external clock pins channel a-phase b-phase when channel 1 or 5 is set to phase counting mode tclka tclkb when channel 2 or 4 is set to phase counting mode tclkc tclkd rev. 1.0, 08/99, page 409 of 875 example of phase counting mode setting procedure: figure 10.27 shows an example of the phase counting mode setting procedure. phase counting mode rev. 1.0, 08/99, page 410 of 875 examples of phase counting mode operation: in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four modes, according to the count conditions. phase counting mode 1 figure 10.28 shows an example of phase counting mode 1 operation, and table 10.9 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 10.28 example of phase counting mode 1 operation table 10.9 up/down-count conditions in phase counting mode 1 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level high level high level down-count low level high level low level note: : rising edge : falling edge rev. 1.0, 08/99, page 411 of 875 phase counting mode 2 figure 10.29 shows an example of phase counting mode 2 operation, and table 10.10 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 10.29 example of phase counting mode 2 operation table 10.10 up/down-count conditions in phase counting mode 2 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level dont care low level dont care low level dont care high level up-count high level dont care low level dont care high level dont care low level down-count note: : rising edge : falling edge rev. 1.0, 08/99, page 412 of 875 phase counting mode 3 figure 10.30 shows an example of phase counting mode 3 operation, and table 10.11 summarizes the tcnt up/down-count conditions. tcnt value time up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) down-count figure 10.30 example of phase counting mode 3 operation table 10.11 up/down-count conditions in phase counting mode 3 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level dont care low level dont care low level dont care high level up-count high level down-count low level dont care high level dont care low level dont care note: : rising edge : falling edge rev. 1.0, 08/99, page 413 of 875 phase counting mode 4 figure 10.31 shows an example of phase counting mode 4 operation, and table 10.12 summarizes the tcnt up/down-count conditions. tcnt value time tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) up-count down-count figure 10.31 example of phase counting mode 4 operation table 10.12 up/down-count conditions in phase counting mode 4 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level dont care high level high level down-count low level high level dont care low level note: : rising edge : falling edge rev. 1.0, 08/99, page 414 of 875 phase counting mode application example: figure 10.32 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgr0c compare match; tgr0a and tgr0c are used for the compare match function, and are set with the speed control period and position control period. tgr0b is used for input capture, with tgr0b and tgr0d operating in buffer mode. the channel 1 counter input clock is designated as the tgr0b input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. tgr1a and tgr1b for channel 1 are designated for input capture, channel 0 tgr0a and tgr0c compare matches are selected as the input capture source, and these registers store the up/down-counter values for the respective control periods. this procedure enables accurate position/speed detection to be achieved. rev. 1.0, 08/99, page 415 of 875 tcnt1 tcnt0 channel 1 tgr1a (speed period capture) tgr0a (speed control period) tgr1b (position period capture) tgr0c (position control period) tgr0b (pulse width capture) tgr0d (buffer operation) channel 0 tclka tclkb edge detection circuit + C + C figure 10.32 phase counting mode application example rev. 1.0, 08/99, page 416 of 875 10.5 interrupts 10.5.1 interrupt sources and priorities there are three kinds of tpu interrupt source: tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disable bit, allowing generation of internal reset signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by clearing the status flag to 0. relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. for details, see section 6, interrupt controller (intc). table 10.13 lists the tpu interrupt sources. rev. 1.0, 08/99, page 417 of 875 table 10.13 tpu interrupts channel interrupt source description dmac activation priority 0 tgi0a tgr0a input capture/compare match possible tgi0b tgr0b input capture/compare match not possible tgi0c tgr0c input capture/compare match not possible tgi0d tgr0d input capture/compare match not possible tci0v tcnt0 overflow not possible 1 tgi1a tgr1a input capture/compare match possible tgi1b tgr1b input capture/compare match not possible tci1v tcnt1 overflow not possible tci1u tcnt1 underflow not possible 2 tgi2a tgr2a input capture/compare match possible tgi2b tgr2b input capture/compare match not possible tci2v tcnt2 overflow not possible tci2u tcnt2 underflow not possible 3 tgi3a tgr3a input capture/compare match possible tgi3b tgr3b input capture/compare match not possible tgi3c tgr3c input capture/compare match not possible tgi3d tgr3d input capture/compare match not possible tci3v tcnt3 overflow not possible 4 tgi4a tgr4a input capture/compare match possible tgi4b tgr4b input capture/compare match not possible tci4v tcnt4 overflow not possible tci4u tcnt4 underflow not possible 5 tgi5a tgr5a input capture/compare match possible tgi5b tgr5b input capture/compare match not possible tci5v tcnt5 overflow not possible tci5u tcnt5 underflow not possible high - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. rev. 1.0, 08/99, page 418 of 875 input capture/compare match interrupts: an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a particular channel. the interrupt request is cleared by clearing the tgf flag to 0. the tpu has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. overflow interrupts: an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of tcnt overflow on a particular channel. the interrupt request is cleared by clearing the tcfv flag to 0. the tpu has six overflow interrupts, one for each channel. underflow interrupts: an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a particular channel. the interrupt request is cleared by clearing the tcfu flag to 0. the tpu has four overflow interrupts, one each for channels 1, 2, 4, and 5. 10.5.2 dmac activation the tgra input capture/compare match interrupt for a channel can be used as a dmac activation source. for details, see section 9, dma controller. in the tpu, a total of six tgra input capture/compare match interrupts can be used as dmac activation sources, one for each channel. 10.5.3 a/d converter activation the a/d converter can be activated by the tgra input capture/compare match interrupt for a channel. if the ttge bit in tier is set to 1 when the tfga flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match interrupt on a particular channel, a request to start a/d conversion is sent to the a/d converter. if the tpu conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. in the tpu, a total of six tgra input capture/compare match interrupts can be used as a/d converter conversion start sources, one for each channel. rev. 1.0, 08/99, page 419 of 875 10.6 operation timing 10.6.1 input/output timing tcnt count timing: figure 10.33 shows tcnt count timing in input clock operation, and figure 10.34 shows tcnt count timing in external clock operation. tcnt tcnt input clock internal clock p f n C 1 n n + 1 n + 2 falling edge rising edge figure 10.33 count timing in internal clock operation tcnt tcnt input clock external clock p f n C 1 n n + 1 n + 2 falling edge rising edge falling edge figure 10.34 count timing in external clock operation output compare output timing: a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin (the tioc pin). after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. rev. 1.0, 08/99, page 420 of 875 figure 10.35 shows output compare output timing. tgr tcnt tcnt input clock p f n n n + 1 compare match signal tioc pin figure 10.35 output compare output timing input capture signal timing: figure 10.36 shows input capture signal timing. tcnt input capture input p f n n + 1 n + 2 n n + 2 tgr input capture signal figure 10.36 input capture input signal timing rev. 1.0, 08/99, page 421 of 875 timing of counter clearing by compare match/input capture: figure 10.37 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.38 shows the timing when counter clearing by input capture occurrence is specified. tcnt counter clear signal compare match signal p f tgr n n h'0000 figure 10.37 counter clear timing (compare match) tcnt counter clear signal input capture signal p f tgr n h'0000 n figure 10.38 counter clear timing (input capture) rev. 1.0, 08/99, page 422 of 875 buffer operation timing: figures 10.39 and 10.40 show the timing in buffer operation. tgra, tgrb compare match signal tcnt p f tgrc, tgrd nn n n n + 1 figure 10.39 buffer operation timing (compare match) tgra, tgrb tcnt input capture signal p f tgrc, tgrd n n n n + 1 n n n + 1 figure 10.40 buffer operation timing (input capture) rev. 1.0, 08/99, page 423 of 875 10.6.2 interrupt signal timing tgf flag setting timing in case of compare match: figure 10.41 shows the timing of setting of the tgf flag in tsr by compare match occurrence, and the tgi interrupt request signal timing. tgr tcnt tcnt input clock p f n n n + 1 compare match signal tgf flag tgi interrupt figure 10.41 tgi interrupt timing (compare match) rev. 1.0, 08/99, page 424 of 875 tgf flag setting timing in case of input capture: figure 10.42 shows the timing of setting of the tgf flag in tsr by input capture occurrence, and the tgi interrupt request signal timing. tgr tcnt input capture signal p f n n tgf flag tgi interrupt figure 10.42 tgi interrupt timing (input capture) rev. 1.0, 08/99, page 425 of 875 tcfv flag/tcfu flag setting timing: figure 10.43 shows the timing of setting of the tcfv flag in tsr by overflow occurrence, and the tciv interrupt request signal timing. figure 10.44 shows the timing of setting of the tcfu flag in tsr by underflow occurrence, and the tciu interrupt request signal timing. overflow signal tcnt (overflow) tcnt input clock p f h'ffff h'0000 tcfv flag tciv interrupt figure 10.43 tciv interrupt setting timing underflow signal tcnt (underflow) tcnt input clock p f h'0000 h'ffff tcfu flag tciu interrupt figure 10.44 tciu interrupt setting timing rev. 1.0, 08/99, page 426 of 875 status flag clearing timing: after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dmac is activated, the flag is cleared automatically. figure 10.45 shows the timing of status flag clearing by the cpu, and figure 10.46 shows the timing of status flag clearing by the dmac. status flag write signal address p f tsr address interrupt request signal tsr write cycle t1 t2 figure 10.45 timing of status flag clearing by cpu interrupt request signal status flag address p f source address dmac read cycle t1 t2 destination address t1 t2 dmac write cycle figure 10.46 timing of status flag clearing by dmac activation rev. 1.0, 08/99, page 427 of 875 10.7 usage notes note that the kinds of operation and contention described below occur during tpu operation. input clock restrictions: the input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. the tpu will not operate properly with a narrower pulse width. in phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 10.47 shows the input clock conditions in phase counting mode. overlap phase difference phase difference overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width note: phase difference and overlap: 1.5 states or more pulse width: 2.5 states or more figure 10.47 phase difference, overlap, and pulse width in phase counting mode caution on period setting: when counter clearing by compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = f: counter frequency p f : operating frequency n: tgr set value (n + 1) p f rev. 1.0, 08/99, page 428 of 875 contention between tcnt write and clear operations: if the counter clear signal is generated in the t2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 10.48 shows the timing in this case. counter clear signal write signal address p f tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 10.48 contention between tcnt write and clear operations rev. 1.0, 08/99, page 429 of 875 contention between tcnt write and increment operations: if incrementing occurs in the t2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 10.49 shows the timing in this case. tcnt input clock write signal address p f tcnt address tcnt tcnt write cycle t1 t2 n m tcnt write data figure 10.49 contention between tcnt write and increment operations rev. 1.0, 08/99, page 430 of 875 contention between tgr write and compare match: if a compare match occurs in the t2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is inhibited. a compare match does not occur even if the same value as before is written. figure 10.50 shows the timing in this case. compare match signal write signal address p f tgr address tcnt tgr write cycle t1 t2 n m tgr write data tgr n n + 1 inhibited figure 10.50 contention between tgr write and compare match rev. 1.0, 08/99, page 431 of 875 contention between buffer register write and compare match: if a compare match occurs in the t2 state of a tgr write cycle, the data transferred to tgr by the buffer operation will be the write data. figure 10.51 shows the timing in this case. compare match signal write signal address p f buffer register address buffer register tgr write cycle t1 t2 m tgr n m buffer register write data figure 10.51 contention between buffer register write and compare match rev. 1.0, 08/99, page 432 of 875 contention between tgr read and input capture: if the input capture signal is generated in the t1 state of a tgr read cycle, the data that is read will be the data after input capture transfer. figure 10.52 shows the timing in this case. input capture signal read signal address p f tgr address tgr tgr read cycle t1 t2 m internal data bus x m figure 10.52 contention between tgr read and input capture rev. 1.0, 08/99, page 433 of 875 contention between tgr write and input capture: if the input capture signal is generated in the t2 state of a tgr write cycle, the input capture operation takes precedence and the write to tgr is not performed. figure 10.53 shows the timing in this case. input capture signal write signal address p f tcnt tgr write cycle t1 t2 m tgr m tgr address figure 10.53 contention between tgr write and input capture rev. 1.0, 08/99, page 434 of 875 contention between buffer register write and input capture: if the input capture signal is generated in the t2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 10.54 shows the timing in this case. input capture signal write signal address p f tcnt buffer register write cycle t1 t2 n tgr n m m buffer register buffer register address figure 10.54 contention between buffer register write and input capture rev. 1.0, 08/99, page 435 of 875 contention between overflow/underflow and counter clearing: if overflow/underflow and counter clearing occur simultaneously, tcnt clearing takes precedence and the tcfv/tcfu flag in tsr is not set. figure 10.55 shows the operation timing when a tgr compare match is specified as the clearing source, and h'ffff is set in tgr. counter clear signal tcnt tcnt input clock p f h'ffff h'0000 tgf tcfv inhibited figure 10.55 contention between overflow and counter clearing rev. 1.0, 08/99, page 436 of 875 contention between tcnt write and overflow/underflow: if there is an up-count or down- count in the t2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set. figure 10.56 shows the operation timing in case of contention between a tcnt write and overflow. write signal address p f tcnt address tcnt tcnt write cycle t1 t2 h'ffff m tcnt write data tcfv flag figure 10.56 contention between tcnt write and overflow rev. 1.0, 08/99, page 437 of 875 section 11 motor management timer (mmt) 11.1 overview the sh7065 has an on-chip motor management timer (mmt) consisting of a 16-bit timer. the mmt is a single-channel timer capable of outputting 6-phase pwm waveforms with non-overlap times. 11.1.1 features the mmt has the following features: triangular wave comparison type 6-phase pwm waveform output with non-overlap times ? non-overlap times generated by timer dead time counters toggle output synchronized with pwm period counter clearing can be performed by an external signal provision for data transfer by means of dmac activation a/d converter conversion start trigger can be generated ? compare match signal used as a/d converter conversion start trigger output-off functions ? pwm output halted by external signal ? pwm output halted when oscillation stops rev. 1.0, 08/99, page 438 of 875 11.1.2 block diagram figure 11.1 shows a block diagram of the mmt. p f is obtained by division of ckp according to a setting in the module clock division setting register. tgruu +2td +td +2td +td +2td +td a/d conversion start request signal tgru tgrud tgrvu tgrv tgrvd tgrwu tgrw tgrwd tmdr pco pci puoa puob pvoa pvob pwoa pwob tcnt tsr tbru tbrv tbrw tpbr tpdr 2 +2td tpdr compare match interrupt 2td compare match interrupt tddr tdcnt0 comparators magnitude comparators tcnt p f comparators tgr: timer general register tbr: timer buffer register tddr: timer dead time data register tpdr: timer period data register tpbr: timer period buffer register td: dead time control circuit tmdr: timer mode register tcnr: timer control register tsr: timer status register tcnt: timer counter tdcnt: timer dead time counter figure 11.1 block diagram of mmt rev. 1.0, 08/99, page 439 of 875 11.1.3 pin configuration table 11.1 shows the pin configuration of the mmt. table 11.1 mmt pins pin name signal name i/o function counter clear input pci input counter clear signal input pwm period output pco output toggle output synchronized with pwm period pwmu phase output a puoa output pwmu phase output (positive phase) pwmu phase output b puob output pwmu phase output (negative phase) pwmv phase output a pvoa output pwmv phase output (positive phase) pwmv phase output b pvob output pwmv phase output (negative phase) pwmw phase output a pwoa output pwmw phase output (positive phase) pwmw phase output b pwob output pwmw phase output (negative phase) 11.1.4 register configuration table 11.2 summarizes the mmt registers. table 11.2 mmt registers name abbre- viation r/w initial value address access size timer mode register tmdr r/w h'00 h'ffff 0480 8, 16, 32 timer control register tcnr r/w h'00 h'ffff 0482 8, 16, 32 timer status register tsr r/(w) h'80 h'ffff 0484 8, 16, 32 timer counter tcnt r/w h'0000 h'ffff 0486 16, 32 timer buffer register u tbru r/w h'ffff h'ffff 0490, h'ffff 049c * 16, 32 timer buffer register v tbrv r/w h'ffff h'ffff 04a0, h'ffff 04ac * 16, 32 timer buffer register w tbrw r/w h'ffff h'ffff 04b0, h'ffff 04bc * 16, 32 timer general register uu tgruu r/w h'ffff h'ffff 0492 16, 32 timer general register vu tgrvu r/w h'ffff h'ffff 04a2 16, 32 timer general register wu tgrwu r/w h'ffff h'ffff 04b2 16, 32 timer general register u tgru r/w h'ffff h'ffff 0494 16, 32 timer general register v tgrv r/w h'ffff h'ffff 04a4 16, 32 rev. 1.0, 08/99, page 440 of 875 table 11.2 mmt registers (cont) name abbre- viation r/w initial value address access size timer general register w tgrw r/w h'ffff h'ffff 04b4 16, 32 timer general register ud tgrud r/w h'ffff h'ffff 0496 16, 32 timer general register vd tgrvd r/w h'ffff h'ffff 04a6 16, 32 timer general register wd tgrwd r/w h'ffff h'ffff 04b6 16, 32 timer dead time counter 0 tdcnt0 r h'0000 h'ffff 0498 16, 32 timer dead time counter 1 tdcnt1 r h'0000 h'ffff 049a 16, 32 timer dead time counter 2 tdcnt2 r h'0000 h'ffff 04a8 16, 32 timer dead time counter 3 tdcnt3 r h'0000 h'ffff 04aa 16, 32 timer dead time counter 4 tdcnt4 r h'0000 h'ffff 04b8 16, 32 timer dead time counter 5 tdcnt5 r h'0000 h'ffff 04ba 16, 32 timer dead time data register tddr r/w h'ffff h'ffff 048c 16, 32 timer period buffer register tpbr r/w h'ffff h'ffff 048a 16, 32 timer period data register tpdr r/w h'ffff h'ffff 0488 16, 32 note: registers tbru to tbrw each have two addresses, a buffer operation address (shown first) and a free operation address (shown second). a value written to the buffer operation address is transferred to the corresponding tgr at the timing set in bits md1 and md0 in the timer mode register (tmdr). a value set in the free operation address is transferred to the corresponding tgr immediately. rev. 1.0, 08/99, page 441 of 875 11.2 register descriptions 11.2.1 timer mode register (tmdr) the timer mode register (tmdr) is an 8-bit readable/writable register that sets the operating mode and selects the pwm output level. tmdr is initialized to h'00 by a power-on reset and in standby mode. it is not initialized in module standby mode. bit:76543210 olsnolspmd1md0 initial value:00000000 r/w:r/wr/wr/wr/w bits 7 to 4reserved: these bits are always read as 0 and should only be written with 0. bit 3output level select n (olsn): selects the negative phase output level in the operating modes. bit 3: olsn description 0 active level is low (initial value) 1 active level is high bit 2output level select p (olsp): selects the positive phase output level in the operating modes. bit 2: olsp description 0 active level is low (initial value) 1 active level is high bits 1 and 0mode 1 and 0 (md1, md0): these bits set the timer operating mode. bit 1: md1 bit 0: md0 description 0 0 operation halted (initial value) 1 operating mode 1 (transfer at crest) 1 0 operating mode 2 (transfer at trough) 1 operating mode 3 (transfer at crest and trough) rev. 1.0, 08/99, page 442 of 875 11.2.2 timer control register (tcnr) the timer control register (tcnr) is an 8-bit readable/writable register that controls enabling or disabling of interrupt requests, selects enabling or disabling of register access, selects counter operation or halting, and controls enabling or disabling of toggle output synchronized with the pwm period. tcnr is initialized to h'00 by a power-on reset and in standby mode. it is not initialized in module standby mode. bit:76543210 ttge cst rpro tgien tgiem initial value:00000000 r/w: r/w r/w r/w r/w r/w bit 7a/d conversion start request enable (ttge): enables or disables generation of a/d conversion start requests by a compare match between tcnt and the tpdr register, and by a compare match between tcnt and 2td (td: dead time). bit 7: ttge description 0 a/d conversion start request generation disabled (initial value) 1 a/d conversion start request generation enabled the a/d conversion start timing in each operating mode is shown in table 11.3. table 11.3 conversion start timing in each operating mode operating mode a/d conversion start timing operating mode 1 (transfer at crest) a/d conversion starts at trough operating mode 2 (transfer at trough) a/d conversion starts at crest operating mode 3 (transfer at crest and trough) a/d conversion starts at crest or trough bit 6timer counter start (cst): selects operation or halting of the timer counter (tcnt) and timer dead time counter (tdcnt). bit 6: cst description 0 tcnt and tdcnt operation is halted (initial value) 1 tcnt and tdcnt perform count operations rev. 1.0, 08/99, page 443 of 875 bit 5register protect (rpro): enables or disables reading of registers other than tsr and writes to registers other than tbru to tbrw, tpbr, and tsr. writes to tcnr itself are also disabled. note that reset input is necessary in order to write to these registers again. bit 5: rpro description 0 register access enabled (initial value) 1 register access disabled bits 4 to 2reserved: these bits are always read as 0 and should only be written with 0. bit 1tgr interrupt enable n (tgien): enables or disables interrupt requests by the tgfn bit in the tsr register when tgfn is set to 1. bit 1: tgien description 0 interrupt requests (tgin) by tgfn bit disabled (initial value) 1 interrupt requests (tgin) by tgfn bit enabled bit 0tgr interrupt enable m (tgiem): enables or disables interrupt requests by the tgfm bit in the tsr register when tgfm is set to 1. bit 0: tgiem description 0 interrupt requests (tgim) by tgfm bit disabled (initial value) 1 interrupt requests (tgim) by tgfm bit enabled 11.2.3 timer status register (tsr) the timer status register (tsr) is an 8-bit register containing status flags. tsr is initialized to h'80 by a power-on reset and in standby mode. it is not initialized in module standby mode. bit:76543210 tcfdtgfntgfm initial value:10000000 r/w:r r/(w) * r/(w) * note: * can only be written with 0 for flag clearing. rev. 1.0, 08/99, page 444 of 875 bit 7count direction flag (tcfd): status flag that indicates the count direction of the tcnt counter. bit 7: tcfd description 0 tcnt counts down 1 tcnt counts up (initial value) bits 6 to 2reserved: these bits are always read as 0 and should only be written with 0. bit 1output compare flag n (tgfn): status flag that indicates the occurrence of a compare match between tcnt and 2td (td: tddr value). bit 1: tgfn description 0 [clearing condition] (initial value) when 0 is written to tgfn after reading tgfn = 1 1 [setting condition] when tcnt = 2td bit 0output compare flag m (tgfm): status flag that indicates the occurrence of a compare match between tcnt and the tpdr register. bit 0: tgfm description 0 [clearing condition] (initial value) when 0 is written to tgfm after reading tgfm = 1 1 [setting condition] when tcnt = tgrm rev. 1.0, 08/99, page 445 of 875 11.2.4 timer counter (tcnt) the timer counter (tcnt) is a 16-bit counter. tcnt is initialized to h'0000 by a power-on reset and in standby mode. it is not initialized in module standby mode. only 16-bit access can be used on tcnt; 8-bit access is not possible. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value:0000000000000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 11.2.5 timer buffer registers (tbr) the timer buffer registers (tbr) function as 16-bit buffer registers. the mmt has three tbr registers. the tbr value is transferred to the tgr register at the timing set in the tmdr register (except in the case of a write to the tbrs free operation address, in which case the value is transferred to the tgr register immediately). the tbr registers are initialized to h'ffff by a power-on reset and in standby mode. they are not initialized in module standby mode. only 16-bit access can be used on the tbr registers; 8-bit access is not possible. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value:1111111111111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w rev. 1.0, 08/99, page 446 of 875 11.2.6 timer general registers (tgr) the timer general registers (tgr) function as 16-bit compare registers. the mmt has nine tgr registers, which are compared with the tcnt counter in the operating modes. the tgr registers are initialized to h'ffff by a power-on reset and in standby mode. they are not initialized in module standby mode. only 16-bit access can be used on the tgr registers; 8-bit access is not possible. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value:1111111111111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 11.2.7 timer dead time counters (tdcnt) the timer dead time counters (tdcnt) are 16-bit read-only counters. the tdcnt counters are initialized to h'0000 by a power-on reset and in standby mode. they are not initialized in module standby mode. only 16-bit access can be used on the tdcnt counters; 8-bit access is not possible. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value:0000000000000000 r/w:rrrrrrrrrrrrrrrr 11.2.8 timer dead time data register (tddr) the timer dead time data register (tddr) is a 16-bit register that sets the positive phase and negative phase non-overlap time (dead time). tddr is initialized to h'ffff by a power-on reset and in standby mode. it is not initialized in module standby mode. only 16-bit access can be used on tddr ; 8-bit access is not possible. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value:1111111111111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w rev. 1.0, 08/99, page 447 of 875 11.2.9 timer period buffer register (tpbr) the timer period buffer register (tpbr) is a 16-bit register that functions as a buffer register for the tpdr register. a value of 1/2 the pwm carrier period should be set as the tpbr value. the tpbr value is transferred to the tpdr register at the transfer timing set in the tmdr register. tpbr is initialized to h'ffff by a power-on reset and in standby mode. it is not initialized in module standby mode. only 16-bit access can be used on tpbr ; 8-bit access is not possible. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value:1111111111111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 11.2.10 timer period data register (tpdr) the timer period data register (tpdr) functions as a 16-bit compare register. in the operating modes, the tpdr register value is constantly compared with the tcnt counter value, and when they match the tcnt counter changes its count direction from up to down. tpdr is initialized to h'ffff by a power-on reset and in standby mode. it is not initialized in module standby mode. only 16-bit access can be used on tpdr ; 8-bit access is not possible. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 initial value:1111111111111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 11.3 operation when the operating mode is selected, 3-phase pwm waveform output is performed with a non- overlap relationship between the positive and negative phases. the puoa, puob, pvoa, pvob, pwoa, and pwob pins are pwm output pins, and the pcio pin functions as a toggle output synchronized with the pwm waveform, or as the counter clear signal input. the tcnt counter performs up- and down-count operations, while the tdcnt counters perform up-count operations. rev. 1.0, 08/99, page 448 of 875 11.3.1 sample setting procedure an example of the operating mode setting procedure is shown in figure 11.2. halt count operation set tcnt set tbr set pwm output level set operating mode set external pin functions start count operation rev. 1.0, 08/99, page 449 of 875 11.3.2 overview of operation count operation: set 2td (td: value set in tddr) as the initial value of the tcnt counter when the setting of the cst bit in tcnr is 0. when the cst bit is set to 1, tcnt counts up to {value set in tpbr + 2td}, and then starts counting down. when tcnt reaches 2td, it starts counting up again, and continues in this way. tcnt is constantly compared with tgru, tgrv, and tgrw. in addition, it is compared with tgruu, tgrvu, tgrwu, and tpdr when counting up, and with tgrud, tgrvd, tgrwd, and 2td when counting down. tdcnt0 to tdcnt5 are read-only counters. it is not necessary to set their initial values. tdcnt0, tdcnt2, and tdcnt4 start counting up at the falling edge of positive phase compare match output when tcnt is counting up, and when they match tddr they are cleared to 0 and halt. tdcnt1, tdcnt3, and tdcnt5 start counting up at the falling edge of negative phase compare match output when tcnt is counting up, and when they match tddr they are cleared to 0 and halt. tdcnt0 to tdcnt5 are compared with tddr only while a count operation is in progress. no count operation is performed when the tddr value is 0. figure 11.3 shows an example of the tcnt count operation. rev. 1.0, 08/99, page 450 of 875 tcnt td h'ffff h'0000 tpdr tgruu tgru tgrud 2td td td 2td 2td 1/2 period (tpbr) figure 11.3 example of tcnt count operation register operation: in the operating modes, four buffer registers and ten compare registers are used. the registers constantly compared with the tcnt counter are tgru, tgrv, and tgrw. in addition, tgruu, tgrvu, tgrwu, and tpdr are compared with tcnt when it is when counting up, and tgrud, tgrvd, tgrwd are compared with tcnt when it is counting down. the buffer register for tpdr is tpbr; the buffer register for tgruu, tgru, and tgrud is tbru; the buffer register for tgrvu, tgrv, and tgrvd is tbrv; and the buffer register for tgrwu, tgrw, and tgrwd is tbrw. to change compare register data, the new data should be written to the corresponding buffer register. the buffer registers can be read and written to at all times. data written to tpbr and to the buffer operation addresses for and tbru to tbrw is transferred at the timing specified by bits md1 and md0 in the timer mode register (tmdr). data written to the free operation addresses for tbru to tbrw is transferred immediately. after data transfer is completed, the relationship between the compare registers and buffer registers is as follows. tgru (tgrv, tgrw) value = tbru (tbrv, tbrw) value + td (td: value set in tddr) tgruu (tgrvu, tgrwu) value = tbru (tbrv, tbrw) value + 2td tgrud (tgrvd, tgrwd) value = tbru (tbrv, tbrw) value tpdr value = tpbr value + 2td rev. 1.0, 08/99, page 451 of 875 the values of tbru to tbrw should always be set in the range h'0000 to h'ffff C 2td, and the value of tpbr should always be set in the range h'0000 to h'ffff C 4td. figure 11.4 shows examples of counter and register operations. + + compared during up-count compared during down-count compared during up-count compared during down-count up-count ? compare match ? down-count down-count ? compare match ? up-count constantly compared (tbr + 2td) (tbr + td) tgruu tgrvu tgrwu tgru tgrv tgrw (tbr) tgrud tgrvd tgrwd tpdr tcnt (1/2 period + 2td) tddr (td) tpbr (1/2 period) tddr tddr tdcnt (td) (td) tbru tbrv tbrw (tbr) (2td) 2 2 up-count ? compare match ? halt tcnt + figure 11.4 examples of counter and register operations rev. 1.0, 08/99, page 452 of 875 initial settings: in the operating modes, there are five registers that require initial settings. make the following register settings before setting the operating mode with bits md1 and md0 in the timer mode register (tmdr). set 1/2 the pwm carrier period in the timer period buffer register (tpbr), dead time td in the timer dead time data register (tddr) (when outputting an ideal waveform, td = h'0000), and {tpbr value + 2td} in the timer period data register (tpdr). set {pwm duty initial value C td} in the free write operation addresses for tbru to tbrw. the values of tbru to tbrw should always be set in the range h'0000 to h'ffff C 2td, and the value of tpbr should always be set in the range h'0000 to h'ffff C 4td. pwm output active level setting: in the operating modes, the active level of pwm pulses is set with bits olsn and olsp in the timer mode register (tmdr). the output level can be set for the three positive phases and the three negative phases of 6-phase output. the operating mode must be exited before setting or changing the output level. dead time setting: in the operating modes, pwm pulses are output with a non-overlap relationship between the positive and negative phases. this non-overlap time is known as the dead time. the non-overlap time is set in the timer dead time data register (tddr). the dead time generation waveform is generated by comparing the value set in tddr with the timer dead time counters (tdcnt) for each phase. the operating mode must be exited before changing the contents of tddr. pwm period setting: in the operating modes, 1/2 the pwm pulse period is set in the tpbr register. the tpbr value should always be set in the range h'0000 to h'ffff C 4td. the value set in tpbr is transferred to tpdr at the timing selected with bits md1 and md0 in the timer mode register (tmdr). after the transfer, the value in tpdr is {tpbr value + 2td}. the new pwm period is effective from the next period when data updating is performed at the tcnt counter crest, and from the same period when data updating is performed at the trough. register updating: in the operating modes, buffer registers are used to update compare register data. update data can be written to a buffer register at all times. the buffer register value is transferred to the compare register at the timing set by bits md1 and md0 in the timer mode register (tmdr) (except in the case of a write to the free operation address for tbru to tbrw, in which case the value is transferred to the compare register immediately). rev. 1.0, 08/99, page 453 of 875 initial output in operating modes: the initial output in the operating modes is determined by the initial value of tbru to tbrw. table 11.4 shows the relationship between the initial value of tbru to tbrw and the initial output. table 11.4 initial values of tbru to tbrw and initial output initial output initial value of tbru to tbrw olsp = 1, olsn = 1 olsp = 0, olsn = 0 tbr = h'0000 positive phase: 1 negative phase: 0 positive phase: 0 negative phase: 1 h'0000 < tbr td positive phase: 0 negative phase: 0 positive phase: 1 negative phase: 1 td < tbr h'ffff C 2td positive phase: 0 negative phase: 1 positive phase: 1 negative phase: 0 pwm output generation in operating modes: in the operating modes, 3-phase pwm waveform output is performed with a non-overlap relationship between the positive and negative phases. this non-overlap time is called the dead time. the pwm waveform is generated from an output generation waveform generated by anding the compare output waveform with the dead time generation waveform. waveform generation for one phase (the u-phase) is shown here. the v-phase and w-phase waveforms are generated in the same way. compare output waveform the compare output waveform is generated by comparing the values in the tcnt counter and the tgr registers. for compare output waveform u phase a (cmoua), 0 is output if tgruu > tcnt in the t1 interval (when tcnt is counting up), and 1 is output if tgruu tcnt. in the t2 interval (when tcnt is counting down), 0 is output if tgru > tcnt, and 1 is output if tgru tcnt. for compare output waveform u phase b (cmoub), 1 is output if tgru > tcnt in the t1 interval, and 0 is output if tgru tcnt. in the t2 interval, 1 is output if tgrud > tcnt, and 0 is output if tgrud tcnt. dead time generation waveform for dead time generation waveform u phase a (dtgua) and b (dtgub), 1 is output as the initial value. tdcnt0 starts counting at the falling edge of cmoua. dtgua outputs 0 while tdcnt0 is counting, and 1 otherwise. rev. 1.0, 08/99, page 454 of 875 tdcnt1 starts counting at the falling edge of cmoub. dtgub outputs 0 while tdcnt1 is counting, and 1 otherwise. output generation waveform output generation waveform u phase a (ogua) is generated by anding cmoua and dtgub, and output generation waveform u phase b (ogub) is generated by anding cmoub and dtgua. pwm waveform the pwm waveform is generated by converting the output generation waveform to the output level set in bits olsn and olsp in the timer mode register (tmdr). figure 11.5 shows an example of pwm waveform generation (operating mode 3, olsn = 1, olsp = 1). when writing to free operation address tpdr 2td compare output waveform dead time generation waveform output generation waveform pwm waveform figure 11.5 example of pwm waveform generation 0% to 100% duty output: in the operating modes, pwm waveforms with any duty from 0% to 100% can be output. the output pwm duty is set by means of the buffer registers (tbru to tbrw). 100% duty output is performed when the buffer register (tbru to tbrw) value is set to h'0000. the waveform in this case has the positive phase in the 100% on state. 0% duty output is performed when a value greater than the tpdr value is set as the buffer register (tbru to tbrw) value. the waveform in this case has the positive phase in the 100% off state. rev. 1.0, 08/99, page 455 of 875 external counter clear function: in the operating modes, the tcnt counter can be cleared from an external source. when using the counter clear function, the pcio pin function should be set to input with the pin function controller (pfc). at the falling edge of pcio, the tcnt counter is cleared to 2td (initial set value), counts up until it reaches the tpdr value, and then starts counting down. when the count reaches 2td, tcnt starts counting up again, and this sequence is repeated. an example of counter clearing is shown in figure 11.6. tcnt tpdr 2td h'0000 pcio pin (counter clear input) figure 11.6 example of tcnt counter clearing toggle output synchronized with pwm period: in the operating modes, output can be toggled in synchronization with the pwm carrier period. when outputting the pwm period, the pcio pin function should be set to output with the pin function controller (pfc). an example of the toggle output waveform is shown in figure 11.7. pwm output is toggled according to the tcnt count direction. the toggle output pin is pcio. pcio outputs 1 when tcnt is counting up, and 0 when counting down. rev. 1.0, 08/99, page 456 of 875 tcnt tpdr 2td h'0000 pcio pin (toggle output) figure 11.7 example of toggle output waveform synchronized with pwm period a/d conversion start request setting: an a/d conversion start request can be made using a compare match between tcnt and tpdr or between tcnt and 2td. when a start request using a compare match between tcnt and tpdr is set, a/d conversion can be started in the middle of a pwm pulse (at the tcnt counter crest). when a start request using a compare match between tcnt and 2td is set, a/d conversion can be started at the edge of a pwm pulse (at the tcnt counter trough). a/d conversion start requests can be set by setting the ttge bit to 1 in the timer control register (tcnr). 11.3.3 output protection functions operating mode output has the following protection functions. halting pwm output by external signal the 6-phase pwm output pins can be placed in the high-impedance state automatically by inputting a specified external signal. there are four external signal input pins. for details, see section 11.7, port output enable (poe). halting pwm output when oscillation stops the 6-phase pwm output pins are placed in the high-impedance state automatically when stoppage of the clock input to the sh7065 is detected. however, pin states are not guaranteed when the clock is restarted. rev. 1.0, 08/99, page 457 of 875 11.4 interrupts 11.4.1 compare match interrupts when the tgfm (tgfn) flag is set to 1 in the timer status register (tsr) by a compare match between tcnt and the tpdr register (2td), if the setting of the tgiem (tgien) bit in the timer control register (tcnr) is 1 an interrupt is requested. the interrupt request is cleared by clearing the tgf flag to 0. 11.4.2 dma controller activation the on-chip dma controller can be activated by a compare match between tcnt and tpdr or between tcnt and 2td. 11.4.3 a/d converter activation the on-chip a/d converter can be activated by a compare match between tcnt and tpdr or between tcnt and 2td. when the tgf flag is set to 1 in the timer status register (tsr) by either of these compare matches, an a/d conversion start request is sent to the a/d converter. if the mmt start trigger has been selected on the a/d converter side, a/d conversion begins. 11.5 operation timing 11.5.1 input/output timing tcnt and tdcnt count timing: figure 11.8 shows the tcnt and tdcnt count timing. n C 3 n C 2 n C 1 n n + 1 n + 2 n + 3 n + 4 p f tcnt, tdcnt figure 11.8 tcnt and tdcnt count timing rev. 1.0, 08/99, page 458 of 875 tcnt counter clearing timing: figure 11.9 shows the timing of tcnt counter clearing by an external signal. n C 3 n C 2 n C 1 n n + 1 2td 2td + 1 2td + 2 td counter clear signal p f tcnt tddr figure 11.9 tcnt counter clearing timing tdcnt operation timing: figure 11.10 shows the tdcnt operation timing. h'0001 . . . . td C 1 td h'0000 h'0000 td cmo p f tdcnt tddr compare match signal dtg tdcnt clear signal figure 11.10 tdcnt operation timing rev. 1.0, 08/99, page 459 of 875 buffer operation timing: figure 11.11 shows the compare match buffer operation timing. m1 m2 m0 td p f tpbr tddr l0 + 2td l2 + 2td l1 + 2td tgruu, tgrvu, tgrwu l0 + td l2 + td l1 + td tgru, tgrv, tgrw l0 l2 l1 tgrud, tgrvd, tgrwd l1 l2 l0 tbru, tbrv, tbrw m1 + 2td m2 + 2td m0 + 2td tpdr compare match signal n C 1 . . . . n C 1 n 2td + 1 2td 2td + 1 2td + 2 tcnt figure 11.11 buffer operation timing rev. 1.0, 08/99, page 460 of 875 11.5.2 interrupt signal timing timing of tgf flag setting by compare match: figure 11.12 shows the timing of setting of the tgf flag in the timer status register (tsr) by a compare match between tcnt and tpdr, and the timing of the tgi interrupt request signal. the timing is the same for a compare match between tcnt and 2td. n compare match signal tgf flag tgi interrupt tpdr n C 3 n C 2 n C 1 n n + 1 n + 2 n + 3 n + 4 tcnt p f figure 11.12 tgi interrupt timing rev. 1.0, 08/99, page 461 of 875 status flag clearing timing: a status flag is cleared when the cpu reads 1 from the flag, then writes 0 to it. when the dma controller is activated, the flag is cleared automatically. figure 11.13 shows the timing of status flag clearing by the cpu, and figure 11.14 shows the timing of status flag clearing by the dma controller. tsr address p f address interrupt request signal status flag write signal t1 t2 tsr write cycle figure 11.13 timing of status flag clearing by cpu source address p f address interrupt request signal status flag destination address t1 t2 dmac read cycle t1 t2 dmac write cycle figure 11.14 timing of status flag clearing by dma controller rev. 1.0, 08/99, page 462 of 875 11.6 usage notes note that the kinds of operation and contention described below occur during mmt operation. contention between buffer register write and compare match: if a compare match occurs in the t2 state of a buffer register (tbru, tbrv, tbrw, or tpbr) write cycle, data is transferred from the buffer register to the compare register (tgr or tpdr) by means of a buffer operation. the data transferred is the buffer register write data. figure 11.15 shows the timing in this case. buffer register write data nm m p f address compare match signal interrupt request signal buffer register compare register write signal buffer register address t1 t2 buffer register write cycle figure 11.15 contention between buffer register write and compare match rev. 1.0, 08/99, page 463 of 875 contention between compare register write and compare match: if a compare match occurs in the t2 state of a compare register (tgr or tpdr) write cycle, the compare register write is not performed, and data is transferred from the buffer register (tbru, tbrv, tbrw, or tpbr) to the compare register (tgr or tpdr) by means of a buffer operation. figure 11.16 shows the timing in this case. n n p f address compare match signal interrupt request signal buffer register compare register write signal compare register address t1 t2 compare register write cycle figure 11.16 contention between compare register write and compare match rev. 1.0, 08/99, page 464 of 875 11.7 port output enable (poe) 11.7.1 overview the port output enable (poe) circuit enables the mmts 6-phase output pins (poua, poub, pova, povb, powa, and powb) to be placed in the high-impedance state by varying the input at pins poe0 to poe3 . an interrupt can also be requested at the same time. separately from this function, the mmts 6-phase output pins go to the high-impedance state when the oscillator halts. for details, see section 4, clock pulse generator (cpg) and power- down modes. features: the poe circuit has the following features: falling edge, p f /8 16 times, p f /16 16 times, or p f /128 16 times low-level sampling settings can be made for each of input pins poe0 to poe3 . the mmts 6-phase output pins can be placed in the high-impedance state on sampling of a falling edge or low level at pins poe0 to poe3 . an interrupt request can be initiated by input level sampling. block diagram: figure 11.17 shows a block diagram of the poe circuit. p f /8 poe3 poe2 poe1 poe0 p f /16 low level detection circuit frequency divider falling edge detection circuit icsr input level detection circuit p f /128 high impedance request control signal interrupt request p f figure 11.17 block diagram of poe rev. 1.0, 08/99, page 465 of 875 pin configuration: table 11.5 shows the pin configuration of the poe circuit. table 11.5 poe pins name abbreviation i/o function port output enable input pins poe0 C poe3 input input request signals for placing mmts 6-phase output pins in high-impedance state register configuration: the poe circuit has the single register summarized in table 11.6. the input level control/status register (icsr) controls detection of the input signals on pins poe0 to poe3 , and interrupt requests. table 11.6 poe register name abbre- viation r/w initial value address access size input level control/status register icsr r/(w) * h'0000 h'ffff 04e0 h'ffff 04e1 8, 16, 32 note: * bits 15 to 12 can only be written with 0, to clear the flags. rev. 1.0, 08/99, page 466 of 875 11.7.2 register description input level control/status register (icsr) the input level control/status register (icsr) is a 16-bit readable/writable register that selects the input mode for pins poe0 to poe3 , controls enabling or disabling of interrupts, and gives status indications. icsr is initialized to h'0000 by an external power-on reset, but is not initialized, and retains its prior data, in a wdt reset, in standby mode, and in sleep mode. bit: 15 14 13 12 11 10 9 8 poe3f poe2f poe1f poe0f pie initial value:00000000 r/w: r/(w) * r/(w) * r/(w) * r/(w) * r/w bit:76543210 poe3 m1 poe3 m0 poe2 m1 poe2 m0 poe1 m1 poe1 m0 poe0 m1 poe0 m0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w note: * only 0 can be written, for flag clearing. bit 15poe3 flag (poe3f): indicates that a high impedance request has been input to the poe3 pin. bit 15: poe3f description 0 [clearing condition] (initial value) when 0 is written to poe3f after reading poe3f = 1 1 [setting condition] when the input set by bits 7 and 6 of icsr occurs at the poe3 pin bit 14poe2 flag (poe2f): indicates that a high impedance request has been input to the poe2 pin. bit 14: poe2f description 0 [clearing condition] (initial value) when 0 is written to poe2f after reading poe2f = 1 1 [setting condition] when the input set by bits 5 and 4 of icsr occurs at the poe2 pin rev. 1.0, 08/99, page 467 of 875 bit 13poe1 flag (poe1f): indicates that a high impedance request has been input to the poe1 pin. bit 13: poe1f description 0 [clearing condition] (initial value) when 0 is written to poe1f after reading poe1f = 1 1 [setting condition] when the input set by bits 3 and 2 of icsr occurs at the poe1 pin bit 12poe0 flag (poe0f): indicates that a high impedance request has been input to the poe0 pin. bit 12: poe0f description 0 [clearing condition] (initial value) when 0 is written to poe0f after reading poe0f = 1 1 [setting condition] when the input set by bits 1 and 0 of icsr occurs at the poe0 pin bits 11 to 9reserved: these bits are always read as 0 and should only be written with 0. bit 8port interrupt enable (pie): enables or disables an interrupt request when 1 is set in any of bits poe0f to poe3f in icsr. bit 8: pie description 0 interrupt request disabled (initial value) 1 interrupt request enabled rev. 1.0, 08/99, page 468 of 875 bits 7 and 6poe3 mode 1 and 0 (poe3m1, poe3m0): these bits select the input mode of the poe3 pin. bit 7: poe3m1 bit 6: poe3m0 description 0 0 request accepted at falling edge of poe3 input (initial value) 1 poe3 input is sampled for low level 16 times every p f /8 clock, and request is accepted when all samples are low level 10 poe3 input is sampled for low level 16 times every p f /16 clock, and request is accepted when all samples are low level 1 poe3 input is sampled for low level 16 times every p f /128 clock, and request is accepted when all samples are low level bits 5 and 4poe2 mode 1 and 0 (poe2m1, poe2m0): these bits select the input mode of the poe2 pin. bit 5: poe2m1 bit 4: poe2m0 description 0 0 request accepted at falling edge of poe2 input (initial value) 1 poe2 input is sampled for low level 16 times every p f /8 clock, and request is accepted when all samples are low level 10 poe2 input is sampled for low level 16 times every p f /16 clock, and request is accepted when all samples are low level 1 poe2 input is sampled for low level 16 times every p f /128 clock, and request is accepted when all samples are low level rev. 1.0, 08/99, page 469 of 875 bits 3 and 2poe1 mode 1 and 0 (poe1m1, poe1m0): these bits select the input mode of the poe1 pin. bit 3: poe1m1 bit 2: poe1m0 description 0 0 request accepted at falling edge of poe1 input (initial value) 1 poe1 input is sampled for low level 16 times every p f /8 clock, and request is accepted when all samples are low level 10 poe1 input is sampled for low level 16 times every p f /16 clock, and request is accepted when all samples are low level 1 poe1 input is sampled for low level 16 times every p f /128 clock, and request is accepted when all samples are low level bits 1 and 0poe0 mode 1 and 0 (poe0m1, poe0m0): these bits select the input mode of the poe0 pin. bit 1: poe0m1 bit 0: poe0m0 description 0 0 request accepted at falling edge of poe0 input (initial value) 1 poe0 input is sampled for low level 16 times every p f /8 clock, and request is accepted when all samples are low level 10 poe0 input is sampled for low level 16 times every p f /16 clock, and request is accepted when all samples are low level 1 poe0 input is sampled for low level 16 times every p f /128 clock, and request is accepted when all samples are low level rev. 1.0, 08/99, page 470 of 875 11.7.3 operation input level detection: when the input condition set in icsr occurs on any one of the poe pins, the mmts 6-phase output pins go to the high-impedance state. 1. pins placed in high-impedance state the 12 pins pd26/d26/pwob, pd25/d25/pvob, pd24/d24/puob, pd22/d22/pwoa/sck0, pd21/d21/pvoa/ irq7 , pd20/d20/puoa/ irq6 , pe23/ irq7 /pwob, pe22/ irq6 /pvob, pe21/ irq5 /puob, pe19/ irq3 /pwoa, pe18/ irq2 /pvoa, and pe17/ irq1 /puoa/sck0 are placed in the high-impedance state. 2. falling edge detection when a transition from high- to low-level input occurs on a poe pin. 3. low level detection figure 11.18 shows the low level detection operation. low level sampling is performed 16 times in succession using the sampling clock set in icsr. the input is not accepted if a high level is detected even once among these samples. the timing of entry of the mmts 6-phase output pins into the high-impedance state from the sampling clock is the same for falling edge detection and low level detection. p f 8, 16, or 128 clocks sampling clock poe input puoa all samples low-level at least one high-level sample [1] [1] [2] [2] [3] [16] high-impedance state flag set (poe accepted) flag not set [13] note: the other mmt 6-phase output pins also go to the high-impedance state at the same timing. figure 11.18 low level detection operation exiting high-impedance state: mmt 6-phase output pins that have entered the high-impedance state as the result of input level detection are released from this state by restoring them to their initial states by means of a power-on reset, or by clearing all the poe flags in icsr (poe0f to poe3f: bits 12 to 15). rev. 1.0, 08/99, page 471 of 875 section 12 compare match timer (cmt) 12.1 overview the sh7065 has an on-chip compare match timer (cmt) consisting of a two-channel 16-bit timer. the cmt has a 16-bit counter, and can generate interrupts at set intervals. 12.1.1 features the cmt has the following features: choice of four counter input clocks any of four internal clocks (p f /8, p f /32, p f /128, p f /512) can be selected independently for each channel (where p f is the clock input to the cmt). the cmts input clock is obtained by frequency division of an external clock. interrupt sources a compare match interrupt can be requested independently for each channel. rev. 1.0, 08/99, page 472 of 875 12.1.2 block diagram figure 12.1 shows a block diagram of the cmt. cmstr cmcsr0 cmcor0 cmcnt0 cmcsr1 cmcor1 cmcnt1 channel 0 channel 1 bus interface module bus clock selection control circuit clock selection control circuit cmi0 p f /32 p f /512 p f /8 p f /128 p f /32 p f /512 p f /8 p f /128 cmi1 cmt internal bus comparator cmstr: compare match timer start register cmcsr: compare match timer control/status register cmcor: compare match timer constant register cmcnt: compare match timer counter cmi: compare match interrupt comparator figure 12.1 block diagram of cmt rev. 1.0, 08/99, page 473 of 875 12.1.3 register configuration table 12.1 summarizes the cmt registers. table 12.1 cmt registers channel name abbre- viation r/w initial value address access size both compare match timer start register cmstr r/w h'0000 h'ffff04c0 8, 16, 32 0 compare match timer control/status register 0 cmcsr0 r/(w) * h'0000 h'ffff04c2 8, 16, 32 compare match timer counter 0 cmcnt0 r/w h'0000 h'ffff04c4 8, 16, 32 compare match timer constant register 0 cmcor0 r/w h'ffff h'ffff04c6 8, 16, 32 1 compare match timer control/status register 1 cmcsr1 r/(w) * h'0000 h'ffff04c8 8, 16, 32 compare match timer counter 1 cmcnt1 r/w h'0000 h'ffff04ca 8, 16, 32 compare match timer constant register 1 cmcor1 r/w h'ffff h'ffff04cc 8, 16, 32 note: * the cmf bit in cmcsr0 and cmcsr1 can only be written with 0, to clear the flag. rev. 1.0, 08/99, page 474 of 875 12.2 register descriptions 12.2.1 compare match timer start register (cmstr) the compare match timer start register (cmstr) is a 16-bit register that specifies operation or stoppage of the counters (cmcnt) in channels 0 and 1. cmstr is initialized by a power-on reset, and in hardware standby mode and software standby mode. it is not initialized in module standby mode. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w: bit:76543210 str1str0 initial value:00000000 r/w:r/wr/w bits 15 to 2reserved: these bits are always read as 0 and cannot be modified. bit 1count start 1 (str1): selects operation or stoppage of compare match timer counter 1. bit 1: str1 description 0 cmcnt1 count operation is stopped (initial value) 1 cmcnt1 performs count operation bit 0count start 0 (str0): selects operation or stoppage of compare match timer counter 0. bit 0: str0 description 0 cmcnt0 count operation is stopped (initial value) 1 cmcnt0 performs count operation rev. 1.0, 08/99, page 475 of 875 12.2.2 compare match timer control/status registers 0 and 1 (cmcsr0, cmcsr1) the compare match timer control/status registers (cmcsr0, cmcsr1) are 16-bit registers that indicate compare match occurrence, enable or disable interrupts, and select the clock to be used for the up-count. the cmcsr registers are initialized by a power-on reset, and in hardware standby mode and software standby mode. they are not initialized in module standby mode. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w: bit:76543210 cmfcmiecks1cks0 initial value:00000000 r/w: r/(w) * r/wr/wr/w note: * only 0 can be written, to clear the flag. bits 15 to 8reserved: these bits are always read as 0 and cannot be modified. bit 7compare match flag (cmf): indicates a match between the values of cmcnt and cmcor. bit 7: cmf description 0 cmcnt and cmcor values do not match (initial value) [clearing condition] when 0 is written to cmf after reading cmf = 1 1 cmcnt and cmcor values match bit 6compare match interrupt enable (cmie): enables or disables generation of a compare match interrupt (cmti) when the cmcnt and cmcor values match (cmf = 1). bit 6: cmie description 0 compare match interrupt (cmi) is disabled (initial value) 1 compare match interrupt (cmi) is enabled rev. 1.0, 08/99, page 476 of 875 bits 5 to 2reserved: these bits are always read as 0 and cannot be modified. bits 1 and 0clock select 1 and 0 (cks1, cks0): these bits select the clock to be input to cmcnt from four internal clocks obtained by frequency division of p f . when the str bit is set to 1 in cmstr, cmcnt starts counting up on the clock selected by cks1 and cks0. bit 1: cks1 bit 0: cks0 description 00p f /8 (initial value) 1p f /32 10p f /128 1p f /512 12.2.3 compare match counters 0 and 1 (cmcnt0, cmcnt1) the compare match counters (cmcnt0, cmcnt1) are 16-bit registers used as up-counters to generate interrupt requests. when an internal clock is selected with bits cks1 and cks0 in cmcsr, cmcnt starts counting up on that clock. when the cmcnt value matches the value in the compare match constant register (cmcor), cmcnt is cleared to h'0000 and the cmf flag is set to 1 in cmcsr. if the setting of the cmie bit in cmcsr is 1 at this time, a compare match interrupt (cmi0 or cmi1) is requested. the cmcnt registers are initialized by a power-on reset, and in hardware standby mode and software standby mode. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w rev. 1.0, 08/99, page 477 of 875 12.2.4 compare match constant registers 0 and 1 (cmcor0, cmcor1) the compare match constant registers (cmcor0, cmcor1) are 16-bit registers that set the compare match cycle. the cmcor registers are initialized by a power-on reset, and in hardware standby mode and software standby mode. bit: 15 14 13 12 11 10 9 8 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 12.3 operation 12.3.1 cyclic count operation when an internal clock is selected with bits cks1 and cks0 in cmcsr, and the str bit is set to 1 in cmstr, cmcnt starts counting up on that clock. when the cmcnt value matches the value in the compare match constant register (cmcor), cmcnt is cleared to h'0000 and the cmf flag is set to 1 in cmcsr. if the setting of the cmie bit in cmcsr is 1 at this time, a compare match interrupt (cmt1) is requested. cmcnt then starts counting up from h'0000 again. figure 12.2 shows the operation of the compare match counter. counter cleared by cmcor compare match cmcnt value cmcor h'0000 time figure 12.2 counter operation rev. 1.0, 08/99, page 478 of 875 12.3.2 cmcnt count timing one of four clocks (p f /8, p f /32, p f /128, or p f /512) scaled from p f can be selected with bits cks1 and cks0 in cmcsr. figure 12.3 shows the count timing. n n + 1 n C 1 p f internal clock cmcnt input clock cmcnt figure 12.3 count timing rev. 1.0, 08/99, page 479 of 875 12.4 interrupts 12.4.1 interrupt sources the cmt has a compare match interrupt for each channel, each assigned a different vector address. when interrupt request flag cmf is set to 1, and of interrupt enable bit cmie is also 1, the corresponding interrupt request is output. when a cpu interrupt is initiated by an interrupt request, the relative channel priorities can be changed by means of an interrupt controller setting. for details, see section 6, interrupt controller (intc). 12.4.2 timing of compare match flag setting the cmf bit is cmcsr is set to 1 by a compare match signal generated when the cmcor and cmcnt values match. the compare match signal is generated in the last state in which the match is true (when the value at which the cmcnt match occurred is about to be updated). therefore, after a match between cmcnt and cmcor, the compare match signal is not generated until the next cmcnt counter input clock pulse. figure 12.4 shows the timing of cmf bit setting. 0 n n p f cmcnt input clock cmcnt cmcor compare match signal cmf cmi0, 1 figure 12.4 timing of cmf setting rev. 1.0, 08/99, page 480 of 875 12.4.3 timing of compare match flag clearing the cmf bit in cmcsr is cleared by reading the bit when it is set to 1, then writing 0 to it . figure 12.5 shows the timing of cmf bit clearing. p f cmf t1 t2 cmcsr write cycle figure 12.5 timing of cmf clearing 12.5 usage notes note that the kinds of operation and contention described below occur during cmt operation. contention between cmcnt write and compare match: if a compare match occurs in the t2 state of a cmcnt write cycle, the cmcnt clearing takes precedence and the write to cmcnt is not performed. figure 12.6 shows the timing in this case. p f address internal write signal counter clear signal cmcnt t1 cmcnt n h'0000 t2 cmcnt write cycle figure 12.6 contention between cmcnt write and compare match rev. 1.0, 08/99, page 481 of 875 contention between cmcnt word write and increment: if an increment pulse occurs in the t2 state of a cmcnt word write cycle, the counter write takes precedence and counter is not incremented. figure 12.7 shows the timing in this case. p f address internal write signal cmcnt input clock cmcnt t1 cmcnt nm cmcnt write data t2 cmcnt write cycle figure 12.7 contention between cmcnt word write and increment rev. 1.0, 08/99, page 482 of 875 contention between cmcnt byte write and increment: if an increment pulse occurs in the t2 state of a cmcnt byte write cycle, the counter write takes precedence and the byte data for which the write was performed is not incremented. the byte data for which a write was not performed is not incremented either, and retains its previous value. figure 12.8 shows the timing when an increment pulse occurs in the t2 state of a cmcnth write cycle. p f address internal write signal cmcnt input clock cmcnth t1 cmcnth nm cmcnth write data t2 cmcnt write cycle cmcntl xx figure 12.8 contention between cmcnt byte write and increment rev. 1.0, 08/99, page 485 of 875 section 13 watchdog timer 13.1 overview the sh7065 has a single-channel on-chip watchdog timer (wdt) for monitoring system operation. the wdt outputs an overflow signal ( wdtovf ) externally if a system crash prevents the cpu from writing to the timer counter, allowing it to overflow. at the same time, the wdt can also generate an internal reset signal for the sh7065. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is requested each time the counter overflows. the wdt is also in exiting software standby mode. 13.1.1 features the wdt has the following features: switchable between watchdog timer mode and interval timer mode wdtovf output when in watchdog timer mode if the counter overflows, the wdt outputs wdtovf externally. it is possible to select whether or not the sh7065 is reset internally at the same time. interrupt generation when in interval timer mode if the counter overflows, the wdt generates an interval timer interrupt. used when exiting software standby mode choice of eight counter input clocks rev. 1.0, 08/99, page 486 of 875 13.1.2 block diagram figure 13.1 shows a block diagram of the wdt. interrupt control internal bus bus interface tcnt tcsr rstcsr reset control overflow clock standby control standby release internal reset request interrupt request clock selector frequency divider standby mode clock selection m f wdt tcsr: timer control/status register tcnt: timer counter rstcsr: reset control/status register m f : clock further scaled from the fastest master clock by means of the module clock control register (see section 4, clock pulse generator (cpg ) and power-down modes). figure 13.1 block diagram of wdt rev. 1.0, 08/99, page 487 of 875 13.1.3 pin configuration table 13.1 shows details of the wdt output pin. table 13.1 wdt pin name abbreviation i/o function watchdog timer overflow wdtovf output outputs counter overflow signal in watchdog timer mode 13.1.4 register configuration the wdt has the three registers shown in table 13.2. these registers control clock selection, wdt mode switching, and the reset signal. table 13.2 wdt registers address name abbre- viation r/w initial value write * 1 read * 2 timer control/status register tcsr r/(w) * 3 h'18 h'ffff 1000 h'ffff 1000 timer counter tcnt r/w h'00 h'ffff 1000 h'ffff 1001 reset control/status register rstcsr r/(w) * 3 h'1f h'ffff 1002 h'ffff 1003 notes: 1. use word writes; byte and longword writes cannot be used. 2. use byte reads; a word or longword read will not return the correct value. 3. only 0 can be written to bit 7, to clear the flag. rev. 1.0, 08/99, page 488 of 875 13.2 register descriptions 13.2.1 timer counter (tcnt) bit:76543210 tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the timer counter (tcnt) is an 8-bit readable/writable up-counter. when the timer enable bit (tme) bit is set to 1 in the timer control/status register (tcsr), tcnt starts counting up on the internal clock selected with bits cks2 to cks0 in tcsr. when the count overflows (changes from h'ff to h'00), either the watchdog timer overflow signal ( wdtovf ) or an interval timer interrupt (iti) is generated, depending on the mode selected with the wt/ it bit in tcsr. tcnt is initialized to h'00 by a power-on reset, or when the tme bit is cleared to 0. it is not initialized in standby mode. note: the method of writing to tcnt is different from that for general registers to prevent inadvertent overwriting. for details see section 13.2.4, notes on register access. 13.2.2 timer control/status register (tcsr) bit:76543210 ovf wt/ it tme cks2 cks1 cks0 initial value:00011000 r/w: r/(w) * r/w r/w r r r/w r/w r/w note: * only 0 can be written to bit 7, to clear the flag. the timer control/status register (tcsr) is an 8-bit readable/writable register whose functions include selecting the clock source to be input to the timer counter (tcnt), and the timer mode. bits 7 to 5 are initialized to 000 by a power-on reset and in standby mode. bits 2 to 0 are initialized to 000 by a power-on reset, but are not initialized in standby mode. note: the method of writing to tcsr is different from that for general registers to prevent inadvertent overwriting. for details see section 13.2.4, notes on register access. rev. 1.0, 08/99, page 489 of 875 bit 7overflow flag (ovf): indicates that tcnt has overflowed from h'ff to h'00 when in interval timer mode. this flag is not set in watchdog timer (wdt) mode. bit 7: ovf description 0 no tcnt overflow in interval timer mode (initial value) 1 tcnt overflow has occurred in interval timer mode [clearing condition] cleared by reading ovf, then writing 0 to ovf bit 6timer mode select (wt/ it it it it ): selects whether the wdt is used as a watchdog timer or interval timer. if used as an interval timer, the wdt generates an interval timer interrupt request (iti) when tcnt overflows. if used as a watchdog timer, the wdt generates the wdtovf signal when tcnt overflows. bit 6: wt/ it it it it description 0 interval timer mode: interval timer interrupt (iti) request is sent to cpu when tcnt overflows (initial value) 1 watchdog timer mode: wdtovf signal is output externally when tcnt overflows note: for details of what happens when tcnt overflows during watchdog timer operation, see section 13.2.3, reset control/status register (rstcsr). bit 5timer enable (tme): selects whether the timer runs or is halted. bit 5: tme description 0 timer disable: tcnt is initialized to h'00 and halted (initial value) 1 timer enable: tcnt counts up bits 4 and 3reserved: these bits are always read as 1 and should only be written with 1. rev. 1.0, 08/99, page 490 of 875 bits 2 to 0clock select 2 to 0 (cks2 to cks0): these bits select one of eight clocks, obtained by dividing the m f clock, for input to tcnt. description bit 2: cks2 bit 1: cks1 bit 0: cks0 clock division ratio overflow period (when m f f f f = 60 mhz) 0 0 0 1/2 (initial value) 8.5 m s 1 1/4 17.1 m s 1 0 1/8 34.1 m s 1 1/32 136.5 m s 1 0 0 1/256 1.1 ms 1 1/1024 4.4 ms 1 0 1/2048 8.7 ms 1 1/4096 17.5 ms note: the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. m f is a clock further scaled from the master clock by means of the module clock control register. for details see section 4, clock pulse generator (cpg) and power-down modes. 13.2.3 reset control/status register (rstcsr) bit:76543210 wovfrste initial value:00011111 r/w: r/(w) * r/wrrrrrr note: * only 0 can be written to bit 7, to clear the flag. the reset control/status register (rstcsr) is an 8-bit readable/writable register that controls generation of the internal reset signal when the timer counter (tcnt) overflows. rstcsr is initialized to h'1f by a reset signal from the res pin, but is not initialized by the internal reset signal caused by wdt overflow. it is also initialized to h'1f in standby mode. note: the method of writing to rstcsr is different from that for general registers to prevent inadvertent overwriting. for details see section 13.2.4, notes on register access. rev. 1.0, 08/99, page 491 of 875 bit 7watchdog overflow flag (wovf): indicates that tcnt has overflowed (changed from h'ff to h'00) in watchdog timer mode. this bit is not set in interval timer mode. bit 7: wovf description 0 no tcnt overflow in watchdog timer mode (initial value) 1 tcnt overflow has occurred in watchdog timer mode [clearing condition] cleared by reading wovf, then writing 0 to wovf bit 6reset enable (rste): specifies whether or not a reset signal is to be generated in the sh7065 if tcnt overflows in watchdog timer mode. bit 6: rste description 0 internal reset is not performed if tcnt overflows (initial value) 1 internal reset is performed if tcnt overflows note: the modules in the sh7065 are not reset, but tcnt and tcsr within the wdt are reset. bit 5reserved: this bit is always read as 0 and should only be written with 0. bits 4 to 0reserved: these bits are always read as 1 and should only be written with 1. 13.2.4 notes on register access the method of writing to the watchdog timers timer counter (tcnt), timer control/status register (tcsr), and reset control/status register (rstcsr) differs from that for other registers to prevent inadvertent overwriting. the procedures for writing to and reading these registers are given below. writing to tcnt and tcsr: a word transfer instruction must be used to write to tcnt and tcsr. they cannot be written to with a byte transfer instruction. figure 13.2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. for a write to tcnt, the upper byte of the written word must contain h'5a and the lower byte must contain the write data. for a write to tcsr, the upper byte of the written word must contain h'a5 and the lower byte must contain the write data. this transfers the write data from the lower byte to tcnt or tcsr. rev. 1.0, 08/99, page 492 of 875 h'5a 15 tcnt write address: h'ffff 1000 tcsr write address: h'ffff 1000 8 7 0 write data h'a5 15 8 7 0 write data figure 13.2 writing to tcnt and tcsr writing to rstcsr: to write to rstcsr, a word transfer must be made to address h'ffff1002. rstcsr cannot be written to with a byte transfer instruction. figure 13.3 shows the format of data written to rstcsr. the method of writing 0 to the wovf bit (bit 7) differs from that for writing to the rste bit (bit 6). to write 0 to the wovf bit, the write data must have h'a5 in the upper byte and h'00 in the lower byte. this clears the wovf bit to 0, but has no effect on the rste bit. to write to the rste bit, the upper byte must contain h'5a and the lower byte must contain the write data. this writes the value in bit 6 of the lower byte into the rste bit, but has no effect on the wovf bit. h'a5 15 writing 0 to wovf bit address: h'ffff 1002 writing to rste bit address: h'ffff 1002 8 7 0 write data h'5a 15 8 7 0 write data figure 13.3 writing to rstcsr reading tcnt, tcsr, and rstcsr: these registers are read in the same way as other registers. the read addresses are h'ffff1000 for tcsr, h'ffff1001 for tcnt, and h'ffff1003 for rstcsr. byte transfer instructions must be used to read these registers. rev. 1.0, 08/99, page 493 of 875 13.3 operation 13.3.1 operation in watchdog timer mode figure 13.4 illustrates wdt operation in watchdog timer mode. to use the wdt as a watchdog timer, set the wt/ it and tme bits to 1 in the timer control/status register (tcsr). software must prevent tcnt overflows by rewriting the tcnt value (normally be writing h'00) before overflows occurs. this ensures that tcnt does not overflow while the system is operating normally. if tcnt overflows without being rewritten because of a system crash or other error, the wdtovf signal is output. this wdtovf signal can be used to reset the system. the wdtovf signal is output for 128 (wdt) clock cycles. this (wdt) clock is a clock further scaled from the internal clock by means of the module clock control register (see section 4, clock pulse generator (cpg) and power-down modes). if tcnt overflows when 1 is set in the rste bit in the reset control/status register (rstcsr), a signal that resets the sh7065 internally is generated at the same time as the wdtovf signal. the internal reset signal is output for 512 (wdt) clock cycles. if a reset caused by a signal input to the res pin occurs at the same time as a reset caused by a wdt overflow, the res pin reset has priority and the wovf bit in rstcsr is cleared to 0. the following registers are not initialized by the wdt reset signal: (1) the mmts poe (port output enable) function registers, (2) pin function controller (pfc) registers, (3) i/o port registers. these registers are initialized only by a power-on reset from off-chip. rev. 1.0, 08/99, page 494 of 875 wt/ = 1 tme = 1 h'ff h'00 tcnt value overflow wovf = 1 and internal reset are generated h'00 written to tcnt wt/ = 1 tme = 1 h'00 written to tcnt time 128 (wdt) clocks 512 (wdt) clocks signal internal reset signal* wt/ : timer mode select bit tme: timer enable bit note: * the internal reset signal is generated only if the rste bit is set to 1. figure 13.4 operation in watchdog timer mode rev. 1.0, 08/99, page 495 of 875 13.3.2 operation in interval timer mode figure 13.5 illustrates wdt operation in interval timer mode. to use the wdt as an interval timer, clear the wt/ it bit in tcsr to 0 and set the tme bit to 1. when the wdt is operating as an interval timer, an interval timer interrupt (iti) is generated each time tcnt overflows. this function can be used to generate interrupt requests at regular intervals. wt/ = 0 tme = 1 h'ff h'00 tcnt value iti: interval timer interrupt request generation overflow overflow overflow overflow iti iti iti iti time figure 13.5 operation in interval timer mode 13.3.3 operation when clearing software standby mode the wdt is used when software standby mode is cleared by an nmi interrupt. when software standby mode is used, the wdt should be set as described in 1 below. 1. settings before transition to software standby mode before making a transition to software standby mode, the wdt must be halted by clearing the tme bit to 0 in the timer control/status register (tcsr). a transition to software standby mode cannot be made while the tme bit is set to 1. also set bits cks2 to cks0 in tcsr so that the timer counter (tcnt) overflow period is at least as long as the oscillation settling time (see section 22.3, ac characteristics). 2. operation when software standby mode is cleared when an nmi interrupt is generated in software standby mode, the oscillator starts operating and tcnt begins counting up on the clock selected with bits cks2 to cks0 prior to the transition to software standby mode. when tcnt overflows (from h'ff to h'00), the clock is judged to be stable and ready for use, and clocks are supplied throughout the chip. this clears software standby mode. rev. 1.0, 08/99, page 497 of 875 section 14 serial communication interface (sci) 14.1 overview the sh7065 is equipped with a three-channel serial communication interface with built-in fifo buffers (sci: sci with fifo). the sci can handle both asynchronous and synchronous serial communication. a function is also provided for serial communication between processors (multiprocessor communication function). an on-chip infrared data association (irda) interface based on the irda 1.0 system is also provided, enabling infrared communication. sixteen-stage fifo registers are provided for both transmission and reception, enabling fast, efficient, and continuous communication. 14.1.1 features the sci has the following features: choice of synchronous or asynchronous serial communication mode ? asynchronous mode serial data communication is executed using an asynchronous system in which synchronization is achieved character by character. serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia). a multiprocessor communication function is also provided that enables serial data communication with a number of processors. there is a choice of 12 serial data transfer formats. data length: 7 or 8 bits stop bit length: 1 or 2 bits parity: even/odd/none multiprocessor bit: 1 or 0 receive error detection: parity, overrun, and framing errors auto break detection: a break can be detected automatically. ? synchronous mode serial data communication is synchronized with a clock. serial data communication can be carried out with other chips that have a synchronous communication function. there is a single serial data transfer format. data length: 8 bits receive error detection: overrun errors rev. 1.0, 08/99, page 498 of 875 irda 1.0 compliance full-duplex communication capability the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. in addition, the transmitter and receiver both have a 16-stage fifo buffer structure, enabling continuous serial data transmission and reception. (however, irda communication is carried out in half-duplex mode.) built-in baud rate generator allows any bit rate to be selected. choice of serial clock source: internal clock from baud rate generator or external clock from sck pin four interrupt sources there are four interrupt sourcestransmit-fifo-data-empty, transmit-end, receive-fifo-data- full, and receive-errorthat can issue requests independently. the transmit-fifo-data-empty and receive-fifo-data-full interrupts can activate the on-chip dmac to execute data transfer when not in use, the sci can be stopped by halting its clock supply to reduce power consumption. choice of lsb-first or msb-first mode in asynchronous mode, operation can be selected on a base clock of 4, 8, or 16 times the bit rate. rev. 1.0, 08/99, page 499 of 875 14.1.2 block diagrams a block diagram of the sci is shown in figure 14.1, and a diagram of the irda block in figure 14.2. module data bus scfrdr (16-stage) scftdr (16-stage) scrsr rxd txd sck sctsr scfdr scfcr sc1ssr sc2ssr scscr scsmr scfer scimr scbrr parity generation parity check transmission/ reception control baud rate generator clock external clock p f p f /4 p f /16 p f /64 tei irda/sci switchover (to irda block) txi rxi eri sci scrsr: receive shift register scfrdr: receive fifo data register sctsr: transmit shift register scftdr: transmit fifo data register scsmr: serial mode register scscr: serial control register bus interface internal data bus sc1ssr: serial status 1 register sc2ssr: serial status 2 register scbrr: bit rate register scfcr: fifo control register scfdr: fifo data count register scfer: fifo error register scimr: irda mode register figure 14.1 block diagram of sci rev. 1.0, 08/99, page 500 of 875 sci irda/sci switchover sck irda txd txd rxd rxd demodulation unit modulation unit clock input transmit clock figure 14.2 diagram of irda block 14.1.3 pin configuration the sci has the serial pins shown in table 14.1 for each channel. table 14.1 sci pins channel name abbreviation i/o function 0C2 serial clock pin sck0C2 i/o clock input/output receive data pin rxd0C2 input receive data input transmit data pin txd0C2 output transmit data output 14.1.4 register configuration the sci has the internal registers shown in table 14.2. these registers are used to specify asynchronous mode/synchronous mode and the irda communication mode, the data format and the bit rate, and to perform transmitter/receiver control. rev. 1.0, 08/99, page 501 of 875 table 14.2 sci registers channel name abbre- viation r/w initial value address access size 0 serial mode register scsmr0 r/w h'00 h'ffff0500 8 bit rate register scbrr0 r/w h'ff h'ffff0502 8 serial control register scscr0 r/w h'00 h'ffff0504 8 transmit fifo data register scftdr0 w h'ffff0506 8 serial status 1 register sc1ssr0 r/(w) * h'84 h'ffff0508 16 serial status 2 register sc2ssr0 r/(w) * h'20 h'ffff050a 8 receive fifo data register scfrdr0 r undefined h'ffff050c 8 fifo control register scfcr0 r/w h'00 h'ffff050e 8 fifo data count register scfdr0 r h'00 h'ffff0510 16 fifo error register scfer0 r h'00 h'ffff0512 16 irda mode register scimr0 r/w h'00 h'ffff0514 8 1 serial mode register scsmr1 r/w h'00 h'ffff0520 8 bit rate register scbrr1 r/w h'ff h'ffff0522 8 serial control register scscr1 r/w h'00 h'ffff0524 8 transmit fifo data register scftdr1 w h'ffff0526 8 serial status 1 register sc1ssr1 r/(w) * h'84 h'ffff0528 16 serial status 2 register sc2ssr1 r/(w) * h'20 h'ffff052a 8 receive fifo data register scfrdr1 r undefined h'ffff052c 8 fifo control register scfcr1 r/w h'00 h'ffff052e 8 fifo data count register scfdr1 r h'00 h'ffff0530 16 fifo error register scfer1 r h'00 h'ffff0532 16 irda mode register scimr1 r/w h'00 h'ffff0534 8 2 serial mode register scsmr2 r/w h'00 h'ffff0540 8 bit rate register scbrr2 r/w h'ff h'ffff0542 8 serial control register scscr2 r/w h'00 h'ffff0544 8 transmit fifo data register scftdr2 w h'ffff0546 8 serial status 1 register sc1ssr2 r/(w) * h'84 h'ffff0548 16 serial status 2 register sc2ssr2 r/(w) * h'20 h'ffff054a 8 receive fifo data register scfrdr2 r undefined h'ffff054c 8 fifo control register scfcr2 r/w h'00 h'ffff054e 8 fifo data count register scfdr2 r h'00 h'ffff0550 16 fifo error register scfer2 r h'00 h'ffff0552 16 irda mode register scimr2 r/w h'00 h'ffff0554 8 rev. 1.0, 08/99, page 502 of 875 note: * only 0 can be written, to clear flags. use byte access on registers with an access size of 8, and word access on registers with an access size of 16. 14.2 register descriptions with the exception of the irda mode register (scimr) and bits 6 to 3 (ick3 to ick0) of the serial mode register (scsmr), irda communication mode settings are the same as for asynchronous mode. 14.2.1 receive shift register (scrsr) bit:76543210 r/w: the receive shift register (scrsr) is the register used to receive serial data. the sci sets serial data input from the rxd pin in scrsr in the order received, starting with the lsb (bit 0) or msb (bit 7), and converts it to parallel data. when one byte of data has been received, it is transferred to the receive fifo data register, scfrdr, automatically. scrsr cannot be read or written to directly. 14.2.2 receive fifo data register (scfrdr) bit:76543210 r/w:rrrrrrrr the receive fifo data register (scfrdr) is a 16-stage fifo register (8 bits per stage) that stores received serial data. when the sci has received one byte of serial data, it transfers the received data from scrsr to scfrdr where it is stored, and completes the receive operation. scrsr is then enabled for reception, and consecutive receive operations can be performed until the receive fifo data register is full (16 data bytes). scfrdr is a read-only register, and cannot be written to. if a read is performed when there is no receive data in the receive fifo data register, an undefined value will be returned. when the receive fifo data register is full of receive data, subsequent receive data is lost. rev. 1.0, 08/99, page 503 of 875 14.2.3 transmit shift register (sctsr) bit:76543210 r/w: the transmit shift register (sctsr) is the register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from scftdr to sctsr, then sends the data to the txd pin starting with the lsb (bit 0) or msb (bit 7). when transmission of one byte is completed, the next transmit data is transferred from scftdr to sctsr, and transmission started, automatically. sctsr cannot be read or written to directly. 14.2.4 transmit fifo data register (scftdr) bit:76543210 r/w:wwwwwwww the transmit fifo data register (scftdr) is a 16-stage fifo register (8 bits per stage) that stores data for serial transmission. if sctsr is empty when transmit data has been written to scftdr, the sci transfers the transmit data written in scftdr to sctsr and starts serial transmission. scftdr is a write-only register, and cannot be read. the next data cannot be written when scftdr is filled with 16 bytes of transmit data. data written in this case is ignored. rev. 1.0, 08/99, page 504 of 875 14.2.5 serial mode register (scsmr) bit:76543210 c/ a chr/ ick3 pe/ick2 o/ e /ick1 stop/ ick0 mp cks1 cks0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the serial mode register (scsmr) is an 8-bit register used to set the scis serial transfer format and select the baud rate generator clock source. in irda communication mode, it is used to select the output pulse width. scsmr can be read or written to by the cpu at all times. scsmr is initialized to h'00 by a reset, by the module standby function, and in standby mode. bit 7communication mode (c/ a a a a ): selects asynchronous mode or synchronous mode as the sci operating mode. in irda communication mode, this bit must be cleared to 0. bit 7: c/ a a a a description 0 asynchronous mode (initial value) 1 synchronous mode bit 6character length (chr)/irda clock select 3 (ick3): selects 7 or 8 bits as the data length in asynchronous mode. in synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting, bit 6: chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of the transmit fifo data register (scftdr) is not transmitted. in irda communication mode, bit 6 is the irda clock select 3 (ick3) bit, enabling appropriate clock pulses to be generated according to its setting. see, pulse width selection, in section 14.3.6, operation in irda mode, for details. rev. 1.0, 08/99, page 505 of 875 bit 5parity enable (pe)/irda clock select 2 (ick2): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in synchronous mode, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5: pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. in irda communication mode, bit 5 is the irda clock select 2 (ick2) bit, enabling appropriate clock pulses to be generated according to its setting. see, pulse width selection, in section 14.3.6, operation in irda mode, for details. bit 4parity mode (o/ e e e e )/irda clock select 1 (ick1): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is invalid in synchronous mode, and when parity addition and checking is disabled in asynchronous mode. bit 4: o/ e e e e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1-bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1-bits in the receive character plus the parity bit is odd. in irda communication mode, bit 4 is the irda clock select 1 (ick1) bit, enabling appropriate clock pulses to be generated according to its setting. see, pulse width selection, in section 14.3.6, operation in irda mode, for details. rev. 1.0, 08/99, page 506 of 875 bit 3stop bit length (stop)/irda clock select 0 (ick0): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bit setting is only valid in asynchronous mode. if synchronous mode is set, the stop bit setting is invalid since stop bits are not added. bit 3: stop description 01 stop bit * 1 (initial value) 1 2 stop bits * 2 notes: 1. in transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. 2. in transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. in irda communication mode, bit 3 is the irda clock select 0 (ick0) bit, enabling appropriate clock pulses to be generated according to its setting. see, pulse width selection, in section 14.3.6, operation in irda mode, for details. bit 2multiprocessor mode (mp): selects a multiprocessor format. when a multiprocessor format is selected, the pe bit and o/ e bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in synchronous mode and irda mode. for details of the multiprocessor communication function, see section 14.3.3, multiprocessor communication function. bit 2: mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0clock select 1 and 0 (cks1, cks0): these bits select the clock source for the built-in baud rate generator. the clock source can be selected from p f , p f /4, p f /16, and p f /64, according to the setting of bits cks1 and cks0. for the relationship between the clock source, the bit rate register setting, and the baud rate, see section 14.2.9, bit rate register (scbrr). rev. 1.0, 08/99, page 507 of 875 bit 1: cks1 bit 0: cks0 description 00p f clock (initial value) 1p f /4 clock 10p f /16 clock 1p f /64 clock note: p f (sci) is a clock scaled from the ckp peripheral clock according to the setting in the module clock control register. for details see section 4, clock pulse generator (cpg) and power-down modes. 14.2.6 serial control register (scscr) bit:76543210 tie rie te re mpie teie cke1 cke0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the serial control register (scscr) performs enabling or disabling of sci transmit/receive operations, and interrupt requests, and selection of the transmit/receive clock source. scscr can be read or written to by the cpu at all times. scscr is initialized to h'00 by a reset, by the module standby function, and in standby mode. bit 7transmit interrupt enable (tie): enables or disables transmit-fifo-data-empty interrupt (txi) request generation when, after serial transmit data is transferred from the transmit fifo data register (scftdr) to the transmit shift register (sctsr), the number of data bytes in scftdr falls to or below the transmit trigger set number, and the tdfe flag is set to 1 in the serial status 1 register (sc1ssr). bit 7: tie description 0 transmit-fifo-data-empty interrupt (txi) request disabled * (initial value) 1 transmit-fifo-data-empty interrupt (txi) request enabled note: * txi interrupt requests can be cleared by writing transmit data exceeding the transmit trigger set number to scftdr, reading 1 from the tdfe flag, then clearing it to 0, or by clearing the tie bit to 0. when transmit data is written to scftdr using the on-chip dmac, the tdfe flag is cleared automatically. rev. 1.0, 08/99, page 508 of 875 bit 6receive interrupt enable (rie): enables or disables generation of a receive-fifo-data- full interrupt (rxi) request and receive-error interrupt (eri) request when, after serial receive data is transferred from the receive shift register (scrsr) to the receive fifo data register (scfrdr), the number of data bytes in scfrdr reaches or exceeds the receive trigger set number, and the rdf flag is set to 1 in sc1ssr. bit 6: rie description 0 receive-fifo-data-full interrupt (rxi) request and receive-error interrupt (eri) request disabled * (initial value) 1 receive-fifo-data-full interrupt (rxi) request and receive-error interrupt (eri) request enabled note: * rxi and eri interrupt requests can be cleared by reading 1 from the rdf flag, or the orer, brk, dr, or er flag, then clearing the flag to 0, or by clearing the rie bit to 0. when orer occurs, read at least the receive trigger set number of receive data bytes from scfrdr, then read 1 from the orer flag and clear it to 0. bit 5transmit enable (te): enables or disables the start of serial transmission by the sci. bit 5: te description 0 transmission disabled * 1 (initial value) 1 transmission enabled * 2 notes: 1. the tdfe flag in sc1ssr is fixed at 1, and the txd pin is fixed high. 2. serial transmission is started when transmit data is written to scftdr in this state. serial mode register (scsmr) and fifo control register (scfcr) settings must be made, the transmission format decided, and the transmit fifo reset, before the te bit is set to 1. bit 4receive enable (re): enables or disables the start of serial reception by the sci. bit 4: re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdf, fer, per, orer, dr, and brk flags, which retain their states. 2. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in synchronous mode. scsmr setting must be made to decide the reception format before setting the re bit to 1. rev. 1.0, 08/99, page 509 of 875 bit 3multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when the mp bit in scsmr is set to 1. the mpie bit setting is invalid in synchronous mode and irda mode, and when the mp bit is cleared to 0. bit 3: mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] when the mpie bit is cleared to 0 when data with mpb = 1 is received 1 multiprocessor interrupts enabled * receive interrupt (rxi) requests, receive-error interrupt (eri) requests, and setting of the rdf, orer, and fer flags in sc1ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * receive data transfer from scrsr to scfrdr, receive error detection, and setting of the rdf, fer, and orer flags in sc1ssr, is not performed. when receive data including mpb = 1 is received, the mpb flag in sc1ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scscr are set to 1) and fer and orer flag setting is enabled. bit 2transmit-end interrupt enable (teie): enables or disables transmit-end interrupt (tei) request generation when there is no valid transmit data in scftdr when the last bit of the transmit data is sent. bit 2: teie description 0 transmit-end interrupt (tei) request disabled * (initial value) 1 transmit-end interrupt (tei) request enabled * note: * tei interrupt requests can be cleared by writing data to scftdr and clearing the tend flag to 0 in sc1ssr, or by clearing the teie bit to 0. bits 1 and 0clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as the serial clock output pin or the serial clock input pin. the function of the sck pin should be selected with the pin function controller (pfc). the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in synchronous mode and in the case of external clock operation (cke1 = 1). the cke1 and cke0 bits must be set before determining the scis operating mode with scsmr. rev. 1.0, 08/99, page 510 of 875 for details of clock source selection, see table 14.9 in section 14.3, operation. bit 1: cke1 bit 0: cke0 description 0 0 asynchronous mode internal clock/sck pin functions as input pin (input signal ignored) * 1 synchronous mode internal clock/sck pin functions as serial clock output * 1 1 asynchronous mode internal clock/sck pin functions as clock output * 2 synchronous mode internal clock/sck pin functions as serial clock output 1 * 4 asynchronous mode external clock/sck pin functions as clock input * 3 synchronous mode external clock/sck pin functions as serial clock input notes: 1. initial value 2. outputs a clock with a frequency of 16/8/4 times the bit rate. 3. inputs a clock with a frequency 16/8/4 times the bit rate. 4. dont care rev. 1.0, 08/99, page 511 of 875 14.2.7 serial status 1 register (sc1ssr) bit: 15 14 13 12 11 10 9 8 per3 per2 per1 per0 fer3 fer2 fer1 fer0 initial value:00000000 r/w:rrrrrrrr bit:76543210 tdfe rdf orer fer per tend mpb mpbt initial value:10000100 r/w: r/(w) * r/(w) * r/(w) * rrrrr/w note: * only 0 can be written, to clear the flag. the serial status 1 register (sc1ssr) is a 16-bit register in which the lower 8 bits consist of status flags that indicate the operating status of the sci plus the multiprocessor bit, and the upper 8 bits indicate the number of receive errors in the data in the receive fifo register. sc1ssr can be read or written to at all times. however, 1 cannot be written to the tdfe, rdf, orer, per, fer, and tend flags. also note that in order to clear the tdfe, rdf, and orer flags to 0, they must first be read as 1. the per, fer, tend, and mpb flags are read-only and cannot be modified. sc1ssr is initialized to h'0084 by a reset, in module standby mode, and in standby mode. bits 15 to 12number of parity errors (per3 to per0): these bits indicate the number of data bytes in which a parity error occurred in the receive data in the receive fifo data register. these bits are cleared by reading all the receive data in the receive fifo data register or setting the rfrst bit to 1 in scfcr to reset the receive fifo data register to the empty state. bits 11 to 8number of framing errors (fer3 to fer0): these bits indicate the number of data bytes in which a framing error occurred in the receive data in the receive fifo data register. these bits are cleared by reading all the receive data in the receive fifo data register or setting the rfrst bit to 1 in scfcr to reset the receive fifo data register to the empty state. rev. 1.0, 08/99, page 512 of 875 bit 7transmit fifo data register empty (tdfe): indicates that data has been transferred from the transmit fifo data register (scftdr) to the transmit shift register (sctsr), the number of data bytes in scftdr has fallen to or below the transmit trigger data number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr), and transmit data can be written to scftdr. bit 7: tdfe description 0 a number of transmit data bytes exceeding the transmit trigger set number have been written to scftdr [clearing conditions] when transmit data exceeding the transmit trigger set number is written to scftdr, and 0 is written to tdfe after reading tdfe = 1 when transmit data exceeding the transmit trigger set number is written to scftdr by the on-chip dmac 1 the number of transmit data bytes in scftdr does not exceed the transmit trigger set number (initial value) [setting conditions] in a reset, in standby mode, or when the te bit in scscr is 0 when the number of scftdr transmit data bytes falls to or below the transmit trigger set number as the result of a transmit operation * note: * as scftdr is a 16-byte fifo register, the maximum number of bytes that can be written when tdfe = 0 is {16 C (transmit trigger set number)}. data written in excess of this will be ignored. the number of data bytes in scftdr is indicated by the upper 8 bits of scfdr. rev. 1.0, 08/99, page 513 of 875 bit 6receive fifo data register full (rdf): indicates that the received data has been transferred to the receive fifo data register (scfrdr), and the number of receive data bytes in scfrdr is equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr). bit 6: rdf description 0 the number of receive data bytes in scfrdr is less than the receive trigger set number (initial value) [clearing conditions] in a reset or in standby mode when scfrdr is read until the number of receive data bytes in scfrdr falls below the receive trigger set number, and 0 is written to rdf after reading rdf = 1 when scfrdr is read by the on-chip dmac until the number of receive data bytes in scfrdr falls below the receive trigger set number 1 the number of receive data bytes in scfrdr is equal to or greater than the receive trigger set number [setting condition] when scfrdr contains at least the receive trigger set number of receive data bytes * note: * scfrdr is a 16-byte fifo register. when rdf = 1, at least the receive trigger set number of data bytes can be read. if all the data in scfrdr is read and another read is performed, the data value will be undefined. the number of receive data bytes in scfrdr is indicated by the lower 8 bits of scfdr. rev. 1.0, 08/99, page 514 of 875 bit 5overrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 5: orer description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] in a reset or in standby mode when 0 is written to orer after reading orer = 1 1 an overrun error occurred during reception * 2 [setting condition] when the next serial receive operation is completed while there are 16 receive data bytes in scfrdr notes: 1. the orer flag is not affected and retains its previous state when the re bit in scscr is cleared to 0. 2. the receive data prior to the overrun error is retained in scfrdr, and the data received subsequently is lost. serial reception cannot be continued while the orer flag is set to 1. also, serial transmission cannot be continued in synchronous mode. bit 4framing error (fer): indicates a framing error in the data read from the receive fifo data register (scfrdr). bit 4: fer description 0 there is no framing error in the receive data read from scfrdr (initial value) [clearing conditions] in a reset or in standby mode when there is no framing error in scfrdr read data 1 there is a framing error in the receive data read from scfrdr [setting condition] when there is a framing error in scfrdr read data rev. 1.0, 08/99, page 515 of 875 bit 3parity error (per): in asynchronous mode, indicates a parity error in the data read from the receive fifo data register (scfrdr). bit 3: per description 0 there is no parity error in the receive data read from scfrdr (initial value) [clearing conditions] in a reset or in standby mode when there is no parity error in scfrdr read data 1 there is a parity error in the receive data read from scfrdr [setting condition] when there is a parity error in scfrdr read data bit 2transmit end (tend): indicates that there is no valid data in scftdr when the last bit of the transmit character is sent, and transmission has been ended. bit 2: tend description 0 transmission is in progress [clearing condition] when data is written to scftdr while te = 1 1 transmission has been ended (initial value) [setting conditions] in a reset or in standby mode when the te bit in scscr is 0 when there is no transmit data in scftdr on transmission of the last bit of a 1-byte serial transmit character bit 1multiprocessor bit (mpb): when reception is performed using a multiprocessor format in asynchronous mode, mpb stores the multiprocessor bit in the receive data. the mpb flag is read-only and cannot be modified. bit 1: mpb description 0 data with a 0 multiprocessor bit has been received * (initial value) 1 data with a 1 multiprocessor bit has been received note: * retains its previous state when the re bit is cleared to 0 while using a multiprocessor format. rev. 1.0, 08/99, page 516 of 875 bit 0multiprocessor bit transfer (mpbt): when transmission is performed using a multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid in synchronous mode and irda mode, when a multiprocessor format is not used, and when the operation is not transmission. bit 0: mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted 14.2.8 serial status 2 register (sc2ssr) bit:76543210 tlm rlm n1 n0 brk dr ei er initial value:00100000 r/w: r/w r/w r/w r/w r/(w) * r/(w) * r/w r/(w) * note: * only 0 can be written, to clear the flag. the serial status 2 register (sc2ssr) is an 8-bit register. sc2ssr can be read or written to at all times. however, 1 cannot be written to the brk, dr, and er flags. also note that in order to clear these flags to 0, they must first be read as 1. sc2ssr is initialized to h'20 by a reset, in module standby mode, and in standby mode. bit 7transmit lsb/msb-first select (tlm): selects lsb-first or msb-first mode in data transmission. bit 7: tlm description 0 lsb-first transmission (initial value) 1 msb-first transmission bit 6receive lsb/msb-first select (rlm): selects lsb-first or msb-first mode in data reception. bit 6: rlm description 0 lsb-first reception (initial value) 1 msb-first reception rev. 1.0, 08/99, page 517 of 875 bits 5 and 4clock bit rate ratio (n1, n0): these bits select the ratio of the base clock to the bit rate. bit 5: n1 bit 4: n0 description 0 0 sci operates on base clock of 4 times the bit rate 1 sci operates on base clock of 8 times the bit rate 1 0 sci operates on base clock of 16 times the bit rate (initial value) 1 setting prohibited bit 3break detect (brk): indicates that a receive data break signal has been detected. bit 3: brk description 0 a break signal has not been received (initial value) [clearing conditions] in a reset or in standby mode when 0 is written to brk after reading brk = 1 1 a break signal has been received * [setting condition] when data with a framing error is received, and a framing error also occurs in the next receive data (all space 0) note: * when a break is detected, the receive data (h'00) following detection is not transferred to scfrdr. when the break ends and the receive signal returns to mark 1, receive data transfer is resumed. rev. 1.0, 08/99, page 518 of 875 bit 2receive data ready (dr): indicates that there are fewer than the receive trigger set number of data bytes in the receive fifo data register (scfrdr), and no further data has arrived for at least 15 etu after the stop bit of the last data received. bit 2: dr description 0 reception is in progress or has ended normally and there is no receive data left in scfrdr (initial value) [clearing conditions] in a reset or in standby mode when 0 is written to dr after reading dr = 1 * 1 1 no further receive data has arrived, and scfrdr contains fewer than the receive trigger set number of data bytes [setting condition] when scfrdr contains fewer than the receive trigger set number of receive data bytes, and no further data has arrived for at least 15 etu after the stop bit of the last data received * 2 notes: 1. all remaining receive data should be read before clearing the dr flag. 2. equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. etu: elementary time unit = sec/bit bit 1receive data error ignore enable (ei): selects whether or not the receive operation is to be continued when a framing error or parity error occurs in receive data (er = 1). bit 1: ei description 0 receive operation is halted when framing error or parity error occurs during reception (er = 1) (initial value) 1 receive operation is continued when framing error or parity error occurs during reception (er = 1) note: when ei = 0, only the last data in scfrdr is treated as data containing an error. when ei = 1, receive data is sent to scfrdr even if it contains an error. rev. 1.0, 08/99, page 519 of 875 bit 0receive error (er): indicates that a framing error, parity error, or overrun error occurred during reception. bit 0: er description 0 reception in progress, or reception has ended normally * 1 (initial value) [clearing conditions] in a reset or in standby mode when 0 is written to er after reading er = 1 1 a framing error, parity error, or overrun error occurred during reception [setting conditions] when the sci checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 * 2 when, in reception, the number of 1-bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in the serial mode register (scsmr) when the next serial receive operation is completed while there are 16 receive data bytes in scfrdr notes: 1. the er flag is not affected and retains its previous state when the re bit in scscr is cleared to 0. when a framing error or parity error occurs, the receive data is still transferred to scfrdr, and reception is then halted or continued according to the setting of the ei bit. when an overrun error occurs, the receive data is not transferred to scfrdr and reception cannot be continued. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 1; the second stop bit is not checked. 14.2.9 bit rate register (scbrr) bit:76543210 initial value:11111111 r/w: r/w r/w r/w r/w r/w r/w r/w r/w the bit rate register (scbrr) is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in the serial mode register (scsmr). scbrr can be read or written to by the cpu at all times. rev. 1.0, 08/99, page 520 of 875 scbrr is initialized to h'ff by a reset, by the module standby function, and in software standby mode and hardware standby mode. the scbrr setting is found from the following equations. asynchronous mode: n = 64 2 2nC1 b 10 6 C 1 (when operating on a base clock of 16 times the bit rate) p f n = 32 2 2nC1 b 10 6 C 1 (when operating on a base clock of 8 times the bit rate) p f n = 16 2 2nC1 b 10 6 C 1 (when operating on a base clock of 4 times the bit rate) p f synchronous mode: n = 8 2 2nC1 b 10 6 C 1 p f where b: bit rate (bits/s) n: scbrr setting for baud rate generator (0 n 255) p f : peripheral module operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) scsmr settings n clock cks1 cks0 0p f 00 1p f /4 0 1 2p f /16 1 0 3p f /64 1 1 rev. 1.0, 08/99, page 521 of 875 the bit rate error in asynchronous mode is found from the following equations: error (%) = (n + 1) b 64 2 2nC1 C 1 100 p f 10 6 (when operating on a base clock of 16 times the bit rate) error (%) = (n + 1) b 32 2 2nC1 C 1 100 p f 10 6 (when operating on a base clock of 8 times the bit rate) error (%) = (n + 1) b 16 2 2nC1 C 1 100 p f 10 6 (when operating on a base clock of 4 times the bit rate) table 14.3 shows sample scbrr settings in asynchronous mode, and table 14.4 shows sample scbrr settings in synchronous mode. rev. 1.0, 08/99, page 522 of 875 table 14.3 examples of bit rates and scbrr settings in asynchronous mode p f f f f (mhz) 2 2.097152 2.4576 3 bit rate (bits/s) nn error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 C0.04 1 174 C0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 C0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 C2.48 0 15 0.00 0 19 C2.34 9600 0 6 C6.99 0 6 C2.48 0 7 0.00 0 9 C2.34 19200 0 2 8.51 0 2 13.78 0 3 0.00 0 4 C2.34 31250 0 1 0.00 0 1 4.86 0 1 22.88 0 2 0.00 38400 0 1 C18.62 0 1 C14.67 0 1 0.00 p f f f f (mhz) 3.6864 4 4.9152 5 bit rate (bits/s) n n error (%) nn error (%) nn error (%) nn error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 C0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 C1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 6 C6.99 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 C1.70 0 4 0.00 38400 0 2 0.00 0 2 8.51 0 3 0.00 0 3 1.73 rev. 1.0, 08/99, page 523 of 875 table 14.3 examples of bit rates and scbrr settings in asynchronous mode (cont) p f f f f (mhz) 6 6.144 7.37288 8 bit rate (bits/s) nn error (%) n n error (%) n n error (%) n n error (%) 110 2 106 C0.44 2 108 0.08 2 130 C0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 C2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 C2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 6 5.33 0 7 0.00 38400 0 4 ? 2.34 0 4 0.00 0 5 0.00 0 6 ? 6.99 p f f f f (mhz) 9.8304 10 12 12.288 bit rate (bits/s) n n error (%) nn error (%) nn error (%) nn error (%) 110 2 174 C0.26 2 177 C0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 C1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 0.16 0 19 0.00 31250 0 9 C1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 C2.34 0 9 0.00 rev. 1.0, 08/99, page 524 of 875 table 14.3 examples of bit rates and scbrr settings in asynchronous mode (cont) p f f f f (mhz) 14.7456 16 30 bit rate (bits/s) nn error (%) n n error (%) n n error (%) 110 3 64 0.70 3 70 0.03 3 132 0.13 150 2 191 0.00 2 207 0.16 3 97 C0.35 300 2 95 0.00 2 103 0.16 2 194 0.16 600 1 191 0.00 1 207 0.16 2 97 C0.35 1200 1 95 0.00 1 103 0.16 1 194 0.16 2400 0 191 0.00 0 207 0.16 1 97 C0.35 4800 0 95 0.00 0 103 0.16 0 197 0.16 9600 0 47 0.00 0 51 0.16 0 97 C0.35 19200 0 23 0.00 0 25 0.16 0 48 C0.35 31250 0 14 C1.70 0 15 0.00 0 29 0.00 38400 0 11 0.00 0 12 0.16 0 23 1.73 rev. 1.0, 08/99, page 525 of 875 table 14.4 examples of bit rates and scbrr settings in synchronous mode p f f f f (mhz) 4816 bit rate (bits/s) n n n n n n 110 250 2 249 3 124 3 249 500 2 124 2 249 3 124 1 k 1 249 2 124 2 249 2.5 k 1 99 1 199 2 99 5 k 0 199 1 99 1 199 10 k 0 99 0 199 1 99 25 k 0 39 0 79 0 159 50 k 0 19 0 39 0 79 100 k 0 9 0 19 0 39 250 k 0 3 0 7 0 15 500 k 0 1 0 3 0 7 1 m 0 0 * 01 03 2 m 0 0 * 01 note: as far as possible, the setting should be made so that the error is within 1%. legend blank: no setting is available. : a setting is available but error occurs. * continuous transmission/reception is not possible. rev. 1.0, 08/99, page 526 of 875 table 14.5 shows the maximum bit rate for various frequencies in asynchronous mode when using the baud rate generator. tables 14.6 and 14.7 show the maximum bit rates when using external clock input. table 14.5 maximum bit rate for various frequencies with baud rate generator (asynchronous mode) settings p f f f f (mhz) maximum bit rate (bits/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 8 250000 0 0 9.8304 307200 0 0 12 375000 0 0 14.7456 460800 0 0 16 500000 0 0 19.66080 614400 0 0 20 625000 0 0 24 750000 0 0 24.57600 768000 0 0 28 896875 0 0 30 937500 0 0 rev. 1.0, 08/99, page 527 of 875 table 14.6 maximum bit rate with external clock input (asynchronous mode) p f f f f (mhz) external input clock (mhz) maximum bit rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 8 2.0000 125000 9.8304 2.4576 153600 12 3.0000 187500 14.7456 3.6864 230400 16 4.0000 250000 30 7.5000 468750 table 14.7 maximum bit rate with external clock input (synchronous mode) p f f f f (mhz) external input clock (mhz) maximum bit rate (bits/s) 8 1.3333 1333333.3 16 2.6667 2666666.7 30 5.0 5000000.0 rev. 1.0, 08/99, page 528 of 875 14.2.10 fifo control register (scfcr) bit:76543210 rtrg1 rtrg0 ttrg1 ttrg0 tfrst rfrst loop initial value:00000000 r/w: r/w r/w r/w r/w r r/w r/w r/w the fifo control register (scfcr) performs data count resetting and trigger data number setting for the transmit and receive fifo registers, and also contains a loopback test enable bit. scfcr can be read or written to at all times. scfcr is initialized to h'00 by a reset, by the module standby function, and in software standby mode and hardware standby mode. bits 7 and 6receive fifo data number trigger (rtrg1, rtrg0): these bits are used to set the number of receive data bytes that sets the receive data full (rdf) flag in the serial status 1 register (sc1ssr). the rdf flag is set when the number of receive data bytes in the receive fifo data register (scfrdr) is equal to or greater than the trigger set number shown in the following table. bit 7: rtrg1 bit 6: rtrg0 receive trigger number 001 * 14 108 114 note: * initial value bits 5 and 4transmit fifo data number trigger (ttrg1, ttrg0): these bits are used to set the number of remaining transmit data bytes that sets the transmit fifo data register empty (tdfe) flag in the serial status 1 register (sc1ssr). the tdfe flag is set when the number of transmit data bytes in the transmit fifo data register (scftdr) is equal to or less than the trigger set number shown in the following table. rev. 1.0, 08/99, page 529 of 875 bit 5: ttrg1 bit 4: ttrg0 transmit trigger number 0 0 8 (8) * 1 4 (12) 1 0 2 (14) 1 1 (15) note: * initial value. figures in parentheses are the number of empty bytes in scftdr when the flag is set. bit 3reserved: this bit is always read as 0 and should only be written with 0. bit 2transmit fifo data register reset (tfrst): invalidates the transmit data in the transmit fifo data register and resets it to the empty state. bit 2: tfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a reset or in standby mode. bit 1receive fifo data register reset (rfrst): invalidates the receive data in the receive fifo data register and resets it to the empty state. bit 1: rfrst description 0 reset operation disabled * (initial value) 1 reset operation enabled note: * a reset operation is performed in the event of a reset or in standby mode. bit 0loopback test (loop): internally connects the transmit output pin (txd) and receive output pin (rxd), enabling loopback testing. bit 0: loop description 0 loopback test disabled (initial value) 1 loopback test enabled rev. 1.0, 08/99, page 530 of 875 14.2.11 fifo data count register (scfdr) the fifo data count register (scfdr) is a 16-bit register that indicates the number of data bytes stored in the transmit fifo data register (scftdr) and receive fifo data register (scfrdr). the upper 8 bits show the number of transmit data bytes in scftdr, and the lower 8 bits show the number of receive data bytes in scfrdr. scfdr is initialized to h'00 by a reset, in module standby mode, and in standby mode. it is also initialized to h'00 by setting the tfrst and rfrst bits to 1 in scfcr to reset scftdr and scfrdr to the empty state. scfdr can be read by the cpu at all times. upper 8 bits: 76543210 t4 t3 t2 t1 t0 initial value:00000000 r/w:rrrrrrrr bits 15 to 13reserved: these bits are always read as 0 and should only be written with 0. bits 12 to 8transmit fifo data count (t4 to t0): these bits show the number of untransmitted data bytes in scftdr. a value of h'00 indicates that there is no transmit data, and a value of h'10 indicates that scftdr is full of transmit data. the value is cleared to h'00 by transmitting all the data, as well as by the above initialization conditions. lower 8 bits:76543210 r4 r3 r2 r1 r0 initial value:00000000 r/w:rrrrrrrr bits 7 to 5reserved: these bits are always read as 0 and should only be written with 0. bits 4 to 0receive fifo data count (r4 to r0): these bits show the number of receive data bytes in scfrdr. a value of h'00 indicates that there is no receive data, and a value of h'10 indicates that scfrdr is full of receive data. the value is cleared to h'00 by reading all the receive data from scfrdr, as well as by the above initialization conditions. rev. 1.0, 08/99, page 531 of 875 14.2.12 fifo error register (scfer) the fifo error register (scfer) indicates the data location at which a parity error or framing error occurred in receive data stored in the receive fifo data register (scfrdr). scfer can be read at all times. upper 8 bits: 15 14 13 12 11 10 9 8 ed15 ed14 ed13 ed12 ed11 ed10 ed9 ed8 initial value:00000000 r/w:rrrrrrrr lower 8 bits:76543210 ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 initial value:00000000 r/w:rrrrrrrr bits 15 to 0error data flags (ed15 to ed0): these flags indicate the data location in the receive fifo data register at which an error occurred. when data in the nth stage of the buffer contains an error, the nth bit is set to 1. note that this register is not cleared by setting the rfrst bit to 1 in scfcr. to clear this register, read all the receive data in which the error occurred from the scfrdr register before setting the rfrst bit to 1 in scfcr to clear scfrdr. bits 15 to 0: ed15 to ed0 description 0 no parity or framing error in data in corresponding stage of register fifo (initial value) 1 parity or framing error present in data in corresponding stage of register fifo note: a reset operation is performed in the event of a reset, when the module standby function is initiated, or in standby mode. also, these flags are cleared by reading the data in which the parity error or framing error occurred from scfrdr. rev. 1.0, 08/99, page 532 of 875 14.2.13 irda mode register (scimr) the irda mode register (scimr) allows selection of the irda mode and the irda output pulse width, and inversion of the irda receive data polarity. scimr can be read and written to at all times. scimr is initialized to h'00 by a reset, by the module standby function, and in software standby mode and hardware standby mode. bit:76543210 irmod psel rivs initial value:00000000 r/w:r/wr/wr/wrrrrr bit 7irda mode (irmod): selects operation as an irda serial communication interface. bit 7: irmod description 0 operation as sci is selected (initial value) 1 operation as irda is selected * note: * when operation as an irda interface is selected, bit 7 (c/ a ) of the serial mode register (scsmr) must be cleared to 0. bit 6output pulse width select (psel): selects either 3/16 of the bit length set by bits ick3 to ick0 in the serial status 1 register (sc1ssr), or 3/16 of the bit length corresponding to the selected bit rate, as the irda output pulse width. the setting is shown together with bits 6 to 3 (ick3 to ick0) of the serial mode register (scsmr). serial mode register (scsmr) scimr bit 6: ick3 bit 5: ick2 bit 4: ick1 bit 3: ick0 bit 2: psel description ick3 ick2 ick1 ick0 1 pulse width: 3/16 of bit length set in bits ick3 to ick0 dont care dont care dont care dont care 0 pulse width: 3/16 of bit length set in scbrr note: a fixed clock pulse signal, irclk, must be generated by multiplying the p f clock by 1/n + 2 (where n is determined by the value set in ick3 to ick0). for details, see pulse width selection in section 14.3.6. rev. 1.0, 08/99, page 533 of 875 bit 5irda receive data inverse (rivs): allows inversion of the receive data polarity to be selected in irda communication. bit 5: rivs description 0 receive data polarity inverted in reception (initial value) 1 receive data polarity not inverted in reception note: make the selection according to the characteristics of the irda modulation/demodulation module. bits 4 to 0reserved: these bits are always read as 0 and should only be written with 0. 14.3 operation 14.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. an irda block is also provided, enabling infrared communication conforming to irda 1.0 to be executed by connecting an infrared transmission/reception unit. sixteen-stage fifo buffers are provided for both transmission and reception, reducing the cpu overhead and enabling fast, continuous communication to be performed. selection of asynchronous, synchronous, or irda mode and the transmission format is made by means of the serial mode register (scsmr) and irda mode register (scimr) as shown in table 14.8. the sci clock source is determined by a combination of the c/ a bit in scsmr, the irmod bit in scimr, and the cke1 and cke0 bits in the serial control register (scscr), as shown in table 14.9. rev. 1.0, 08/99, page 534 of 875 asynchronous mode ? data length: choice of 7 or 8 bits ? choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transmit/receive format and character length) ? detection of framing, parity, and overrun errors, receive fifo data full and receive data ready conditions, and breaks, during reception ? detection of transmit fifo data empty condition during transmission ? choice of internal or external clock as sci clock source when internal clock is selected: the sci operates on a clock with a frequency of 16, 8, or 4 times the bit rate of the baud rate generator, and can output this operating clock. when external clock is selected: a clock with a frequency of 16, 8, or 4 times the bit rate must be input (the built-in baud rate generator is not used). synchronous mode ? transfer format: fixed 8-bit data ? detection of overrun errors during reception ? choice of internal or external clock as sci clock source when internal clock is selected: the sci operates on the baud rate generator clock and can output a serial clock to external devices. when external clock is selected: the on-chip baud rate generator is not used, and the sci operates on the input serial clock. irda mode ? irda 1.0 compliance ? data length: 8 bits ? stop bit length: 1 bit ? protection function to prevent receiver being affected during transmission ? clock source: internal clock rev. 1.0, 08/99, page 535 of 875 table 14.8 scsmr and scimr settings for serial transmit/receive format selection scimr scsmr settings sci transmit/receive format bit 7: irmod bit 7: c/ a a a a bit 6: chr bit 2: mp bit 5: pe bit 3: stop mode data length mp bit parity bit stop bit length 0 00000 absentabsent1 bit 12 bits 1 0 present 1 bit 1 8-bit data 2 bits 1 0 0 absent 1 bit 12 bits 1 0 present 1 bit 1 asynchronous mode 7-bit data 2 bits 01 * 0 present absent 1 bit * 1 8-bit data 2 bits 1 * 01 bit * 1 asynchronous mode (multi- processor format) 7-bit data 2 bits 01 **** synchronous mode 8-bit data absent absent none 1 0 ick3 ick2 ick1 ick0 irda mode 8-bit data absent absent 1 bit 1 **** setting prohibited note: an asterisk in the table means dont care. rev. 1.0, 08/99, page 536 of 875 table 14.9 scsmr and scscr settings for sci clock source selection scsmr scscr setting sci transmit/receive clock bit 7: c/ a a a a bit 1: cke1 bit 0: cke0 mode clock source sck pin function 0 0 0 sci does not use sck pin 1 internal outputs clock with frequency of 16/8/4 times bit rate 1 0 inputs clock with frequency of 16/8/4 times bit rate 1 asynchronous mode external 1 0 0 outputs serial clock 1 internal 1 0 inputs serial clock 1 synchronous mode external 14.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and followed by one or two stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by- character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receiver also have a 16-stage fifo buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 14.3 shows the general format for asynchronous serial communication. in asynchronous serial communication, the communication line is usually held in the mark state (high level). the sci monitors the line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. one serial communication character consists of a start bit (low level), followed by data (lsb-first or msb-first order selectable), a parity bit (high or low level), and finally one or two stop bits (high level). in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the eighth pulse of a clock with a frequency of 16, 8, or 4 times the length of one bit, so that the transfer data is latched at the center of each bit. rev. 1.0, 08/99, page 537 of 875 serial data (lsb) 7 or 8 bits one unit of transfer data (character or frame) parity bit 1 bit, or none 1 or 2 bits 1 1 0 d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 idle state (mark state) start bit 1 bit (msb) transmit/receive data stop bits figure 14.3 data format in asynchronous communication (example with 8-bit data, parity, two stop bits, lsb-first transfer) rev. 1.0, 08/99, page 538 of 875 transmit/receive format: table 14.10 shows the transmit/receive formats that can be used in asynchronous mode. any of 12 transmit/receive formats can be selected by means of settings in the serial mode register (scsmr). table 14.10 serial transmit/receive formats (asynchronous mode) scsmr settings serial transmit/receive format and frame length chrpempstop 123456789101112 0000 s 8-bit data stop 0001 s 8-bit data stop stop 0100 s 8-bit data pstop 0101 s 8-bit data p stop stop 1000 s 8-bit data stop 1001 s 8-bit data stop stop 1100 s 7-bit data pstop 1101 s 7-bit data p stop stop 0 * 10 s 8-bit data mpb stop 0 * 11 s 8-bit data mpb stop stop 1 * 10 s 7-bit data mpb stop 1 * 11 s 7-bit data mpb stop stop legend s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit note: an asterisk in the table means dont care. rev. 1.0, 08/99, page 539 of 875 clock: either an internal clock generated by the built-in baud rate generator or an external clock input at the sck pin can be selected as the scis serial clock, according to the setting of the c/ a bit in scsmr and the cke1 and cke0 bits in scscr. for details of sci clock source selection, see table 14.9. when an external clock is input at the sck pin, the clock frequency should be 16, 8, or 4 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is 16, 8, or 4 times the bit rate. data transmit/receive operations: sci initialization (asynchronous mode) before transmitting and receiving data, it is necessary to clear the te and re bits to 0 in scscr, then initialize the sci as described below. when the operating mode, communication format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the transmit shift register (sctsr) is initialized. note that clearing the te and re bits to 0 does not change the contents of the serial status 1 register (sc1ssr), the transmit fifo data register (scftdr), or the receive fifo data register (scfrdr). the te bit should not be cleared to 0 until all transmit data has been transmitted and the tend flag has been set in sc1ssr. it is possible to clear the te bit to 0 during transmission, but the data being transmitted will go to the high-impedance state after te is cleared. also, before starting transmission by setting te again, the tfrst bit should first be set to 1 in scfcr to reset scftdr. when an external clock is used the clock should not be stopped during operation, including initialization, since operation will be unreliable in this case. figure 14.4 shows a sample sci initialization flowchart. rev. 1.0, 08/99, page 540 of 875 initialization set tfrst and rfrst bits to 1 in scfcr, and clear fifo buffer read brk, dr, and er flags in sc2ssr, then clear them by writing 0 set tie, rie, mpie, teie, cke1 and cke0 bits in scscr (leaving te and re bits cleared to 0) set transmit/receive format in scsmr set value in scbrr 1-bit interval elapsed? set rtrg1C0 and ttrg1C0 bits in scfcr, and clear tfrst and rfrst bits to 0 pfc setting for external pins used (sck, txd, rxd) end 2 3 4 clear te and re bits to 0 in scscr 1 set te or re bit to 1 in scscr 6 5 1. clear bits te and re to 0 before end of initialization. 2. set enabling/disabling of txi, rxi, and tei interrupt requests. if interrupt requests are enabled, also make a setting in the intcs iprk register. 3. set the transmit/receive format in scsmr. when using irda mode, also set scimr. 4. write a value corresponding to the bit rate to the bit rate register (scbrr). not necessary if an external clock is used. wait for at least one bit interval after making this setting. 5. make pfc settings for the external pins to be used. make a setting for rxd input when receiving, and for txd output when transmitting. make an sck input/output setting according to the setting of bits cke1 and cke0. an sck pin setting is not necessary when cke1 and cke0 are cleared to 0 in asynchronous mode. when serial clock output is set, clock output from the sck pin begins at this point. 6. set the te bit or re bit in scscr to 1. setting the te and re bits enables the txd, rxd and sck pins to be used. when transmitting, the txd pin will go to the mark state; when receiving, rxd pin will go to the idle state, waiting for a start bit. yes no wait figure 14.4 sample sci initialization flowchart serial data transmission (asynchronous mode) figure 14.5 shows a sample flowchart for serial transmission. rev. 1.0, 08/99, page 541 of 875 use the following procedure for serial data transmission after enabling the sci for transmission. end of transmission read tdfe bit in sc1ssr write {16 C (transmit trigger set number)} bytes of transmit data to scftdr, and clear tdfe bit to 0 in sc1ssr after reading tdfe = 1 tdfe = 1? all data transmitted? read tend bit in sc1ssr tend = 1? break output? clear dr to 0 clear te bit to 0 in scscr, and set txd pin as output port with pfc start of transmission initialization yes no no no no yes yes yes 1 2 3 4 1. sci initialization: see figure 14.4, sample sci initialization flowchart. 2. sci status check and transmit data write: read the serial status 1 register (sc1ssr) and check that the tdfe bit is set to 1, then write transmit data to the transmit fifo data register (scftdr) and clear the tdfe bit to 0 after reading tdfe = 1. the tend bit is cleared automatically when transmission is started by writing transmit data. the number of data bytes that can be written is {16 C (transmit trigger set number)}. 3. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe bit to confirm that writing is possible, then write data to scftdr, and then clear the tdfe bit to 0. (checking and clearing of the tdfe bit is automatic when the dmac is activated by a transmit-fifo-data-empty interrupt (txi) request, and data is written to scftdr.) 4. break output at the end of serial transmission: to output a break in serial transmission, clear the port data register (dr) to 0, then clear the te bit to 0 in scscr, and set the txd pin as an output port with the pfc. in steps 2 and 3, the number of transmit data bytes that can be written can be ascertained from the number of transmit data bytes in scftdr indicated in the upper 8 bits of the fifo data count register (scfdr). figure 14.5 sample serial transmission flowchart rev. 1.0, 08/99, page 542 of 875 in serial transmission, the sci operates as described below. 1. when data is written to the transmit fifo data register (scftdr), the sci transfers the data to the transmit shift register (sctsr), and starts transmitting. check that the tdfe flag is set to 1 in the serial status 1 register (sc1ssr) before writing transmit data to scftdr. the number of data bytes that can be written is at least {16 C (transmit trigger set number)}. 2. when data is transferred from scftdr to sctsr and transmission is started, transmit operations are performed continually until there is no transmit data left in scftdr. if the number of data bytes in scftdr falls to or below the transmit trigger number set in the fifo control register (scfcr) during transmission, the tdfe flag is set. if the te bit setting in the serial control register (scscr) is 1 at this time, a transmit-fifo-data-empty interrupt (txi) is requested. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first or msb-first order according to the setting of the tlm bit in sc2ssr. c. parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. (a format in which neither a parity bit nor a multiprocessor bit is output can also be selected.) d. stop bit(s): one or two 1-bits (stop bits) are output. 3. the sci checks for transmit data in scftdr at the timing for sending the stop bit. if there is data in scftdr, it is transferred to sctsr, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data in scftdr, the tend flag is set to 1 in the serial status 1 register (sc1ssr), the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. if the teie bit setting in scscr is 1 at this time, a tei interrupt is requested. figure 14.6 shows an example of the operation for transmission in asynchronous mode. rev. 1.0, 08/99, page 543 of 875 serial data 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 tdfe tend start bit data parity bit stop bit idle state (mark state) data parity bit stop bit txi interrupt request data written to scftdr and tdfe flag cleared to 0 by txi interrupt handler one frame tei interrupt request txi interrupt request figure 14.6 example of transmit operation in asynchronous mode (example with 8-bit data, parity, one stop bit, lsb-first transfer) serial data reception (asynchronous mode) figure 14.7 shows a sample flowchart for serial reception. use the following procedure for serial data reception after enabling the sci for reception. rev. 1.0, 08/99, page 544 of 875 1. sci initialization: see figure 14.4, sample sci initialization flowchart. 2. receive error handling and break detection: read the brk, dr, and er bits in sc2ssr to check whether a receive error has occurred. if a receive error occurs, read the orer, per3 to 0, and fer3 to 0 flags in sc1ssr, and the dr and brk flags in sc2ssr to identify the error. after performing the appropriate error handling, ensure that the orer, brk, dr, and er bits are all cleared to 0. reception cannot be resumed if the orer bit is set to 1. the setting of the ei bit in sc2ssr determines whether reception is continued or halted when either per3 to 0 or fer3 to 0 is set to 1. in the case of a framing error, a break can be detected by reading the value of the rxd pin. 3. sci status check and receive data read : read the serial status 1 register (sc1ssr) and check that rdf = 1, then read receive data from the receive fifo data register (scfrdr) and clear the rdf bit to 0. transition of the rdf bit from 0 to 1 can also be identified by means of an rxi interrupt. 4. serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of data bytes from scfrdr, and write 0 to the rdf flag after reading 1 from it. the number of receive data bytes in scfrdr can be ascertained by reading the lower 8 bits of the fifo data count register (scfdr). (the rdf bit is cleared automatically when the dmac is activated by an rxi interrupt and the scfrdr value is read.) initialization start of reception read brk, dr, and er bits in sc2ssr brk dr er = 1? error handling read rdf flag in sc1ssr rdf = 1? read receive data from scfrdr, and clear rdf flag to 0 in sc1ssr all data received? clear re bit to 0 in scscr end of reception yes no yes no no yes 1 2 3 4 figure 14.7 sample serial reception flowchart (1) rev. 1.0, 08/99, page 545 of 875 1. whether a framing error or parity error has occurred in the receive data read from scfrdr can be ascertained from the fer and per bits in sc1ssr. 2. when a break signal is received, receive data is not transferred to scfrdr while the brk flag is set. however, note that the last data in scfrdr is h'00 and the break data in which a framing error occurred is stored. error handling overrun error handling orer = 1? brk = 1? dr = 1? fer = 1? framing error handling per = 1? parity error handling all data read? clear orer, brk, dr, and er flags to 0 end no no no no no no yes yes yes yes yes yes clear re bit to 0 in scscr read receive data from scfrdr 1 2 figure 14.7 sample serial reception flowchart (2) rev. 1.0, 08/99, page 546 of 875 in serial reception, the sci operates as described below. 1. the sci monitors the communication line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. the received data is stored in scrsr in lsb-to-msb order or msb-to-lsb order according to the setting of the rlm bit in sc2ssr. 3. the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks. a. parity check: the sci checks whether the number of 1-bits in the receive data agrees with the parity (even or odd) set in the o/e bit in the serial mode register (scsmr). b. stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. c. status check: the sci checks whether receive data can be transferred from the receive shift register (scrsr) to scfrdr. d. break check: the sci checks that the brk flag is 0, indicating no break. if all the above checks are passed, the receive data is stored in scfrdr. if a receive error is detected in the error check, the operation is as shown in table 14.11. note: no further receive operations can be performed when an overrun error has occurred. the setting of the ei bit in sc2ssr determines whether reception is continued or halted when a framing error or parity error occurs. also, as the rdf flag is not set to 1 when receiving, the error flags must be cleared to 0. 4. if the rie bit setting in scscr is 1 when the rdf flag changes to 1, a receive-fifo-data- full interrupt (rxi) is requested. if the rie bit setting in scscr is 1 when the orer, per, fer, or dr flag changes to 1, a receive-error interrupt (eri) is requested. table 14.11 receive error conditions receive error abbreviation condition data transfer overrun error orer next serial receive operation is completed while there are 16 receive data bytes in scfrdr receive data is not transferred from scrsr to scfrdr framing error fer stop bit is 0 receive data is transferred from scrsr to scfrdr parity error per received data parity differs from that (even or odd) set in scsmr receive data is transferred from scrsr to scfrdr rev. 1.0, 08/99, page 547 of 875 figure 14.8 shows an example of the operation for reception in asynchronous mode. serial data 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 rdf fer start bit parity bit stop bit start bit data data parity bit stop bit idle state (mark state) rxi interrupt request one frame data read and rdf flag cleared to 0 by rxi interrupt handler eri interrupt request due to framing error figure 14.8 example of sci receive operation (example with 8-bit data, parity, one stop bit, lsb-first transfer) 14.3.3 multiprocessor communication function the multiprocessor communication function performs serial communication using a multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing a serial communication line. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two cycles: an id transmission cycle which specifies the receiving station, and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. the transmitting station first sends the id of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving stations skip the data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, each receiving stations compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. in this way, data communication is carried out among a number of processors. rev. 1.0, 08/99, page 548 of 875 figure 14.9 shows an example of inter-processor communication using a multiprocessor format. transmitting station receiving station a (id = 01) (id = 02) (id = 03) (id = 04) serial communication line serial data id transmission cycle: receiving station specification data transmission cycle: data transmission to receiving station specified by id (mpb = 1) (mpb = 0) h'01 h'aa mpb: multiprocessor bit receiving station b receiving station c receiving station d figure 14.9 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) transmit/receive formats: there are four transmit/receive formats. when the multiprocessor format is specified, the parity bit specification is invalid. for details, see table 14.10. clock: see the section on asynchronous mode. data transmit/receive operations: sci initialization see the section on asynchronous mode. multiprocessor serial data transmission figure 14.10 shows a sample flowchart for multiprocessor serial data transmission. use the following procedure for multiprocessor serial data transmission after enabling the sci for transmission. rev. 1.0, 08/99, page 549 of 875 end of transmission read tdfe bit in sc1ssr write {16 C (transmit trigger set number)} bytes of transmit data to scftdr, and set mpbt in sc1ssr tdfe = 1? end of transmission? read tend bit in sc1ssr tend = 1? break output? clear dr to 0 clear te bit to 0 in scscr, and set txd pin as output port with pfc start of transmission initialization yes no no no no yes yes yes 1 2 3 4 1. sci initialization: see figure 14.4, sample sci initialization flowchart. 2. sci status check and transmit data write: read the serial status 1 register (sc1ssr) and check that the tdfe bit is set to 1, then write transmit data to the transmit fifo data register (scftdr). set the mpbt bit to 0 or 1 in sc1ssr. finally, clear the tdfe and tend flags to 0 after reading 1 from them. the number of data bytes that can be written is {16 C (transmit trigger set number)}. 3. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe bit to confirm that writing is possible, then write data to scftdr, and then clear the tdfe bit to 0. (checking and clearing of the tdfe bit is automatic when the dmac is activated by a transmit-fifo-data- empty interrupt (txi) request, and data is written to scftdr.) 4. break output at the end of serial transmission: to output a break in serial transmission, clear the port data register (dr) to 0, then clear the te bit to 0 in scscr, and set the txd pin as an output port with the pfc. in steps 2 and 3, the number of transmit data bytes that can be written can be ascertained from the number of transmit data bytes in scftdr indicated in the upper 8 bits of the fifo data count register (scfdr). clear tdfe and tend flags to 0 figure 14.10 sample multiprocessor serial transmission flowchart rev. 1.0, 08/99, page 550 of 875 in serial transmission, the sci operates as described below. 1. when data is written to scftdr, the sci transfers the data to sctsr and starts transmitting. check that the tdfe flag is set to 1 in sc1ssr before writing transmit data to scftdr. the number of data bytes that can be written is at least {16 C (transmit trigger set number)}. 2. when data is transferred from scftdr to sctsr and transmission is started, transmit operations are performed continually until there is no transmit data left in scftdr. if the number of data bytes in scftdr falls to or below the transmit trigger number set in scfcr during transmission, the tdfe flag is set to 1. if the te bit setting in scscr is 1 at this time, a transmit-fifo-data-empty interrupt (txi) is requested. the serial transmit data is sent from the txd pin in the following order. a. start bit: one 0-bit is output. b. transmit data: 8-bit or 7-bit data is output in lsb-first or msb-first order according to the setting of the tlm bit in sc2ssr. c. multiprocessor bit: one multiprocessor bit (mpbt value) is output. d. stop bit(s): one or two 1-bits (stop bits) are output. e. mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. the sci checks for transmit data in scftdr at the timing for sending the stop bit. if there is data in scftdr, it is transferred to sctsr, the stop bit is sent, and then serial transmission of the next frame is started. if there is no transmit data in scftdr, the tend flag is set to 1 in sc1ssr, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. if the teie bit setting in scscr is 1 at this time, a transmit-end interrupt (tei) is requested. figure 14.11 shows an example of sci operation for transmission using a multiprocessor format. rev. 1.0, 08/99, page 551 of 875 serial data 1 0 d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 tdfe tend txi interrupt request start bit data multi- processor bit stop bit start bit multi- processor bit stop bit idle state (mark state) data written to scftdr and tdfe flag cleared to 0 by txi interrupt handler txi interrupt request one frame tei interrupt request figure 14.11 example of sci transmit operation (example with 8-bit data, multiprocessor bit, one stop bit, lsb-first transfer) multiprocessor serial data reception figure 14.12 shows a sample flowchart for multiprocessor serial reception. use the following procedure for multiprocessor serial data reception after enabling the sci for reception. rev. 1.0, 08/99, page 552 of 875 1. sci initialization: see figure 14.4, sample sci initialization flowchart. 2. id reception cycle: set the mpie bit to 1 in scscr. 3. sci status check, id reception and comparison: read sc1ssr and check that the rdf bit is set to 1, then read the receive data in the receive fifo data register (scfrdr) and compare it with this stations id. if the data is not this stations id, set the mpie bit to 1 again, and clear the rdf bit to 0. if the data is this stations id, clear the rdf bit to 0. 4. receive error handling and break detection: read the brk, dr, and er bits in sc2ssr to check whether a receive error has occurred. if a receive error occurs, read the orer and fer3 to 0 flags in sc1ssr, and the brk, dr, and er flags in sc2ssr to identify the error. after performing the appropriate error handling, ensure that the orer, brk, dr, and er bits are all cleared to 0. the setting of the ei bit in sc2ssr determines whether reception is continued or halted when the orer bit is set to 1. in the case of a framing error, a break can be detected by reading the value of the rxd pin. 5. sci status check and receive data read: read the serial status 1 register (sc1ssr) and check that rdf = 1, then read receive data from the receive fifo data register (scfrdr). start of reception set mpie bit to 1 in scscr read brk, dr, and er bits in sc2ssr initialization brk dr er = 1? read rdf flag in sc1ssr rdf = 1? read receive data from scfrdr, and clear rdf flag to 0 in sc1ssr this stations id? read brk, dr, and er bits in sc2ssr brk dr er = 1? read rdf flag in sc1ssr rdf = 1? read receive data from scfrdr all data received? clear re bit to 0 in scscr end of reception error handling yes yes no yes yes no no no yes yes no no 1 2 3 4 5 figure 14.12 sample multiprocessor serial reception flowchart (1) rev. 1.0, 08/99, page 553 of 875 1. whether a framing error has occurred in the receive data read from scfrdr can be ascertained from the fer bit in sc1ssr. 2. when a break signal is received, receive data is not transferred to scfrdr while the brk flag is set. however, note that the last data in scfrdr is h'00 and the break data in which a framing error occurred is stored. error handling clear re bit to 0 in scscr overrun error handling read receive data from scfrdr framing error handling clear orer, brk, dr, and er flags to 0 end orer = 1? brk = 1? dr = 1? fer = 1? all data read? no no no no 1 2 no yes yes yes yes yes figure 14.12 sample multiprocessor serial reception flowchart (2) rev. 1.0, 08/99, page 554 of 875 figure 14.13 shows an example of sci operation for multiprocessor format reception. 1 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 mpb mpb id1 id2 data2 serial data 1 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 mpb mpb idle state (mark state) mpie rdf scfrdr value id1 start bit data (id1) stop bit start bit stop bit data (data1) serial data mpie rdf scfrdr value start bit data (id2) stop bit start bit stop bit data (data2) idle state (mark state) rxi interrupt request (multiprocessor interrupt) mpie = 0 scfrdr data read and rdf flag cleared to 0 by rxi interrupt handler as data is not this stations id, mpie bit is set to 1 again rxi interrupt request is not generated, and scfrdr retains its state rxi interrupt request (multiprocessor interrupt) mpie = 0 scfrdr data read and rdf flag cleared to 0 by rxi interrupt handler as data matches this stations id, reception continues and data is received by rxi interrupt handler (a) data does not match stations id mpie bit set to 1 again (b) data matches stations id figure 14.13 example of sci receive operation (example with 8-bit data, multiprocessor bit, one stop bit, lsb-first transfer) rev. 1.0, 08/99, page 555 of 875 14.3.4 operation in synchronous mode in synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication using a common clock. both the transmitter and the receiver also have a 16-stage fifo buffer structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 14.14 shows the general format for synchronous serial communication. one unit of transfer data (character or frame) serial clock serial data lsb bit 0 msb * * dont care dont care note: * high except in continuous transmission/reception bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 figure 14.14 data format in synchronous communication in synchronous serial communication, data on the communication line is output from one fall of the serial clock to the next. data is guaranteed valid at the rise of the serial clock. in serial communication, each character is output starting with the lsb and ending with the msb, or vice versa, according to the setting of the tlm bit in the serial status 2 register (sc2ssr). after the last data is output, the communication line remains in the state of the last data. in synchronous mode, the sci receives data in synchronization with the fall of the serial clock. rev. 1.0, 08/99, page 556 of 875 transmit/receive format: a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock: either an internal clock generated by the built-in baud rate generator or an external serial clock input at the sck pin can be selected, according to the setting of the c/ a bit in scsmr and the cke1 and cke0 bits in scscr. for details of sci clock source selection, see table 14.9. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transfer of one character, and when no transmission/reception is performed the clock is fixed high. in receive-only operation, however, the sci receives two characters as one unit, and so a 16-pulse serial clock is output. to perform single-character receive operations, an external clock should be selected as the clock source. transmit/receive operations: sci initialization (synchronous mode) before transmitting and receiving data, it is necessary to clear the te and re bits to 0 in the serial control register (scscr), then initialize the sci as described below. when the operating mode, communication format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdfe flag is set to 1 and the transmit shift register (sctsr) is initialized. note that clearing the re bit to 0 does not change the contents of the rdf, per, fer, and orer flags, or the receive data register (scrdr). figure 14.15 shows a sample sci initialization flowchart. rev. 1.0, 08/99, page 557 of 875 initialization clear te and re bits to 0 in scscr read brk, dr, and er flags in sc2ssr, then clear them by writing 0 set tfrst and rfrst bits to 1 in scfcr, and clear fifo buffer set tie, rie, teie, cke1 and cke0 bits in scscr (leaving te and re bits cleared to 0) set transmit/receive format in scsmr set rtrg1 and 0 bits and ttrg1 and 0 bits in scfcr, and clear tfrst and rfrst bits to 0 pfc setting for external pins used (sck, txd, rxd) set value in scbrr 1-bit interval elapsed? set te or re bit to 1 in scscr end 1. clear bits te and re to 0 before end of initialization. 2. set enabling/disabling of txi, rxi, and tei interrupt requests. if interrupt requests are enabled, also make a setting in the intcs iprk register. 3. set the transmit/receive format in scsmr. when using irda mode, also set scimr. 4. write a value corresponding to the bit rate to the bit rate register (scbrr). not necessary if an external clock is used. wait for at least one bit interval after making this setting. 5. make pfc settings for the external pins to be used. make a setting for rxd input when receiving, and for txd output when transmitting. make an sck input/output setting according to the setting of bits cke1 and cke0. 6. set the te bit or re bit to 1 in scscr. the txd or rxd pin and the sck pin become available for use at this point. when transmitting, the txd pin goes to the mark state. when receiving in synchronous mode with serial clock output (clock master) set, clock output from the sck pin begins at this point. yes no wait 3 4 6 5 2 1 figure 14.15 sample sci initialization flowchart rev. 1.0, 08/99, page 558 of 875 serial data transmission (synchronous mode) figure 14.16 shows a sample flowchart for serial transmission. use the following procedure for serial data transmission after enabling the sci for transmission. end read tdfe flag in sc1ssr initialization write transmit data to scftdr and clear tdfe flag to 0 in sc1ssr tdfe = 1? all data transmitted? read tend flag in sc1ssr tend = 1? clear te bit to 0 in scscr start of transmission yes no no no 2 1 3 yes yes 1. sci initialization: see figure 14.15, sample sci initialization flowchart. 2. sci status check and transmit data write: read sc1ssr and check that the tdfe =1, then write transmit data to the transmit fifo data register (scftdr) and clear the tdfe flag to 0. 3. serial transmission continuation procedure: to continue serial transmission, read 1 from the tdfe flag to confirm that writing is possible, then write data to scftdr, and then clear the tdfe flag to 0. figure 14.16 sample serial transmission flowchart rev. 1.0, 08/99, page 559 of 875 in serial transmission, the sci operates as described below. 1. when data is written to the transmit fifo data register (scftdr), the sci transfers the data from scftdr to the transmit shift register (sctsr), and starts transmitting. check that the tdfe flag is set to 1 in the serial status 1 register (sc1ssr) before writing transmit data to scftdr. the number of data bytes that can be written is at least {16 C (transmit trigger set number)}. 2. when data is transferred from scftdr to sctsr and transmission is started, transmit operations are performed continually until there is no transmit data left in scftdr. if the number of data bytes in scftdr falls to or below the transmit trigger number set in the fifo control register (scfcr) during transmission, the tdfe flag is set. if the tie bit setting in the serial control register (scscr) is 1 at this time, a transmit-fifo-data-empty interrupt (txi) is requested. when clock output mode has been set, the sci outputs 8 serial clock pulses for one unit of data. when use of an external clock has been specified, data is output in synchronization with the input clock. the serial transmit data is sent from the txd pin starting with the lsb (bit 0) or msb (bit 7) according to the setting of the tlm bit in the serial status 2 register (sc2ssr). 3. the sci checks for transmit data in scftdr at the timing for sending the last bit. if there is data in scftdr, it is transferred to sctsr and then serial transmission of the next frame is started. if there is no transmit data in scftdr, the tend flag is set to 1 in the serial status 1 register (sc1ssr), the last bit is sent, and then the transmit data pin (txd) holds its state. if the transmit-end interrupt enable bit (teie) setting in scscr is 1 at this time, a transmit-end interrupt (tei) is requested. 4. after completion of serial transmission, the sck pin is fixed high. figure 14.17 shows an example of sci operation in transmission. rev. 1.0, 08/99, page 560 of 875 lsb tdfe tend bit 0 bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 transfer direction serial clock serial data txi interrupt request data written to scftdr and tdfe flag cleared to 0 by txi interrupt handler tei interrupt request one frame txi interrupt request msb figure 14.17 example of sci transmit operation serial data reception (synchronous mode) figure 14.18 shows a sample flowchart for serial reception. use the following procedure for serial data reception after enabling the sci for reception. when changing the operating mode from asynchronous to synchronous without resetting scfrdr and scftdr by means of sci initialization, be sure to check that the orer, per, and fer3 to fer0 flags are all cleared to 0. the rdf flag will not be set if any of flags fer3 to fer0 or per3 to per0 are set to 1, and neither transmit nor receive operations will be possible. rev. 1.0, 08/99, page 561 of 875 1. sci initialization: see figure 14.15, sample sci initialization flowchart. 2. receive error handling: if a receive error occurs, read the orer flag in sc1ssr , and after performing the appropriate error handling, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. 3. sci status check and receive data read: read the serial status 1 register (sc1ssr) and check that the rdf flag is set to 1, then read receive data from the receive fifo data register (scfrdr) and clear the rdf flag to 0. transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. 4. serial reception continuation procedure: to continue serial reception, read at least the receive trigger set number of data bytes from scfrdr, and write 0 to the rdf flag after reading 1 from it. the number of receive data bytes in scfrdr can be ascertained by reading the lower 8 bits of the fifo data count register (scfdr). (the rdf bit is cleared automatically when the dmac is activated by an rxi interrupt and the scfrdr value is read.) start of reception read orer flag in sc1ssr initialization error handling 2 3 4 1 read rdf flag in sc1ssr rdf = 1? read receive data from scfrdr, and clear rdf flag to 0 in sc1ssr all data received? clear re bit to 0 in scscr end of reception yes no yes no no yes orer = 1? figure 14.18 sample serial reception flowchart (1) rev. 1.0, 08/99, page 562 of 875 error handling overrun error handling yes no orer = 1? clear orer flag to 0 in sc1ssr end figure 14.18 sample serial reception flowchart (2) in serial reception, the sci operates as described below. 1. the sci performs internal initialization in synchronization with serial clock input or output. 2. the received data is stored in the receive shift register (scrsr) in lsb-to-msb order or msb-to-lsb order according to the setting of the rlm bit in sc2ssr. after reception, the sci checks whether the receive data can be transferred from scrsr to the receive fifo data register (scfrdr). if this check is passed, the receive data is stored in scfrdr. if a receive error is detected in the error check, the operation is as shown in table 14.11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. also, as the rdf flag is not set to 1 when receiving, the orer flag must be cleared to 0. 3. if the rie bit setting in the serial control register (scscr) is 1 when the rdf flag changes to 1, a receive-fifo-data-full interrupt (rxi) is requested. if the rie bit setting in scrsr is 1 when the orer flag changes to 1, a receive-error interrupt (eri) is requested. figure 14.19 shows an example of sci operation in reception. rev. 1.0, 08/99, page 563 of 875 serial clock serial data transfer direction data read from scfrdr and rdf flag cleared to 0 by rxi interrupt handler rxi interrupt request rdf orer bit 7 bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request eri interrupt request due to overrun error one frame figure 14.19 example of sci receive operation simultaneous serial data transmission and reception (synchronous mode) figure 14.20 shows a sample flowchart for simultaneous serial transmit and receive operations. use the following procedure for simultaneous serial data transmit and receive operations after enabling the sci for transmission and reception. rev. 1.0, 08/99, page 564 of 875 1. sci initialization: see figure 14.15, sample sci initialization flowchart. 2. sci status check and transmit data write: read sc1ssr and check that the tdfe flag is set to 1, then write transmit data to scftdr and clear the tdfe flag to 0. transition of the tdfe flag from 0 to 1 can also be identified by a txi interrupt. 3. receive error handling: if a receive error occurs, read the orer flag in sc1ssr , and after performing the appropriate error handling, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. 4. sci status check and receive data read: read sc1ssr and check that the rdf flag is set to 1, then read receive data from scfrdr and clear the rdf flag to 0. transition of the rdf flag from 0 to 1 can also be identified by an rxi interrupt. 5. serial transmission/reception continuation procedure: to continue serial transmission/ reception, finish reading the rdf flag, reading scfrdr, and clearing the rdf flag to 0, before the msb (bit 7) of the current frame is received. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdfe flag to confirm that writing is possible, then write data to scftdr and clear the tdfe flag to 0. note: when switching from transmitting or receiving to simultaneous transmitting and receiving, first clear the te bit and re bit to 0, then set the te bit and re bit to 1 simultaneously. read tdfe flag in sc1ssr initialization 1 2 4 5 3 write transmit data to scftdr and clear tdfe flag to 0 in sc1ssr read orer flag in sc1ssr read rdf flag in sc1ssr read receive data from scfrdr, and clear rdf flag to 0 in sc1ssr clear te and re bits to 0 in scrsr error handling start of transmission/ reception tdfe = 1? orer = 1? rdf = 1? all data transferred? end of transmission/ reception yes no yes no no yes yes no figure 14.20 sample flowchart for serial transmission and reception rev. 1.0, 08/99, page 565 of 875 14.3.5 use of transmit/receive fifo buffers the sci has independent 16-stage fifo buffers for transmission and reception. the configuration of these buffers is shown in figure 14.21. txd rxd sctsr t3C0 transmit data writes by cpu or dmac receive data reads by cpu or dmac r3C0 p p/g ed15C0 per3C0 sc1ssr fer3C0 1st stage 2nd stage 3rd stage data counter error counter 16th stage scftdr scfrdr sc1ssr scfer scrsr p f 16th stage 1st stage 2nd stage 3rd stage figure 14.21 transmit/receive fifo configuration rev. 1.0, 08/99, page 566 of 875 in serial data transmit operations: in transmission, when transmit data is written to the transmit fifo by the cpu or dmac and the te bit is set to 1 in the serial control register (scscr), the data is first transferred to the transmit shift register (sctsr) in the order of writing to the transmit fifo, a parity bit is added by the parity generator (p/g), and then serial data is transmitted from the txd pin. each time data is written into the transmit fifo, the value in bits t4 to t0 in the fifo data count register (scfdr) is incremented, and each time data is transferred to sctsr the value in bits t4 to t0 is decremented. the current number of data bytes in the transmit fifo can thus be found by reading bits t4 to t0 in scfdr. a value of h'10 in bits t4 to t0 means that data has been written into all 16 stages of the transmit fifo. if additional data is written to the fifo in this state, bits t4 to t0 will not be incremented and the written data will be lost. when the transmit trigger number is set and transmit data is written to the fifo by the dmac, if bit 17 (flag clear timing select (fcs)) in the dmac's dma channel control register (chcrn) is 0 and bit 6 (dreq select (ds)) is 1, even though tdfe in serial status register 1 (scissr) is cleared to 0 by execution of the dmac transfer, the dmac will continue to transfer data to the fifo until the value in the dma transfer count register reaches 0. in this case, therefore, care must be taken not to write data exceeding the number of empty bytes in scftdr indicated by the fifo control register (scfcr) (see section 14.2.10). in serial data receive operations: in reception, serial data input from the rxd pin is first captured in the receive shift register (scrsr) in the order specified by the rlm bit in the serial status 2 register (sc2ssr). a parity bit check is carried out, and if there is a parity error the p (parity error) flag for that data is set to 1. a stop bit check is also performed, and if a framing error is found the f (framing error) flag for that data is set to 1. the receive fifo buffer has a 10-bit configuration, with the p and f flags for each 8-bit data unit stored together with that data. receive fifo control in normal operation receive data held in the receive fifo buffer is read by the cpu or dmac. each time data is transferred from scrsr to the receive fifo, the value in bits r4 to r0 in scfdr is incremented, and each time the cpu or dmac reads receive data from the receive fifo, the value in bits r4 to r0 is decremented. the current number of data bytes in the receive fifo can thus be found by reading bits r4 to r0 in scfdr. a value of h'10 in bits r4 to r0 means that receive data has been transferred to all 16 stages of the receive fifo. if the next serial receive operation is completed before the cpu or dmac reads data from the fifo, an overrun error will result and the serial data will be lost. if receive fifo data is read when the value of bits r4 to r0 is h'00, an undefined value will be returned. rev. 1.0, 08/99, page 567 of 875 receive fifo control in error data reception when data is transferred from scrsr to the receive fifo, the p and f flags are also transferred. if either of these flags is set to 1, the error counter is incremented and the corresponding bit (per3 to per0, fer3 to fer0) is updated in the serial status 1 register (sc1ssr). the error counter is also incremented if the p or f flag is 1 when data in the receive fifo is read by the cpu or dmac. the settings of the p and f flags for the read receive data are also reflected in the per and fer flags in sc1ssr. per and fer are set when data containing a parity error or framing error is read from the receive fifo; they are not set when serial data containing a parity error or framing error is received from the rxd pin. per and fer are cleared when data with no parity error or framing error is read from the receive fifo. this data is transferred to the receive fifo even if it contains a parity error or framing error. whether or not the receive operation is to be continued at this point can be specified with the ei bit in sc2ssr. if the ei bit is set to 1, specifying continuation of the receive operation, receive data is still transferred sequentially to the receive fifo after an error occurs. the stage of the 16-stage fifo buffer in which the data with the error is located can be determined by reading bits ed15 to ed0 in the fifo error register (scfer). when the receive trigger number is set and receive data is read from the receive fifo by the dmac, care must be taken not to read data exceeding the receive trigger number indicated by the fifo control register (scfcr) (see section 14.2.10). fifo control by dr flag when a number of data bytes equal to or exceeding the receive trigger number have been received, a receive data read request is issued to the cpu or dmac by means of an rxi interrupt. however, an rxi interrupt is not requested if all reception has been completed with fewer than the receive trigger number of data bytes having been received. in this case, the dr flag is set and an eri interrupt is requested 15 etu after reception of the last data is completed. the cpu should therefore read bits r4 to r0 in scfdr to find the number of data bytes left in the receive fifo, and read all the data in the fifo. note: etu: elementary time unit = sec/bit an etu is equivalent to 1.5 frames with an 8-bit, 1-stop-bit format. rev. 1.0, 08/99, page 568 of 875 14.3.6 operation in irda mode in irda mode, the waveform of txd/rxd transmit/receive data is modified to comply with the irda 1.0 infrared communication specification. this makes it possible to carry out infrared transmission and reception conforming to the irda standard by connecting an infrared transmission/reception transceiver/receiver. in the irda 1.0 specification, communication is initially executed at 9600 bps, and then the transfer rate can be changed as required. however, the communication speed is not changed automatically in this module. when executing communication, therefore, it is necessary to check the communication speed and have the appropriate speed set in this module by software. note: in irda mode, reception is not possible when the te bit is set to 1 (enabling communication) in the serial control register (scscr). when performing reception, the te bit in scscr must be cleared to 0. transmission: in the case of a serial output signal (uart frame) from the sci, the waveform is corrected and the signal is converted to an ir frame serial output signal by the irda module as shown in figure 14.22. when the serial data is 0, if the psel bit is 0 in the irda mode register (scimr) a pulse of 3/16 the ir frame bit width is generated and output, and if the psel bit is 1 a pulse of 3/16 the bit width of the bit rate set in bits ick3 to 0 in the serial mode register (scsmr) is generated and output. when the serial data is 1, a pulse is not output. an infrared led is driven by a signal demodulated to a 3/16 width. reception: received pulses of 3/16 the ir frame bit width are converted to uart frames after demodulation as shown in figure 14.22. demodulation to 0 is executed for pulse output and demodulation to 1 when there is no pulse output. rev. 1.0, 08/99, page 569 of 875 0101001101 uart frame data start bit transmission reception stop bit 01 01 0011 01 ir frame data start bit bit cycle stop bit 3/16 bit cycle pulse width figure 14.22 irda mode transmit/receive operations pulse width selection: in transition, the ir frame pulse width can be selected as either 3/16 of the transmission bit rate or a smaller pulse width by means of the psel bit in the irda mode register (scimr). the sci includes a baud rate generator that generates the transmit frame bit rate and a baud rate generator that generates the irclk signal for varying the pulse width. when the psel bit is cleared to 0 in scimr, a width of 3/16 the bit rate set in the bit rate register (scbrr) is output as the ir frame pulse width. as the pulse width is the direct infrared emission time; if the user wishes to minimize the pulse width in order to reduce power consumption, the psel bit should be set to 1 in scimr and a setting should also be made in bits ick3 to ick0 in the serial mode register (scsmr) to generate the irclk signal, resulting in output with the minimum settable pulse width. rev. 1.0, 08/99, page 570 of 875 the minimum ir frame pulse width must be 3/16 of the 115.2 kbps bit rate (= 1.63 sec). with this minimum pulse width, irclk = 921.6 khz, and so the setting for bits ick3 to ick0 to give the minimum settable pulse width is given by the following equation. p f : operating clock frequency irclk: 921.6 khz (fixed) n: set value of ick3 to ick0 (0 n 15) n 3 2 irclk C 1 p f for example, when p f = 20 mhz, n = 10. table 14.12 shows the settings of bits ick3 to ick0 that can be used to obtain the minimum pulse width for various operating frequencies. table 14.12 bits ick3 to ick0 and operating frequencies in irda mode(when psel = 1) setting of bits ick3 to ick0 operating frequency p f f f f (mhz) ick3 ick2 ick1 ick0 2 0000 3 1 510 6 1 8 100 10 1 12 1 0 14 1 16 1000 18 1 20 1 0 21 1 22 1 23 100 24 1 25 1 26 1 0 27 0 28 1 rev. 1.0, 08/99, page 571 of 875 14.4 sci interrupt sources and the dmac the sci has four interrupt sources: the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-fifo-data-full interrupt (rxi) request, and transmit-fifo-data-empty interrupt (txi) request. table 14.13 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in scscr. each kind of interrupt request is sent to the interrupt controller independently. when the tdfe flag is set to 1 in the serial status register (sc1ssr), a txi interrupt is requested. a txi interrupt request can activate the on-chip dmac to perform data transfer. the tdfe bit is cleared to 0 automatically when all transmit fifo data register (scftdr) writes by the dmac are completed. when the rdf flag is set to 1 in sc1ssr, an rxi interrupt is requested. an rxi interrupt request can activate the on-chip dmac to perform data transfer. the rdf bit is cleared to 0 automatically when all receive fifo data register (scfrdr) reads by the dmac are completed. when the er or dr flag is set to 1 in sc2ssr, an eri interrupt is requested. the on-chip dmac cannot be activated by an eri interrupt request. when the tend flag is set to 1 in sc1ssr, a tei interrupt is requested. the on-chip dmac cannot be activated by a tei interrupt request. a txi interrupt indicates that transmit data can be written, and an rxi interrupt indicates that there is receive data in scfrdr. the tei interrupt indicates that the transmit operation has ended. table 14.13 sci interrupt sources interrupt source description dmac activation priority on reset release eri receive error (er or dr) not possible rxi receive fifo data register full (rdf) possible txi transmit fifo data register empty (tdfe) possible tei transmit end (tend) not possible high - ? low rev. 1.0, 08/99, page 572 of 875 14.5 usage notes the following points should be noted when using the sci. scftdr writing and the tdfe flag: the tdfe flag in the serial status 1 register (sc1ssr) is set when the number of transmit data bytes written in the transmit fifo data register (scftdr) has fallen to or below the transmit trigger number set by bits ttrg1 and ttrg0 in the fifo control register (scfcr). after tdfe is set, transmit data up to the number of empty bytes in scftdr can be written, allowing efficient continuous transmission. however, if the number of data bytes written in scftdr is equal to or less than the transmit trigger number, the tdfe flag will be set to 1 again after being read as 1 and cleared to 0. tdfe clearing should therefore be carried out when scftdr contains more than the transmit trigger number of transmit data bytes. the number of transmit data bytes in scftdr can be found from the upper 8 bits of the fifo data count register (scfdr). simultaneous multiple receive errors: if a number of receive errors occur at the same time, the state of the status flags in sc1ssr is as shown in table 14.14. if there is an overrun error, data is not transferred from the receive shift register (scrsr) to the receive fifo data register (scfrdr), and the receive data is lost. table 14.14 sc1ssr status flags and transfer of receive data sc1ssr status flags receive errors rdf orer fer per receive data transfer scrsr ? ? ? ? scfrdr overrun error 1 1 0 0 framing error 0 0 1 0 o parity error 0 0 0 1 o overrun error + framing error 1 1 1 0 overrun error + parity error 1 1 0 1 framing error + parity error 0 0 1 1 o overrun error + framing error + parity error 1111 o: receive data is transferred from scrsr to scfrdr. : receive data is not transferred from scrsr to scfrdr. break detection and processing: break signals can be detected by reading the rxd pin directly when a framing error (fer) is detected. in the break state the input from the rxd pin consists of all 0s, so the fer flag is set and the parity error flag (per) may also be set. note that although the sci stops transferring receive data to scfrdr after receiving a break, the receive operation continues, so if the fer and brk flags are cleared to 0 they will be set to 1 again. rev. 1.0, 08/99, page 573 of 875 sending a break signal: the txd pin is a general i/o pin whose input/output direction and level are determined by the i/o port data register (dr) and the control register (cr) of the pin function controller (pfc). this fact can be used to send a break signal. the dr value substitutes for the mark state until the pfc setting is made. the initial setting should therefore be as an output port outputting 1. to send a break signal during serial transmission, clear dr to 0, then set the txd pin as an output port with the pfc. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state. receive error flags and transmit operations (synchronous mode only): transmission cannot be started when a receive error flag (orer, per3 to 0, or fer3 to 0) is set to 1, even if the tdfe flag is set to 1. be sure to clear the receive error flags to 0 before starting transmission. note also that the receive error flags are not cleared to 0 by clearing the re bit to 0. receive data sampling timing and receive margin in asynchronous mode: the sci operates on a base clock with a frequency of 16, 8, or 4 times the transfer rate. in reception, the sci synchronizes internally with the fall of the start bit, which it samples on the base clock. receive data is latched at the rising edge of the eighth, fourth, or second base clock pulse. the timing is shown in figure 14.23. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 base clock 16 clocks 8 clocks C7.5 clocks +7.5 clocks start bit d0 d1 receive data (rxd) synchronization sampling timing data sampling timing figure 14.23 receive data sampling timing in asynchronous mode (using base clock with frequency of 16 times the transfer rate, sampled in 8th clock cycle) rev. 1.0, 08/99, page 574 of 875 the receive margin in asynchronous mode can therefore be expressed as shown in equation (1). m = 0.5 C 1 2n d C 0.5 n C (l C 0.5) f C (1 + f) 100% ......................... (1) m: receive margin (%) n: ratio of clock frequency to bit rate (n = 16, 8, or 4) d: clock duty cycle (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute deviation of clock frequency from equation (1), if f = 0 and d = 0.5, the receive margin is 46.875%, as given by equation (2). when d = 0.5, f = 0, and n = 16: m = (0.5 C 1/(2 16)) 100% = 46.875% ............................................................................................. (2) this is a theoretical value. a reasonable margin to allow in system designs is 20% to 30%. when using synchronous external clock mode: do not set te or re to 1 until at least 4 peripheral operating clock cycles after external clock sck has changed from 0 to 1. only set both te and re to 1 when external clock sck is 1. in reception, note that if re is cleared to 0 from 2.3 to 3.5 peripheral operating clock cycles after the rising edge of the rxd d7 bit sck input, rdf will be set to 1 but copying to scfrdr will not be possible. when using synchronous internal clock mode: in reception, note that if re is cleared to 0 1.5 peripheral operating clock cycles after the rising edge of the rxd d7 bit sck output, rdf will be set to 1 but copying to scfrdr will not be possible. when using the dmac: when an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 p f clock cycles after scftdr is updated by the dmac. incorrect operation may result if the transmit clock is input within 4 p f cycles after scftdr is updated. (see figure 14.24.) when performing scfrdr reads by the dmac, be sure to set the relevant sci receive-fifo- data-full interrupt (rxi) as an activation source. rev. 1.0, 08/99, page 575 of 875 sck tdfe txd d0 d1 d2 d3 d4 d5 d6 t figure 14.24 example of synchronous transmission by dmac scfrdr reading and the rdf flag: the rdf flag in the serial status 1 register (sc1ssr) is set when the number of receive data bytes in the receive fifo data register (scfrdr) has become equal to or greater than the receive trigger number set by bits rtrg1 and rtrg0 in the fifo control register (scfcr). after rdf is set, receive data equivalent to the trigger number can be read from scfrdr, allowing efficient continuous reception. however, if the number of data bytes in scfrdr is equal to or greater than the trigger number, the rdf flag will be set to 1 again if it is cleared to 0. rdf should therefore be cleared to 0 after being read as 1 after receive data has been read to reduce the number of data bytes in scfrdr to less than the trigger number. the number of receive data bytes in scfrdr can be found from the lower 8 bits of the fifo data count register (scfdr). rev. 1.0, 08/99, page 577 of 875 section 15 a/d converter 15.1 overview the on-chip a/d converter has 10-bit resolution and allows selection of up to 8 analog input channels. the a/d converter is composed of two independent modules, a/d0 and a/d1. 15.1.1 features the a/d converter has the following features: 10-bit resolution eight input channels (4 channels 2) conversion time minimum conversion time (per channel): 6.7 s (20 mhz, cks = 1) operating frequency: p f > 20 mhz, cks = 0 p f 20 mhz, cks = 0, 1 choice of conversion mode single mode or multi mode can be selected. conversion can be carried out simultaneously on two channels. three conversion start methods software, timer conversion start trigger (mmt), tpu or adtrg pin can be selected. eight a/d data registers conversion results are held in 16-bit data registers for each channel. sample and hold function a/d conversion end interrupt an a/d conversion end interrupt (adi) can be requested on completion of a/d conversion. the dmac can be activated by adi0 (a/d0 interrupt request) and adi1 (a/d1 interrupt request). 15.1.2 block diagram figure 15.1 shows a block diagram of the a/d converter. av cc and av ss for both a/d modules are common pins in the chip. rev. 1.0, 08/99, page 578 of 875 control circuit comparator sample-and-hold circuit 10-bit d/a a/d0 module data bus adcr0 adcsr0 addrd0 addrc0 addrb0 addra0 + C avcc avss an0 an1 an2 an3 a/d1 module data bus adcr1 adcsr1 addrd1 addrc1 addrb1 addra1 avcc avss an4 an5 an6 an7 tpu trigger mmt trigger signal trigger or circuit interrupt signal adi1 bus interface analog multiplexer successive- approximations register interrupt signal adi0 bus interface 10-bit d/a analog multiplexer sample-and-hold circuit comparator control circuit + C successive- approximations register adcr0: a/d0 control register adcsr0: a/d0 control/status register addra0: a/d0 data register a addrb0: a/d0 data register b addrc0: a/d0 data register c addrd0: a/d0 data register d adcr1: a/d1 control register adcsr1: a/d1 control/status register addra1: a/d1 data register a addrb1: a/d1 data register b addrc1: a/d1 data register c addrd1: a/d1 data register d figure 15.1 block diagram of a/d converter rev. 1.0, 08/99, page 579 of 875 15.1.3 pin configuration figure 15.1 shows the pins used by the a/d converter. av cc and av ss are power supply pins for the analog circuits in the a/d converter. table 15.1 a/d converter pins pin name abbreviation i/o function analog power supply av cc input analog circuit power supply analog ground av ss input analog circuit ground and a/d conversion reference voltage a/d0 analog input 0 an0 input analog input channel 0 analog input 1 an1 input analog input channel 1 analog input 2 an2 input analog input channel 2 analog input 3 an3 input analog input channel 3 a/d1 analog input 4 an4 input analog input channel 4 analog input 5 an5 input analog input channel 5 analog input 6 an6 input analog input channel 6 analog input 7 an7 input analog input channel 7 a/d external trigger input adtrg input external trigger for starting a/d conversion rev. 1.0, 08/99, page 580 of 875 15.1.4 register configuration table 15.2 summarizes the a/d converters registers. table 15.2 a/d converter registers name abbreviation r/w initial value address access size a/d0 data register ah addra0h r h'00 h'ffff0080 8, 16 a/d0 data register al addra0l r h'00 h'ffff0081 8, 16 a/d0 data register bh addrb0h r h'00 h'ffff0082 8, 16 a/d0 data register bl addrb0l r h'00 h'ffff0083 8, 16 a/d0 data register ch addrc0h r h'00 h'ffff0084 8, 16 a/d0 data register cl addrc0l r h'00 h'ffff0085 8, 16 a/d0 data register dh addrd0h r h'00 h'ffff0086 8, 16 a/d0 data register dl addrd0l r h'00 h'ffff0087 8, 16 a/d0 control/status register adcsr0 r/(w) * h'00 h'ffff0098 8 a/d0 control register adcr0 r/w h'3f h'ffff0099 8 a/d1 data register ah addra1h r h'00 h'ffff00a0 8, 16 a/d1 data register al addra1l r h'00 h'ffff00a1 8, 16 a/d1 data register bh addrb1h r h'00 h'ffff00a2 8, 16 a/d1 data register bl addrb1l r h'00 h'ffff00a3 8, 16 a/d1 data register ch addrc1h r h'00 h'ffff00a4 8, 16 a/d1 data register cl addrc1l r h'00 h'ffff00a5 8, 16 a/d1 data register dh addrd1h r h'00 h'ffff00a6 8, 16 a/d1 data register dl addrd1l r h'00 h'ffff00a7 8, 16 a/d1 control/status register adcsr1 r/(w) * h'00 h'ffff00b8 8 a/d1 control register adcr1 r/w h'3f h'ffff00b9 8 note: * bit 7 can only be written with 0, to clear the flag. rev. 1.0, 08/99, page 581 of 875 15.2 register descriptions 15.2.1 a/d data registers a to d (addra0 to addrd0, addra1 to addrd1) bit: 15 14 13 12 11 10 9 8 addrn ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 initial value:00000000 r/w:rrrrrrrr bit:76543210 addrn ad1 ad0 initial value:00000000 r/w:rrrrrrrr (n = a to d) the a/d data registers (addr) are 16-bit read-only registers that store the results of a/d conversion. there are eight registers, addra0 to addrd0, addra1 to addrd1. the result of a/d conversion is 10-bit data which is transferred to and stored in the addr register for the selected channel. the upper 8 bits of the converted data correspond to the upper byte of addr, and the lower 2 bits correspond to the lower byte. bits 5 to 0 of the lower byte of addr are reserved, and are always read as 0. table 15.3 shows the correspondence between the analog input channels and the a/d data registers. the addr registers can be read by the cpu at all times. the upper byte is read directly, but the lower byte data is transferred via a temporary register (temp). for details, see section 15.3, cpu interface. the addr registers are initialized to h'0000 by a power-on reset and in standby mode. rev. 1.0, 08/99, page 582 of 875 table 15.3 analog input channels and a/d data registers analog input channel a/d data register module an0 addra0 a/d0 an1 addrb0 an2 addrc0 an3 addrd0 an4 addra1 a/d1 an5 addrb1 an6 addrc1 an7 addrd1 15.2.2 a/d control/status registers (adcsr0, adcsr1) bit:76543210 adf adie adst multi cks ch1 ch0 initial value:00000000 r/w: r/(w) * r/w r/w r/w r/w r r/w r/w note: * only 0 can be written, to clear the flag. the a/d control/status registers (adcsr0, adcsr1) are 8-bit readable/writable registers that perform a/d converter operation control, including selection of the a/d conversion mode. adcsr0 is used for a/d0, and adcsr1 for a/d1. the adcsr registers are initialized to h'00 by a power-on reset and in standby mode. bit 7a/d end flag (adf): indicates the end of a/d conversion. bit 7: adf description 0 [clearing conditions] (initial value) when 0 is written to adf after reading adf = 1 when the dmac is activated by and adi interrupt, and an a/d converter register is accessed 1 [setting conditions] single mode: when a/d conversion ends multi mode: when a/d conversion ends on all selected channels rev. 1.0, 08/99, page 583 of 875 bit 6a/d interrupt enable (adie): enables or disables the interrupt request (adi) at the end of a/d conversion. bit 6: adie description 0 a/d end interrupt request (adi) is disabled (initial value) 1 a/d end interrupt request (adi) is enabled bit 5a/d start (adst): starts or stops a/d conversion. the adst bit remains set to 1 during a/d conversion. it can also be set to 1 by a conversion start trigger from a timer (mmt, tpu), and by means of the a/d conversion trigger input pin ( adtrg ). bit 5: adst description 0 a/d conversion is stopped (initial value) 1 single mode: a/d conversion is started. adst is automatically cleared to 0 when a/d conversion ends on the specified channel. multi mode: a/d conversion is started. conversion continues, once on each channel in turn, until adst is cleared to 0 by software. bit 4multi mode (multi): selects single mode or multi mode as the a/d conversion mode. for details of the operation in single mode and multi mode, see section 15.4, operation. change the mode only when adst = 0. bit 4: multi description 0 single mode (initial value) 1 multi mode bit 3clock select (cks): sets the a/d conversion time. change the conversion time only when adst = 0. bit 3: cks description 0 conversion time = 266 states (max.) (initial value) 1 conversion time = 134 states (max.) bit 2reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 584 of 875 bits 1 and 0channel select 1 and 0 (ch1, ch0): these bits, together with the multi mode bit, select the analog input channels. change the channel selection only when adst = 0. channel select bits description single mode multi mode ch1 ch0 a/d0 a/d1 a/d0 a/d1 0 0 an0 (initial value) an4 (initial value) an0 an4 1 an1 an5 an0, an1 an4, an5 1 0 an2 an6 an0Can2 an4Can6 1 an3 an7 an0Can3 an4Can7 15.2.3 a/d control registers (adcr0, adcr1) bit:76543210 trge1trge0 initial value:00111111 r/w:r/wr/wrrrrrr the a/d control registers (adcr0, adcr1) are 8-bit readable/writable registers that enable or disable starting of a/d conversion by external trigger input. adcr0 is used for a/d0, and adcr1 for a/d1. the adcr registers are initialized to h'3f by a power-on reset and in standby mode. bits 7 and 6trigger enable (trge1, trge0): these bits enable or disable starting of a/d conversion by input of an adtrg pin or an mmt or tpu trigger. bit 7: trge1 bit 6: trge0 description 0 0 start of a/d conversion by adtrg pin or mtt/tpu trigger input is disabled (initial value) 1 a/d conversion is started at mmt or tpu trigger input 1 0 start of a/d conversion by adtrg pin or mtt/tpu trigger input is enabled 1 a/d conversion is started at falling edge of adtrg pin the adtrg pin and the mmt/tpu trigger are shared by a/d0 and a/d1. the settings for a/d0 and a/d1 are ored. bits 5 to 0reserved: these bits are always read as 1 and should only be written with 1. rev. 1.0, 08/99, page 585 of 875 15.3 cpu interface the a/d data registers (addra0 to addrd0, addra1 to addrd1) are 16-bit registers, but they are connected to the cpu by an 8-bit data bus. therefore, the upper and lower bytes of these registers must be read separately. to prevent the data being changed between the reads of the upper and lower bytes of an a/d data register, the lower byte is read via a temporary register (temp). the upper byte can be read directly. data is read from an a/d data register as follows. when the upper byte is read, the upper-byte value is transferred directly to the cpu and the lower-byte value is transferred into temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when performing byte-size reads on an a/d data register, always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. if a word-size read is performed on an a/d data register, reading is performed in upper byte, lower byte order automatically. figure 15.2 shows the data flow when reading an a/d data register. rev. 1.0, 08/99, page 586 of 875 upper-byte read cpu (h'aa) bus interface module data bus (8 bits) transfer addrnh (h'aa) addrnl (h'40) temp (h'40) lower-byte read cpu (h'40) bus interface module data bus (8 bits) addrnh (h'aa) addrnl (h'40) temp (h'40) figure 15.2 a/d data register access operation (reading h'aa40) rev. 1.0, 08/99, page 587 of 875 15.4 operation the a/d converter operates by successive approximations with 10-bit resolution. it has two operating modes: single mode and multi mode. the operation in these two modes is described below. 15.4.1 single mode (multi = 0) single mode should be selected for a/d conversion on only one channel. a/d conversion starts when the adst bit in the a/d control/status register (adcsr) is set to 1 by software or external trigger input. the adst bit remains set to 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. when conversion ends, the adf bit in adcsr is set to 1. if the adie bit in adcsr is also 1, an adi interrupt is requested. to clear the adf bit, first read adf when set to 1, then write 0 to adf. to prevent incorrect operation, a/d conversion should be halted by clearing the adst bit to 0 before changing the mode or analog input channel. after the change is made, a/d conversion is restarted by setting the adst bit to 1 (the mode or channel change and setting of the adst bit can be carried out simultaneously). an example of the operation when channel 1 (an1) is selected and a/d conversion is performed in single mode is described below. figure 15.3 shows a timing diagram for this example (bit specifications in the operation example refer to the adcsr0 register). 1. single mode is selected (multi = 0), input channel an1 is selected (ch1 = 0, ch0 = 1), the a/d interrupt request is enabled (adie = 1), and a/d conversion is started (adst = 1). 2. when a/d conversion ends, the result is transferred to addrb0. at the same time adf is set to 1, adst is cleared to 0, and the a/d converter becomes idle. 3. since adf = 1 and adie = 1, an adi interrupt is requested. 4. the a/d interrupt service routine is started. 5. the routine reads adf set to 1, then writes 0 to adf. 6. the routine reads and processes the conversion result (addrb0). 7. execution of the a/d interrupt service routine ends. after this, if the adst bit is set to 1, a/d conversion starts again and steps (2) to (7) are repeated. rev. 1.0, 08/99, page 588 of 875 adie adst adf channel 0 (an0) operating state channel 1 (an1) operating state channel 2 (an2) operating state channel 3 (an3) operating state addra addrb addrc addrd start of a/d conversion idle idle idle conversion result read conversion result read idle a/d conversion (1) a/d conversion (2) a/d conversion result (1) a/d conversion result (2) idle idle set * set * set * clear * clear * note: * vertical arrows ( ) indicate instructions executed by software. figure 15.3 example of a/d converter operation (single mode, channel 1 selected) rev. 1.0, 08/99, page 589 of 875 15.4.2 multi mode multi mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit in the a/d control/status register (adcsr) is set to 1 by software or external trigger input, a/d conversion starts on the first channel in the group (an0 in a/d0, or an4 in a/d1). when more than one channel has been selected, a/d conversion starts on the second channel (an1 or an5) as soon as conversion ends on the first channel. after a/d conversion has been performed once on each of the selected channels, the adst bit is cleared to 0 automatically. the conversion results are transferred to and stored in the addr register for each channel. to prevent incorrect operation, a/d conversion should be halted by clearing the adst bit to 0 before changing the mode or analog input channels. after the change is made, the first channel is selected and a/d conversion is restarted by setting the adst bit to 1 (the mode or channel change and setting of the adst bit can be carried out simultaneously). an example of the a/d conversion operation in multi mode when three channels (an0 to an2) in group 0 are selected is described below. figure 15.4 shows a timing diagram for this example (bit specifications in the operation example refer to the adcsr0 register). 1. multi mode is selected (multi = 1), analog input channels an0 to an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1). 2. a/d conversion starts on the first channel (an0), and when completed, the result is transferred to addra0. conversion then starts automatically on the second channel (an1). 3. conversion proceeds in the same way through the third channel (an2). 4. when conversion is completed for all the selected channels (an0 to an2), adf is set to 1 adst is cleared to 0, and conversion stops. if the adie bit is 1, an adi interrupt is requested when conversion ends. when the adst bit is cleared to 0, a/d conversion stops. 5. adf is read while set to 1, then written with 0. after this, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0). rev. 1.0, 08/99, page 590 of 875 adst adf idle idle a/d conversion (1) idle idle idle a/d conversion result (2) a/d conversion result (3) transfer channel 0 (an0) operating state channel 1 (an1) operating state channel 2 (an2) operating state channel 3 (an3) operating state addra addrb addrc addrd note: * vertical arrows ( ) indicate instructions executed by software. set * clear * a/d conversion (2) idle idle a/d conversion (3) continuous a/d conversion a/d conversion result (1) figure 15.4 example of a/d converter operation (multi mode, channels an0 to an2 selected) rev. 1.0, 08/99, page 591 of 875 15.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample and hold circuit. the a/d converter samples the analog input at time t d after access to the a/d control/status register (adcsr) is started, then starts conversion. figure 15.5 shows the a/d conversion timing, and table 15.4 shows a/d conversion times. as shown in figure 15.5, a/d conversion time t conv includes a/d conversion start delay time t d and analog input sampling time t spl . the length of t d is not fixed, but is determined by the timing of the write to adscr. the total conversion time therefore varies within the ranges shown in table 15.4. in multi mode, the t conv values given in table 15.4 apply to the first conversion. in the second and subsequent conversions, t conv is fixed at 266 states (p f ) when cks = 0, or 134 states (p f ) when cks = 1. (1) (2) p f adf address write signal input sampling timing t d t spl t conv (1): adcsr write cycle (2): adcsr address t d : a/d conversion start delay time t spl : input sampling time t conv : a/d conversion time figure 15.5 a/d conversion timing rev. 1.0, 08/99, page 592 of 875 table 15.4 a/d conversion times (single mode) cks = 0 cks = 1 symbol min typ max min typ max a/d conversion start delay time t d 1017 6 9 input sampling time t spl 64 32 a/d conversion time t conv 259 266 131 134 note: unit: states (p f ) 15.4.4 external trigger input timing a/d conversion can also be started by external trigger input. when the trge bit is set to 1 in the a/d control register (adcr), an external trigger is input from the adtrg pin, or from the mmt or tpu. when a falling edge on the adtrg input pin or an mmt trigger is detected, the adst bit is set to 1 in the a/d control/status register (adst), and a/d conversion starts. other operations, for both single mode and multi mode, are the same as when the adst bit is set to 1 by software. figure 15.6 shows the timing for external trigger input. a/d conversion p f external trigger signal adst figure 15.6 timing of external trigger input by means of adtrg adtrg adtrg adtrg pin rev. 1.0, 08/99, page 593 of 875 15.5 interrupt sources and dma transfer requests the a/d converter generates an a/d conversion end interrupt (adi) on completion of a/d conversion. the adi interrupt can be enabled or disabled with the adie bit in adcsr. dma transfer can be initiated by an adi interrupt. when the dmac is activated by an adi interrupt, the adf bit in the a/d control/status register (adcsr) is automatically cleared to 0 when an a/d register is accessed. 15.6 a/d conversion accuracy definitions the a/d converter converts analog values input from analog input channels to 10-bit digital values by comparing them with an analog reference voltage. in this operation, the absolute accuracy of the a/d conversion (i.e. the deviation between the input analog value and the output digital value) includes the following kinds of error. 1. offset error 2. full-scale error 3. quantization error 4. nonlinearity error the above four kinds of error are described below with reference to figure 15.7. for the sake of clarity, this figure shows 3-bit a/d conversion rather than 10-bit a/d conversion. offset error (see figure 15.7 (1)) is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic when the digital output value changes from the minimum value (zero voltage) of 0000000000 (000 in the figure) to 0000000001 (001 in the figure ). full-scale error (see figure 15.7 (2)) is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic when the digital output value changes from 1111111110 (110 in the figure) to the maximum value (full-scale voltage) of 1111111111 (111 in the figure). quantization error is the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 15.7 (3)). nonlinearity error is the deviation between the actual a/d conversion characteristic and the ideal a/d conversion characteristic from zero voltage to full-scale voltage (see figure 15.7 (4)). this does not include offset error, full-scale error, and quantization error. rev. 1.0, 08/99, page 594 of 875 0 1/8 2/8 3/8 4/8 5/8 6/8 7/8 fs 111 110 101 100 011 010 001 000 analog input voltage (3) quantization error (4) nonlinearity error (2) full-scale error ideal a/d conversion characteristic digital output fs: full-scale voltage fs analog input voltage actual a/d conversion characteristic (1) offset error ideal a/d conversion characteristic digital output figure 15.7 a/d conversion accuracy definitions 15.7 usage notes the following points should be noted when using the a/d converter. 15.7.1 analog voltage settings 1. analog input voltage range the voltage applied to analog input pins during a/d conversion should be in the range av ss ann av cc (n = 0 to 7). 2. av cc and av ss input voltages for the av cc and av ss input voltages, set av cc = v cc 10%, and av ss = v ss . when the a/d converter is not used, set av cc = v cc and av ss = v ss . 3. av cc must be connected to the power supply (v cc ) even when the a/d converter is not used, and in standby mode. rev. 1.0, 08/99, page 595 of 875 15.7.2 handling of analog input pins to prevent damage from surges and other abnormal voltages at the analog input pins (an0-an7), a protection circuit such as that shown in figure 15.8 should be connected. this circuit also includes a cr filter function that suppresses error due to noise. the circuit shown here is only a design example; circuit constants must be decided on the basis of the actual operating conditions. figure 15.9 shows an equivalent circuit for the analog input pins, and table 15.5 summarizes the analog input pin specifications. sh7065 av cc an0Can7 av ss 100 w * note: * 0.1 m f 10 m f 0.01 m f figure 15.8 example of analog input pin protection circuit (preliminary) rev. 1.0, 08/99, page 596 of 875 an0 C an7 1.0 k w 20 pf 1 m w analog multiplexer a/d converter note: values are reference values (preliminary). figure 15.9 analog input pin equivalent circuit (preliminary) table 15.5 analog input pin specifications (preliminary) item min max unit analog input capacitance 20 pf permissible signal source impedance 1 k w 15.7.3 note on ph0 and ph1 output the ph0 and ph1 outputs must not be changed during a/d conversion, as the conversion accuracy cannot be guaranteed in this case. 15.7.4 port i pfc settings function switching for port i pins, which are used as a/d converter analog input pins, is performed automatically when a/d conversion is started, so no pfc settings are necessary for port i. rev. 1.0, 08/99, page 597 of 875 section 16 d/a converter 16.1 overview the sh7065 includes a two-channel d/a converter. 16.1.1 features the d/a converter has the following features: 8-bit resolution two output channels conversion time: maximum 10 s (with 20 pf capacitive load) output voltage: 0 v to av cc 16.1.2 block diagram figure 16.1 shows a block diagram of the d/a converter. av cc da 0 da 1 dacr dadr0 dadr1 module data bus internal data bus control circuit 8-bit d/a av ss bus interface figure 16.1 block diagram of d/a converter rev. 1.0, 08/99, page 598 of 875 16.1.3 pin configuration table 16.1 summarizes the input and output pins of the d/a converter. table 16.1 d/a converter pins pin name abbreviation i/o function analog power supply pin av cc input analog power supply analog ground pin av ss input analog ground and reference voltage analog output pin 0 da0 output channel 0 analog output analog output pin 1 da1 output channel 1 analog output 16.1.4 register configuration table 16.2 summarizes the registers of the d/a converter. table 16.2 d/a converter registers name abbreviation r/w initial value address access size d/a data register 0 dadr0 r/w h'00 h'ffff00c0 8, 16 d/a data register 1 dadr1 r/w h'00 h'ffff00c1 8, 16 d/a control register dacr r/w h'1f h'ffff00c2 8, 16 rev. 1.0, 08/99, page 599 of 875 16.2 register descriptions 16.2.1 d/a data registers 0 and 1 (dadr0, dadr1) bit:76543210 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w d/a data registers 0 and 1 (dadr0 and dadr1) are 8-bit readable/writable registers that store the data to be converted. when analog output is enabled, the values in dadr0 and dadr1 are constantly converted and output at the analog output pins. the d/a data registers are initialized to h'00 by a reset and in standby mode. 16.2.2 d/a control register (dacr) bit:76543210 daoe1daoe0dae initial value:00011111 r/w:r/wr/wr/w the d/a control register (dacr) is an 8-bit readable/writable register that controls the operation of the d/a converter. dacr is initialized to h'1f by a reset and in standby mode. bit 7d/a output enable 1 (daoe1): controls d/a conversion and analog output. bit 7: daoe1 description 0 da1 analog output is disabled (initial value) 1 channel 1 d/a conversion and da1 analog output are enabled bit 6d/a output enable 0 (daoe0): controls d/a conversion and analog output. bit 6: daoe0 description 0 da0 analog output is disabled (initial value) 1 channel 0 d/a conversion and da0 analog output are enabled rev. 1.0, 08/99, page 600 of 875 bit 5d/a enable (dae): controls d/a conversion, together with bits daoe0 and daoe1. when the dae bit is cleared to 0, d/a conversion is controlled independently in channels 0 and 1. description channel 1 channel 0 bit 7: daoe1 bit 6: daoe0 bit 5: dae d/a conversion analog output d/a conversion analog output 000halted halted 1executed halted 10halted 1executed halted executed executed 100 halted 1 halted 10 1 executed executed executed executed when the dae bit is set to 1, even if bits daoe0 and daoe1 in dacr and the adst bit in adcsr are cleared to 0, the same current is drawn from the analog power supply as during simultaneous a/d and d/a conversion. bits 4 to 0reserved: read-only bits, always read as 1. rev. 1.0, 08/99, page 601 of 875 16.3 operation the d/a converter has two built-in d/a conversion circuits that can perform conversion independently. d/a conversion is performed constantly while enabled in dacr. if the dadr0 or dadr1 value is modified, conversion of the new data begins immediately. the conversion results are output when bits daoe0 and daoe1 are set to 1. an example of d/a conversion on channel 0 is given below. the timing is shown in figure 16.2. 1. data to be converted is written in dadr0. 2. bit daoe0 is set to 1 in dacr. d/a conversion starts and da0 becomes an output pin. the conversion result is output after the conversion time. the output value is (dadr0 contents/256) av cc . output of this conversion result continues until the value in dadr0 is modified or the daoe0 bit is cleared to 0. 3. if the dadr0 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. when the daoe0 bit is cleared to 0, da0 becomes an input pin. dadr0 write cycle t dconv high-impedance state conversion result 1 conversion data 1 conversion data 2 conversion result 2 t dconv p f address dadr0 daoe0 da 0 t dconv : d/a conversion time dacr write cycle dadr0 write cycle dacr write cycle figure 16.2 example of d/a converter operation rev. 1.0, 08/99, page 602 of 875 16.4 usage note if the digital output at the ph1 pin is changed during analog output from the da0 pin, noise may be introduced into the da0 analog output. similarly, if the digital output at the ph0 pin is changed during analog output from the da1 pin, noise may be introduced into the da1 analog output. caution is therefore necessary if the ph0 or ph1 output level is changed during analog output. da0 and da1 pin settings should be made with the port h pfc. rev. 1.0, 08/99, page 603 of 875 section 17 pin function controller (pfc) 17.1 overview the pin function controller (pfc) consists of registers for selecting multiplex pin functions and their input/output direction. table 17.1 shows the sh7065s multiplex pins. the functions of the multiplex pins are determined by the operating mode. table 17.2 shows the pin functions in each operating mode, together with the initial functions. table 17.1 multiplex pins (port a) (1) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) function 5 (related module) a pa25 i/o (port) cs5 output (bsc) pa24 i/o (port) cs4 output (bsc) pa23 i/o (port) cs3 output (bsc) pa22 i/o (port) cs2 output (bsc) pa21 i/o (port) cs1 output (bsc) pa20 i/o (port) cs0 output (bsc) pa19 i/o (port) bs output (bsc) pa18 i/o (port) rd output (bsc) pa17 i/o (port) wr output (bsc) pa16 i/o (port) wrhh output (bsc) hhbs output (bsc) tclkc input (tpu) tioc3a i/o (tpu) pa15 i/o (port) wrhl output (bsc) hlbs output (bsc) tclkd input (tpu) tioc3b i/o (tpu) pa14 i/o (port) wrlh output (bsc) lhbs output (bsc) pa13 i/o (port) wrll output (bsc) llbs output (bsc) pa12 i/o (port) wait input (bsc) pa9 i/o (port) ras1 output (bsc) pa8 i/o (port) ras0 output (bsc) pa1 i/o (port) oe1 output (bsc) pa0 i/o (port) oe0 output (bsc) rev. 1.0, 08/99, page 604 of 875 table 17.1 multiplex pins (port b) (2) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) function 5 (related module) b pb23 i/o (port) cashh1 output (bsc) txd1 output (sci) tend0 output (dmac) pb22 i/o (port) cashl1 output (bsc) rxd1 input (sci) tend1 output (dmac) pb21 i/o (port) caslh1 output (bsc) pb20 i/o (port) casll1 output (bsc) pb19 i/o (port) cashh0 output (bsc) txd0 output (sci) pb18 i/o (port) cashl0 output (bsc) rxd0 input (sci) pb17 i/o (port) caslh0 output (bsc) pb16 i/o (port) casll0 output (bsc) pb13 i/o (port) rdwr output (bsc) pb7 i/o (port) back output (bsc) pb6 i/o (port) breq input (bsc) rev. 1.0, 08/99, page 605 of 875 table 17.1 multiplex pins (port c) (3) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) c pc25 i/o (port) a25 output (bsc) tioc3b i/o (tpu) tclkd input (tpu) pc24 i/o (port) a24 output (bsc) tioc3a i/o (tpu) tclkc input (tpu) pc23 i/o (port) a23 output (bsc) tioc1b i/o (tpu) tclkb input (tpu) pc22 i/o (port) a22 output (bsc) tioc1a i/o (tpu) tclka input (tpu) pc21 i/o (port) a21 output (bsc) tioc5b i/o (tpu) pc20 i/o (port) a20 output (bsc) tioc5a i/o (tpu) pc19 i/o (port) a19 output (bsc) tioc4b i/o (tpu) pc18 i/o (port) a18 output (bsc) tioc4a i/o (tpu) pc17 i/o (port) a17 output (bsc) tioc3b i/o (tpu) pc16 i/o (port) a16 output (bsc) tioc3a i/o (tpu) pc15 i/o (port) a15 output (bsc) tioc3d i/o (tpu) pc14 i/o (port) a14 output (bsc) tioc3c i/o (tpu) pc13 i/o (port) a13 output (bsc) pc12 i/o (port) a12 output (bsc) pc11 i/o (port) a11 output (bsc) pc10 i/o (port) a10 output (bsc) pc9 i/o (port) a9 output (bsc) pc8 i/o (port) a8 output (bsc) pc7 i/o (port) a7 output (bsc) pc6 i/o (port) a6 output (bsc) pc5 i/o (port) a5 output (bsc) pc4 i/o (port) a4 output (bsc) pc3 i/o (port) a3 output (bsc) pc2 i/o (port) a2 output (bsc) pc1 i/o (port) a1 output (bsc) pc0 i/o (port) a0 output (bsc) rev. 1.0, 08/99, page 606 of 875 table 17.1 multiplex pins (port d) (4) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) function 5 (relatedmodule) d pd31 i/o (port) d31 i/o (bsc) rxd2 input (sci) tioc5a i/o (tpu) pd30 i/o (port) d30 i/o (bsc) txd2 output (sci) tioc4b i/o (tpu) pd29 i/o (port) d29 i/o (bsc) sck2 i/o (sci) tioc4a i/o (tpu) pd28 i/o (port) d28 i/o (bsc) tclkb input (tpu) tioc3d i/o (tpu) pd27 i/o (port) d27 i/o (bsc) tclka input (tpu) tioc3c i/o (tpu) pd26 i/o (port) d26 i/o (bsc) pwob output (mmt) pd25 i/o (port) d25 i/o (bsc) pvob output (mmt) pd24 i/o (port) d24 i/o (bsc) puob output (mmt) pd23 i/o (port) d23 i/o (bsc) pco output (mmt) pci input (mmt) sck1 i/o (sci) pd22 i/o (port) d22 i/o (bsc) pwoa output (mmt) sck0 i/o (sci) pd21 i/o (port) d21 i/o (bsc) pvoa output (mmt) irq7 input (intc) pd20 i/o (port) d20 i/o (bsc) puoa output (mmt) irq6 input (intc) pd19 i/o (port) d19 i/o (bsc) poe3 input (mmt) irq5 input (intc) pd18 i/o (port) d18 i/o (bsc) poe2 input (mmt) irq4 input (intc) pd17 i/o (port) d17 i/o (bsc) poe1 input (mmt) adtrg input (a/d) pd16 i/o (port) d16 i/o (bsc) poe0 input (mmt) pd15 i/o (port) d15 i/o (bsc) tioc5b i/o (tpu) pd14 i/o (port) d14 i/o (bsc) tioc5a i/o (tpu) pd13 i/o (port) d13 i/o (bsc) tioc4b i/o (tpu) pd12 i/o (port) d12 i/o (bsc) tioc4a i/o (tpu) pd11 i/o (port) d11 i/o (bsc) tioc2b i/o (tpu) pd10 i/o (port) d10 i/o (bsc) tioc2a i/o (tpu) pd9 i/o (port) d9 i/o (bsc) tioc1b i/o (tpu) pd8 i/o (port) d8 i/o (bsc) tioc1a i/o (tpu) pd7 i/o (port) d7 i/o (bsc) pd6 i/o (port) d6 i/o (bsc) pd5 i/o (port) d5 i/o (bsc) pd4 i/o (port) d4 i/o (bsc) pd3 i/o (port) d3 i/o (bsc) pd2 i/o (port) d2 i/o (bsc) pd1 i/o (port) d1 i/o (bsc) pd0 i/o (port) d0 i/o (bsc) rev. 1.0, 08/99, page 607 of 875 table 17.1 multiplex pins (port e) (5) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) e pe23 i/o (port) irq7 input (intc) pwob output (mmt) pe22 i/o (port) irq6 input (intc) pvob output (mmt) pe21 i/o (port) irq5 input (intc) puob output (mmt) pe20 i/o (port) irq4 input (intc) pco output (mmt) pci input (mmt) pe19 i/o (port) irq3 input (intc) pwoa output (mmt) pe18 i/o (port) irq2 input (intc) pvoa output (mmt) pe17 i/o (port) irq1 input (intc) puoa output (mmt) sck0 i/o (sci) pe16 i/o (port) irq0 input (intc) sck1 i/o (sci) ah output (bsc) pe15 i/o (port) irq7 input (intc) pe14 i/o (port) irq6 input (intc) pe13 i/o (port) irq5 input (intc) pe12 i/o (port) irq4 input (intc) table 17.1 multiplex pins (port f) (6) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) f pf7 i/o (port) dreq1 input (dmac) irqout output (intc) tioc0d i/o (tpu) pf6 i/o (port) drak1 output (dmac) txd1 output (sci) tioc2a i/o (tpu) pf5 i/o (port) dack1 output (dmac) rxd1 input (sci) tioc2b i/o (tpu) pf3 i/o (port) dreq0 input (dmac) tioc0a i/o (tpu) pf2 i/o (port) drak0 output (dmac) tioc0c i/o (tpu) pf1 i/o (port) dack0 output (dmac) tioc0b i/o (tpu) rev. 1.0, 08/99, page 608 of 875 table 17.1 multiplex pins (port g) (7) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) g pg31 i/o (port) rxd2 input (sci) pg30 i/o (port) txd2 output (sci) pg29 i/o (port) sck2 i/o (sci) table 17.1 multiplex pins (port h) (8) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) h ph1 input/output (port) da1 output (d/a) ph0 input/output (port) da0 output (d/a) table 17.1 multiplex pins (port i) (9) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) i pi7 input (port) an7 input (a/d) pi6 input (port) an6 input (a/d) pi5 input (port) an5 input (a/d) pi4 input (port) an4 input (a/d) pi3 input (port) an3 input (a/d) pi2 input (port) an2 input (a/d) pi1 input (port) an1 input (a/d) pi0 input (port) an0 input (a/d) note: switching to port i function 2 (an7 to an0 input) is performed automatically when the a/d converter is started, and switching to function 1 (port input) is performed automatically when a/d conversion ends. rev. 1.0, 08/99, page 609 of 875 table 17.2 pin functions in each operating mode pin name on-chip rom disabled on-chip rom enabled mcu mode 4 mcu mode 3 mcu mode 2 mcu mode 1 single-chip mode pin no. initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc 17, 26, 39, 48, 58, 70, 79, 92, 105, 118, 126, 140 v cc v cc v cc v cc v cc v cc v cc v cc v cc v cc 10, 13, 21, 25, 31, 38, 45, 54, 64, 76, 88, 89, 101, 110, 113, 124, 128, 133, 135, 147 v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss 5, 160, 173 pv cc pv cc pv cc pv cc pv cc pv cc pv cc pv cc pv cc pv cc 1, 166 pv ss pv ss pv ss pv ss pv ss pv ss pv ss pv ss pv ss pv ss 129 pllv cc pllv cc pllv cc pllv cc pllv cc pllv cc pllv cc pllv cc pllv cc pllv cc 132 pllv ss pllv ss pllv ss pllv ss pllv ss pllv ss pllv ss pllv ss pllv ss pllv ss 130 pllcap1 pllcap1 pllcap1 pllcap1 pllcap1 pllcap1 pllcap1 pllcap1 pllcap1 pllcap1 131 pllcap2 pllcap2 pllcap2 pllcap2 pllcap2 pllcap2 pllcap2 pllcap2 pllcap2 pllcap2 159 av cc av cc av cc av cc av cc av cc av cc av cc av cc av cc 148 av ss av ss av ss av ss av ss av ss av ss av ss av ss av ss 114 extal extal extal extal extal extal extal extal extal extal 112 xtal xtal xtal xtal xtal xtal xtal xtal xtal xtal 127 ckio ckio ckio ckio ckio ckio ckio ckio ckio ckio 134 ck ck ck ck ck ck ck ck ck ck 123 res res res res res res res res res res 146 wdtovf wdtovf wdtovf wdtovf wdtovf wdtovf wdtovf wdtovf wdtovf wdtovf 125 hstby hstby hstby hstby hstby hstby hstby hstby hstby hstby 121 md5 md5 md5 md5 md5 md5 md5 md5 md5 md5 119 md4 md4 md4 md4 md4 md4 md4 md4 md4 md4 117 md3 md3 md3 md3 md3 md3 md3 md3 md3 md3 116 md2 md2 md2 md2 md2 md2 md2 md2 md2 md2 115 md1 md1 md1 md1 md1 md1 md1 md1 md1 md1 rev. 1.0, 08/99, page 610 of 875 table 17.2 pin functions in each operating mode (cont) pin name on-chip rom disabled on-chip rom enabled mcu mode 4 mcu mode 3 mcu mode 2 mcu mode 1 single-chip mode pin no. initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc 111 md0 md0 md0 md0 md0 md0 md0 md0 md0 md0 122 nmi nmi nmi nmi nmi nmi nmi nmi nmi nmi 120 fwe fwe fwe fwe fwe fwe fwe fwe fwe fwe 41 pa25 pa25/ cs5 pa25 pa25/ cs5 pa25 pa25/ cs5 pa25 pa25/ cs5 pa25 pa25 42 pa24 pa24/ cs4 pa24 pa24/ cs4 pa24 pa24/ cs4 pa24 pa24/ cs4 pa24 pa24 43 pa23 pa23/ cs3 pa23 pa23/ cs3 pa23 pa23/ cs3 pa23 pa23/ cs3 pa23 pa23 44 pa22 pa22/ cs2 pa22 pa22/ cs2 pa22 pa22/ cs2 pa22 pa22/ cs2 pa22 pa22 46 pa21 pa21/ cs1 pa21 pa21/ cs1 pa21 pa21/ cs1 pa21 pa21/ cs1 pa21 pa21 47 cs0 cs0 cs0 cs0 cs0 cs0 pa20 pa20/ cs0 pa20 pa20 142 bs bs bs bs bs bs pa19 pa19/ bs pa19 pa19 49 rd rd rd rd rd rd pa18 pa18/ rd pa18 pa18 50 pa17 pa17/ wr pa17 pa17/ wr pa17 pa17/ wr pa17 pa17/ wr pa17 pa17 51 wrhh wrhh / hhbs / tclkc/ tioc3a wrhh wrhh / hhbs / tclkc/ tioc3a wrhh wrhh / hhbs / tclkc/ tioc3a pa16 pa16/ wrhh / hhbs / tclkc/ tioc3a pa16 pa16/ tclkc/ tioc3a 52 wrhl wrhl / hlbs / tclkd/ tioc3b wrhl wrhl / hlbs / tclkd/ tioc3b wrhl wrhl / hlbs / tclkd/ tioc3b pa15 pa15/ wrhl / hlbs / tclkd/ tioc3b pa15 pa15/ tclkd/ tioc3b 53 wrlh wrlh / lhbs wrlh wrlh / lhbs wrlh wrlh / lhbs pa14 pa14/ wrlh / lhbs pa14 pa14 55 wrll wrll / llbs wrll wrll / llbs wrll wrll / llbs pa13 pa13/ wrll / llbs pa13 pa13 56 pa12 pa12/ wait pa12 pa12/ wait pa12 pa12/ wait pa12 pa12/ wait pa12 pa12 57 pa9 pa9/ ras1 pa9 pa9/ ras1 pa9 pa9/ ras1 pa9 pa9/ ras1 pa9 pa9 59 pa8 pa8/ ras0 pa8 pa8/ ras0 pa8 pa8/ ras0 pa8 pa8/ ras0 pa8 pa8 136 pa1 pa1/ oe1 pa1 pa1/ oe1 pa1 pa1/ oe1 pa1 pa1/ oe1 pa1 pa1 137 pa0 pa0/ oe0 pa0 pa0/ oe0 pa0 pa0/ oe0 pa0 pa0/ oe0 pa0 pa0 60 pb23 pb23/ cashh1 / txd1/ tend0 pb23 pb23/ cashh1 / txd1/ tend0 pb23 pb23/ cashh1 / txd1/ tend0 pb23 pb23/ cashh1 / txd1/ tend0 pb23 pb23/ txd1 rev. 1.0, 08/99, page 611 of 875 table 17.2 pin functions in each operating mode (cont) pin name on-chip rom disabled on-chip rom enabled mcu mode 4 mcu mode 3 mcu mode 2 mcu mode 1 single-chip mode pin no. initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc 61 pb22 pb22/ cashl1 / rxd1/ tend1 pb22 pb22/ cashl1 / rxd1/ tend1 pb22 pb22/ cashl1 / rxd1/ tend1 pb22 pb22/ cashl1 / rxd1/ tend1 pb22 pb22/ rxd1 62 pb21 pb21/ caslh1 pb21 pb21/ caslh1 pb21 pb21/ caslh1 pb21 pb21/ caslh1 pb21 pb21 63 pb20 pb20/ casll1 pb20 pb20/ casll1 pb20 pb20/ casll1 pb20 pb20/ casll1 pb20 pb20 65 pb19 pb19/ cashh0 / txd0 pb19 pb19/ cashh0 / txd0 pb19 pb19/ cashh0 / txd0 pb19 pb19/ cashh0 / txd0 pb19 pb19/ txd0 66 pb18 pb18/ cashl0 / rxd0 pb18 pb18/ cashl0 / rxd0 pb18 pb18/ cashl0 / rxd0 pb18 pb18/ cashl0 / rxd0 pb18 pb18/ rxd0 67 pb17 pb17/ caslh0 pb17 pb17/ caslh0 pb17 pb17/ caslh0 pb17 pb17/ caslh0 pb17 pb17 68 pb16 pb16/ casll0 pb16 pb16/ casll0 pb16 pb16/ casll0 pb16 pb16/ casll0 pb16 pb16 69 pb13 pb13/ rdwr pb13 pb13/ rdwr pb13 pb13/ rdwr pb13 pb13/ rdwr pb13 pb13 164 pb7 pb7/ back pb7 pb7 / back pb7 pb7/ back pb7 pb7/ back pb7 pb7 165 pb6 pb6/ breq pb6 pb6/ breq pb6 pb6/ breq pb6 pb6/ breq pb6 pb6 40 a25 a25/ tioc3b/ tclkd a25 a25/ tioc3b/ tclkd a25 a25/ tioc3b/ tclkd pc25 pc25/a25/ tioc3b/ tclkd pc25 pc25/ tioc3b/ tclkd 37 a24 a24/ tioc3a/ tclkc a24 a24/ tioc3a/ tclkc a24 a24/ tioc3a/ tclkc pc24 pc24/a24/ tioc3a/ tclkc pc24 pc24/ tioc3a/ tclkc 36 a23 a23/ tioc1b/ tclkb a23 a23/ tioc1b/ tclkb a23 a23/ tioc1b/ tclkb pc23 pc23/a23/ tioc1b/ tclkb pc23 pc23/ tioc1b/ tclkb 35 a22 a22/ tioc1a/ tclka a22 a22/ tioc1a/ tclka a22 a22/ tioc1a/ tclka pc22 pc22/a22/ tioc1a/ tclka pc22 pc22/ tioc1a/ tclka 34 a21 a21/ tioc5b a21 a21/ tioc5b a21 a21/ tioc5b pc21 pc21/a21/ tioc5b pc21 pc21/ tioc5b 33 a20 a20/ tioc5a a20 a20/ tioc5a a20 a20/ tioc5a pc20 pc20/a20/ tioc5a pc20 pc20/ tioc5a rev. 1.0, 08/99, page 612 of 875 table 17.2 pin functions in each operating mode (cont) pin name on-chip rom disabled on-chip rom enabled mcu mode 4 mcu mode 3 mcu mode 2 mcu mode 1 single-chip mode pin no. initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc 32 a19 a19/ tioc4b a19 a19/ tioc4b a19 a19/ tioc4b pc19 pc19/a19/ tioc4b pc19 pc19/ tioc4b 30 a18 a18/ tioc4a a18 a18/ tioc4a a18 a18/ tioc4a pc18 pc18/a18/ tioc4a pc18 pc18/ tioc4a 29 a17 a17/ tioc3b a17 a17/ tioc3b a17 a17/ tioc3b pc17 pc17/a17/ tioc3b pc17 pc17/ tioc3b 28 a16 a16/ tioc3a a16 a16/ tioc3a a16 a16/ tioc3a pc16 pc16/a16/ tioc3a pc16 pc16/ tioc3a 27 a15 a15/ tioc3d a15 a15/ tioc3d a15 a15/ tioc3d pc15 pc15/a15/ tioc3d pc15 pc15/ tioc3d 24 a14 a14/ tioc3c a14 a14/ tioc3c a14 a14/ tioc3c pc14 pc14/a14/ tioc3c pc14 pc14/ tioc3c 23 a13 a13 a13 a13 a13 a13 pc13 pc13/a13 pc13 pc13 22 a12 a12 a12 a12 a12 a12 pc12 pc12/a12 pc12 pc12 20 a11 a11 a11 a11 a11 a11 pc11 pc11/a11 pc11 pc11 19 a10 a10 a10 a10 a10 a10 pc10 pc10/a10 pc10 pc10 18 a9 a9 a9 a9 a9 a9 pc9 pc9/a9 pc9 pc9 16 a8 a8 a8 a8 a8 a8 pc8 pc8/a8 pc8 pc8 15 a7 a7 a7 a7 a7 a7 pc7 pc7/a7 pc7 pc7 14 a6 a6 a6 a6 a6 a6 pc6 pc6/a6 pc6 pc6 12 a5 a5 a5 a5 a5 a5 pc5 pc5/a5 pc5 pc5 11 a4 a4 a4 a4 a4 a4 pc4 pc4/a4 pc4 pc4 9a3a3a3a3a3a3pc3pc3/a3pc3pc3 8a2a2a2a2a2a2pc2pc2/a2pc2pc2 7a1a1a1a1a1a1pc1pc1/a1pc1pc1 6a0a0a0a0a0a0pc0pc0/a0pc0pc0 71 pd31 pd31/d31/ rxd2/ tioc5a pd31 pd31/d31/ rxd2/ tioc5a d31 d31/ rxd2/ tioc5a pd31 pd31/d31/ rxd2/ tioc5a pd31 pd31/ rxd2/ tioc5a 72 pd30 pd30/d30/ txd2/ tioc4b pd30 pd30/d30/ txd2/ tioc4b d30 d30/ txd2/ tioc4b pd30 pd30/d30/ txd2/ tioc4b pd30 pd30/ txd2/ tioc4b 73 pd29 pd29/d29/ sck2/ tioc4a pd29 pd29/d29/ sck2/ tioc4a d29 d29/ sck2/ tioc4a pd29 pd29/d29/ sck2/ tioc4a pd29 pd29/ sck2/ tioc4a rev. 1.0, 08/99, page 613 of 875 table 17.2 pin functions in each operating mode (cont) pin name on-chip rom disabled on-chip rom enabled mcu mode 4 mcu mode 3 mcu mode 2 mcu mode 1 single-chip mode pin no. initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc 74 pd28 pd28/d28/ tclkb/ tioc3d pd28 pd28/d28/ tclkb/ tioc3d d28 d28/ tclkb/ tioc3d pd28 pd28/d28/ tclkb/ tioc3d pd28 pd28/ tclkb/ tioc3d 75 pd27 pd27/d27/ tclka/ tioc3c pd27 pd27/d27/ tclka/ tioc3c d27 d27/ tclka/ tioc3c pd27 pd27/d27/ tclka/ tioc3c pd27 pd27/ tclka/ tioc3c 77 pd26 pd26/d26/ pwob pd26 pd26/d26/ pwob d26 d26/ pwob pd26 pd26/d26/ pwob pd26 pd26/ pwob 78 pd25 pd25/d25/ pvob pd25 pd25/d25/ pvob d25 d25/ pvob pd25 pd25/d25/ pvob pd25 pd25/ pvob 80 pd24 pd24/d24/ puob pd24 pd24/d24/ puob d24 d24/ puob pd24 pd24/d24/ puob pd24 pd24/ puob 81 pd23 pd23/d23/ pco/pci/ sck1 pd23 pd23/d23/ pco/pci/ sck1 d23 d23/ pco/pci/ sck1 pd23 pd23/d23/ pco/pci/ sck1 pd23 pd23/ pco/pci/ sck1 82 pd22 pd22/d22/ pwoa/ sck0 pd22 pd22/d22/ pwoa/ sck0 d22 d22/ pwoa/ sck0 pd22 pd22/d22/ pwoa/ sck0 pd22 pd22/ pwoa/ sck0 83 pd21 pd21/d21/ pvoa/ irq7 pd21 pd21/d21/ pvoa/ irq7 d21 d21/ pvoa/ irq7 pd21 pd21/d21/ pvoa/ irq7 pd21 pd21/ pvoa/ irq7 84 pd20 pd20/d20/ puoa/ irq6 pd20 pd20/d20/ puoa/ irq6 d20 d20/ puoa/ irq6 pd20 pd20/d20/ puoa/ irq6 pd20 pd20/ puoa/ irq6 85 pd19 pd19/d19/ poe3 / irq5 pd19 pd19/d19/ poe3 / irq5 d19 d19/ poe3 / irq5 pd19 pd19/d19/ poe3 / irq5 pd19 pd19/ poe3 / irq5 86 pd18 pd18/ d18/ poe2 / irq4 pd18 pd18/d18/ poe2 / irq4 d18 d18/ poe2 / irq4 pd18 pd18/d18/ poe2 / irq4 pd18 pd18/ poe2 / irq4 87 pd17 pd17/d17/ poe1 / adtrg pd17 pd17/d17/ poe1 / adtrg d17 d17/ poe1 / adtrg pd17 pd17/d17/ poe1 / adtrg pd17 pd17/ poe1 / adtrg 90 pd16 pd16/ d16/ poe0 pd16 pd16/d16/ poe0 d16 d16/ poe0 pd16 pd16/d16/ poe0 pd16 pd16/ poe0 91 pd15 d15/ tioc5b d15 d15/ tioc5b d15 d15/ tioc5b pd15 pd15/d15/ tioc5b pd15 pd15/ tioc5b rev. 1.0, 08/99, page 614 of 875 table 17.2 pin functions in each operating mode (cont) pin name on-chip rom disabled on-chip rom enabled mcu mode 4 mcu mode 3 mcu mode 2 mcu mode 1 single-chip mode pin no. initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc 93 pd14 d14/ tioc5a d14 d14/ tioc5a d14 d14/ tioc5a pd14 pd14/d14/ tioc5a pd14 pd14/ tioc5a 94 pd13 d13/ tioc4b d13 d13/ tioc4b d13 d13/ tioc4b pd13 pd13/d13/ tioc4b pd13 pd13/ tioc4b 95 pd12 d12/ tioc4a d12 d12/ tioc4a d12 d12/ tioc4a pd12 pd12/d12/ tioc4a pd12 pd12/ tioc4a 96 pd11 d11/ tioc2b d11 d11/ tioc2b d11 d11/ tioc2b pd11 pd11/d11/ tioc2b pd11 pd11/ tioc2b 97 pd10 d10/ tioc2a d10 d10/ tioc2a d10 d10/ tioc2a pd10 pd10/d10/ tioc2a pd10 pd10/ tioc2a 98 pd9 d9/ tioc1b d9 d9/ tioc1b d9 d9/ tioc1b pd9 pd9/d9/ tioc1b pd9 pd9/ tioc1b 99 pd8 d8/ tioc1a d8 d8/ tioc1a d8 d8/ tioc1a pd8 pd8/d8/ tioc1a pd8 pd8/ tioc1a 100 d7 d7 d7 d7 d7 d7 pd7 pd7/d7 pd7 pd7 102 d6 d6 d6 d6 d6 d6 pd6 pd6/d6 pd6 pd6 103 d5 d5 d5 d5 d5 d5 pd5 pd5/d5 pd5 pd5 104 d4 d4 d4 d4 d4 d4 pd4 pd4/d4 pd4 pd4 106 d3 d3 d3 d3 d3 d3 pd3 pd3/d3 pd3 pd3 107 d2 d2 d2 d2 d2 d2 pd2 pd2/d2 pd2 pd2 108 d1 d1 d1 d1 d1 d1 pd1 pd1/d1 pd1 pd1 109 d0 d0 d0 d0 d0 d0 pd0 pd0/d0 pd0 pd0 167 pe23 pe23/ irq7 / pwob pe23 pe23/ irq7 / pwob pe23 pe23/ irq7 / pwob pe23 pe23/ irq7 / pwob pe23 pe23/ irq7 / pwob 168 pe22 pe22/ irq6 / pvob pe22 pe22/ irq6 / pvob pe22 pe22/ irq6 / pvob pe22 pe22/ irq6 / pvob pe22 pe22/ irq6 / pvob 169 pe21 pe21/ irq5 / puob pe21 pe21/ irq5 / puob pe21 pe21/ irq5 / puob pe21 pe21/ irq5 / puob pe21 pe21/ irq5 / puob 170 pe20 pe20/ irq4 / pco/pci pe20 pe20/ irq4 / pco/pci pe20 pe20/ irq4 / pco/pci pe20 pe20/ irq4 / pco/pci pe20 pe20/ irq4 / pco/pci 171 pe19 pe19/ irq3 / pwoa pe19 pe19/ irq3/ pwoa pe19 pe19/ irq3 / pwoa pe19 pe19/ irq3 / pwoa pe19 pe19/ irq3 / pwoa rev. 1.0, 08/99, page 615 of 875 table 17.2 pin functions in each operating mode (cont) pin name on-chip rom disabled on-chip rom enabled mcu mode 4 mcu mode 3 mcu mode 2 mcu mode 1 single-chip mode pin no. initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc 172 pe18 pe18/ irq2 / pvoa pe18 pe18/ irq2 / pvoa pe18 pe18/ irq2 / pvoa pe18 pe18/ irq2/ pvoa pe18 pe18/ irq2 / pvoa 174 pe17 pe17/ irq1 / puoa/ sck0 pe17 pe17/ irq1 / puoa/ sck0 pe17 pe17/ irq1 / puoa/ sck0 pe17 pe17/ irq1 / puoa/ sck0 pe17 pe17/ irq1 / puoa/ sck0 175 pe16 pe16/ irq0 / sck1/ ah pe16 pe16/ irq0 / sck1/ ah pe16 pe16/ irq0 / sck1/ ah pe16 pe16/ irq0 / sck1/ ah pe16 pe16/ irq0 / sck1 176 pe15 pe15/ irq7 pe15 pe15/ irq7 pe15 pe15/ irq7 pe15 pe15/ irq7 pe15 pe15/ irq7 2 pe14 pe14/ irq6 pe14 pe14/ irq6 pe14 pe14/ irq6 pe14 pe14/ irq6 pe14 pe14/ irq6 3 pe13 pe13/ irq5 pe13 pe13/ irq5 pe13 pe13/ irq5 pe13 pe13/ irq5 pe13 pe13/ irq5 4 pe12 pe12/ irq4 pe12 pe12/ irq4 pe12 pe12/ irq4 pe12 pe12/ irq4 pe12 pe12/ irq4 145 pf7 pf7/ dreq1 / irqout/ tioc0d pf7 pf7/ dreq1 / irqout/ tioc0d pf7 pf7/ dreq1 / irqout/ tioc0d pf7 pf7/ dreq1 / irqout/ tioc0d pf7 pf7/ irqout / tioc0d 144 pf6 pf6/ drak1 / txd1/ tioc2a pf6 pf6/ drak1 / txd1/ tioc2a pf6 pf6/ drak1 / txd1/ tioc2a pf6 pf6/ drak1 / txd1/ tioc2a pf6 pf6/ txd1/ tioc2a 143 pf5 pf5/ dack1 / rxd1/ tioc2b pf5 pf5/ dack1 / rxd1/ tioc2b pf5 pf5/ dack1 / rxd1/ tioc2b pf5 pf5/ dack1 / rxd1/ tioc2b pf5 pf5/ rxd1/ tioc2b 138 pf3 pf3/ dreq0 / tioc0a pf3 pf3/ dreq0 / tioc0a pf3 pf3/ dreq0 / tioc0a pf3 pf3/ dreq0 / tioc0a pf3 pf3/ tioc0a 139 pf2 pf2/ drak0 / tioc0c pf2 pf2/ drak0 / tioc0c pf2 pf2/ drak0 / tioc0c pf2 pf2/ drak0 / tioc0c pf2 pf2/ tioc0c 141 pf1 pf1/ dack0 / tioc0b pf1 pf1/ dack0 / tioc0b pf1 pf1/ dack0 / tioc0b pf1 pf1/ dack0 / tioc0b pf1 pf1/ tioc0b 161 pg31 pg31/ rxd2 pg31 pg31/ rxd2 pg31 pg31/ rxd2 pg31 pg31/ rxd2 pg31 pg31/ rxd2 rev. 1.0, 08/99, page 616 of 875 table 17.2 pin functions in each operating mode (cont) pin name on-chip rom disabled on-chip rom enabled mcu mode 4 mcu mode 3 mcu mode 2 mcu mode 1 single-chip mode pin no. initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc initial function functions settable by pfc 162 pg30 pg30/ txd2 pg30 pg30/ txd2 pg30 pg30/ txd2 pg30 pg30/ txd2 pg30 pg30/ txd2 163 pg29 pg29/ sck2 pg29 pg29/ sck2 pg29 pg29/ sck2 pg29 pg29/ sck2 pg29 pg29/ sck2 150 ph1 ph1/da1 ph1 ph1/da1 ph1 ph1/da1 ph1 ph1/da1 ph1 ph1/da1 149 ph0 ph0/da0 ph0 ph0/da0 ph0 ph0/da0 ph0 ph0/da0 ph0 ph0/da0 158 * pi7 pi7/an7 pi7 pi7/an7 pi7 pi7/an7 pi7 pi7/an7 pi7 pi7/an7 157 * pi6 pi6/an6 pi6 pi6/an6 pi6 pi6/an6 pi6 pi6/an6 pi6 pi6/an6 156 * pi5 pi5/an5 pi5 pi5/an5 pi5 pi5/an5 pi5 pi5/an5 pi5 pi5/an5 155 * pi4 pi4/an4 pi4 pi4/an4 pi4 pi4/an4 pi4 pi4/an4 pi4 pi4/an4 154 * pi3 pi3/an3 pi3 pi3/an3 pi3 pi3/an3 pi3 pi3/an3 pi3 pi3/an3 153 * pi2 pi2/an2 pi2 pi2/an2 pi2 pi2/an2 pi2 pi2/an2 pi2 pi2/an2 152 * pi1 pi1/an1 pi1 pi1/an1 pi1 pi1/an1 pi1 pi1/an1 pi1 pi1/an1 151 * pi0 pi0/an0 pi0 pi0/an0 pi0 pi0/an0 pi0 pi0/an0 pi0 pi0/an0 note: * since switching to the port i ann (a/d converter analog input) function is performed automatically when a/d conversion is started, and the pin (port input) function is restored when a/d conversion ends, port i has no register for pfc settings. rev. 1.0, 08/99, page 617 of 875 17.2 register configuration pfc registers are listed in table 17.3. table 17.3 pfc registers name abbreviation r/w initial value address access size port a io register h paiorh r/(w) h'0000 h'ffff1204 8, 16, 32 port a io register l paiorl r/(w) h'0000 h'ffff1206 8, 16, 32 port a control register h1 pacrh1 r/(w) h'0000 h'ffff1208 8, 16, 32 port a control register h2 pacrh2 r/(w) h'0000 h'ffff120a 8, 16, 32 port a control register l1 pacrl1 r/(w) h'0000 h'ffff120c 8, 16, 32 port a control register l2 pacrl2 r/(w) h'0000 h'ffff120e 8, 16, 32 port b io register h pbiorh r/(w) h'0000 h'ffff1214 8, 16, 32 port b io register l pbiorl r/(w) h'0000 h'ffff1216 8, 16, 32 port b control register h2 pbcrh2 r/(w) h'0000 h'ffff121a 8, 16, 32 port b control register l1 pbcrl1 r/(w) h'0000 h'ffff121c 8, 16, 32 port b control register l2 pbcrl2 r/(w) h'0000 h'ffff121e 8, 16, 32 port c io register h pciorh r/(w) h'0000 h'ffff1224 8, 16, 32 port c io register l pciorl r/(w) h'0000 h'ffff1226 8, 16, 32 port c control register h1 pccrh1 r/(w) h'0000 h'ffff1228 8, 16, 32 port c control register h2 pccrh2 r/(w) h'0000 h'ffff122a 8, 16, 32 port c control register l1 pccrl1 r/(w) h'0000 h'ffff122c 8, 16, 32 port c control register l2 pccrl2 r/(w) h'0000 h'ffff122e 8, 16, 32 port d io register h pdiorh r/(w) h'0000 h'ffff1234 8, 16, 32 port d io register l pdiorl r/(w) h'0000 h'ffff1236 8, 16, 32 port d control register h1 pdcrh1 r/(w) h'0000 h'ffff1238 8, 16, 32 port d control register h2 pdcrh2 r/(w) h'0000 h'ffff123a 8, 16, 32 port d control register l1 pdcrl1 r/(w) h'0000 h'ffff123c 8, 16, 32 port d control register l2 pdcrl2 r/(w) h'0000 h'ffff123e 8, 16, 32 port e io register h peiorh r/(w) h'0000 h'ffff1244 8, 16, 32 port e io register l peiorl r/(w) h'0000 h'ffff1246 8, 16, 32 port e control register h2 pecrh2 r/(w) h'0000 h'ffff124a 8, 16, 32 port e control register l pecrl r/(w) h'0000 h'ffff124c 8, 16, 32 rev. 1.0, 08/99, page 618 of 875 table 17.3 pfc registers (cont) name abbreviation r/w initial value address access size port f io register l pfiorl r/(w) h'0000 h'ffff1266 8, 16, 32 port f control register l2 pfcrl2 r/(w) h'0000 h'ffff126e 8, 16, 32 port g io register pgior r/(w) h'0000 h'ffff1274 8, 16, 32 port g control register h1 pgcrh1 r/(w) h'0000 h'ffff1278 8, 16, 32 port h io register phior r/(w) h'0000 h'ffff1286 8, 16, 32 port h control register phcr r/(w) h'0000 h'ffff128e 8, 16, 32 function control register fcr r/(w) h'0000 h'ffff1250 8, 16, 32 17.3 register descriptions 17.3.1 port a io register h (paiorh) bit: 15 14 13 12 11 10 9 8 pa25iorpa24ior initial value:00000000 r/w:rrrrrrr/wr/w bit:76543210 pa23ior pa22ior pa21ior pa20ior pa19ior pa18ior pa17ior pa16ior initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port a io register h (paiorh) is a 16-bit readable/writable register that selects the input/output direction of pins in port a. bits pa25ior to pa16ior correspond to pins pa25/ cs5 to pa16/ wrhh / hhbs /tclkc/tioc3a. paiorh is enabled when port a pins function as general input/output pins (pa25 to pa16) or pa16 functions as a tpu tioc pin, and disabled otherwise. when port a pins function as pa25 to pa16, or pa16 functions as a tpu tioc pin, a pin becomes an output when the corresponding bit in paiorh is set to 1, and an input when the bit is cleared to 0. paiorh is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. rev. 1.0, 08/99, page 619 of 875 17.3.2 port a io register l (paiorl) bit: 15 14 13 12 11 10 9 8 pa15ior pa14ior pa13ior pa12ior pa9ior pa8ior initial value:00000000 r/w: r/w r/w r/w r/w r r r/w r/w bit:76543210 C pa1ior pa0ior initial value:00000000 r/w:rrrrrrr/wr/w port a io register l (paiorl) is a 16-bit readable/writable register that selects the input/output direction of pins in port a. bits pa15ior to pa0ior correspond to pins pa15/ wrhl / hlbs /tclkd/tioc3b to pa0/ oe0 . paiorl is enabled when port a pins function as general input/output pins (pa15 to pa0) or a tpu tioc pin, and disabled otherwise. when port a pins function as pa15 to pa0, or pa15 functions as a tpu tioc pin, a pin becomes an output when the corresponding bit in paiorl is set to 1, and an input when the bit is cleared to 0. paiorl is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. 17.3.3 port a control registers h1 and h2 (pacrh1, pacrh2) port a control registers h1 and h2 (pacrh1, pacrh2) are 16-bit readable/writable registers that select the functions of the upper 16 multiplex pins in port a. pacrh1 selects the functions of port a pins pa25/ cs5 to pa24/ cs4 , and pacrh2 selects the functions of port a pins pa23/ cs3 to pa16/ wrhh / hhbs /tclkc/tioc3a. port a includes bus control signals ( cs0 to cs5 , bs , rd , wr , wrhh , and hhbs ), but register settings relating to the selection of these pin functions may not be valid in all operating modes. for details, see table 17.2, pin functions in each operating mode. pacrh1 and pacrh2 are initialized to h'0000 by an external power-on reset, but are not initialized by a wdt reset, in standby mode, or in sleep mode. rev. 1.0, 08/99, page 620 of 875 port a control register h1 (pacrh1) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 pa25mdpa24md initial value:00000000 r/w:rrrrrr/wrr/w bits 15 to 3reserved: these bits are always read as 0 and should only be written with 0. bit 2pa25 mode (pa25md): selects the function of the pa25/ cs5 pin. bit 2: pa25md description 0 general input/output (pa25) (initial value) 1 chip select output ( cs5 ) (pa25 in single-chip mode) bit 1reserved: this bit is always read as 0 and should only be written with 0. bit 0pa24 mode (pa24md): selects the function of the pa24/ cs4 pin. bit 0: pa24md description 0 general input/output (pa24) (initial value) 1 chip select output ( cs4 ) (pa24 in single-chip mode) rev. 1.0, 08/99, page 621 of 875 port a control register h2 (pacrh2) bit: 15 14 13 12 11 10 9 8 pa23 md pa22 md pa21 md pa20 md initial value:00000000 r/w:rr/wrr/wrr/wrr/w bit:76543210 pa19 md pa18 md pa17 md pa16 md1 pa16 md0 initial value:00000000 r/w: r r/w r r/w r r/w r/w r/w bit 15reserved: this bit is always read as 0 and should only be written with 0. bit 14pa23 mode (pa23md): selects the function of the pa23/ cs3 pin. bit 14: pa23md description 0 general input/output (pa23) (initial value) 1 chip select output ( cs3 ) (pa23 in single-chip mode) bit 13reserved: this bit is always read as 0 and should only be written with 0. bit 12pa22 mode (pa22md): selects the function of the pa22/ cs2 pin. bit 12: pa22md description 0 general input/output (pa22) (initial value) 1 chip select output ( cs2 ) (pa22 in single-chip mode) bit 11reserved: this bit is always read as 0 and should only be written with 0. bit 10pa21 mode (pa21md): selects the function of the pa21/ cs1 pin. bit 10: pa21md description 0 general input/output (pa21) (initial value) 1 chip select output ( cs1 ) (pa21 in single-chip mode) bit 9reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 622 of 875 bit 8pa20 mode (pa20md): selects the function of the pa20/ cs0 pin. bit 8: pa20md description 0 general input/output (pa20) ( cs0 in on-chip rom disabled modes) (initial value) 1 chip select output ( cs0 ) (pa20 in single-chip mode) bit 7reserved: this bit is always read as 0 and should only be written with 0. bit 6pa19 mode (pa19md): selects the function of the pa19/ bs pin. bit 6: pa19md description 0 general input/output (pa19) ( bs in on-chip rom disabled modes) (initial value) 1 bus start output ( bs ) (pa19 in single-chip mode) bit 5reserved: this bit is always read as 0 and should only be written with 0. bit 4pa18 mode (pa18md): selects the function of the pa18/ rd pin. bit 4: pa18md description 0 general input/output (pa18) ( rd in on-chip rom disabled modes) (initial value) 1 read output ( rd ) (pa18 in single-chip mode) bit 3reserved: this bit is always read as 0 and should only be written with 0. bit 2pa17 mode (pa17md): selects the function of the pa17/ wr pin. bit 2: pa17md description 0 general input/output (pa17) (initial value) 1 write output ( wr ) (pa17 in single-chip mode) rev. 1.0, 08/99, page 623 of 875 bits 1 and 0pa16 mode 1 and 0 (pa16md1, pa16md0): these bits select the function of the pa16/ wrhh / hhbs /tclkc/tioc3a pin. bit 1: pa16md1 bit 0: pa16md0 description 0 0 general input/output (pa16) (initial value) ( wrhh or hhbs in on-chip rom disabled modes) 1 byte write output ( wrhh ) or byte strobe output ( hhbs ) (pa16 in single-chip mode) 1 0 tpu clock input (tclkc) 1 tpu input capture input/output compare output (tioc3a) 17.3.4 port a control registers l1 and l2 (pacrl1, pacrl2) port a control registers l1 and l2 (pacrl1, pacrl2) are 16-bit readable/writable registers that select the functions of pins in port a. pacrl1 selects the functions of port a pins pa15/ wrhl / hlbs /tclkd/tioc3b to pa8/ ras0 , and pacrl2 selects the functions of port a pins pa1/ oe1 and pa0/ oe0 . port a includes bus control signals ( wrhl , wrlh , wrll , hlbs , lhbs , llbs , wait , ras0 , ras1 , oe0 , and oe1 ), but register settings relating to the selection of these pin functions may not be valid in all operating modes. for details, see table 17.2, pin functions in each operating mode. pacrl1 and pacrl2 are initialized to h'0000 by an external power-on reset, but are not initialized by a wdt reset, in standby mode, or in sleep mode. port a control register l1 (pacrl1) bit: 15 14 13 12 11 10 9 8 pa15 md1 pa15 md0 pa14 md pa13 md pa12 md initial value:00000000 r/w: r/w r/w r r/w r r/w r r/w bit:76543210 pa9 md pa8 md initial value:00000000 r/w:rrrrrr/wrr/w rev. 1.0, 08/99, page 624 of 875 bits 15 and 14pa15 mode 1 and 0 (pa15md1, pa15md0): these bits select the function of the pa15/ wrhl / hlbs /tclkd/tioc3b pin. bit 15: pa15md1 bit 14: pa15md0 description 0 0 general input/output (pa15) (initial value) ( wrh l or hlbs in on-chip rom disabled modes) 1 byte write output ( wrhl ) or byte strobe output ( hlbs ) (pa15 in single-chip mode) 1 0 tpu clock input (tclkd) 1 tpu input capture input/output compare output (tioc3b) bit 13reserved: this bit is always read as 0 and should only be written with 0. bit 12pa14 mode (pa14md): selects the function of the pa14/ wrlh / lhbs pin. bit 12: pa14md description 0 general input/output (pa14) (initial value) ( wrlh or lhbs in on-chip rom disabled modes) 1 byte write output ( wrlh ) or byte strobe output ( lhbs ) (pa14 in single-chip mode) bit 11reserved: this bit is always read as 0 and should only be written with 0. bit 10pa13 mode (pa13md): selects the function of the pa13/ wrll / llbs pin. bit 10: pa13md description 0 general input/output (pa13) (initial value) ( wrll or llbs in on-chip rom disabled modes) 1 byte write output ( wrll ) or byte strobe output ( llbs ) (pa13 in single-chip mode) bit 9reserved: this bit is always read as 0 and should only be written with 0. bit 8pa12 mode (pa12md): selects the function of the pa12/ wait pin. bit 8: pa12md description 0 general input/output (pa12) (initial value) 1 wait request input ( wait ) (pa12 in single-chip mode) rev. 1.0, 08/99, page 625 of 875 bits 7 to 3reserved: these bits are always read as 0 and should only be written with 0. bit 2pa9 mode (pa9md): selects the function of the pa9/ ras1 pin. bit 2: pa9md description 0 general input/output (pa9) (initial value) 1 row address strobe output ( ras1 ) (pa9 in single-chip mode) bit 1reserved: this bit is always read as 0 and should only be written with 0. bit 0pa8 mode (pa8md): selects the function of the pa8/ ras0 pin. bit 0: pa8md description 0 general input/output (pa8) (initial value) 1 row address strobe output ( ras0 ) (pa8 in single-chip mode) port a control register l2 (pacrl2) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 pa1mdpa0md initial value:00000000 r/w:rrrrrr/wrr/w bits 15 to 3reserved: these bits are always read as 0 and should only be written with 0. bit 2pa1 mode (pa1md): selects the function of the pa1/ oe1 pin. bit 2: pa1md description 0 general input/output (pa1) (initial value) 1 output enable output ( oe1 ) (pa1 in single-chip mode) bit 1reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 626 of 875 bit 0pa0 mode (pa0md): selects the function of the pa0/ oe0 pin. bit 0: pa0md description 0 general input/output (pa0) (initial value) 1 output enable output ( oe0 ) (pa0 in single-chip mode) 17.3.5 port b io register h (pbiorh) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 pb23ior pb22ior pb21ior pb20ior pb19ior pb18ior pb17ior pb16ior initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port b io register h (pbiorh) is a 16-bit readable/writable register that selects the input/output direction of pins in port b. bits pb23ior to pb16ior correspond to pins pb23/ cashh1 /txd1/ tend0 to pb16/ casll0 . pbiorh is enabled when port b pins function as general input/output pins (pb23 to pb16), and disabled otherwise. when port b pins function as pb23 to pb16, a pin becomes an output when the corresponding bit in pbiorh is set to 1, and an input when the bit is cleared to 0. pbiorh is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. rev. 1.0, 08/99, page 627 of 875 17.3.6 port b io register l (pbiorl) bit: 15 14 13 12 11 10 9 8 pb13ior initial value:00000000 r/w:rrr/wrrrrr bit:76543210 pb7iorpb6ior initial value:00000000 r/w:r/wr/wrrrrrr port b io register l (pbiorl) is a 16-bit readable/writable register that selects the input/output direction of pins in port b. bits pb13ior to pb6ior correspond to pins pb13/rdwr to pb6/ breq . pbiorl is enabled when port b pins function as general input/output pins (pb13 to pb6), and disabled otherwise. when port b pins function as pb13 to pb6, a pin becomes an output when the corresponding bit in pbiorl is set to 1, and an input when the bit is cleared to 0. pbiorl is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. 17.3.7 port b control register h2 (pbcrh2) port b control register h2 (pbcrh2) is a 16-bit readable/writable register that selects the functions of the upper 8 multiplex pins in port b. pbcrh2 selects the functions of port b pins pb23/ cashh1 /txd1/ tend0 to pb16/ casll0 . port b includes bus control signals ( casll0 , casll1 , caslh0 , caslh1 , cashl0 , cashl1 , cashh0 , and cashh1 ) and dmac control signals ( tend0 and tend1 ), but register settings relating to the selection of these pin functions may not be valid in all operating modes. for details, see table 17.2, pin functions in each operating mode. pbcrh2 is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. rev. 1.0, 08/99, page 628 of 875 port b control register h2 (pbcrh2) bit: 15 14 13 12 11 10 9 8 pb23 md1 pb23 md0 pb22 md1 pb22 md0 pb21 md pb20 md initial value:00000000 r/w: r/w r/w r/w r/w r r/w r r/w bit:76543210 pb19 md1 pb19 md0 pb18 md1 pb18 md0 pb17 md pb16 md initial value:00000000 r/w: r/w r/w r/w r/w r r/w r r/w bits 15 and 14pb23 mode 1 and 0 (pb23md1, pb23md0): these bits select the function of the pb23/ cashh1 /txd1/ tend0 pin. bit 15: pb23md1 bit 14: pb23md0 description 0 0 general input/output (pb23) (initial value) 1 column address strobe output ( cashh1 ) (pb23 in single-chip mode) 1 0 sci transmit data output (txd1) 1 dmac transfer end output ( tend0 ) (pb23 in single- chip mode) bits 13 and 12pb22 mode 1 and 0 (pb22md1, pb22md0): these bits select the function of the pb22/ cashl1 /rxd1/ tend1 pin. bit 13: pb22md1 bit 12: pb22md0 description 0 0 general input/output (pb22) (initial value) 1 column address strobe output ( cashl1 ) (pb22 in single-chip mode) 1 0 sci receive data input (rxd1) 1 dmac transfer end output ( tend1 ) (pb22 in single- chip mode) bit 11reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 629 of 875 bit 10pb21 mode (pb21md): selects the function of the pb21/ caslh1 pin. bit 10: pb21md description 0 general input/output (pb21) (initial value) 1 column address strobe output ( caslh1 ) (pb21 in single-chip mode) bit 9reserved: this bit is always read as 0 and should only be written with 0. bit 8pb20 mode (pb20md): selects the function of the pb20/ casll1 pin. bit 8: pb20md description 0 general input/output (pb20) (initial value) 1 column address strobe output ( casll1 ) (pb20 in single-chip mode) bits 7 and 6pb19 mode 1 and 0 (pb19md1, pb19md0): these bits select the function of the pb19/ cashh0 /txd0 pin. bit 7: pb19md1 bit 6: pb19md0 description 0 0 general input/output (pb19) (initial value) 1 column address strobe output ( cashh0 ) (pb19 in single-chip mode) 1 0 sci transmit data output (txd0) 1 reserved (do not set) bits 5 and 4pb18 mode 1 and 0 (pb18md1, pb18md0): these bits select the function of the pb18/ cashl0 /rxd0 pin. bit 5: pb18md1 bit 4: pb18md0 description 0 0 general input/output (pb18) (initial value) 1 column address strobe output ( cashl0 ) (pb18 in single-chip mode) 1 0 sci receive data input (rxd0) 1 reserved (do not set) bit 3reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 630 of 875 bit 2pb17 mode (pb17md): selects the function of the pb17/ caslh0 pin. bit 2: pb17md description 0 general input/output (pb17) (initial value) 1 column address strobe output ( caslh0 ) (pb17 in single-chip mode) bit 1reserved: this bit is always read as 0 and should only be written with 0. bit 0pb16 mode (pb16md): selects the function of the pb16/ casll0 pin. bit 0: pb16md description 0 general input/output (pb16) (initial value) 1 column address strobe output ( casll0 ) (pb16 in single-chip mode) 17.3.8 port b control registers l1 and l2 (pbcrl1, pbcrl2) port b control registers l1 and l2 (pbcrl1, pbcrl2) are 16-bit readable/writable registers that select the functions of pins in port b. pbcrl1 selects the functions of port b pin pb13/rdwr , and pbcrl2 selects the functions of port b pins pb7/ back to pb6/ breq . port b includes bus control signals (rdwr, back , and breq ), but register settings relating to the selection of these pin functions may not be valid in all operating modes. for details, see table 17.2, pin functions in each operating mode. pbcrl1 and pbcrl2 are initialized to h'0000 by an external power-on reset, but are not initialized by a wdt reset, in standby mode, or in sleep mode. bit: 15 14 13 12 11 10 9 8 pb13md initial value:00000000 r/w:rrrrrr/wrr bit:76543210 initial value:00000000 r/w:rrrrrrrr bits 15 to 11reserved: these bits are always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 631 of 875 bit 10pb13 mode (pb13md): selects the function of the pb13/rdwr pin. bit 10: pb13md description 0 general input/output (pb13) (initial value) 1 read/write output (rdwr) (pb13 in single-chip mode) bits 9 to 0reserved: these bits are always read as 0 and should only be written with 0. port b control register l2 (pbcrl2) bit: 15 14 13 12 11 10 9 8 pb7mdpb6md initial value:00000000 r/w:rr/wrr/wrrrr bit:76543210 initial value:00000000 r/w:rrrrrrrr bit 15reserved: this bit is always read as 0 and should only be written with 0. bit 14pb7 mode (pb7md): selects the function of the pb7/ back pin. bit 14: pb7md description 0 general input/output (pb7) (initial value) 1 bus request acknowledge output ( back ) (pb7 in single-chip mode) bit 13reserved: this bit is always read as 0 and should only be written with 0. bit 12pb6 mode (pb6md): selects the function of the pb6/ breq pin. bit 12: pb6md description 0 general input/output (pb6) (initial value) 1 bus release request input ( breq ) (pb6 in single-chip mode) bits 11 to 0reserved: these bits are always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 632 of 875 17.3.9 port c io register h (pciorh) bit: 15 14 13 12 11 10 9 8 pc25iorpc24ior initial value:00000000 r/w:rrrrrrr/wr/w bit:76543210 pc23ior pc22ior pc21ior pc20ior pc19ior pc18ior pc17ior pc16ior initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port c io register h (pciorh) is a 16-bit readable/writable register that selects the input/output direction of pins in port c. bits pc25ior to pc16ior correspond to pins pc25/a25/tioc3b/tclkd to pc16/a16/tioc3a. pciorh is enabled when port c pins function as general input/output pins (pc25 to pc16) or tpu tioc pins, and disabled otherwise. when port c pins function as pc25 to pc16 or tpu tioc pins, a pin becomes an output when the corresponding bit in pciorh is set to 1, and an input when the bit is cleared to 0. pciorh is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. 17.3.10 port c io register l (pciorl) bit: 15 14 13 12 11 10 9 8 pc15ior pc14ior pc13ior pc12ior pc11ior pc10ior pc9ior pc8ior initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pc7ior pc6ior pc5ior pc4ior pc3ior pc2ior pc1ior pc0ior initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port c io register l (pciorl) is a 16-bit readable/writable register that selects the input/output direction of pins in port c. bits pc15ior to pc0ior correspond to pins pc15/a15/tioc3d to pc0/a0. pciorl is enabled when port c pins function as general input/output pins (pc15 to pc0) or tpu tioc pins, and disabled otherwise. rev. 1.0, 08/99, page 633 of 875 when port c pins function as pc15 to pc0 or tpu tioc pins, a pin becomes an output when the corresponding bit in pciorl is set to 1, and an input when the bit is cleared to 0. pciorl is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. 17.3.11 port c control registers h1 and h2 (pccrh1, pccrh2) port c control registers h1 and h2 (pccrh1, pccrh2) are 16-bit readable/writable registers that select the functions of pins in port c. pccrh1 selects the functions of port c pins pc25/a25/tioc3b/tclkd and pc24/a24/tioc3a/tclkc, and pccrh2 selects the functions of port c pins pc23/a23/tioc1b/tclkb to pc16/a16/tioc3a. port c includes address outputs (a16 to a25), but register settings relating to the selection of these pin functions may not be valid in all operating modes. for details, see table 17.2, pin functions in each operating mode. pccrh1 and pccrh2 are initialized to h'0000 by an external power-on reset, but are not initialized by a wdt reset, in standby mode, or in sleep mode. port c control register h1 (pccrh1) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 pc25 md1 pc25 md0 pc24 md1 pc24 md0 initial value:00000000 r/w:rrrrr/wr/wr/wr/w bits 15 to 4reserved: these bits are always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 634 of 875 bits 3 and 2pc25 mode 1 and 0 (pc25md1, pc25md0): these bits select the function of the pc25/a25/tioc3b/tclkd pin. bit 3: pc25md1 bit 2: pc25md0 description 0 0 general input/output (pc25) (initial value) (a25 in on-chip rom disabled modes) 1 address output (a25) (pc25 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc3b) 1 tpu clock input (tclkd) bits 1 and 0pc24 mode 1 and 0 (pc24md1, pc24md0): these bits select the function of the pc24/a24/tioc3a/tclkc pin. bit 1: pc24md1 bit 0: pc24md0 description 0 0 general input/output (pc24) (initial value) (a24 in on-chip rom disabled modes) 1 address output (a24) (pc24 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc3a) 1 tpu clock input (tclkc) port c control register h2 (pccrh2) bit: 15 14 13 12 11 10 9 8 pc23 md1 pc23 md0 pc22 md1 pc22 md0 pc21 md1 pc21 md0 pc20 md1 pc20 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pc19 md1 pc19 md0 pc18 md1 pc18 md0 pc17 md1 pc17 md0 pc16 md1 pc16 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w rev. 1.0, 08/99, page 635 of 875 bits 15 and 14pc23 mode 1 and 0 (pc23md1, pc23md0): these bits select the function of the pc23/a23/tioc1b/tclkb pin. bit 15: pc23md1 bit 14: pc23md0 description 0 0 general input/output (pc23) (initial value) (a23 in on-chip rom disabled modes) 1 address output (a23) (pc23 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc1b) 1 tpu clock input (tclkb) bits 13 and 12pc22 mode 1 and 0 (pc22md1, pc22md0): these bits select the function of the pc22/a22/tioc1a/tclka pin. bit 13: pc22md1 bit 12: pc22md0 description 0 0 general input/output (pc22) (initial value) (a22 in on-chip rom disabled modes) 1 address output (a22) (pc22 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc1a) 1 tpu clock input (tclka) bits 11 and 10pc21 mode 1 and 0 (pc21md1, pc21md0): these bits select the function of the pc21/a21/tioc5b pin. bit 11: pc21md1 bit 10: pc21md0 description 0 0 general input/output (pc21) (initial value) (a21 in on-chip rom disabled modes) 1 address output (a21) (pc21 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc5b) 1 reserved (do not set) rev. 1.0, 08/99, page 636 of 875 bits 9 and 8pc20 mode 1 and 0 (pc20md1, pc20md0): these bits select the function of the pc20/a20/tioc5a pin. bit 9: pc20md1 bit 8: pc20md0 description 0 0 general input/output (pc20) (initial value) (a20 in on-chip rom disabled modes) 1 address output (a20) (pc20 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc5a) 1 reserved (do not set) bits 7 and 6pc19 mode 1 and 0 (pc19md1, pc19md0): these bits select the function of the pc19/a19/tioc4b pin. bit 7: pc19md1 bit 6: pc19md0 description 0 0 general input/output (pc19) (initial value) (a19 in on-chip rom disabled modes) 1 address output (a19) (pc19 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc4b) 1 reserved (do not set) bits 5 and 4pc18 mode 1 and 0 (pc18md1, pc18md0): these bits select the function of the pc18/a18/tioc4a pin. bit 5: pc18md1 bit 4: pc18md0 description 0 0 general input/output (pc18) (initial value) (a18 in on-chip rom disabled modes) 1 address output (a18) (pc18 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc4a) 1 reserved (do not set) rev. 1.0, 08/99, page 637 of 875 bits 3 and 2pc17 mode 1 and 0 (pc17md1, pc17md0): these bits select the function of the pc17/a17/tioc3b pin. bit 3: pc17md1 bit 2: pc17md0 description 0 0 general input/output (pc17) (initial value) (a17 in on-chip rom disabled modes) 1 address output (a17) (pc17 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc3b) 1 reserved (do not set) bits 1 and 0pc16 mode 1 and 0 (pc16md1, pc16md0): these bits select the function of the pc16/a16/tioc3a pin. bit 1: pc16md1 bit 0: pc16md0 description 0 0 general input/output (pc16) (initial value) (a16 in on-chip rom disabled modes) 1 address output (a16) (pc16 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc3a) 1 reserved (do not set) 17.3.12 port c control registers l1 and l2 (pccrl1, pccrl2) port c control registers l1 and l2 (pccrl1, pccrl2) are 16-bit readable/writable registers that select the functions of pins in port c. pccrl1 selects the functions of port c pins pc15/a15/tioc3d to pc8/a8, and pccrl2 selects the functions of port c pins pc7/a7 to pc0/a0. port c includes address outputs (a0 to a15), but register settings relating to the selection of these pin functions may not be valid in all operating modes. for details, see table 17.2, pin functions in each operating mode. pccrl1 and pccrl2 are initialized to h'0000 by an external power-on reset, but are not initialized by a wdt reset, in standby mode, or in sleep mode. rev. 1.0, 08/99, page 638 of 875 port c control register l1 (pccrl1) bit: 15 14 13 12 11 10 9 8 pc15 md1 pc15 md0 pc14 md1 pc14 md0 pc13 md pc12 md initial value:00000000 r/w: r/w r/w r/w r/w r r/w r r/w bit:76543210 pc11 md pc10 md pc9 md pc8 md initial value:00000000 r/w:rr/wrr/wrr/wrr/w bits 15 and 14pc15 mode 1 and 0 (pc15md1, pc15md0): these bits select the function of the pc15/a15/tioc3d pin. bit 15: pc15md1 bit 14: pc15md0 description 0 0 general input/output (pc15) (initial value) (a15 in on-chip rom disabled modes) 1 address output (a15) (pc15 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc3d) 1 reserved (do not set) bits 13 and 12pc14 mode 1 and 0 (pc14md1, pc14md0): these bits select the function of the pc14/a14/tioc3c pin. bit 13: pc14md1 bit 12: pc14md0 description 0 0 general input/output (pc14) (initial value) (a14 in on-chip rom disabled modes) 1 address output (a14) (pc14 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc3c) 1 reserved (do not set) bit 11reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 639 of 875 bit 10pc13 mode (pc13md): selects the function of the pc13/a13 pin. bit 10: pc13md description 0 general input/output (pc13) (initial value) (a13 in on-chip rom disabled modes) 1 address output (a13) (pc13 in single-chip mode) bit 9reserved: this bit is always read as 0 and should only be written with 0. bit 8pc12 mode (pc12md): selects the function of the pc12/a12 pin. bit 8: pc12md description 0 general input/output (pc12) (initial value) (a12 in on-chip rom disabled modes) 1 address output (a12) (pc12 in single-chip mode) bit 7reserved: this bit is always read as 0 and should only be written with 0. bit 6pc11 mode (pc11md): selects the function of the pc11/a11 pin. bit 6: pc11md description 0 general input/output (pc11) (initial value) (a11 in on-chip rom disabled modes) 1 address output (a11) (pc11 in single-chip mode) bit 5reserved: this bit is always read as 0 and should only be written with 0. bit 4pc10 mode (pc10md): selects the function of the pc10/a10 pin. bit 4: pc10md description 0 general input/output (pc10) (initial value) (a10 in on-chip rom disabled modes) 1 address output (a10) (pc10 in single-chip mode) bit 3reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 640 of 875 bit 2pc9 mode (pc9md): selects the function of the pc9/a9 pin. bit 2: pc9md description 0 general input/output (pc9) (initial value) (a9 in on-chip rom disabled modes) 1 address output (a9) (pc9 in single-chip mode) bit 1reserved: this bit is always read as 0 and should only be written with 0. bit 0pc8 mode (pc8md): selects the function of the pc8/a8 pin. bit 0: pc8md description 0 general input/output (pc8) (initial value) (a8 in on-chip rom disabled modes) 1 address output (a8) (pc8 in single-chip mode) port c control register l2 (pccrl2) bit: 15 14 13 12 11 10 9 8 pc7mdpc6mdpc5mdpc4md initial value:00000000 r/w:rr/wrr/wrr/wrr/w bit:76543210 pc3mdpc2mdpc1mdpc0md initial value:00000000 r/w:rr/wrr/wrr/wrr/w bit 15reserved: this bit is always read as 0 and should only be written with 0. bit 14pc7 mode (pc7md): selects the function of the pc7/a7 pin. bit 14: pc7md description 0 general input/output (pc7) (initial value) (a7 in on-chip rom disabled modes) 1 address output (a7) (pc7 in single-chip mode) bit 13reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 641 of 875 bit 12pc6 mode (pc6md): selects the function of the pc6/a6 pin. bit 12: pc6md description 0 general input/output (pc6) (initial value) (a6 in on-chip rom disabled modes) 1 address output (a6) (pc6 in single-chip mode) bit 11reserved: this bit is always read as 0 and should only be written with 0. bit 10pc5 mode (pc5md): selects the function of the pc5/a5 pin. bit 10: pc5md description 0 general input/output (pc5) (initial value) (a5 in on-chip rom disabled modes) 1 address output (a5) (pc5 in single-chip mode) bit 9reserved: this bit is always read as 0 and should only be written with 0. bit 8pc4 mode (pc4md): selects the function of the pc4/a4 pin. bit 8: pc4md description 0 general input/output (pc4) (initial value) (a4 in on-chip rom disabled modes) 1 address output (a4) (pc4 in single-chip mode) bit 7reserved: this bit is always read as 0 and should only be written with 0. bit 6pc3 mode (pc3md): selects the function of the pc3/a3 pin. bit 6: pc3md description 0 general input/output (pc3) (initial value) (a3 in on-chip rom disabled modes) 1 address output (a3) (pc3 in single-chip mode) bit 5reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 642 of 875 bit 4pc2 mode (pc2md): selects the function of the pc2/a2 pin. bit 4: pc2md description 0 general input/output (pc2) (initial value) (a2 in on-chip rom disabled modes) 1 address output (a2) (pc2 in single-chip mode) bit 3reserved: this bit is always read as 0 and should only be written with 0. bit 2pc1 mode (pc1md): selects the function of the pc1/a1 pin. bit 2: pc1md description 0 general input/output (pc1) (initial value) (a1 in on-chip rom disabled modes) 1 address output (a1) (pc1 in single-chip mode) bit 1reserved: this bit is always read as 0 and should only be written with 0. bit 0pc0 mode (pc0md): selects the function of the pc0/a0 pin. bit 0: pc0md description 0 general input/output (pc0) (initial value) (a0 in on-chip rom disabled modes) 1 address output (a0) (pc0 in single-chip mode) 17.3.13 port d io register h (pdiorh) bit: 15 14 13 12 11 10 9 8 pd31ior pd30ior pd29ior pd28ior pd27ior pd26ior pd25ior pd24ior initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pd23ior pd22ior pd21ior pd20ior pd19ior pd18ior pd17ior pd16ior initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port d io register h (pdiorh) is a 16-bit readable/writable register that selects the input/output direction of pins in port d. bits pd31ior to pd16ior correspond to pins pd31/d31/rxd2/tioc5a to pd16/d16/ poe0 . pdiorh is enabled when port d pins function as rev. 1.0, 08/99, page 643 of 875 general input/output pins (pd31 to pd16), sci sck pins, or tpu tioc pins, or when pd23 functions as the mmt pcio pin, and disabled otherwise. when port d pins function as pd31 to pd16, sci sck pins, or tpu tioc pins, or when pd23 functions as the mmt pcio pin, a pin becomes an output when the corresponding bit in pdiorh is set to 1, and an input when the bit is cleared to 0. pdiorh is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. 17.3.14 port d io register l (pdiorl) bit: 15 14 13 12 11 10 9 8 pd15ior pd14ior pd13ior pd12ior pd11ior pd10ior pd9ior pd8ior initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pd7ior pd6ior pd5ior pd4ior pd3ior pd2ior pd1ior pd0ior initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port d io register l (pdiorl) is a 16-bit readable/writable register that selects the input/output direction of pins in port d. bits pd15ior to pd0ior correspond to pins pd15/d15/tioc5b to pd0/d0. pdiorl is enabled when port d pins function as general input/output pins (pd15 to pd0) or tpu tioc pins, and disabled otherwise. when port d pins function as pd15 to pd0 or tpu tioc pins, a pin becomes an output when the corresponding bit in pdiorl is set to 1, and an input when the bit is cleared to 0. pdiorl is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. rev. 1.0, 08/99, page 644 of 875 17.3.15 port d control registers h1 and h2 (pdcrh1, pdcrh2) port d control registers h1 and h2 (pdcrh1, pdcrh2) are 16-bit readable/writable registers that select the functions of pins in port d. pdcrh1 selects the functions of port d pins pd31/d31/rxd2/tioc5a to pd24/d24/puob, and pdcrh2 selects the functions of port d pins pd23/d23/pcio/sck1 to pd16/d16/ poe 0. port d includes data input/output functions (d16 to d31), but register settings relating to the selection of these pin functions may not be valid in all operating modes. for details, see table 17.2, pin functions in each operating mode. pdcrh1 and pdcrh2 are initialized to h'0000 by an external power-on reset, but are not initialized by a wdt reset, in standby mode, or in sleep mode. port d control register h1 (pdcrh1) bit: 15 14 13 12 11 10 9 8 pd31 md1 pd31 md0 pd30 md1 pd30 md0 pd29 md1 pd29 md0 pd28 md1 pd28 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pd27 md1 pd27 md0 pd26 md1 pd26 md0 pd25 md1 pd25 md0 pd24 md1 pd24 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14pd31 mode 1 and 0 (pd31md1, pd31md0): these bits select the function of the pd31/d31/rxd2/tioc5a pin. bit 15: pd31md1 bit 14: pd31md0 description 0 0 general input/output (pd31) (initial value) (d31 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d31) (pd31 in single-chip mode) 1 0 sci receive data input (rxd2) 1 tpu input capture input/output compare output (tioc5a) rev. 1.0, 08/99, page 645 of 875 bits 13 and 12pd30 mode 1 and 0 (pd30md1, pd30md0): these bits select the function of the pd30/d30/txd2/tioc4b pin. bit 13: pd30md1 bit 12: pd30md0 description 0 0 general input/output (pd30) (initial value) (d30 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d30) (pd30 in single-chip mode) 1 0 sci transmit data output (txd2) 1 tpu input capture input/output compare output (tioc4b) bits 11 and 10pd29 mode 1 and 0 (pd29md1, pd29md0): these bits select the function of the pd29/d29/sck2/tioc4a pin. bit 11: pd29md1 bit 10: pd29md0 description 0 0 general input/output (pd29) (initial value) (d29 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d29) (pd29 in single-chip mode) 1 0 sci clock input/output (sck2) 1 tpu input capture input/output compare output (tioc4a) bits 9 and 8pd28 mode 1 and 0 (pd28md1, pd28md0): these bits select the function of the pd28/d28/tclkb/tioc3d pin. bit 9: pd28md1 bit 8: pd28md0 description 0 0 general input/output (pd28) (initial value) (d28 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d28) (pd28 in single-chip mode) 1 0 tpu clock input (tclkb) 1 tpu input capture input/output compare output (tioc3d) rev. 1.0, 08/99, page 646 of 875 bits 7 and 6pd27 mode 1 and 0 (pd27md1, pd27md0): these bits select the function of the pd27/d27/tclka/tioc3c pin. bit 7: pd27md1 bit 6: pd27md0 description 0 0 general input/output (pd27) (initial value) (d27 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d27) (pd27 in single-chip mode) 1 0 tpu clock input (tclka) 1 tpu input capture input/output compare output (tioc3c) bits 5 and 4pd26 mode 1 and 0 (pd26md1, pd26md0): these bits select the function of the pd26/d26/pwob pin. bit 5: pd26md1 bit 4: pd26md0 description 0 0 general input/output (pd26) (initial value) (d26 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d26) (pd26 in single-chip mode) 1 0 mmt pwm w-phase output (pwob) 1 reserved (do not set) bits 3 and 2pd25 mode 1 and 0 (pd25md1, pd25md0): these bits select the function of the pd25/d25/pvob pin. bit 3: pd25md1 bit 2: pd25md0 description 0 0 general input/output (pd25) (initial value) (d25 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d25) (pd25 in single-chip mode) 1 0 mmt pwm v-phase output (pvob) 1 reserved (do not set) rev. 1.0, 08/99, page 647 of 875 bits 1 and 0pd24 mode 1 and 0 (pd24md1, pd24md0): these bits select the function of the pd24/d24/puob pin. bit 1: pd24md1 bit 0: pd24md0 description 0 0 general input/output (pd24) (initial value) (d24 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d24) (pd24 in single-chip mode) 1 0 mmt pwm u-phase output (puob) 1 reserved (do not set) port d control register h2 (pdcrh2) bit: 15 14 13 12 11 10 9 8 pd23 md1 pd23 md0 pd22 md1 pd22 md0 pd21 md1 pd21 md0 pd20 md1 pd20 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pd19 md1 pd19 md0 pd18 md1 pd18 md0 pd17 md1 pd17 md0 pd16 md1 pd16 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bits 15 and 14pd23 mode 1 and 0 (pd23md1, pd23md0): these bits select the function of the pd23/d23/pcio/sck1 pin. bit 15: pd23md1 bit 14: pd23md0 description 0 0 general input/output (pd23) (initial value) (d23 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d23) (pd23 in single-chip mode) 1 0 mmt pwm cycle output (pco)/counter clear input (pci) 1 sci clock input/output (sck1) rev. 1.0, 08/99, page 648 of 875 bits 13 and 12pd22 mode 1 and 0 (pd22md1, pd22md0): these bits select the function of the pd22/d22/pwoa/sck0 pin. bit 13: pd22md1 bit 12: pd22md0 description 0 0 general input/output (pd22) (initial value) (d22 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d22) (pd22 in single-chip mode) 1 0 mmt pwm w-phase output (pwoa) 1 sci clock input/output (sck0) bits 11 and 10pd21 mode 1 and 0 (pd21md1, pd21md0): these bits select the function of the pd21/d21/pvoa/ irq7 pin. bit 11: pd21md1 bit 10: pd21md0 description 0 0 general input/output (pd21) (initial value) (d21 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d21) (pd21 in single-chip mode) 1 0 mmt pwm v-phase output (pvoa) 1 external interrupt request input ( irq7 ) bits 9 and 8pd20 mode 1 and 0 (pd20md1, pd20md0): these bits select the function of the pd20/d20/puoa/ irq6 pin. bit 9: pd20md1 bit 8: pd20md0 description 0 0 general input/output (pd20) (initial value) (d20 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d20) (pd20 in single-chip mode) 1 0 mmt pwm u-phase output (puoa) 1 external interrupt request input ( irq6 ) rev. 1.0, 08/99, page 649 of 875 bits 7 and 6pd19 mode 1 and 0 (pd19md1, pd19md0): these bits select the function of the pd19/d19/ poe3 / irq5 pin. bit 7: pd19md1 bit 6: pd19md0 description 0 0 general input/output (pd19) (initial value) (d19 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d19) (pd19 in single-chip mode) 1 0 mmt port output enable input ( poe3 ) 1 external interrupt request input ( irq5 ) bits 5 and 4pd18 mode 1 and 0 (pd18md1, pd18md0): these bits select the function of the pd18/d18/ poe2 / irq4 pin. bit 5: pd18md1 bit 4: pd18md0 description 0 0 general input/output (pd18) (initial value) (d18 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d18) (pd18 in single-chip mode) 1 0 mmt port output enable input ( poe2 ) 1 external interrupt request input ( irq4 ) bits 3 and 2pd17 mode 1 and 0 (pd17md1, pd17md0): these bits select the function of the pd17/d17/ poe1 / adtrg pin. bit 3: pd17md1 bit 2: pd17md0 description 0 0 general input/output (pd17) (initial value) (d17 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d17) (pd17 in single-chip mode) 1 0 mmt port output enable input ( poe1 ) 1 a/d conversion trigger input ( adtrg ) rev. 1.0, 08/99, page 650 of 875 bits 1 and 0pd16 mode 1 and 0 (pd16md1, pd16md0): these bits select the function of the pd16/d16/ poe0 pin. bit 1: pd16md1 bit 0: pd16md0 description 0 0 general input/output (pd16) (initial value) (d16 in on-chip rom disabled modes with 32-bit cs0 bus width) 1 data input/output (d16) (pd16 in single-chip mode) 1 0 mmt port output enable input ( poe0 ) 1 reserved (do not set) 17.3.16 port d control registers l1 and l2 (pdcrl1, pdcrl2) port d control registers l1 and l2 (pdcrl1, pdcrl2) are 16-bit readable/writable registers that select the functions of pins in port d. pdcrl1 selects the functions of port d pins pd15/d15/tioc5b to pd8/d8/tioc1a, and pdcrl2 selects the functions of port d pins pd7/d7 to pd0/d0. port d includes data input/output functions (d0 to d15), but register settings relating to the selection of these pin functions may not be valid in all operating modes. for details, see table 17.2, pin functions in each operating mode. pdcrl1 and pdcrl2 are initialized to h'0000 by an external power-on reset, but are not initialized by a wdt reset, in standby mode, or in sleep mode. port d control register l1 (pdcrl1) bit: 15 14 13 12 11 10 9 8 pd15 md1 pd15 md0 pd14 md1 pd14 md0 pd13 md1 pd13 md0 pd12 md1 pd12 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pd11 md1 pd11 md0 pd10 md1 pd10 md0 pd9 md1 pd9 md0 pd8 md1 pd8 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w rev. 1.0, 08/99, page 651 of 875 bits 15 and 14pd15 mode 1 and 0 (pd15md1, pd15md0): these bits select the function of the pd15/d15/tioc5b pin. bit 15: pd15md1 bit 14: pd15md0 description 0 0 general input/output (pd15) (initial value) (d15 in on-chip rom disabled modes with 32-bit/16-bit cs0 bus width) 1 data input/output (d15) (pd15 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc5b) 1 reserved (do not set) bits 13 and 12pd14 mode 1 and 0 (pd14md1, pd14md0): these bits select the function of the pd14/d14/tioc5a pin. bit 13: pd14md1 bit 12: pd14md0 description 0 0 general input/output (pd14) (initial value) (d14 in on-chip rom disabled modes with 32-bit/16-bit cs0 bus width) 1 data input/output (d14) (pd14 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc5a) 1 reserved (do not set) bits 11 and 10pd13 mode 1 and 0 (pd13md1, pd13md0): these bits select the function of the pd13/d13/tioc4b pin. bit 11: pd13md1 bit 10: pd13md0 description 0 0 general input/output (pd13) (initial value) (d13 in on-chip rom disabled modes with 32-bit/16-bit cs0 bus width) 1 data input/output (d13) (pd13 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc4b) 1 reserved (do not set) rev. 1.0, 08/99, page 652 of 875 bits 9 and 8pd12 mode 1 and 0 (pd12md1, pd12md0): these bits select the function of the pd12/d12/tioc4a pin. bit 9: pd12md1 bit 8: pd12md0 description 0 0 general input/output (pd12) (initial value) (d12 in on-chip rom disabled modes with 32-bit/16-bit cs0 bus width) 1 data input/output (d12) (pd12 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc4a) 1 reserved (do not set) bits 7 and 6pd11 mode 1 and 0 (pd11md1, pd11md0): these bits select the function of the pd11/d11/tioc2b pin. bit 7: pd11md1 bit 6: pd11md0 description 0 0 general input/output (pd11) (initial value) (d11 in on-chip rom disabled modes with 32-bit/16-bit cs0 bus width) 1 data input/output (d11) (pd11 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc2b) 1 reserved (do not set) bits 5 and 4pd10 mode 1 and 0 (pd10md1, pd10md0): these bits select the function of the pd10/d10/tioc2a pin. bit 5: pd10md1 bit 4: pd10md0 description 0 0 general input/output (pd10) (initial value) (d10 in on-chip rom disabled modes with 32-bit/16-bit cs0 bus width) 1 data input/output (d10) (pd10 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc2a) 1 reserved (do not set) rev. 1.0, 08/99, page 653 of 875 bits 3 and 2pd9 mode 1 and 0 (pd9md1, pd9md0): these bits select the function of the pd9/d9/tioc1b pin. bit 3: pd9md1 bit 2: pd9md0 description 0 0 general input/output (pd9) (initial value) (d9 in on-chip rom disabled modes with 32-bit/16-bit cs0 bus width) 1 data input/output (d9) (pd9 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc1b) 1 reserved (do not set) bits 1 and 0pd8 mode 1 and 0 (pd8md1, pd8md0): these bits select the function of the pd8/d8/tioc1a pin. bit 1: pd8md1 bit 0: pd8md0 description 0 0 general input/output (pd8) (initial value) (d8 in on-chip rom disabled modes with 32-bit/16-bit cs0 bus width) 1 data input/output (d8) (pd8 in single-chip mode) 1 0 tpu input capture input/output compare output (tioc1a) 1 reserved (do not set) port d control register l2 (pdcrl2) bit: 15 14 13 12 11 10 9 8 pd7mdpd6mdpd5mdpd4md initial value:00000000 r/w:rr/wrr/wrr/wrr/w bit:76543210 pd3mdpd2mdpd1mdpd0md initial value:00000000 r/w:rr/wrr/wrr/wrr/w bit 15reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 654 of 875 bit 14pd7 mode (pd7md): selects the function of the pd7/d7 pin. bit 14: pd7md description 0 general input/output (pd7) (initial value) (d7 in on-chip rom disabled modes) 1 data input/output (d7) (pd7 in single-chip mode) bit 13reserved: this bit is always read as 0 and should only be written with 0. bit 12pd6 mode (pd6md): selects the function of the pd6/d6 pin. bit 12: pd6md description 0 general input/output (pd6) (initial value) (d6 in on-chip rom disabled modes) 1 data input/output (d6) (pd6 in single-chip mode) bit 11reserved: this bit is always read as 0 and should only be written with 0. bit 10pd5 mode (pd5md): selects the function of the pd5/d5 pin. bit 10: pd5md description 0 general input/output (pd5) (initial value) (d5 in on-chip rom disabled modes) 1 data input/output (d5) (pd5 in single-chip mode) bit 9reserved: this bit is always read as 0 and should only be written with 0. bit 8pd4 mode (pd4md): selects the function of the pd4/d4 pin. bit 8: pd4md description 0 general input/output (pd4) (initial value) (d4 in on-chip rom disabled modes) 1 data input/output (d4) (pd4 in single-chip mode) bit 7reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 655 of 875 bit 6pd3 mode (pd3md): selects the function of the pd3/d3 pin. bit 6: pd3md description 0 general input/output (pd3) (initial value) (d3 in on-chip rom disabled modes) 1 data input/output (d3) (pd3 in single-chip mode) bit 5reserved: this bit is always read as 0 and should only be written with 0. bit 4pd2 mode (pd2md): selects the function of the pd2/d2 pin. bit 4: pd2md description 0 general input/output (pd2) (initial value) (d2 in on-chip rom disabled modes) 1 data input/output (d2) (pd2 in single-chip mode) bit 3reserved: this bit is always read as 0 and should only be written with 0. bit 2pd1 mode (pd1md): selects the function of the pd1/d1 pin. bit 2: pd1md description 0 general input/output (pd1) (initial value) (d1 in on-chip rom disabled modes) 1 data input/output (d1) (pd1 in single-chip mode) bit 1reserved: this bit is always read as 0 and should only be written with 0. bit 0pd0 mode (pd0md): selects the function of the pd0/d0 pin. bit 0: pd0md description 0 general input/output (pd0) (initial value) (d0 in on-chip rom disabled modes) 1 data input/output (d0) (pd0 in single-chip mode) rev. 1.0, 08/99, page 656 of 875 17.3.17 port e io register h (peiorh) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 pe23ior pe22ior pe21ior pe20ior pe19ior pe18ior pe17ior pe16ior initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port e io register h (peiorh) is a 16-bit readable/writable register that selects the input/output direction of pins in port e. bits pe23ior to pe16ior correspond to pins pe23/ irq7 /pwob to pe16/ irq0 /sck1/ ah . peiorh is enabled when port e pins function as general input/output pins (pe23 to pe16) or as sci sck pins, or when pe20 functions as the mmt pcio pin, and disabled otherwise. when port e pins function as pe23 to pe16 or as sci sck pins, or when pe20 functions as the mmt pcio pin, a pin becomes an output when the corresponding bit in peiorh is set to 1, and an input when the bit is cleared to 0. peiorh is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. 17.3.18 port e io register l (peiorl) bit: 15 14 13 12 11 10 9 8 pe15iorpe14iorpe13iorpe12ior initial value:00000000 r/w:r/wr/wr/wr/wrrrr bit:76543210 initial value:00000000 r/w:rrrrrrrr port e io register l (peiorl) is a 16-bit readable/writable register that selects the input/output direction of pins in port e. bits pe15ior to pe12ior correspond to pins pe15/ irq7 to rev. 1.0, 08/99, page 657 of 875 pe12/ irq4 . peiorl is enabled when port e pins function as general input/output pins (pe15 to pe12), and disabled otherwise. when port e pins function as pe15 to pe12, a pin becomes an output when the corresponding bit in peiorl is set to 1, and an input when the bit is cleared to 0. peiorl is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. 17.3.19 port e control register h2 (pecrh2) bit: 15 14 13 12 11 10 9 8 pe23 md1 pe23 md0 pe22 md1 pe22 md0 pe21 md1 pe21 md0 pe20 md1 pe20 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pe19 md1 pe19 md0 pe18 md1 pe18 md0 pe17 md1 pe17 md0 pe16 md1 pe16 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port e control register h2 (pecrh2) is a 16-bit readable/writable register that selects the functions of pins in port e. pecrh2 selects the functions of port e pins pe23/ irq7 /tioc0c to pe16/ irq0 /sck1/ ah . port e includes a bus control signal ( ah ), but register settings relating to the selection of this pin function may not be valid in all operating modes. for details, see table 17.2, pin functions in each operating mode. pecrh2 is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. rev. 1.0, 08/99, page 658 of 875 bits 15 and 14pe23 mode 1 and 0 (pe23md1, pe23md0): these bits select the function of the pe23/ irq7 /pwob pin. bit 15: pe23md1 bit 14: pe23md0 description 0 0 general input/output (pe23) (initial value) 1 external interrupt request input ( irq7 ) 1 0 mmt pwm w-phase output (pwob) 1 reserved (do not set) bits 13 and 12pe22 mode 1 and 0 (pe22md1, pe22md0): these bits select the function of the pe22/ irq6 /pvob pin. bit 13: pe22md1 bit 12: pe22md0 description 0 0 general input/output (pe22) (initial value) 1 external interrupt request input ( irq6 ) 1 0 mmt pwm v-phase output (pvob) 1 reserved (do not set) bits 11 and 10pe21 mode 1 and 0 (pe21md1, pe21md0): these bits select the function of the pe21/ irq5 /puob pin. bit 11: pe21md1 bit 10: pe21md0 description 0 0 general input/output (pe21) (initial value) 1 external interrupt request input ( irq5 ) 1 0 mmt pwm u-phase output (puob) 1 reserved (do not set) bits 9 and 8pe20 mode 1 and 0 (pe20md1, pe20md0): these bits select the function of the pe20/ irq4 /pcio pin. bit 9: pe20md1 bit 8: pe20md0 description 0 0 general input/output (pe20) (initial value) 1 external interrupt request input ( irq4 ) 1 0 mmt pwm cycle output (pco)/counter clear input (pci) 1 reserved (do not set) rev. 1.0, 08/99, page 659 of 875 bits 7 and 6pe19 mode 1 and 0 (pe19md1, pe19md0): these bits select the function of the pe19/ irq3 /pwoa pin. bit 7: pe19md1 bit 6: pe19md0 description 0 0 general input/output (pe19) (initial value) 1 external interrupt request input ( irq3 ) 1 0 mmt pwm w-phase output (pwoa) 1 reserved (do not set) bits 5 and 4pe18 mode 1 and 0 (pe18md1, pe18md0): these bits select the function of the pe18/ irq2 /pvoa pin. bit 5: pe18md1 bit 4: pe18md0 description 0 0 general input/output (pe18) (initial value) 1 external interrupt request input ( irq2 ) 1 0 mmt pwm v-phase output (pvoa) 1 reserved (do not set) bits 3 and 2pe17 mode 1 and 0 (pe17md1, pe17md0): these bits select the function of the pe17/ irq1 /puoa/sck0 pin. bit 3: pe17md1 bit 2: pe17md0 description 0 0 general input/output (pe17) (initial value) 1 external interrupt request input ( irq1 ) 1 0 mmt pwm u-phase output (puoa) 1 sci clock input/output (sck0) bits 1 and 0pe16 mode 1 and 0 (pe16md1, pe16md0): these bits select the function of the pe16/ irq0 /sck1/ ah pin. bit 1: pe16md1 bit 0: pe16md0 description 0 0 general input/output (pe16) (initial value) 1 external interrupt request input ( irq0 ) 1 0 sci clock input/output (sck1) 1 address hold output ( ah ) (pe16 in single-chip mode) rev. 1.0, 08/99, page 660 of 875 17.3.20 port e control register l (pecrl) bit: 15 14 13 12 11 10 9 8 pe15md pe14md pe13md pe12md initial value:00000000 r/w:rr/wrr/wrr/wrr/w bit:76543210 initial value:00000000 r/w:rrrrrrrr port e control register l (pecrl) is a 16-bit readable/writable register that selects the functions of pins in port e. pecrl selects the functions of port e pins pe15/ irq7 to pe12/ irq4 . pecrl is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. bit 15reserved: this bit is always read as 0 and should only be written with 0. bit 14pe15 mode (pe15md): selects the function of the pe15/ irq7 pin. bit 14: pe15md description 0 general input/output (pe15) (initial value) 1 external interrupt request input ( irq7 ) bit 13reserved: this bit is always read as 0 and should only be written with 0. bit 12pe14 mode (pe14md): selects the function of the pe14/ irq6 pin. bit 12: pe14md description 0 general input/output (pe14) (initial value) 1 external interrupt request input ( irq6 ) bit 11reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 661 of 875 bit 10pe13 mode (pe13md): selects the function of the pe13/ irq5 pin. bit 10: pe13md description 0 general input/output (pe13) (initial value) 1 external interrupt request input ( irq5 ) bit 9reserved: this bit is always read as 0 and should only be written with 0. bit 8pe12 mode (pe12md): selects the function of the pe12/ irq4 pin. bit 8: pe12md description 0 general input/output (pe12) (initial value) 1 external interrupt request input ( irq4 ) bits 7 to 0reserved: these bits are always read as 0 and should only be written with 0. 17.3.21 port f io register l (pfiorl) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 pf7ior pf6ior pf5ior pf3ior pf2ior pf1ior initial value:00000000 r/w: r/w r/w r/w r r/w r/w r/w r port f io register l (pfiorl) is a 16-bit readable/writable register that selects the input/output direction of pins in port f. bits pf7ior to pf1ior correspond to pins pf7/ dreq1 / irqout /tioc0d to pf1/ dack0 /tioc0b. pfiorl is enabled when port f pins function as general input/output pins (pf7 to pf1) or tpu tioc pins, and disabled otherwise. when port f pins function as pf7 to pf1 or tpu tioc pins, a pin becomes an output when the corresponding bit in pfiorl is set to 1, and an input when the bit is cleared to 0. pfiorl is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. rev. 1.0, 08/99, page 662 of 875 17.3.22 port f control register l2 (pfcrl2) bit: 15 14 13 12 11 10 9 8 pf7 md1 pf7 md0 pf6 md1 pf6 md0 pf5 md1 pf5 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r r bit:76543210 pf3 md1 pf3 md0 pf2 md1 pf2 md0 pf1 md1 pf1 md0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r r port f control register l2 (pfcrl2) is a 16-bit readable/writable register that selects the functions of pins in port f. pfcrl2 selects the functions of port f pins pf7/ dreq1 / irqout /tioc0d to pf1/ dack0 /tioc0b. port f includes dmac control signals ( dreq0 , dreq1 , drak0 , drak1 , dack0 , and dack1 ), but register settings relating to the selection of these pin functions may not be valid in all operating modes. for details, see table 17.2, pin functions in each operating mode. pfcrl2 is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. bits 15 and 14pf7 mode 1 and 0 (pf7md1, pf7md0): these bits select the function of the pf7/ dreq1 / irqout /tioc0d pin. bit 15: pf7md1 bit 14: pf7md0 description 0 0 general input/output (pf7) (initial value) 1 dma transfer request input ( dreq1 ) (pf7 in single-chip mode) 1 0 interrupt request acknowledge output ( irqout ) 1 tpu input capture input/output compare output (tioc0d) rev. 1.0, 08/99, page 663 of 875 bits 13 and 12pf6 mode 1 and 0 (pf6md1, pf6md0): these bits select the function of the pf6/ drak1 /txd1/tioc2a pin. bit 13: pf6md1 bit 12: pf6md0 description 0 0 general input/output (pf6) (initial value) 1 dma transfer request sampling output( drak1 ) (pf6 in single-chip mode) 1 0 sci transmit data output (txd1) 1 tpu input capture input/output compare output (tioc2a) bits 11 and 10pf5 mode 1 and 0 (pf5md1, pf5md0): these bits select the function of the pf5/ dack1 /rxd1/tioc2b pin. bit 11: pf5md1 bit 10: pf5md0 description 0 0 general input/output (pf5) (initial value) 1 dma transfer request acknowledge output( dack1 ) (pf5 in single-chip mode) 1 0 sci receive data input (rxd1) 1 tpu input capture input/output compare output (tioc2b) bits 9 and 8reserved: these bits are always read as 0 and should only be written with 0. bits 7 and 6pf3 mode 1 and 0 (pf3md1, pf3md0): these bits select the function of the pf3/ dreq0 /tioc0a pin. bit 7: pf3md1 bit 6: pf3md0 description 0 0 general input/output (pf3) (initial value) 1 dma transfer request input ( dreq0 ) 1 0 tpu input capture input/output compare output (tioc0a) 1 reserved (do not set) rev. 1.0, 08/99, page 664 of 875 bits 5 and 4pf2 mode 1 and 0 (pf2md1, pf2md0): these bits select the function of the pf2/ drak0 /tioc0c pin. bit 5: pf2md1 bit 4: pf2md0 description 0 0 general input/output (pf2) (initial value) 1 dma transfer request sampling output ( drak0 ) 1 0 tpu input capture input/output compare output (tioc0c) 1 reserved (do not set) bits 3 and 2pf1 mode 1 and 0 (pf1md1, pf1md0): these bits select the function of the pf1/ dack0 /tioc0b pin. bit 3: pf1md1 bit 2: pf1md0 description 0 0 general input/output (pf1) (initial value) 1 dma transfer request acknowledge output ( dack0 ) 1 0 tpu input capture input/output compare output (tioc0b) 1 reserved (do not set) bits 1 and 0reserved: these bits are always read as 0 and should only be written with 0. 17.3.23 port g io register (pgior) bit: 15 14 13 12 11 10 9 8 pg31iorpg30iorpg29ior initial value:00000000 r/w:r/wr/wr/wrrrrr bit:76543210 initial value:00000000 r/w:rrrrrrrr the port g io register (pgior) is a 16-bit readable/writable register that selects the input/output direction of pins in port g. bits pg31ior to pg29ior correspond to pins pg31/rxd2 to pg29/sck2. pgior is enabled when port g pins function as general input/output pins (pg31 to pg29) or when pg29 functions as an sci sck pin, and disabled otherwise. rev. 1.0, 08/99, page 665 of 875 when port g pins function as pg31 to pg29 or when pg29 functions as an sci sck pin, a pin becomes an output when the corresponding bit in pgior is set to 1, and an input when the bit is cleared to 0. pgior is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. 17.3.24 port g control register h1 (pgcrh1) bit: 15 14 13 12 11 10 9 8 pg31md pg30md pg29md initial value:00000000 r/w:rr/wrr/wrr/wr r bit:76543210 initial value:00000000 r/w:rrrrrrrr port g control register h1 (pgcrh1) is a 16-bit readable/writable register that selects the functions of pins in port g. pgcrh1 selects the functions of port g pins pg31/rxd2 to pg29/sck2. pgcrh1 is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. bit 15reserved: this bit is always read as 0 and should only be written with 0. bit 14pg31 mode (pg31md): selects the function of the pg31/rxd2 pin. bit 14: pg31md description 0 general input/output (pg31) (initial value) 1 sci receive data input (rxd2) bit 13reserved: this bit is always read as 0 and should only be written with 0. rev. 1.0, 08/99, page 666 of 875 bit 12pg30 mode (pg30md): selects the function of the pg30/txd2 pin. bit 12: pg30md description 0 general input/output (pg30) (initial value) 1 sci transmit data output (txd2) bit 11reserved: this bit is always read as 0 and should only be written with 0. bit 10pg29 mode (pg29md): selects the function of the pg29/sck2 pin. bit 10: pg29md description 0 general input/output (pg29) (initial value) 1 sci clock input/output (sck2) bits 9 to 0reserved: these bits are always read as 0 and should only be written with 0. 17.3.25 port h io register (phior) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 ph1iorph0ior initial value:00000000 r/w:rrrrrrr/wr/w the port h io register (phior) is a 16-bit readable/writable register that selects the input/output direction of pins in port h. bits ph1ior and ph0ior correspond to pins ph1/da1 to ph0/da0. phior is enabled when port h pins function as general input/output pins (ph1 and ph0), and disabled otherwise. when port h pins function as ph1 and ph0, a pin becomes an output when the corresponding bit in phior is set to 1, and an input when the bit is cleared to 0. phior is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. rev. 1.0, 08/99, page 667 of 875 17.3.26 port h control register (phcr) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 ph1mdph0md initial value:00000000 r/w:rrrrrr/wrr/w the port h control register (phcr) is a 16-bit readable/writable register that selects the functions of pins in port h. phcr selects the functions of port h pins ph1/da1 and ph0/da0. phcr is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. bits 15 to 3reserved: these bits are always read as 0 and should only be written with 0. bit 2ph1 mode (ph1md): selects the function of the ph1/da1 pin. bit 2: ph1md description 0 general input/output (ph1) (initial value) 1 d/a converter output (da1) bit 1reserved: this bit is always read as 0 and should only be written with 0. bit 0ph0 mode (ph0md): selects the function of the ph0/da0 pin. bit 0: ph0md description 0 general input/output (ph0) (initial value) 1 d/a converter output (da0) rev. 1.0, 08/99, page 668 of 875 17.3.27 function control register (fcr) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 scimdirqmd1irqmd0 initial value:00000000 r/w:rrrrrr/wr/wr/w the function control register (fcr) is a 16-bit readable/writable register that is sued to control the irqout output and sci outputs (sck0 to sck2 and txd0 to txd2). if the port control register settings specify a function other than irqout or sci output, the settings in this register do not affect the pin functions. fcr is initialized to h'0000 by an external power-on reset, but is not initialized by a wdt reset, in standby mode, or in sleep mode. bits 15 to 3reserved: these bits are always read as 0 and should only be written with 0. bit 2sci output mode (scimd): selects the function of the sci output pins. bit 2: scimd description 0 output by normal cmos circuit (initial value) 1 output by open-drain circuit bits 1 and 0irqout mode 1 and 0 (irqmd1, irqmd0): these bits select the function of the irqout pin. bit 1: irqmd1 bit 0: irqmd0 description 0 0 interrupt request acknowledge output (initial value) 1 refresh signal output 1 0 interrupt request acknowledge or refresh signal output (depending on the current operating state) 1 always high-level output rev. 1.0, 08/99, page 669 of 875 section 18 i/o ports (i/o) 18.1 overview the sh7065 has nine ports: a, b, c, d, e, f, g, h, and i. all the port pins are multiplexed as general input/output pins (general input pins in the case of port i) and special function pins. the functions of the multiplex pins are selected by means of the pin function controller (pfc). each port is provided with a data register for storing the pin data. the initial state of each pin after a power-on reset depends on the operating mode. for details, see table 17.2, pin functions in each operating mode. 18.2 port a port a is an input/output port with the 18 pins shown in figures 18.1 and 18.2. expanded mode with on-chip rom disabled expanded mode with on-chip rom enabled single-chip mode port a pa25 (input/output) / (output) pa24 (input/output) / (output) pa23 (input/output) / (output) pa22 (input/output) / (output) pa21 (input/output) / (output) (output) (output) (output) pa17 (input/output) / (output) (output) / (output) / tclkc (input) / tioc3a (input/output) pa25 (input/output) / (output) pa24 (input/output) / (output) pa23 (input/output) / (output) pa22 (input/output) / (output) pa21 (input/output) / (output) pa20 (input/output) / (output) pa19 (input/output) / (output) pa18 (input/output) / (output) pa17 (input/output) / (output) pa16 (input/output) / (output) / (output) / tclkc (input) / tioc3a (input/output) pa25 (input/output) pa16 (input/output) / tclkc (input) / tioc3a (input/output) pa24 (input/output) pa23 (input/output) pa22 (input/output) pa21 (input/output) pa20 (input/output) pa19 (input/output) pa18 (input/output) pa17 (input/output) figure 18.1 port a (pa25 to pa16) rev. 1.0, 08/99, page 670 of 875 expanded mode with on-chip rom disabled expanded mode with on-chip rom enabled single-chip mode port a (output) / (output) / tclkd (input) / tioc3b (input/output) (output) / (output) l (output) / (output) pa12 (input/output) / (input) pa9 (input/output) / (output) pa8 (input/output) / (output) pa1 (input/output) / (output) pa0 (input/output) / (output) pa15 (input/output) / (output) / (output) / tclkd (input) / tioc3b (input/output) pa14 (input/output) / (output) / (output) pa13 (input/output) / (output) / (output) pa12 (input/output) / (input) pa9 (input/output) / (output) pa8 (input/output) / (output) pa1 (input/output) / (output) pa0 (input/output) / (output) pa15 (input/output) / tclkd (input) / tioc3b (input/output) pa14 (input/output) pa13 (input/output) pa12 (input/output) pa9 (input/output) pa8 (input/output) pa1 (input/output) pa0 (input/output) figure 18.2 port a (pa15 to pa0) 18.2.1 register configuration the port a registers are shown in table 18.1. table 18.1 port a registers name abbreviation r/w initial value address access size port a data register h padrh r/w h'0000 h'ffff 1200 8, 16, 32 port a data register l padrl r/w h'0000 h'ffff 1202 8, 16, 32 rev. 1.0, 08/99, page 671 of 875 18.2.2 port a data register h (padrh) bit: 15 14 13 12 11 10 9 8 pa25drpa24dr initial value:00000000 r/w:rrrrrrr/wr/w bit:76543210 pa23dr pa22dr pa21dr pa20dr pa19dr pa18dr pa17dr pa16dr initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port a data register h (padrh) is a 16-bit readable/writable register that stores port a data. bits pa25dr to pa16dr correspond to pins pa25/ cs5 to pa16/ wrhh / hhbs /tclkc/tioc3a. when a pin functions as a general output, if a value is written to padrh, that value is output directly from the pin, and if padrh is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if padrh is read the pin state, not the register value, is returned directly. if a value is written to padrh, although that value is written into padrh it does not affect the pin state. table 18.2 summarizes port a data register read/write operations. padrh is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. rev. 1.0, 08/99, page 672 of 875 18.2.3 port a data register l (padrl) bit: 15 14 13 12 11 10 9 8 pa15dr pa14dr pa13dr pa12dr pa9dr pa8dr initial value:00000000 r/w: r/w r/w r/w r/w r r r/w r/w bit:76543210 pa1drpa0dr initial value:00000000 r/w:rrrrrrr/wr/w port a data register l (padrl) is a 16-bit readable/writable register that stores port a data. bits pa15dr to pa0dr correspond to pins pa15/ wrhl / hlbs /tclkd/tioc3b to pa0/ oe0 . when a pin functions as a general output, if a value is written to padrl, that value is output directly from the pin, and if padrl is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if padrl is read the pin state, not the register value, is returned directly. if a value is written to padrl, although that value is written into padrl it does not affect the pin state. table 18.2 summarizes port a data register read/write operations. padrl is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. table 18.2 port a data register (padr) read/write operations paior pin function read write 0 general input pin state value is written to padr, but does not affect pin state other than general input pin state or fixed value value is written to padr, but does not affect pin state 1 general output padr value write value is output from pin other than general output padr value value is written to padr, but does not affect pin state rev. 1.0, 08/99, page 673 of 875 18.3 port b port b is an input/output port with the 11 pins shown in figures 18.3 and 18.4. expanded mode with on-chip rom disabled expanded mode with on-chip rom enabled single-chip mode port b pb23 (input/output) / (output) / txd1 (output) / (output) pb22 (input/output) / (output) / rxd1 (input) / (output) pb21 (input/output) / (output) pb20 (input/output) / (output) pb19 (input/output) / (output) / txd0 (output) pb18 (input/output) / (output) / rxd0 (input) pb17 (input/output) / (output) pb16 (input/output) / (output) pb23 (input/output) / txd1 (output) pb22 (input/output) / rxd1 (input) pb21 (input/output) pb20 (input/output) pb19 (input/output) / txd0 (output) pb18 (input/output) / rxd0 (input) pb17 (input/output) pb16 (input/output) pb23 (input/output) / (output) / txd1 (output) / (output) pb22 (input/output) / (output) / rxd1 (input) / (output) pb21 (input/output) / (output) pb20 (input/output) / (output) pb19 (input/output) / (output) / txd0 (output) pb18 (input/output) / (output) / rxd0 (input) pb17 (input/output) / (output) pb16 (input/output) / (output) figure 18.3 port b (pb23 to pb16) expanded mode with on-chip rom disabled expanded mode with on-chip rom enabled single-chip mode port b pb7 (input/output) / (output) pb6 (input/output) / (output) pb7 (input/output) pb7 (input/output) / (output) pb13 (input/output) / rdwr (output) pb13 (input/output) pb13 (input/output) / rdwr (output) pb6 (input/output) / (output) pb6 (input/output) figure 18.4 port b (pb13, pb7, and pb6) rev. 1.0, 08/99, page 674 of 875 18.3.1 register configuration the port b registers are shown in table 18.3. table 18.3 port b registers name abbreviation r/w initial value address access size port b data register h pbdrh r/w h'0000 h'ffff 1210 8, 16, 32 port b data register l pbdrl r/w h'0000 h'ffff 1212 8, 16, 32 18.3.2 port b data register h (pbdrh) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 pb23dr pb22dr pb21dr pb20dr pb19dr pb18dr pb17dr pb16dr initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port b data register h (pbdrh) is a 16-bit readable/writable register that stores port b data. bits pb23dr to pb16dr correspond to pins pb23/ cashh1 /txd1/ tend0 to pb16/ casll0 . when a pin functions as a general output, if a value is written to pbdrh, that value is output directly from the pin, and if pbdrh is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pbdrh is read the pin state, not the register value, is returned directly. if a value is written to pbdrh, although that value is written into pbdrh it does not affect the pin state. table 18.4 summarizes port b data register read/write operations. pbdrh is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. rev. 1.0, 08/99, page 675 of 875 18.3.3 port b data register l (pbdrl) bit: 15 14 13 12 11 10 9 8 pb13dr initial value:00000000 r/w:rrr/wrrrrr bit:76543210 pb7drpb6dr initial value:00000000 r/w:r/wr/wrrrrrr port b data register l (pbdrl) is a 16-bit readable/writable register that stores port b data. bits pb13dr to pb6dr correspond to pins pb13/rdwr to pb6/ breq . when a pin functions as a general output, if a value is written to pbdrl, that value is output directly from the pin, and if pbdrl is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pbdrl is read the pin state, not the register value, is returned directly. if a value is written to pbdrl, although that value is written into pbdrl it does not affect the pin state. table 18.4 summarizes port b data register read/write operations. pbdrl is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. table 18.4 port b data register (pbdr) read/write operations pbior pin function read write 0 general input pin state value is written to pbdr, but does not affect pin state other than general input pin state or fixed value value is written to pbdr, but does not affect pin state 1 general output pbdr value write value is output from pin other than general output pbdr value value is written to pbdr, but does not affect pin state rev. 1.0, 08/99, page 676 of 875 18.4 port c port c is an input/output port with the 26 pins shown in figures 18.5 and 18.6. expanded mode with on-chip rom disabled expanded mode with on-chip rom enabled single-chip mode port c a25 (output) / tioc3b (input/output) / tclkd (input) a24 (output) / tioc3a (input/output) / tclkc (input) a23 (output) / tioc1b (input/output) / tclkb (input) a22 (output) / tioc1a (input/output) / tclka (input) a21 (output) / tioc5b (input/output) a20 (output) / tioc5a (input/output) a19 (output) / tioc4b (input/output) a18 (output) / tioc4a (input/output) a17 (output) / tioc3b (input/output) a16 (output) / tioc3a (input/output) pc25 (input/output) / a25 (output) / tioc3b (input/output) / tclkd (input) pc24 (input/output) / a24 (output) / tioc3a (input/output) / tclkc (input) pc23 (input/output) / a23 (output) / tioc1b (input/output) / tclkb (input) pc22 (input/output) / a22 (output) / tioc1a (input/output) / tclka (input) pc21 (input/output) / a21 (output) / tioc5b (input/output) pc20 (input/output) / a20 (output) / tioc5a (input/output) pc19 (input/output) / a19 (output) / tioc4b (input/output) pc18 (input/output) / a18 (output) / tioc4a (input/output) pc17 (input/output) / a17 (output) / tioc3b (input/output) pc16 (input/output) / a16 (output) / tioc3a (input/output) pc25 (input/output) / tioc3b (input/output) / tclkd (input) pc24 (input/output) / tioc3a (input/output) / tclkc (input) pc3 (input/output) / tioc1b (input/output) / tclkb (input) pc22 (input/output) / tioc1a (input/output) / tclka (input) pc21 (input/output) / tioc5b (input/output) pc20 (input/output) / tioc5a (input/output) pc19 (input/output) / tioc4b (input/output) pc18 (input/output) / tioc4a (input/output) pc17 (input/output) / tioc3b (input/output) pc16 (input/output) / tioc3a (input/output) figure 18.5 port c (pc25 to pc16) rev. 1.0, 08/99, page 677 of 875 expanded mode with on-chip rom disabled expanded mode with on-chip rom enabled single-chip mode port c a15 (output) / tioc3d (input/output) a14 (output) / tioc3c (input/output) a13 (output) a12 (output) a11 (output) a10 (output) a9 (output) a8 (output) a7 (output) a6 (output) pc15 (input/output) / a15 (output) / tioc3d (input/output) pc14 (input/output) / a14 (output) / tioc3c (input/output) pc13 (input/output) / a13 (output) pc12 (input/output) / a12 (output) pc11 (input/output) / a11 (output) pc10 (input/output) / a10 (output) pc9 (input/output) / a9 (output) pc8 (input/output) / a8 (output) pc7 (input/output) / a7 (output) pc6 (input/output) / a6 (output) pc15 (input/output) / tioc3d (input/output) pc14 (input/output) / tioc3c (input/output) pc13 (input/output) pc12 (input/output) pc11 (input/output) pc10 (input/output) pc9 (input/output) pc8 (input/output) pc7 (input/output) pc6 (input/output) a5 (output) pc5 (input/output) / a5 (output) pc5 (input/output) a4 (output) pc4 (input/output) / a4 (output) pc4 (input/output) a3 (output) pc3 (input/output) / a3 (output) pc3 (input/output) a2 (output) pc2 (input/output) / a2 (output) pc2 (input/output) a1 (output) pc1 (input/output) / a1 (output) pc1 (input/output) a0 (output) pc0 (input/output) / a0 (output) pc0 (input/output) figure 18.6 port c (pc15 to pc0) rev. 1.0, 08/99, page 678 of 875 18.4.1 register configuration the port c registers are shown in table 18.5. table 18.5 port c registers name abbreviation r/w initial value address access size port c data register h pcdrh r/w h'0000 h'ffff 1220 8, 16, 32 port c data register l pcdrl r/w h'0000 h'ffff 1222 8, 16, 32 18.4.2 port c data register h (pcdrh) bit: 15 14 13 12 11 10 9 8 pc25drpc24dr initial value:00000000 r/w:rrrrrrr/wr/w bit:76543210 pc23dr pc22dr pc21dr pc20dr pc19dr pc18dr pc17dr pc16dr initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port c data register h (pcdrh) is a 16-bit readable/writable register that stores port c data. bits pc25dr to pc16dr correspond to pins pc25/a25/tioc3b/tclkd to pc16/a16/tioc3a. when a pin functions as a general output, if a value is written to pcdrh, that value is output directly from the pin, and if pcdrh is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pcdrh is read the pin state, not the register value, is returned directly. if a value is written to pcdrh, although that value is written into pcdrh it does not affect the pin state. table 18.6 summarizes port c data register read/write operations. pcdrh is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. rev. 1.0, 08/99, page 679 of 875 18.4.3 port c data register l (pcdrl) bit: 15 14 13 12 11 10 9 8 pc15dr pc14dr pc13dr pc12dr pc11dr pc10dr pc9dr pc8dr initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port c data register l (pcdrl) is a 16-bit readable/writable register that stores port c data. bits pc15dr to pc0dr correspond to pins pc15/a15/tioc3d to pc0/a0. when a pin functions as a general output, if a value is written to pcdrl, that value is output directly from the pin, and if pcdrl is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pcdrl is read the pin state, not the register value, is returned directly. if a value is written to pcdrl, although that value is written into pcdrl it does not affect the pin state. table 18.6 summarizes port c data register read/write operations. pcdrl is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. table 18.6 port c data register (pcdr) read/write operations pcior pin function read write 0 general input pin state value is written to pcdr, but does not affect pin state other than general input pin state or fixed value value is written to pcdr, but does not affect pin state 1 general output pcdr value write value is output from pin other than general output pcdr value value is written to pcdr, but does not affect pin state rev. 1.0, 08/99, page 680 of 875 18.5 port d port d is an input/output port with the 32 pins shown in figures 18.7 and 18.8. expanded mode with on-chip rom disabled (mode 3, 4) expanded mode with on-chip rom disabled (mode 2) single-chip mode port d pd31 (input/output) / d31 (input/output) / rxd2 (input) / tioc5a (input/output) pd31 (input/output) / rxd2 (input) / tioc5a (input/output) pd31 (input/output) / d31 (input/output) / rxd2 (input) / tioc5a (input/output) pd31 (input/output) / rxd2 (input) / tioc5a (input/output) pd30 (input/output) / d30 (input/output) / txd2 (output) / tioc4b (input/output) d30 (input/output) / txd2 (output) / tioc4b (input/output) pd29 (input/output) / d29 (input/output) / sck2 (input/ output) / tioc4a (input/output) d29 (input/output) / sck2 (input/output) / tioc4a (input/output) pd28 (input/output) / d28 (input/output) / tclkb (input) / tioc3d (input/output) d28 (input/output) / tclkb (input) / tioc3d (input/output) pd27 (input/output) / d27 (input/output) / tclka (input) / tioc3c (input/output) d27 (input/output) / tclka (input) / tioc3c (input/output) pd26 (input/output) / d26 (input/output) / pwob (output) d26 (input/output) / pwob (input) pd25 (input/output) / d25 (input/output) / pvob (output) d25 (input/output) / pvob (output) pd24 (input/output) / d24 (input/output) / puob (output) d24 (input/output) / puob (output) pd23 (input/output) / d23 (input/output) / pcio (input/ output) / sck1 (input/output) d23 (input/output) / pcio (input/output) / sck1 (input/output) pd22 (input/output) / d22 (input/output) / pwoa (output) / sck0 (input/output) d22 (input/output) / pwoa (output) / sck0 (input/output) pd21 (input/output) / d21 (input/output) / pvoa (output) / (input) d21 (input/output) / pvoa (output) / (input) pd20 (input/output) / d20 (input/output) / puoa (output) / (input) d20 (input/output) / puoa (output) / (input) pd19 (input/output) / d19 (input/output) / (input) / (input) d19 (input/output) / (input) / (input) pd18 (input/output) / d18 (input/output) / (input) / (input) d18 (input/output) / (input) / (input) pd17 (input/output) / d17 (input/output) / (input) / (input/output) d17 (input/output) / (input) / (input) pd16 (input/output) / d16 (input/output) / (input) d16 (input/output) / (input) expanded mode with on-chip rom enabled pd30 (input/output) / d30 (input/output) / txd2 (output) / tioc4b (input/output) pd30 (input/output) / txd2 (output) / tioc4b (input/output) pd29 (input/output) / d29 (input/output) / sck2 (input/ output) / tioc4a (input/output) pd29 (input/output) / sck2 (input/output) / tioc4a (input/output) pd28 (input/output) / d28 (input/output) / tclkb (input) / tioc3d (input/output) pd28 (input/output) / tclkb (input) / tioc3d (input/output) pd27 (input/output) / d27 (input/output) / tclka (input) / tioc3c (input/output) pd27 (input/output) / tclka (input) / tioc3c (input/output) pd26 (input/output) / d26 (input/output) / pwob (output) pd26 (input/output) / pwob (input) pd25 (input/output) / d25 (input/output) / pvob (output) pd25 (input/output) / pvob (output) pd24 (input/output) / d24 (input/output) / puob (output) pd24 (input/output) / puob (output) pd23 (input/output) / d23 (input/output) / pcio (input/ output) / sck1 (input/output) pd23 (input/output) / pcio (input/output) / sck1 (input/output) pd22 (input/output) / d22 (input/output) / pwoa (output) / sck0 (input/output) pd22 (input/output) / pwoa (output) / sck0 (input/output) pd21 (input/output) / d21 (input/output) / pvoa (output) / (input) pd21 (input/output) / pvoa (output) / (input) pd20 (input/output) / d20 (input/output) / puoa (output) / (input) pd20 (input/output) / puoa (output) / (input) pd19 (input/output) / d19 (input/output) / (input) / (input) pd19 (input/output) / (input) / (input) pd18 (input/output) / d18 (input/output) / (input) / (input) pd18 (input/output) / (input) / (input) pd17 (input/output) / d17 (input/output) / (input) / (input/output) pd17 (input/output) / (input) / (input) pd16 (input/output) / d16 (input/output) / (input) pd16 (input/output) / (input) figure 18.7 port d (pd31 to pd16) rev. 1.0, 08/99, page 681 of 875 expanded mode with on-chip rom disabled (mode 4) expanded mode with on-chip rom disabled (mode 3, 2) single-chip mode port d pd15 (input/output) / d15 (input/output) / tioc5b (input/output) d15 (input/output) / tioc5b (input/output) pd15 (input/output) / d15 (input/output) / tioc5b (input/output) pd15 (input/output) / tioc5b (input/output) pd14 (input/output) / d14 (input/output) / tioc5a (input/output) d14 (input/output) / tioc5a (input/output) pd14 (input/output) / d14 (input/output) / tioc5a (input/output) pd14 (input/output) / tioc5a (input/output) pd13 (input/output) / d13 (input/output) / tioc4b (input/output) d13 (input/output) / tioc4b (input/output) pd13 (input/output) / d13 (input/output) / tioc4b (input/output) pd13 (input/output) / tioc4b (input/output) pd12 (input/output) / d12 (input/output) / tioc4a (input/output) d12 (input/output) / tioc4a (input/output) pd12 (input/output) / d12 (input/output) / tioc4a (input/output) pd12 (input/output) / tioc4a (input/output) pd11 (input/output) / d11 (input/output) / tioc2b (input/output) d11 (input/output) / tioc2b (input/output) pd11 (input/output) / d11 (input/output) / tioc2b (input/output) pd11 (input/output) / tioc2b (input/output) pd10 (input/output) / d10 (input/output) / tioc2a (input/output) d10 (input/output) / tioc2a (input/output) pd10 (input/output) / d10 (input/output) / tioc2a (input/output) pd10 (input/output) / tioc2a (input/output) pd9 (input/output) / d9 (input/output) tioc1b (input/output) d9 (input/output) tioc1b (input/output) pd9 (input/output) / d9 (input/output) tioc1b (input/output) pd9 (input/output) tioc1b (input/output) pd8 (input/output) / d8 (input/output) / tioc1a (input/output) d8 (input/output) / tioc1a (input/output) pd8 (input/output) / d8 (input/output) / tioc1a (input/output) pd8 (input/output) / tioc1a (input/output) d7 (input/output) d7 (input/output) pd7 (input/output) / d7 (input/output) pd7 (input/output) d6 (input/output) d6 (input/output) pd6 (input/output) / d6 (input/output) pd6 (input/output) d5 (input/output) d5 (input/output) pd5 (input/output) / d5 (input/output) pd5 (input/output) d4 (input/output) d4 (input/output) pd4 (input/output) / d4 (input/output) pd4 (input/output) d3 (input/output) d3 (input/output) pd3 (input/output) / d3 (input/output) pd3 (input/output) d2 (input/output) d2 (input/output) pd2 (input/output) / d2 (input/output) pd2 (input/output) d1 (input/output) d1 (input/output) pd1 (input/output) / d1 (input/output) pd1 (input/output) d0 (input/output) d0 (input/output) pd0 (input/output) / d0 (input/output) pd0 (input/output) expanded mode with on-chip rom enabled figure 18.8 port d (pd15 to pd0) rev. 1.0, 08/99, page 682 of 875 18.5.1 register configuration the port d registers are shown in table 18.7. table 18.7 port d registers name abbreviation r/w initial value address access size port d data register h pddrh r/w h'0000 h'ffff 1230 8, 16, 32 port d data register l pddrl r/w h'0000 h'ffff 1232 8, 16, 32 18.5.2 port d data register h (pddrh) bit: 15 14 13 12 11 10 9 8 pd31dr pd30dr pd29dr pd28dr pd27dr pd26dr pd25dr pd24dr initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pd23dr pd22dr pd21dr pd20dr pd19dr pd18dr pd17dr pd16dr initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port d data register h (pddrh) is a 16-bit readable/writable register that stores port d data. bits pd31dr to pd16dr correspond to pins pd31/d31/rxd2/tioc5a to pd16/d16/ poe0 . when a pin functions as a general output, if a value is written to pddrh, that value is output directly from the pin, and if pddrh is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pddrh is read the pin state, not the register value, is returned directly. if a value is written to pddrh, although that value is written into pddrh it does not affect the pin state. table 18.8 summarizes port d data register read/write operations. pddrh is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. rev. 1.0, 08/99, page 683 of 875 18.5.3 port d data register l (pddrl) bit: 15 14 13 12 11 10 9 8 pd15dr pd14dr pd13dr pd12dr pd11dr pd10dr pd9dr pd8dr initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w bit:76543210 pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port d data register l (pddrl) is a 16-bit readable/writable register that stores port d data. bits pd15dr to pd0dr correspond to pins pd15/d15/tioc5b to pd0/d0. when a pin functions as a general output, if a value is written to pddrl, that value is output directly from the pin, and if pddrl is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pddrl is read the pin state, not the register value, is returned directly. if a value is written to pddrl, although that value is written into pddrl it does not affect the pin state. table 18.8 summarizes port d data register read/write operations. pddrl is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. table 18.8 port d data register (pddr) read/write operations pdior pin function read write 0 general input pin state value is written to pddr, but does not affect pin state other than general input pin state or fixed value value is written to pddr, but does not affect pin state 1 general output pddr value write value is output from pin other than general output pddr value value is written to pddr, but does not affect pin state rev. 1.0, 08/99, page 684 of 875 18.6 port e port e is an input/output port with the 12 pins shown in figures 18.9 and 18.10. expanded mode with on-chip rom disabled expanded mode with on-chip rom enabled single-chip mode port e pe23 (input/output) / (input) / pwob (output) pe22 (input/output) / (input) / pvob (output) pe21 (input/output) / (input) / puob (output) pe20 (input/output) / (input) / pco (output) / pci (input) pe19 (input/output) / (input) / pwoa (output) pe18 (input/output) / (input) / pvoa (output) pe17 (input/output) / (input) /puoa (output) / sck0 (input/output) pe16 (input/output) / (input) / sck1 (input/output) / (output) pe23 (input/output) / (input) / pwob (output) pe22 (input/output) / (input) / pvob (output) pe21 (input/output) / (input) / puob (output) pe20 (input/output) / (input) / pco (output) / pci (input) pe19 (input/output) / (input) / pwoa (output) pe18 (input/output) / (input) / pvoa (output) pe17 (input/output) / (input) /puoa (output) / sck0 (input/output) pe16 (input/output) / (input) / sck1 (input/output) / (output) pe23 (input/output) / (input) / pwob (output) pe22 (input/output) / (input) / pvob (output) pe21 (input/output) / (input) / puob (output) pe20 (input/output) / (input) / pco (output) / pci (input) pe19 (input/output) / (input) / pwoa (output) pe18 (input/output) / (input) / pvoa (output) pe17 (input/output) / (input) /puoa (output) / sck0 (input/output) pe16 (input/output) / (input) / sck1 (input/output) figure 18.9 port e (pe23 to pe16) expanded mode with on-chip rom disabled expanded mode with on-chip rom enabled single-chip mode port e pe15 (input/output) / (input) pe14 (input/output) / (input) pe13 (input/output) / (input) pe12 (input/output) / (input) pe15 (input/output) / (input) pe14 (input/output) / (input) pe13 (input/output) / (input) pe12 (input/output) / (input) pe15 (input/output) / (input) pe14 (input/output) / (input) pe13 (input/output) / (input) pe12 (input/output) / (input) figure 18.10 port e (pe15 to pe12) rev. 1.0, 08/99, page 685 of 875 18.6.1 register configuration the port e registers are shown in table 18.9. table 18.9 port e registers name abbreviation r/w initial value address access size port e data register h pedrh r/w h'0000 h'ffff 1240 8, 16, 32 port e data register l pedrl r/w h'0000 h'ffff 1242 8, 16, 32 18.6.2 port e data register h (pedrh) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 pe23dr pe22dr pe21dr pe20dr pe19dr pe18dr pe17dr pe16dr initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w port e data register h (pedrh) is a 16-bit readable/writable register that stores port e data. bits pe23dr to pe16dr correspond to pins pe23/ irq7 /pwob to pe16/ irq0 /sck0/ ah . when a pin functions as a general output, if a value is written to pedrh, that value is output directly from the pin, and if pedrh is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pedrh is read the pin state, not the register value, is returned directly. if a value is written to pedrh, although that value is written into pedrh it does not affect the pin state. table 18.10 summarizes port e data register read/write operations. pedrh is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. rev. 1.0, 08/99, page 686 of 875 18.6.3 port e data register l (pedrl) bit: 15 14 13 12 11 10 9 8 pe15drpe14drpe13drpe12dr initial value:00000000 r/w:r/wr/wr/wr/wrrrr bit:76543210 initial value:00000000 r/w:rrrrrrrr port e data register l (pedrl) is a 16-bit readable/writable register that stores port e data. bits pe15dr to pe12dr correspond to pins pe15/ irq7 to pe12/ irq4 . when a pin functions as a general output, if a value is written to pedrl, that value is output directly from the pin, and if pedrl is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pedrl is read the pin state, not the register value, is returned directly. if a value is written to pedrl, although that value is written into pedrl it does not affect the pin state. table 18.10 summarizes port e data register read/write operations. pedrl is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. table 18.10 port e data register (pedr) read/write operations peior pin function read write 0 general input pin state value is written to pedr, but does not affect pin state other than general input pin state or fixed value value is written to pedr, but does not affect pin state 1 general output pedr value write value is output from pin other than general output pedr value value is written to pedr, but does not affect pin state rev. 1.0, 08/99, page 687 of 875 18.7 port f port f is an input/output port with the 6 pins shown in figure 18.11. expanded mode with on-chip rom disabled expanded mode with on-chip rom enabled single-chip mode port f pf7 (input/output) / (input) / (output) / tioc0d (input/output) pf6 (input/output) / (output) / txd1 (output) / tioc2a (input/output) pf5 (input/output) / (output) / rxd1 (input) / tioc2b (input/output) pf3 (input/output) / dreq0 (output) / tioc0a (input/output) pf2 (input/output) / drak0 (output) / tioc0c (input/output) pf1 (input/output) / dack0 (output) / tioc0b (input/output) pf7 (input/output) / (input) / (output) / tioc0d (input/output) pf6 (input/output) / (output) / txd1 (output) / tioc2a (input/output) pf5 (input/output) / (output) / rxd1 (input) / tioc2b (input/output) pf3 (input/output) / dreq0 (output) / tioc0a (input/output) pf2 (input/output) / drak0 (output) / tioc0c (input/output) pf1 (input/output) / dack0 (output) / tioc0b (input/output) pf7 (input/output) pf6 (input/output) / txd1 (output) / tioc2a (input/output) pf5 (input/output) / rxd1 (input) / tioc2b (input/output) pf3 (input/output) / tioc0a (input/output) pf2 (input/output) / tioc0c (input/output) pf1 (input/output) / tioc0b (input/output) figure 18.11 port f (pf7 to pf1) 18.7.1 register configuration the port f register is shown in table 18.11. table 18.11 port f register name abbreviation r/w initial value address access size port f data register l pfdrl r/w h'0000 h'ffff 1262 8, 16, 32 rev. 1.0, 08/99, page 688 of 875 18.7.2 port f data register l (pfdrl) bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 pf7dr pf6dr pf5dr pf3dr pf2dr pf1dr initial value:00000000 r/w: r/w r/w r/w r r/w r/w r/w r port f data register l (pfdrl) is a 16-bit readable/writable register that stores port f data. bits pf7dr to pf1dr correspond to pins pf7/ dreq1 / irqout /tioc0d to pf1/ dack0 /tioc0b. when a pin functions as a general output, if a value is written to pfdrl, that value is output directly from the pin, and if pfdrl is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pfdrl is read the pin state, not the register value, is returned directly. if a value is written to pfdrl, although that value is written into pfdrl it does not affect the pin state. table 18.12 summarizes port f data register read/write operations. pfdrl is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. table 18.12 port f data register (pfdr) read/write operations pfior pin function read write 0 general input pin state value is written to pfdr, but does not affect pin state other than general input pin state or fixed value value is written to pfdr, but does not affect pin state 1 general output pfdr value write value is output from pin other than general output pfdr value value is written to pfdr, but does not affect pin state rev. 1.0, 08/99, page 689 of 875 18.8 port g port g is an input/output port with the 3 pins shown in figure 18.12. expanded mode with on-chip rom disabled expanded mode with on-chip rom enabled single-chip mode port g pg31 (input/output) / rxd2 (input/output) pg30 (input/output) / txd2 (output) pg29 (input/output) / sck2 (input) pg31 (input/output) / rxd2 (input/output) pg30 (input/output) / txd2 (output) pg29 (input/output) / sck2 (input) pg31 (input/output) / rxd2 (input/output) pg30 (input/output) / txd2 (output) pg29 (input/output) / sck2 (input) figure 18.12 port g (pg31 to pg29) 18.8.1 register configuration the port g register is shown in table 18.13. table 18.13 port g register name abbreviation r/w initial value address access size port g data register h pgdrh r/w h'0000 h'ffff 1270 8, 16, 32 18.8.2 port g data register h (pgdrh) bit: 15 14 13 12 11 10 9 8 pg31drpg30drpg29dr initial value:00000000 r/w:r/wr/wr/wrrrrr bit:76543210 initial value:00000000 r/w:rrrrrrrr port g data register h (pgdrh) is a 16-bit readable/writable register that stores port g data. bits pg31dr to pg29dr correspond to pins pg31/rxd2 to pg29/sck1. rev. 1.0, 08/99, page 690 of 875 when a pin functions as a general output, if a value is written to pgdrh, that value is output directly from the pin, and if pgdrh is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if pgdrh is read the pin state, not the register value, is returned directly. if a value is written to pgdrh, although that value is written into pgdrh it does not affect the pin state. table 18.14 summarizes port g data register read/write operations. pgdrh is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. table 18.14 port g data register (pgdr) read/write operations pgior pin function read write 0 general input pin state value is written to pgdr, but does not affect pin state other than general input pin state or fixed value value is written to pgdr, but does not affect pin state 1 general output pgdr value write value is output from pin other than general output pgdr value value is written to pgdr, but does not affect pin state rev. 1.0, 08/99, page 691 of 875 18.9 port h port h is an input/output port with the 2 pins shown in figure 18.13. port h ph1 (input/output) / da1 (output) ph0 (input/output) / da0 (output) figure 18.13 port h (ph1 and ph0) 18.9.1 register configuration the port h register is shown in table 18.15. table 18.15 port h register name abbreviation r/w initial value address access size port h data register phdr r/w h'0000 h'ffff 1282 8 18.9.2 port h data register (phdr) bit:76543210 ph1drph0dr initial value:00000000 r/w:rrrrrrr/wr/w the port h data register (phdr) is an 8-bit readable/writable register that stores port h data. bits ph1dr and ph0dr correspond to pins ph1/da1 and ph0/da0. when a pin functions as a general output, if a value is written to phdr, that value is output directly from the pin, and if phdr is read, the register value is returned directly regardless of the pin state. when a pin functions as a general input, if phdr is read the pin state, not the register value, is returned directly. if a value is written to phdr, although that value is written into phdr it does not affect the pin state. table 18.16 summarizes port h data register read/write operations. rev. 1.0, 08/99, page 692 of 875 phdr is initialized by an external power-on reset, but is not initialized by a wdt reset or in standby mode or sleep mode. table 18.16 port h data register (phdr) read/write operations phior pin function read write 0 general input pin state value is written to phdr, but does not affect pin state other than general input pin state or fixed value value is written to phdr, but does not affect pin state 1 general output phdr value write value is output from pin other than general output phdr value value is written to phdr, but does not affect pin state rev. 1.0, 08/99, page 693 of 875 18.10 port i port i is an input port with the 8 pins shown in figure 18.14. port i p17 (input) / an7 (input) p16 (input) / an6 (input) p15 (input) / an5 (input) p14 (input) / an4 (input) p13 (input) / an3 (input) p12 (input) / an2 (input) p11 (input) / an1 (input) p10 (input) / an0 (input) figure 18.14 port i (pi7 to pi0) 18.10.1 register configuration the port i register is shown in table 18.17. table 18.17 port i register name abbreviation r/w initial value * address access size port i data register pidr r depends on external pins h'ffff 1290 8 note: * initial value depends on the pin state when a read is performed. rev. 1.0, 08/99, page 694 of 875 18.10.2 port i data register (pidr) bit:76543210 pi7dr pi6dr pi5dr pi4dr pi3dr pi2dr pi1dr pi0dr initial value: ******** r/w:rrrrrrrr note: * initial value depends on the pin state when a read is performed. the port i data register (pidr) is an 8-bit read-only register that stores port i data. bits pi7dr to pi0dr correspond to pins pi7/an7 to pi0/an0. writes to these bits are ignored, and do not affect the pin states. when these bits are read the pin state, not the register value, is returned directly. however, 1 will be returned while a/d converter analog input is being sampled. table 18.18 summarizes port i data register read/write operations. pidr is not initialized by a power-on or wdt reset, or in standby mode or sleep mode. (the bits always reflect the pin states.) table 18.18 port i data register (pidr) read/write operations pin input/output pin function read write input general input pin state is read ignored (does not affect pin state) ann 1 is read ignored (does not affect pin state) ann: analog input rev. 1.0, 08/99, page 695 of 875 section 19 256 kb flash memory (f-ztat) 19.1 features the sh7065 has 256 kbytes of on-chip flash memory. the flash memory has the following features: four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode programming/erase methods the flash memory is programmed 128 bytes at a time. erasing is performed in block units (to erase the entire memory, individual blocks must be erased successively). block erasing can be performed as required on 4 kb, 32 kb, and 64 kb blocks. programming/erase times the flash memory programming time is 25 ms (typ.) for simultaneous 128-byte programming, equivalent to 195 s (typ.) per byte. the erase time is 10 ms (typ.). reprogramming capability the flash memory can be reprogrammed up to 100 times. on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode automatic bit rate adjustment with data transfer in boot mode, the sh7065s bit rate can be automatically adjusted to match the transfer bit rate of the host. flash memory emulation in on-chip ram flash memory programming can be emulated in real time by overlapping a part of on-chip ram onto flash memory. protect modes there are two protect modes, hardware and software, which allow protected status to be designated for flash memory program/erase/verify operations programmer mode flash memory can be programmed/erased in programmer mode, using a prom programmer, as well as in on-board programming mode. rev. 1.0, 08/99, page 696 of 875 19.2 overview 19.2.1 block diagram figure 19.1 shows a block diagram of the flash memory. the on-chip rom is 64 bits wide, and can be accessed in two cycles. the on-chip rom is connected to the internal data bus (c-bus) via a buffer, and has a basic access capability of 32 bits per cycle. internal address bus 64-bit internal data rom bus bus interface/controller operating mode module bus buffer internal data bus flmcr1 flmcr2 ebr1 ebr2 ramer flash memory (256 kb) fwe pin mode pins internal address bus flmcr1: flash memory control register 1 flmcr2: flash memory control register 2 ebr1: erase block register 1 ebr2: erase block register 2 ramer: ram emulation register figure 19.1 block diagram of flash memory rev. 1.0, 08/99, page 697 of 875 19.2.2 mode transitions when the mode pins and the fwe pin are set in the reset state and a reset start is executed, the sh7065 enters one of the operating modes shown in figure 19.2. in user mode, flash memory can be read but not programmed or erased. flash memory can be programmed and erased in boot mode, user program mode, and programmer mode. boot mode on-board programming mode user program mode user mode reset state programmer mode fwe = 1 fwe = 0 * * res = 0 md2, 1, 0 = 1 res = 0 md1 = 0 fwe = 0 res = 0 res = 0 md1 = 0 fwe = 0 md1 = 0 fwe = 0 notes: only make a transition between user mode and user program mode when the cpu is not accessing the flash memory. * ram emulation possible figure 19.2 flash memory mode transitions rev. 1.0, 08/99, page 698 of 875 19.2.3 on-board programming modes boot mode: figure 19.3 shows programming in boot mode. for details of this mode, see section 19.6.1, boot mode. flash memory sh7065 ram host programming control program sci2 application program (old version) new application program flash memory sh7065 ram host sci2 application program (old version) boot program area new application program flash memory sh7065 ram host sci2 flash memory erase boot program new application program flash memory sh7065 : program execution state ram host sci2 new application program boot program programming control program programming control program boot program area programming control program note: boot program boot program boot program area 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in the sh7065 (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. figure 19.3 programming operation in boot mode rev. 1.0, 08/99, page 699 of 875 user program mode: figure 19.4 shows an example of programming in user program mode. for details of this mode, see section 19.6.2, user program mode. flash memory sh7065 ram host sci boot program new application program programming/erase control program flash memory sh7065 ram host sci new application program programming/erase control program flash memory sh7065 ram host sci flash memory erase boot program new application program flash memory sh7065 : program execution state ram host sci boot program boot program fwe assessment program transfer program application program (old version) application program (old version) fwe assessment program transfer program new application program fwe assessment program transfer program note: fwe assessment program transfer program 1. initial state the fwe assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer when user program mode is entered, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/erase control program programming/erase control program figure 19.4 example of programming operation in user program mode rev. 1.0, 08/99, page 700 of 875 19.2.4 flash memory emulation in ram emulation should be performed in user mode or user program mode. when the emulation block set in ramer is accessed while the emulation function is being executed, read and write accesses are performed in the overlap ram. user mode user program mode emulation block application program execution state overlap ram (emulation is performed on data written in ram) flash memory ram figure 19.5 ram emulation (ram overlap) when overlap ram data is confirmed, clear the rams bit to cancel ram overlap, and actually perform writes to the flash memory in user program mode. when the programming control program is transferred to ram, ensure that the transfer destination and the overlap ram do not overlap, as this will cause data in the overlap ram to be rewritten. rev. 1.0, 08/99, page 701 of 875 user program mode programming data application program overlap ram (programming data) programming control program execution state flash memory ram figure 19.6 ram emulation (flash memory programming) 19.2.5 differences between boot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * (2) (1) (2) (3) (1) erase/erase-verify (2) program/program-verify (3) emulation note: * to be provided by the user, in accordance with the recommended algorithm. rev. 1.0, 08/99, page 702 of 875 19.2.6 block configuration the flash memory is divided into eight 4 kb blocks, one 32 kb block, and three 64 kb blocks. in user program mode, erasing can be carried out in block units. address h'00000 address h'3ffff 256 kb 4 kb 4 kb 4 kb 4 kb 4 kb 32 kb 64 kb 64 kb 64 kb 4 kb 4 kb 4 kb figure 19.7 erase area block divisions rev. 1.0, 08/99, page 703 of 875 19.3 pin configuration the flash memory is controlled by means of the pins shown in table 19.1. table 19.1 flash memory pins pin name abbreviation i/o function reset res input reset flash write enable fwe input program/erase protection by hardware mode 5 md5 input sets sh7065 clock operating mode mode 4 md4 input sets sh7065 clock operating mode mode 3 md3 input sets sh7065 clock operating mode mode 2 md2 input sets sh7065 operating mode mode 1 md1 input sets sh7065 operating mode mode 0 md0 input sets sh7065 operating mode transmit data txd2 (pg30) output serial transmit data output receive data rxd2 (pg31) input serial receive data input rev. 1.0, 08/99, page 704 of 875 19.4 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 19.2. table 19.2 flash memory registers register name abbreviation r/w initial value address access size flash memory control register 1 flmcr1 r/w * 1 h'00 * 2 ffff0800 8 flash memory control register 2 flmcr2 r h'00 ffff0801 8 erase block register 1 ebr1 r/w * 1 h'00 * 3 ffff0802 8 erase block register 2 ebr2 r/w * 1 h'00 * 3 ffff0803 8 ram emulation register ramer r/w h'0000 ffff0c70 8, 16, 32 notes: 1. in the on-chip rom disabled modes (mcu modes 2, 3, and 4), a read will return h'00, and writes are invalid. writes are also disabled when the fwe bit is not set to 1 in flmcr1. 2. when a high level is input to the fwe pin, the initial value is h'80. 3. when a low level is input to the fwe pin, or if a high level is input and the swe bit in flmcr1 is not set, these registers are initialized to h'00. 4. flmcr1, flmcr2, ebr1, and ebr2 are 8-bit registers, and ramer is a 16-bit register. 5. only byte accesses are valid for flmcr1, flmcr2, ebr1, and ebr2, the access requiring 3 cycles. three cycles are required for a byte or word access to ramer, and 6 cycles for a longword access. 6. when a longword write is performed on ramer, 0 must always be written to the lower word (address h'ffff0c72). operation is not guaranteed if a nonzero value is written. rev. 1.0, 08/99, page 705 of 875 19.5 register descriptions 19.5.1 flash memory control register 1 (flmcr1) flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode is entered by setting swe to 1 when fwe = 1, then setting the ev or pv bit. program mode is entered by setting swe to 1 when fwe = 1, then setting the psu bit, and finally setting the p bit. erase mode is entered by setting swe to 1 when fwe = 1, then setting the esu bit, and finally setting the e bit. flmcr1 is initialized by a reset, and in hardware standby mode and software standby mode. its initial value is h'80 when a high level is input to the fwe pin, and h'00 when a low level is input. in the on-chip rom disabled modes (mcu modes 2, 3, and 4), a read will return h'00, and writes are invalid. writes to bits esu, psu, ev, and pv in flmcr1 are enabled only when fwe = 1 and swe = 1; writes to the e bit only when fwe = 1, swe = 1, and esu = 1; and writes to the p bit only when fwe = 1, swe = 1, and psu = 1. bit:76543210 fwe swe esu psu ev pv e p initial value:1/00000000 r/w: r r/w r/w r/w r/w r/w r/w r/w bit 7flash write enable (fwe): sets hardware protection against flash memory programming/erasing. bit 7: fwe description 0 when a low level is input to the fwe pin (hardware-protected state) 1 when a high level is input to the fwe pin rev. 1.0, 08/99, page 706 of 875 bit 6software write enable (swe): enables or disables the flash memory. this bit should be set when setting bits 5 to 0, ebr1 bits 7 to 0, and ebr2 bits 3 to 0. when swe = 1, flash memory can only be read in program-verify or erase-verify mode. bit 6: swe description 0 programming/erasing disabled (initial value) 1 programming/erasing enabled [setting condition] when fwe = 1 bit 5erase setup (esu): prepares for a transition to erase mode. do not set the swe, psu, ev, pv, e, or p bit at the same time. bit 5: esu description 0 erase setup cleared (initial value) 1 erase setup [setting condition] when fwe = 1 and swe = 1 bit 4program setup (psu): prepares for a transition to program mode. do not set the swe, esu, ev, pv, e, or p bit at the same time. bit 4: psu description 0 program setup cleared (initial value) 1 program setup [setting condition] when fwe = 1 and swe = 1 bit 3erase-verify (ev): selects erase-verify mode transition or clearing. do not set the swe, esu, psu, pv, e, or p bit at the same time. bit 3: ev description 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] when fwe = 1 and swe = 1 rev. 1.0, 08/99, page 707 of 875 bit 2program-verify (pv): selects program-verify mode transition or clearing. do not set the swe, esu, psu, ev, e, or p bit at the same time. bit 2: pv description 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] when fwe = 1 and swe = 1 bit 1erase (e): selects erase mode transition or clearing. do not set the swe, esu, psu, ev, pv, or p bit at the same time. bit 1: e description 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] when fwe = 1, swe = 1, and esu = 1 bit 0program (p): selects program mode transition or clearing. do not set the swe, esu, psu, ev, pv, or e bit at the same time. bit 0: p description 0 program mode cleared (initial value) 1 transition to program mode [setting condition] when fwe = 1, swe = 1, and psu = 1 rev. 1.0, 08/99, page 708 of 875 19.5.2 flash memory control register 2 (flmcr2) flmcr2 is an 8-bit register used to monitor enabling or disabling of flash memory program/erase protection (error protection). flmcr2 is initialized by a reset and in hardware standby mode. in the on-chip rom disabled modes (mcu modes 2, 3, and 4), a read will return h'00, and writes are invalid. note: flmcr2 is a read-only register, and should not be written to. bit:76543210 fler initial value:00000000 r/w:rrrrrrrr bit 7flash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. bit 7: fler description 0 flash memory is operating normally flash memory program/erase protection (error protection) is disabled [clearing condition] reset or hardware standby mode (initial value) 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see section 19.8.3, error protection bits 6 to 0reserved: these bits are always read as 0. rev. 1.0, 08/99, page 709 of 875 19.5.3 erase block register 1 (ebr1) ebr1 is an 8-bit register that specifies the flash memory erase area block by block. ebr1 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin and the swe bit in flmcr1 is not set. when a bit in ebr1 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one bit can be set in ebr1 and ebr2 together; do not set more than one bit. if more than one bit is set, ebr1 and ebr2 will both be cleared to h'00. in the on-chip rom disabled modes (mcu modes 2, 3, and 4), a read will return h'00, and writes are invalid. the flash memory block configuration is shown in table 19.3. bit:76543210 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value:00000000 r/w: r/w r/w r/w r/w r/w r/w r/w r/w 19.5.4 erase block register 2 (ebr2) ebr2 is an 8-bit register that specifies the flash memory erase area block by block. ebr2 is initialized to h'00 by a reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin and the swe bit in flmcr1 is not set. when a bit in ebr2 is set to 1, the corresponding block can be erased. other blocks are erase-protected. in the on-chip rom disabled modes (mcu modes 2, 3, and 4), a read will return h'00, and writes are invalid. the flash memory block configuration is shown in table 19.3. bit:76543210 eb11eb10eb9eb8 initial value:00000000 r/w:rrrrr/wr/wr/wr/w bits 7 to 4reserved: these bits are always read as 0. rev. 1.0, 08/99, page 710 of 875 table 19.3 flash memory erase blocks block (size) addresses eb0 (4 kb) h'000000Ch'000fff eb1 (4 kb) h'001000Ch'001fff eb2 (4 kb) h'002000Ch'002fff eb3 (4 kb) h'003000Ch'003fff eb4 (4 kb) h'004000Ch'004fff eb5 (4 kb) h'005000Ch'005fff eb6 (4 kb) h'006000Ch'006fff eb7 (4 kb) h'007000Ch'007fff eb8 (32 kb) h'008000Ch'00ffff eb9 (64 kb) h'010000Ch'01ffff eb10 (64 kb) h'020000Ch'02ffff eb11 (64 kb) h'030000Ch'03ffff 19.5.5 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer is initialized to h'0000 by a reset and in hardware standby mode. it is not initialized in software standby mode. ramer settings should be made in user mode or user program mode. flash memory area divisions are shown in table 19.4. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been modified. normal execution of an access immediately after register modification is not guaranteed. bit: 15 14 13 12 11 10 9 8 initial value:00000000 r/w:rrrrrrrr bit:76543210 ramas rams ram2 ram1 ram0 initial value:00000000 r/w: r r r r/w r/w r/w r/w r/w rev. 1.0, 08/99, page 711 of 875 bits 15 to 5reserved: these bits are always read as 0. bit 4ram address select (ramas): selects the ram addresses to be used for flash memory emulation. this bit is ignored in the on-chip rom disabled modes (mcu modes 2, 3, and 4). bit 4: ramas description 0 ram addresses h'ffff8000 to h'ffff8fff are used for emulation (initial value) 1 ram addresses h'ffffa000 to h'ffffafff are used for emulation bit 3ram select (rams): specifies selection or non-selection of flash memory emulation in ram. when rams = 1, all flash memory block are program/erase-protected. this bit is ignored in the on-chip rom disabled modes (mcu modes 2, 3, and 4). bit 3: rams description 0 emulation not selected program/erase-protection of all flash memory blocks is disabled (initial value) 1 emulation selected program/erase-protection of all flash memory blocks is enabled bits 2 to 0flash memory area selection (ram2 to ram0): these bits are used together with bit 3 to select the flash memory area to be overlapped with ram. (see table 19.4.) table 19.4 flash memory area divisions addresses block name rams ram2 ram1 ram0 addresses selected by ramas bit 4 kb ram area 0 *** h'000000Ch'000fff eb0 (4kb) 1 0 0 0 h'001000Ch'001fff eb1 (4kb) 1 0 0 1 h'002000Ch'002fff eb2 (4kb) 1 0 1 0 h'003000Ch'003fff eb3 (4kb) 1 0 1 1 h'004000Ch'004fff eb4 (4kb) 1 1 0 0 h'005000Ch'005fff eb5 (4kb) 1 1 0 1 h'006000Ch'006fff eb6 (4kb) 1 1 1 0 h'007000Ch'007fff eb7 (4kb) 1 1 1 1 * : dont care rev. 1.0, 08/99, page 712 of 875 19.6 on-board programming modes when pins are set to on-board programming mode and a reset start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 19.5. for a diagram of the transitions to the various flash memory modes, see figure 19.2. table 19.5 setting on-board programming modes mode fwe md5 md4 md3 md2 md1 md0 boot mode expanded mode 1 0 1 1 single-chip mode 0 1 0 user program mode expanded mode 1 0 0 1 single-chip mode see section 4, clock pulse generator (cpg) and power- down modes, for the clock modes. 000 19.6.1 boot mode when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. the sci channel to be used is set to asynchronous mode. when a reset start is executed after the sh7065 pins have been set to boot mode, the boot program built into the sh7065 is started and the programming control program prepared in the host is serially transmitted to the sh7065 via sci channel 2 (rxd2 (pg31), txd2 (pg30)). in the sh7065, the user program received via sci channel 2 is written into the user program area in on- chip ram. after the transfer is completed, control branches to the start address of the user program area and the user program execution state is entered (flash memory programming is performed). the transferred user program must therefore include coding that follows the programming algorithm given later. the system configuration in boot mode is shown in figure 19.8, and the boot program mode execution procedure in figure 19.9. rev. 1.0, 08/99, page 713 of 875 rxd2(pg31) sci2 txd2(pg30) sh7065 flash memory write data reception verify data transmission host on-chip ram figure 19.8 system configuration in boot mode rev. 1.0, 08/99, page 714 of 875 n = n? note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. yes no set pins to boot program mode and execute reset start n = 1 n + 1 ? n host transfers data (h'00) continuously at prescribed bit rate sh7065 measures low period of h'00 data transmitted by host after bit rate adjustment, sh7065 transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, sh7065 transmits one h'aa data byte to host host transmits number of user program bytes (n), upper byte followed by lower byte sh7065 transmits received number of bytes to host as verify data (echo-back) host transmits user program sequentially in byte units sh7065 transmits received user program to host as verify data (echo-back) transfer received programming control program to on-chip ram end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, sh7065 transmits one h'aa data byte to host execute programming control program transferred to on-chip ram start sh7065 calculates bit rate and sets value in bit rate register figure 19.9 boot mode execution procedure rev. 1.0, 08/99, page 715 of 875 automatic sci bit rate adjustment start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h'00 data) high period (1 or more bits) when boot mode is initiated, the sh7065 measures the low period of the asynchronous sci communication data (h'00) transmitted continuously from the host. the sci transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. the sh7065 calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the sh7065. if reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. table 19.6 shows host transfer bit rates and peripheral clock frequencies for which automatic adjustment of the sh7065 bit rate is possible. the boot program should set the initial settings for the clock division ratios (in clock mode 7 only, the peripheral clock is set to 1/2 the input), no module clock division, and 4 times the bit rate for the sci2 base clock. the boot program should be executed with a bit rate for which adjustment is possible according to the peripheral clock frequency. table 19.6 peripheral clock frequencies enabling automatic adjustment of sh7065 bit rate host bit rate peripheral clock frequency enabling automatic adjustment of sh7065 bit rate 19200 bps 4C30 mhz 9600 bps 2C30 mhz rev. 1.0, 08/99, page 716 of 875 on-chip ram area divisions in boot mode: in boot mode, the ram area is divided into an area used by the boot program and an area to which the programming control program is transferred via the sci, as shown in figure 19.10. the boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. h'ffff8000 h'ffff87ff h'ffffa000 programming control program area (4 kbytes) boot program area (2 kbytes) h'ffff8fff h'ffffafff figure 19.10 ram areas in boot mode note: the boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note also that the boot program remains in this area of the on-chip ram even after control branches to the programming control program. rev. 1.0, 08/99, page 717 of 875 19.6.2 user program mode after setting the fwe pin, the programming/erase control program prepared by the user beforehand should be branched to and executed. as the flash memory itself cannot be read while flash memory programming/erasing is being executed, the control program that performs programming and erasing should be run in on-chip ram or external memory. use the following procedure (figure 19.11) to execute the programming control program that writes to flash memory (when transferred to ram). execute user application program execute programming/erase control program in ram (flash memory rewriting) transfer programming/erase control program to ram fwe pin = 1 (user program mode) write fwe assessment program and transfer program 1 2 3 4 5 figure 19.11 user program mode execution procedure notes: 1. when programming and erasing, start the watchdog timer so that measures can be taken to prevent program runaway, etc. memory cells may not operate normally if overprogrammed or overerased due to program runaway. 2. if an address at which a flash memory register resides is read in the mask rom version, the value will be undefined. if a flash memory version program is used in the mask rom version, the state of the fwe pin cannot be determined. a modification must therefore be made to prevent operation of the flash memory rewrite program. rev. 1.0, 08/99, page 718 of 875 19.7 programming/erasing flash memory a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes are made by setting the psu, esu, p, e, pv, and ev bits in flmcr1. the flash memory cannot be read while being programmed or erased. therefore, the program (user program) that controls flash memory programming/erasing should be located and executed in on-chip ram or external memory. notes: 1. operation is not guaranteed if setting or clearing of the swe, esu, psu, ev, pv, e, and p bits in flmcr1 is executed by a program in flash memory. 2. when programming or erasing, drive the fwe pin high (programming/erasing will not be executed if the fwe pin is low). 3. programming must be executed in the erased state. do not perform additional programming on addresses that have already been programmed. 19.7.1 program mode when writing data or programs to flash memory, the program/program-verify flowchart shown in figure 19.12 should be followed. performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. programming should be carried out 128 bytes at a time. following the elapse of 1 s or more after the swe bit is set to 1 in flash memory control register 1 (flmcr1), 128-byte data is written consecutively to the write addresses (the lower 8 bits of the first address written to must be h'00 or h'80). 128 consecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. after this, preparation for program mode (program setup) is carried out by setting the psu bit in flmcr1, and after the elapse of 50 s or more, the operating mode is switched to program mode by setting the p bit in flmcr1. the time during which the p bit is set is the flash memory programming time. see the table in the programming flowchart for the programming time. rev. 1.0, 08/99, page 719 of 875 19.7.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of a given programming time, the programming mode is exited (the p bit in flmcr1 is cleared, then the psu bit is cleared at least 5 s later). after the elapse of 5 s or more, the watchdog timer is cleared, and the operating mode is switched to program-verify mode by setting the pv bit in flmcr1. in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of 4 s or more. when the flash memory is read in this state (verify data is read in 32-bit units), the data at the latched address is read. wait at least 2 s after the dummy write before performing this read operation. next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 19.12) and transferred to ram. after 128 bytes of data have been verified, exit program-verify mode, wait for at least 2 s, then clear the swe bit in flmcr1. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. however, ensure that the program/program-verify sequence is not repeated more than 1000 times on the same bits. rev. 1.0, 08/99, page 720 of 875 start end of programming end sub set swe bit in flmcr1 wait 1 m s n = 1 m = 0 sub-routine-call see note 6 for pulse width note 6: write pulse width start of programming sub-routine write pulse set psu bit in flmcr1 enable wdt set p bit in flmcr1 wait 50 m s clear p bit in flmcr1 wait 10 m s, 30 m s, or 200 m s clear psu bit in flmcr1 wait 5 m s disable wdt wait 5 m s write pulse application subroutine ng ng ng ng ok ok wait 4 m s wait 2 m s * 2 * 4 * 5 * 1 wait 2 m s set pv bit in flmcr1 h'ff dummy write to verify address read verify data program data = verify data? transfer additional program data to additional program data area additional program data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 128-byte data verification completed? m = 0? increment address programming failure ok original data (d) 0 1 verify data (v) 0 1 0 1 comments write 128-byte data in reprogram data area in ram consecutively to flash memory write pulse 30 m s or 200 m s ram program data storage area (128 bytes) reprogram data storage area (128 bytes) store 128-byte program data in program data area and reprogram data area number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 . . . 998 999 1000 write time (z) (sec) 30 30 30 30 30 30 200 200 200 200 200 200 200 . . . 200 200 200 reprogram data computation transfer reprogram data to reprogram data area * 4 * 3 6 3 n? ng ok write 128-byte data in additional program data area in ram consecutively to flash memory additional write pulse 10 s wait 100 m s * 1 note: use a 10 m s write pulse for additional programming. reprogram data computation chart additional program data storage area (128 kbytes) ok ok ng programming must be executed in the erased state. do not perform additional programming on addresses that have already been programmed. * 4 n ? n + 1 n 3 1000? clear swe bit in flmcr1 wait 100 m s 6 3 n? notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the first address written to must be h'00 or h'80. a 1 28-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. 2. verify data is read in 32-bit (longword) units. 3. even bits for which programming has been completed in the 128-byte programming loop will be subjected to additional programmi ng if they fail the subsequent verify operation. 4. a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additio nal program data must be provided in ram. the reprogram and additional program data contents are modified as programming proceeds. 5. the write pulse of 30 m s or 200 m s is applied according to the progress of the programming operation. see note 6 for the pulse widths. when writing of additiona l program data is executed, a 10 m s write pulse should be applied. reprogram data x means reprogram data when the write pulse is applied. programming completed programming incomplete; reprogram still in erased state; no action reprogram data (x') 0 1 verify data (v) 0 1 0 1 additional program data (y) 0 1 1 1 comments additional program data computation chart additional programming executed additional programming not executed additional programming not executed additional programming not executed reprogram data (x) 1 0 1 1 figure 19.12 program/program-verify flowchart rev. 1.0, 08/99, page 721 of 875 sample 128-byte programming program: the wait time set values (number of loops) are for the case where f = 60 mhz. for other frequencies, the set value is given by {wait time (s) f (mhz) 4}. registers used r11 (input): program data storage address r12 (input): programming destination address r13 (output): ok (normal) or ng (error) r0C10, 14: work registers flmcr1 .equ h'00 ok .equ h'0 ng .equ h'1 wait_x .equ 15 ; 1 m s wait_y .equ 750 ; 50 m s wait_z1 .equ 450 ; 30 m s (1st to 6th time) wait_z5 .equ 3000 ; 200 m s (7th to 1000th time) wait_za .equ 150 ; 10 m s (additional write) wait_a .equ 75 ; 5 m s wait_b .equ 75 ; 5 m s wait_c .equ 60 ; 4 m s wait_d .equ 30 ; 2 m s wait_e .equ 30 ; 2 m s wait_f .equ 1500 ; 100 m s wdt_tcsr .equ h'ffff1000 wdt_1m .equ h'a57c sweset .equ h'40 ; b'01000000 psuset .equ h'50 ; b'01010000 pset .equ h'51 ; b'01010001 pclear .equ h'50 ; b'01010000 psuclear .equ h'40 ; b'01000000 pvset .equ h'44 ; b'01000100 pvclear .equ h'40 ; b'01000000 sweclear .equ h'00 ; b'00000000 maxverify .equ 1000 ; flashprogram .equ $ mov r11,r3 ; save program data to mov.l #rdatabuff,r0 ; work area rev. 1.0, 08/99, page 722 of 875 mov.l #adatabuff,r2 mov #32,r6 copy_loop1 .equ $ mov.l @r3+,r1 mov.l r1,@r0 mov.l r1,@r2 add #4,r0 add #4,r2 dt r6 bf copy_loop1 mov.l #h'ffff0800,r0 ; initialize gbr ldc r0,gbr ; mov.l #wait_x,r2 mov #sweset,r0 mov.b r0,@(flmcr1,gbr) ; set swe wait_1 dt r2 ; wait 1 m s bf wait_1 ; mov #1,r14 ; initialize n (r14) to 1 program_loop .equ $ mov #0,r5 ; initialize m (r5) to 0 mov.l #128,r2 ; write 128-byte data consecutively mov.l #rdatabuff,r3 mov r12,r6 write_loop1 .equ $ mov.b @r3+,r1 mov.b r1,@r6 add #1,r6 dt r2 bf write_loop1 ; mov.l #wdt_tcsr,r0 ; enable wdt mov.l #wdt_1m,r1 ; 1.1 ms cycle mov.w r1,@r0 ; mov.l #wait_y,r2 rev. 1.0, 08/99, page 723 of 875 mov #psuset,r0 ; set psu mov.b r0,@(flmcr1,gbr) wait_2 dt r2 ; wait 50 m s bf wait_2 ; mov.l #wait_z1,r2 ; 1st to 6th time mov #6,r3 cmp/ge r14,r3 bt under7 mov.l #wait_z5,r2 ; 7th to 1000th time under7 mov #pset,r0 ; set p mov.b r0,@(flmcr1,gbr) wait_3 dt r2 ; wait 30 m s or 200 m s bf wait_3 ; mov.l #wait_a,r2 mov #pclear,r0 ; clear p mov.b r0,@(flmcr1,gbr) wait_4 dt r2 ; wait 5 m s bf wait_4 ; mov.l #wait_b,r2 mov #psuclear,r0 ; clear psu mov.b r0,@(flmcr1,gbr) wait_5 dt r2 ; wait 5 m s bf wait_5 ; mov.l #wdt_tcsr,r0 ; disable wdt mov.w #h'a55f,r1 mov.w r1,@r0 ; mov.l #wait_c,r2 mov #pvset,r0 ; set pv mov.b r0,@(flmcr1,gbr) wait_6 dt r2 ; wait 4 m s bf wait_6 ; rev. 1.0, 08/99, page 724 of 875 mov.l #adatabuff,r9 mov.l #rdatabuff,r7 mov r11,r1 mov r12,r3 mov #32,r6 mov.l #h'ffffffff,r4 ; verifyloop .equ $ mov.l r4,@r3 ; write h'ff to verify address mov.l r4,@r9 ; additional program data ram (adatabuff) initialization mov.l #wait_d,r2 wait_7 dt r2 ; wait 2 m s bf wait_7 ; mov.l @r3+,r2 ; read verify data mov.l @r1+,r0 ; read program data (source data) cmp/eq r2,r0 ; verify check bt verify_ok mov #1,r5 ; if verify ng, assign 1 to m ; verify_ok .equ $ mov #6,r8 ; 6 or more writes? cmp/ge r14,r8 bf no_adwrt mov.l @r7,r10 ; read reprogram data or r2,r10 ; additional program data operation mov.l r10,@r9 ; store in additional program data ram (adatabuff) ; no_adwrt .equ $ mov.l r4,@r7 ; reprogram data ram (rdatabuff) initialization not r2,r2 ; reprogram data computation or r2,r0 mov.l r0,@r7 ; store in reprogram data ram (rdatabuff) ; add #4,r7 add #4,r9 dt r6 rev. 1.0, 08/99, page 725 of 875 bf verifyloop ; mov.l #wait_e,r2 mov #pvclear,r0 ; clear pv mov.b r0,@(flmcr1,gbr) wait_8 dt r2 ; wait 2 m s bf wait_8 ; mov #6,r8 ; 6 or more writes? cmp/ge r14,r8 bf no_adwrt2 ; mov.l #128,r2 ; consecutively write 128-byte date to mov.l #adatabuff,r3 ; additional program data ram (adatabuff) mov r12,r6 write_loop2 .equ $ mov.b @r3+,r1 mov.b r1,@r6 add #1,r6 dt r2 bf write_loop2 ; mov.l #wdt_tcsr,r0 ; enable wdt mov.l #wdt_1m,r1 ; 1.1 ms cycle mov.w r1,@r0 ; mov.l #wait_y,r2 mov #psuset,r0 ; set psu mov.b r0,@(flmcr1,gbr) wait_9 dt r2 ; wait 50 m s bf wait_9 ; mov.l #wait_za,r2 ; 10 s additional write mov #pset,r0 ; set p mov.b r0,@(flmcr1,gbr) wait_10 dt r2 ; wait 10 m s bf wait_10 rev. 1.0, 08/99, page 726 of 875 ; mov.l #wait_a,r2 mov #pclear,r0 ; clear p mov.b r0,@(flmcr1,gbr) wait_11 dt r2 ; wait 5 m s bf wait_11 ; mov.l #wait_b,r2 mov #psuclear,r0 ; clear psu mov.b r0,@(flmcr1,gbr) wait_12 dt r2 ; wait 5 m s bf wait_12 ; mov.l #wdt_tcsr,r0 ; disable wdt mov.w #h'a55f,r1 mov.w r1,@r0 ; no_adwrt2 .equ $ cmp/pl r5 ; if m = 0, end of programming bf program_ok add #1,r14 mov #ng,r13 ; move ng (return value) to r13 mov.l #maxverify,r3 ; if n 3 1000, programming error cmp/gt r14,r3 bf program_end ; bra program_loop nop ; program_ok .equ $ mov #ok,r13 ; move ok (return value) to r13 program_end .equ $ mov #sweclear,r0 ; clear swe mov.b r0,@(flmcr1,gbr) ; mov.l #wait_f,r2 wait_13 dt r2 ; wait 100 m s rev. 1.0, 08/99, page 727 of 875 bf wait_13 ; rts nop ; adatabuff .res.b 128 ; additional programming ram area rdatabuff .res.b 128 ; reprogramming ram area 19.7.3 erase mode (n = 1 for addresses h'00000 to h'07fff, n = 2 for addresses h'08000 to h'3ffff) when erasing flash memory, the erase/erase-verify flowchart (single-block erase) shown in figure 19.13 should be followed for each block. to perform data or program erasure, set the flash memory area to be erased in erase block register n (ebrn) at least 1 s after setting the swe bit to 1 in flash memory control register 1 (flmcr1). next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. after this, preparation for erase mode (erase setup) is carried out by setting the esu bit in flmcr1, and after the elapse of 100 s or more, the operating mode is switched to erase mode by setting the e bit in flmcr1. the time during which the e bit is set is the flash memory erase time. ensure that the erase time does not exceed 10 ms. note: with flash memory erasing, preprogramming (setting all memory data in the memory to be erased to all 0) is not necessary before starting the erase procedure. rev. 1.0, 08/99, page 728 of 875 19.7.4 erase-verify mode (n = 1 for addresses h'00000 to h'07fff, n = 2 for addresses h'08000 to h'3ffff) in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the erase time, erase mode is exited (the e bit in flmcr1 is cleared, then the esu bit is cleared at least 10 s later). after the elapse of 10 s or more, the watchdog timer is cleared, and the operating mode is switched to program-verify mode by setting the pv bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of 6 s or more. when the flash memory is read in this state (verify data is read in 32-bit units), the data at the latched address is read. wait at least 2 s after the dummy write before performing this read operation. if the read data has been erased (all 1), a dummy write is performed to the next address, and erase-verify is performed. if the read data has not been erased, set erase mode again and repeat the erase/erase-verify sequence as before. however, ensure that this operation is not repeated more than 100 times. when verification is completed, exit erase-verify mode, and wait for at least 4 s. when erasure has been completed on all the erase blocks, clear the swe bit in flmcr1. if there are any unerased blocks, make a 1-bit setting for the flash memory area to be erased, and repeat the erase/erase-verify sequence as before. rev. 1.0, 08/99, page 729 of 875 end of erase start set swe bit in flmcr1 set esu bit in flmcr1 set e bit in flmcr1 wait 1 m s wait 100 m s n = 1 set ebr1 (2) enable wdt * 3 wait 10 ms wait 10 m s wait 10 m s wait 6 m s set block start address to verify address wait 2 m s * 2 wait 4 m s * 4 start of erase clear e bit in flmcr1 clear esu bit in flmcr1 set ev bit in flmcr1 h'ff dummy write to verify address read verify data clear ev bit in flmcr1 wait 4 m s clear ev bit in flmcr1 clear swe bit in flmcr1 disable wdt erase halted * 1 verify data = all 1? last address of block? erasing of all erase blocks completed? erase failure clear swe bit in flmcr1 wait 100 m s wait 100 m s n 3 100? no no no no yes yes yes yes n ? n + 1 increment address notes: 1. preprogramming (setting erase block data to all 0) is not necessary. 2. verify data is read in 32-bit (longword) units. 3. set only one bit in the erase block register (ebr). two or more bits must not be set. 4. erasing is performed in block units. for a multiple-block erase, the individual blocks must be erased sequentially. figure 19.13 erase/erase-verify flowchart (single-block erase) rev. 1.0, 08/99, page 730 of 875 sample single-block erase program: the wait time set values (number of loops) are for the case where f = 60 mhz. for other frequencies, the set value is given by {wait time (s) f (mhz) 4}. registers used r5 (input): memory block table pointer r7 (output): ok (normal) or ng (error) r0C3, 6, 8C9: work registers flmcr1 .equ h00 ebr1 .equ h02 ok .equ h0 ng .equ h1 ewait_x .equ 15 ewait_y .equ 1500 ewait_z .equ 150000 ewait_a .equ 150 ewait_b .equ 150 ewait_c .equ 90 ewait_d .equ 30 ewait_e .equ 60 ewait_f .equ 1500 wdt_tcsr equ hffff1000 wdt_4m equ ha57d sweset .equ b01000000 esuset .equ b00100000 eset .equ b00000010 eclear .equ b11111101 esuclear .equ b11011111 evset .equ b00001000 evclear .equ b11110111 sweclear .equ b10111111 maxerase .equ 100 ; flasherase .equ $ mov.l #hffff0800,r0 ldc r0,gbr ; initialize gbr mov.l #1,r2 ; rev. 1.0, 08/99, page 731 of 875 mov,l #ewait_x,r3 mov.l #flmcr1,r0 or.b #sweset,@(r0,gbr) ; set swe ewait_1 subc r2,r3 ; wait 1 s bf ewait_1 ; mov.l #0,r9 ; initialize n (r9) to 0 ; mov.w @(6,r5),r0 mov.w r0,@(ebr1,gbr) ; erase memory block (ebr1/2) setting mov.l @r5,r6 ; erase memory block start address ? ; r6 setting ; eraseloop .equ $ mov.l #wdt_tcsr,r1 ; enable wdt mov.w #wdt_4m,r3 ; 4.4 ms cycle mov.w r3,@r1 mov.l #ewait_y,r3 mov.l #flmcr1,r0 or.b #esuset,@(r0,gbr) ; set esu ewait_2 subc r2,r3 ; wait 100 s bf ewait_2 ; mov.l #ewait_z,r3 or.b #eset,@(r0,gbr) ; set e ewait_3 subc r2,r3 ; wait 10 ms bf ewait_3 ; mov.l #ewait_a,r3 and.b #eclear,@(r0,gbr) ; clear e ewait_4 subc r2,r3 ; wait 10 s bf ewait_4 ; mov.l #ewait_b,r3 and.b #esuclear,@(r0,gbr) ; clear esu ewait_5 subc r2,r3 ; wait 10 s bf ewait_5 rev. 1.0, 08/99, page 732 of 875 ; mov.l #wdt_tcsr,r1 ; disable wdt mov.w #ha55f,r3 mov.w r3,@r1 ; mov.l #ewait_c,r3 or.b #evset,@(r0,gbr) ; set ev ewait_6 subc r2,r3 ; wait 6 s bf ewait_6 ; blockverify_1 .equ $ ; erase-verify mov.l #hffffffff,r8 mov.l r8,@r6 ; h'ff dummy write mov.l #ewait_d,r3 ewait_7 subc r2,r3 ; wait 2 s bf ewait_7 ; mov.l @r6+,r1 ; read verify data cmp/eq r8,r1 bf blockverify_ng mov.l @(8,r5),r7 cmp/eq r6,r7 ; check for last address of memory block bf blockverify_1 mov.l #ewait_e,r3 and.b #evclear,@(r0,gbr) ; clear ev ewait_8 subc r2,r3 ; wait 4 s bf ewait_8 ; mov.l #ok,r7 ; move ok (return value) to r7 bra flasherase_end ; verify ok nop ; blockverify_ng .equ $ add.l #1,r9 ; if verify ng, assign n+1 to n add.l #-4,r6 ; next verify address mov.l #ewait_e,r3 and.b #evclear,@(r0,gbr) ; clear ev rev. 1.0, 08/99, page 733 of 875 ewait_9 subc r2,r3 ; wait 4 s bf ewait_9 ; mov.l #maxerase,r7 ; if n > 100, erase error cmp/eq r7,r9 bf eraseloop mov.l #ng,r7 ; move ng (return value) to r7 flasherase_end .equ $ mov.l #flmcr1,r0 and.b #sweclear,@(r0,gbr) ; clear swe mov.l #ewait_f,r3 ewait_10 subc r2,r3 ; wait 100 s bf ewait_10 ; rts nop ; ; memory block table memory block start address: ebr value .align 4 flash_blockdata .equ $ eb0 .data.l h00000000,h00000100 eb1 .data.l h00001000,h00000200 eb2 .data.l h00002000,h00000400 eb3 .data.l h00003000,h00000800 eb4 .data.l h00004000,h00001000 eb5 .data.l h00005000,h00002000 eb6 .data.l h00006000,h00004000 eb7 .data.l h00007000,h00008000 eb8 .data.l h00008000,h00000001 eb9 .data.l h00010000,h00000002 eb10 .data.l h00020000,h00000004 eb11 .data.l h00030000,h00000008 dummy .data.l h00040000 rev. 1.0, 08/99, page 734 of 875 19.8 protection there are two kinds of flash memory program/erase protection, hardware protection and software protection. 19.8.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. hardware protection is set by settings in flash memory control register 1 (flmcr1), erase block register 1 (ebr1), and erase block register 2 (ebr2). the flmcr1, ebr1, and ebr2 settings are retained in the error protection state. (see table 19.7.) table 19.7 hardware protection functions item description program erase fwe pin protection when a low level is input to the fwe pin, flmcr1, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. yes yes reset/standby protection in a reset (including a wdt overflow reset) and in standby mode, flmcr1, ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. yes yes rev. 1.0, 08/99, page 735 of 875 19.8.2 software protection software protection can be implemented by setting the swe bit in flash memory control register 1 (flmcr1), erase block register 1 (ebr1), erase block register 2 (ebr2), and the rams bit in the ram emulation register (ramer). when software protection is in effect, setting the p or e bit in flash memory control register 1 (flmcr1) does not cause a transition to program mode or erase mode. (see table 19.8.) table 19-8 software protection functions item description program erase swe bit protection clearing the swe bit to 0 in flmcr1 sets the program/erase-protected state for all blocks. (execute in on-chip ram or external memory.) yes yes block specification protection erase protection can be set for individual blocks by settings in erase block register 1 (ebr1) and erase block register 2 (ebr2). setting ebr1 and ebr2 to h'00 places all blocks in the erase-protected state. yes emulation protection setting the rams bit to 1 in the ram emulation register (ramer) places all blocks in the program/erase-protected state. yes yes 19.8.3 error protection in error protection, an error is detected when sh7065 runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if sh7065 malfunctions during flash memory programming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entered. the flmcr1, ebr1, and ebr2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p or e bit. however, pv and ev bit setting is enabled, and a transition can be made to verify mode. rev. 1.0, 08/99, page 736 of 875 fler bit setting conditions are as follows: 1. when flash memory is read during programming/erasing (including a vector read or instruction fetch) 2. immediately after the start of exception handling (excluding a reset and hardware standby mode) during programming/erasing 3. when a sleep instruction (including software standby) is executed during programming/erasing 4. when the bus is released during programming/erasing error protection is released only by a reset or in hardware standby mode. figure 19.14 shows the flash memory state transition diagram. pr er fler = 0 error occurrence = 0 or = 1 = 0 or = 1 fler = 0 program mode erase mode reset or standby (hardware protection) rd vf fler = 1 fler = 1 error protection mode error protection mode (standby) software standby mode flmcr1, ebr1, ebr2 initialization state flmcr1, ebr1, ebr2 initialization state software standby mode release rd: memory read possible : memory read not possible vf: verify-read possible : verify-read not possible pr: programming possible : programming not possible er: erasing possible : erasing not possible = 0 or = 1 error occurrence (software standby) figure 19.14 flash memory state transitions rev. 1.0, 08/99, page 737 of 875 19.9 flash memory emulation in ram making a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. after the ramer setting has been made, accesses can be made from the flash memory area or the ram area overlapping flash memory. emulation can be performed in user mode and user program mode. figure 19.15 shows an example of emulation of real-time flash memory programming. start of emulation program end of emulation program tuning ok? yes no set ramer write tuning data to overlap ram execute application program clear ramer write to flash memory emulation block figure 19.15 flowchart of flash memory emulation in ram note: the number of execution cycles in emulation with ram differs from the number of cycles when using flash memory. rev. 1.0, 08/99, page 738 of 875 this area can be accessed from both the ram area and flash memory area eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 flash memory eb8 to eb11 h'ffff8000 h'000000 h'001000 h'002000 h'003000 h'004000 h'005000 h'006000 h'007000 h'008000 h'03ffff h'ffff8fff h'ffffa000 h'ffffafff on-chip ram on-chip ram figure 19.16 example of ram overlap operation example of flash memory block area eb1 overlapping: 1. set bits ramas, rams, and ram2 to ram0 in ramer to 0,1, 0, 0, 1, to overlap ram (h'ffff8000 to h'ffff8fff) onto the area (eb1) for which real-time programming is required. 2. real-time programming is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, releasing ram overlap. 4. the data written in the overlapping ram is written into the flash memory space (eb1). notes: 1. when the rams bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of ram2 to ram0 (emulation protection). in this state, setting the p or e bit in flash memory control register 1 (flmcr1) will not cause a transition to program mode or erase mode. when actually programming or erasing a flash memory area, the rams bit should be cleared to 0. 2. a ram area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in ram is being used. rev. 1.0, 08/99, page 739 of 875 19.10 note on flash memory programming/erasing in the on-board programming modes (boot mode and user program mode), nmi input should be disabled to give top priority to the program/erase operations (including ram emulation). 19.11 flash memory programmer mode programs and data can be written and erased in programmer mode as well as in the on-board programming modes. in programmer mode, flash memory read mode, auto-program mode, auto- erase mode, and status read mode are supported. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. in programmer mode, set the mode pins to crystal oscillation/pllx4 mode (see table 19.9) and use a 6 mhz crystal oscillator, so that the sh7065 runs at 24 mhz. table 19.9 shows the pin settings for programmer mode. for the pin names in programmer mode, see figure 19.18. table 19.9 programmer mode pin settings pin names settings clock pins: md5 to md3 md5 = 1, md4 = 0, md3 = 1 (crystal oscillator, pll2 4) mode pins: md2 to md0 md2 = 1, md1 = 1, md0 = 1 fwe pin high level input (in auto-program and auto-erase modes) res pin power-on reset circuit xtal, extal, pllv cc , pllcap2, pllv ss pins oscillator circuit rev. 1.0, 08/99, page 740 of 875 19.11.1 socket adapter pin correspondence diagram connect the socket adapter to the chip as shown in figure 19.18. this will enable conversion to a 32-pin arrangement. the on-chip rom memory map is shown in figure 19.17, and the socket adapter pin correspondence diagram in figure 19.18. h'00000000 h'0003ffff h'0000 h'3ffff on-chip rom space (256 kb) addresses in programmer mode addresses in mcu mode figure 19.17 on-chip rom memory map rev. 1.0, 08/99, page 741 of 875 hd64f7065 (176 pins) hn28f101p (32 pins) pin no. 6 7 8 9 11 12 14 15 16 18 19 20 22 23 24 27 28 29 97 98 99 100 102 103 104 106 107 108 109 120 pin no. 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 22 24 31 21 20 19 18 17 15 14 13 1 32 16 pin name a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 ce oe we d7 d6 d5 d4 d3 d2 d1 d0 fwe v cc * 1 v ss * 2 xtal extal res pllvcc pllcap2 pllvss nc(open) pin name a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 ce oe we i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 fwe vcc vss socket adapter (32-pin conversion) 5,17,26,39,48,58,70,79,92,96, 105,111,115,116,117,118,121, 122,125,126,140,159,160,173 1,10,13,21,25,31,38,45,54,64, 76,88,89,101,110,113,119, 124,128,133,135,147,148,166 112 114 123 129 131 132 other pins power-on reset circuit oscillation circuit pll circuit a0C17: address input i/o0C7: data input/output ce: chip enable oe: output enable we: write enable fwe: flash write enable notes: 1. including nmi, hstby, md0, md1, md2, md3, and md5 2. including md4 figure 19.18 socket adapter pin correspondence diagram rev. 1.0, 08/99, page 742 of 875 19.11.2 operation in programmer mode table 19.10 shows how the different operating modes are set when using programmer mode, and table 19.11 lists the commands used in programmer mode. details of each mode are given below. memory read mode: memory read mode supports byte reads. auto-program mode: auto-program mode supports programming of 128 bytes at a time. status polling is used to confirm the end of auto-programming. auto-erase mode: auto-erase mode supports automatic erasing of the entire flash memory mat. status polling is used to confirm the end of auto-erasing. status read mode: status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the i/o6 signal. in status read mode, error information is output if an error occurs. table 19.10 operating mode settings in programmer mode pin names mode fwe ce ce ce ce oe oe oe oe we we we we i/o7C0 a17C0 read h or l l l h data output ain output disable h or l l h h hi-z ain command write h or l l h l data input * ain chip disable h or l h x x hi-z ain notes: 1. chip disable is not a standby state; internally, it is an operation state. 2. * ain indicates that there is also address input in auto-program mode. 3. for command writes in auto-program and auto-erase modes, input a high level to the fwe pin. table 19.11 programmer mode commands 1st cycle 2nd cycle command name number of cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 notes: 1. in auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). rev. 1.0, 08/99, page 743 of 875 19.11.3 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. once memory read mode has been entered, consecutive reads can be performed. 4. after powering on, memory read mode is entered. table 19.12 ac characteristics in memory read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 m s ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns we rise time t r 30 ns we fall time t r 30 ns t ces t wep t f t ds t dh t r t ceh t nxtc note: data is latched at the rising edge of we. command write memory read mode address stable a17C0 ce oe we i/o7C0 figure 19.19 memory read mode timing waveforms after command write rev. 1.0, 08/99, page 744 of 875 table 19.13 ac characteristics in transition from memory read mode to another mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 m s ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns we rise time t r 30 ns we fall time t r 30 ns t ces t wep t f t ds t dh t r t ceh t nxtc note: do not enable ce and oe simultaneously. other mode command write memory read mode address stable a17C0 ce oe we i/o7C0 figure 19.20 timing waveforms in transition from memory read mode to another mode rev. 1.0, 08/99, page 745 of 875 table 19.14 ac characteristics in memory read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes access time t acc 20 m s ce output delay time t ce 150 ns oe output delay time t oe 150 ns output disable delay time t df 100 ns data output hold time t oh 5ns t acc v il v il v ih t acc t oh t oh address stable address stable a17C0 ce oe we i/o7C0 figure 19.21 timing waveforms in ce and oe enable state read t df t df t oh t oh t ce v ih t ce t oe t oe t acc t acc address stable address stable a17C0 ce oe we i/o7C0 figure 19.22 timing waveforms in ce and oe clock system read rev. 1.0, 08/99, page 746 of 875 19.11.4 auto-program mode 1. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. 2. a 128-byte data transfer is necessary even when programming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. the lower 8 bits of the transfer address must be h'00 or h'80. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. memory address transfer is performed in the second cycle (figure 19.23). do not perform transfer after the second cycle. 5. do not perform a command write during a programming operation. 6. perform one auto-programming operation for a 128-byte block for each address. one or more additional programming operations cannot be carried out on address blocks that have already been programmed. 7. confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-program operation end identification pin). 8. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . rev. 1.0, 08/99, page 747 of 875 table 19.15 ac characteristics in auto-program mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 m s ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t wsts 1ms status polling access time t spa 150 ns address setup time t as 0ns address hold time t ah 60 ns memory write time t write 1 3000 ms write setup time t pns 100 ns write end setup time t pnh 100 ns we rise time t r 30 ns we fall time t f 30 ns address stable a17C0 ce oe we i/o7 i/o6 i/o5C0 t ds t dh t f t pns t nxtc t nxtc t ces t ceh t r t as t ah t wep t wsts t write t spa t pnh programming operation end identification signal h'00 h'40 data transfer byte 1 ... byte 128 fwe programming normal end identification signa figure 19.23 auto-program mode timing waveforms rev. 1.0, 08/99, page 748 of 875 19.11.5 auto-erase mode 1. auto-erase mode supports only total memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status output is used to identify the end of an auto-erase operation). 4. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . table 19.16 ac characteristics in auto-erase mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 m s ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t wsts 1ms status polling access time t spa 150 ns memory erase time t erase 100 40000 ms erase setup time t ens 100 ns erase end setup time t enh 100 ns we rise time t r 30 ns we fall time t f 30 ns rev. 1.0, 08/99, page 749 of 875 a17C0 fwe ce oe we i/o7 i/o6 i/o5C0 t ds t dh t f t ens t nxtc t nxtc t ces t ceh t r t wep t ests t erase t spa t pnh erase operation end identification signal erase normal end identification signal h'00 h'20 h'20 figure 19.24 auto-erase mode timing waveforms rev. 1.0, 08/99, page 750 of 875 19.11.6 status read mode 1. status read mode is provided to indicate the type of an abnormal end. it should be used if an error occurs in auto-program or auto-erase mode. 2. the return code is retained until a command write is performed in a mode other than status read mode. table 19.17 ac characteristics in status read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes read time after command write t nxtc 20 m s ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns oe output delay time t oe 150 ns disable delay time t df 100 ns ce output delay time t ce 150 ns we rise time t r 30 ns we fall time t f 30 ns a17C0 ce oe we i/o7C0 t ds t dh t f t nxtc t nxtc t nxtc t ces t ceh t ceh t oe t df t ces t ce t r t wep t ds t dh t f t r t wep h'71 h'71 note: i/o3 and i/o2 are undefined. figure 19.25 timing waveforms in status read mode rev. 1.0, 08/99, page 751 of 875 table 19.18 status read mode return commands pin name i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 attribute normal end identification command error programming error erase error programming or erase count exceeded effective address error initial value 0 0 0 0 0 0 0 0 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 programming error: 1 otherwise: 0 erasing error: 1 otherwise: 0 count exceeded: 1 otherwise: 0 effective address error: 1 otherwise: 0 note: i/o3 and i/o2 are undefined. 19.11.7 status polling 1. i/o7 status polling is a flag that indicates the operating status in auto-program/auto-erase mode. 2. i/o6 status polling is a flag that indicates a normal or abnormal end in auto-program/auto-erase mode. table 19.19 status polling output truth table pin name during internal operation abnormal end normal end i/o7 0 1 0 1 i/o6 0 0 1 1 i/o5C0 0 0 0 0 19.11.8 programmer mode transition time commands cannot be accepted during the oscillation settling period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 19.20 stipulated transition times to command wait state item symbol min max unit notes standby release (oscillation settling time) t osc1 30 ms programmer mode setup time t bmv 10 ms v cc hold time t dwn 0ms rev. 1.0, 08/99, page 752 of 875 vcc fwe t osc1 t bmv t dwn note: except in auto-program mode and auto-erase mode, the fwe input pin should be driven low. memory read mode command wait state auto-program mode auto-erase mode command wait state normal/abnormal termination judgment figure 19.26 oscillation settling time and boot program transfer time 19.11.9 cautions concerning memory programming 1. when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. 2. when performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. notes: 1. the flash memory is initially in the erased state when the device is shipped by hitachi. for other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level. 2. auto-programming should be performed once only on the same address block. additional programming cannot be performed on previously programmed address blocks. rev. 1.0, 08/99, page 753 of 875 19.12 usage notes 1. do not release the fwe pin or clear the swe bit during programming, erasing, or verifying (fwe = 1, swe = 1). 2. if the reset or hstby signal is input during programming, erasing, or verifying (fwe = 1, swe = 1), the signal must be input continuously for at least 100 s. 3. when reading flash memory (including a reset start) immediately after a transition from program/erase/verify mode (fwe = 1, swe = 1) to normal mode (fwe = 0, swe = 0), allow a wait of at least 100 s. 4. when recovery from the flash memory modules module standby state is performed by clearing the mstp bit (see the description of the module standby function in section 4.13), wait at least 100 s before reading the flash memory. 19.13 cautions on transition from f-ztat to mask rom version when switching from the f-ztat version to a mask rom version product, care is needed when using f-ztat application software. if an address at which a flash memory register resides (see table 19.2, flash memory registers) is read in the mask rom version, the read value will be undefined. if f-ztat version application software is used in a mask rom version product, the state of the fwe pin cannot be determined. program modifications must be made to ensure that the flash memory programming (erase/write) sections and ram emulation section are not activated. also ensure that mode pin (fwe, md2 to md0) settings are not made for user program mode, boot mode, or prom mode (programmer mode) in the mask rom version. note: the above applies to all f-ztat version products and mask rom version products with different rom sizes within the same series. rev. 1.0, 08/99, page 755 of 875 section 20 256 kb mask rom 20.1 overview the sh7065 has 256 kbytes of on-chip mask rom. the on-chip rom is connected to the cpu and direct memory access controller (dmac) by a 32-bit-wide data bus (figure 20.1). the cpu and dmac can use 8-, 16-, or 32-bit access to the on-chip rom. the on-chip rom is 64 bits wide, and is accessed in two cycles. it is connected to the internal data bus (c-bus) via an on-chip rom buffer, and has a basic access capability of 32 bits per cycle. internal data bus (32 bits) buffer unit internal rom bus (64 bits) h'00000000 h'00000004 h'00000001 h'00000005 h'00000002 h'00000006 h'00000003 h'00000007 h'0003fffc h'0003fffd h'0003fffe h'0003ffff on-chip rom figure 20.1 block diagram of on-chip rom (256 kb version) the on-chip rom is enabled or disabled depending on the operating mode. for details of the operating modes, see section 3, operating modes. the mode is selected by mode setting pins md3 to md0, as shown in 20.1. select mode 0 or 1 when on-chip rom is used, and mode 2, 3, or 4 when it is not used. the on-chip rom is allocated to addresses h'00000000 to h'0003ffff (256 kb version) in memory area 0. rev. 1.0, 08/99, page 757 of 875 section 21 xram and yram 21.1 overview the sh7065 has 4 kbytes each of xram and yram. the xram and yram are connected to the cpu and dsp by a 16-bit x-bus and y-bus, respectively, (figures 21.1 and 21.2), allowing 16- bit-wide data exchange with the cpu and dsp. the xram and yram are also connected to the cpu by a 32-bit-wide internal data bus (cdb) and to the direct memory access controller (dmac) by a 32-bit internal data bus (idb) (figures 21.1 and 21.2), allowing 8-, 16-, or 32-bit- wide access to the xram and yram. the xram and yram can be accessed in parallel using the x-bus and y-bus, enabling two data transfer instructions to be executed simultaneously. xram and yram data can always be accessed in one state, making this memory suitable for use in areas requiring high-speed access. the contents of xram and yram are retained in sleep mode and standby mode. the xram and yram are allocated to addresses h'ffff8000 to h'ffff8fff and h'ffffa000 to h'ffffafff, respectively. x data bus (16 bits) internal data bus (idb) (32 bits) h'ffff8000 h'ffff8004 h'ffff8ffc h'ffff8001 h'ffff8005 h'ffff8ffd xram h'ffff8002 h'ffff8006 h'ffff8ffe h'ffff8003 h'ffff8007 h'ffff8fff internal data bus (cdb) (32 bits) figure 21.1 block diagram of xram rev. 1.0, 08/99, page 758 of 875 y data bus (16 bits) h'ffffa000 h'ffffa004 h'ffffaffc h'ffffa001 h'ffffa005 h'ffffaffd h'ffffa002 h'ffffa006 h'ffffaffe h'ffffa003 h'ffffa007 h'ffffafff yram internal data bus (idb) (32 bits) internal data bus (cdb) (32 bits) figure 21.2 block diagram of yram 21.2 operation when addresses h'ffff8000 to h'ffff8fff are accessed, xram is accessed, and when addresses h'ffffa000 to h'ffffafff are accessed, yram is accessed. rev. 1.0, 08/99, page 759 of 875 section 22 electrical characteristics 22.1 absolute maximum ratings table 22.1 absolute maximum ratings item symbol value unit vcc C0.3 to + 4.3 v power supply voltage pvcc C0.3 to + 7.0 v input voltage (except a/d ports) vin C0.3 to v cc + 0.3 v input voltage (a/d ports) vin C0.3 to av cc + 0.3 v analog power supply voltage avcc C0.3 to + 4.3 v analog input voltage van C0.3 to + av cc + 0.3 v operating temperature topr C20 to + 75 c storage temperature tstg C55 to + 125 c usage note: permanent damage to the chip may result if the maximum ratings are exceeded. rev. 1.0, 08/99, page 760 of 875 22.2 electrical characteristics 22.2.1 dc characteristics (1) table 22.2 dc characteristics (conditions: v cc = pllv cc = 3.3 v 0.3 v, pv cc = 5.0 v 0.5 v/3.3 v 0.3 v, av cc = 3.3 v 0.3 v, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min typ max unit test conditions res , nmi, hstby vcc C 0.3 vcc + 0.3 v extal, ckio vcc 0.9 vcc + 0.3 v a/d ports 2.6 avcc + 0.3 v 3 v/5 v dual- function pins 2.6 pvcc + 0.3 v input high- level voltage * other input pins v ih 2.6 vcc + 0.3 v res , nmi, hstby C0.3 0.5 v input low- level voltage * other input pins v il C0.3 0.8 v v t + v t + 3 4.0 v (min): 3 v/5 v dual-function pins, pvcc = 5 v 0.5 v v t + 3 2.6 v (min): other cases v t C v t C 0.8 v (max) schmitt- trigger input characteristics tioc0aCtioc5a, tioc0bCtioc5b, tioc0cCtioc3c, tioc0dCtioc3d, tclka, tclkb, tclkc, tclkd, sck0, sck1, sck2, rxd0, rxd1, rxd2, pci v t + C v t C 0.2 v res , nmi, hstby 1.0 m a a/d ports 1.0 m a input leakage current other input pins | iin | 1.0 m a three-state leakage current (off state) a25Ca0, d31Cd0, cs5 C cs0 , rdwr, wrxx , rd , wr , rasx , casxxx | i ts | 1.0 m a note: * except schmitt-trigger inputs rev. 1.0, 08/99, page 761 of 875 table 22.2 dc characteristics (cont) (conditions: v cc = pllv cc = 3.3 v 0.3 v, pv cc = 5.0 v 0.5 v/3.3 v 0.3 v, av cc = 3.3 v 0.3 v, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min typ max unit test conditions 3 v/5 v dual- function pins pvcc C 0.7 v i oh = C200 m a output high- level voltage other output pins v oh vcc C 0.7 v i oh = C200 m a 3 v/5 v dual- function pins 0.6vi ol = 1.6 ma other output pins 0.6 v i ol = 1.6 ma output low- level voltage pe17Cpe19, pe21Cpe23 v ol 1.5vi ol = 15 ma res 60 pf nmi 30 pf input capacitance all other input pins cin tbd (25) pf vin = 0 v f = 1 mhz ta = 25 c normal operation tbd tbd ma sleep mode tbd tbd ma tbd tbd m ata 50 c current dissipation standby mode icc tbd m a50 c < ta tbd tbd ma during a/d conversion analog power supply current aicc tbd tbd m aidle ram standby voltage v ram 2.0 v usage notes: 1. if the a/d converter is not used (including standby mode), do not leave the av cc and av ss pins open. connect the av cc pin to v cc , and the av ss pin to v ss . 2. current dissipation values are for v ih min = v cc C 0.5 v and v il max = 0.5 v with all output pins unloaded. (for standby current specification conditions, values are for v ih = v cc /pv cc and v il = 0 v with all output pins unloaded.) 3. the ztat and mask versions have the same functions, and the electrical characteristics of both are within specification, but characteristic-related performance values, operating margins, noise margins, noise emission, etc., are different. caution is therefore required in carrying out system design, and when switching between ztat and mask versions. rev. 1.0, 08/99, page 762 of 875 22.2.2 dc characteristics (2) table 22.3 permissible output current values (conditions: v cc = pllv cc = 3.3 v 0.3 v, pv cc = 5.0 v 0.5 v/3.3 v 0.3 v, pv cc 3 v cc , av cc = 3.3 v 0.3 v, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min typ max unit output low-level permissible current (per pin) i ol 2.0 * ma output low-level permissible current (total) ? i ol 80ma output high-level permissible current (per pin) Ci oh 2.0ma output high-level permissible current (total) ? (Ci oh )25ma note: * for pe17 to pe19 and pe21 to pe23, i ol = 15 ma (max). however, an i ol current exceeding 2.0 ma should not be applied to more than three of these pins simultaneously. usage note: to protect chip reliability, do not exceed the output current values in table 22.3. rev. 1.0, 08/99, page 763 of 875 22.3 ac characteristics input reference levels: high level: v cc C0.3 v, low level: 0.5 v output reference levels: high level: 2.0 v, low level: 0.8 v v i ol i ol c l dut pin sh7065 output pin v ref c l = 30 pf figure 22.1 output load circuit rev. 1.0, 08/99, page 764 of 875 22.3.1 clock timing table 22.4 clock timing (conditions: v cc = pllv cc = 3.3 v 0.3 v, pv cc = 5.0 v 0.5 v/3.3 v 0.3 v, pv cc 3 v cc , av cc = 3.3 v 0.3 v, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure operating frequency (master clock) fop 2 60.0 mhz figure 22.2 clock cycle time tcyc 16.7 500 ns clock low-level pulse width tcl 4.4 ns clock high-level pulse width tch 4.4 ns clock rise time tcr 4 ns clock fall time tcf 4 ns extal/ckio clock input frequency fex 2 30 mhz figure 22.3 extal/ckio clock input cycle time texcyc 33.3 500 ns extal/ckio clock input low-level pulse width texl 11.6 ns extal/ckio clock input high-level pulse width texh 11.6 ns extal/ckio clock input rise time texr 5 ns extal/ckio clock input fall time texf 5 ns reset oscillation settling time tosc1 10 ms figure 22.4 standby recovery oscillation settling time tosc2 10 ms figure 22.4 rev. 1.0, 08/99, page 765 of 875 ck ckio 1/2v cc 1/2v cc tch tcl tcf tcr tcyc figure 22.2 system clock timing extal ckio 1/2v cc 1/2v cc texh texl vih vih vil vil vih texf texr texcyc figure 22.3 extal clock input timing ck v cc v cc min tosc1 tosc1 tosc2 figure 22.4 oscillation settling time rev. 1.0, 08/99, page 766 of 875 22.3.2 control signal timing table 22.5 control signal timing (conditions: v cc = pllv cc = 3.3 v 0.3 v, pv cc = 5.0 v 0.5 v/3.3 v 0.3 v, pv cc 3 v cc , av cc = 3.3 v 0.3 v, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure res rise and fall tresr, tresf 200 ns figure 22.5 res pulse width tresw 40 tcyc * 1 nmi rise and fall tnmir, tnmif 200 ns nmi pulse width tnmiw 2.5 tcyc * 2 figure 22.6 irq pulse width tirqw 2.5 tcyc * 2 irqout output delay time tirqod 35 ns figure 22.7 bus request setup time tbrqs 35 ns figure 22.8 bus acknowledge delay time 1 tbackd1 35 ns bus acknowledge delay time 2 tbackd2 35 ns bus three-state delay time tbzd 35 ns notes: 1. slowest module clock 2. slower of m f and cke clocks ckm tresf tresr tresw vil vih vih vil figure 22.5 reset input timing rev. 1.0, 08/99, page 767 of 875 ckm nmi tirqw tnmiw vil vih vil vih edge figure 22.6 interrupt signal input timing m f tirqod tirqod figure 22.7 interrupt signal output timing cke tbrqs tbackd1 tbzd tbrqs tbackd2 tbzd breq (input) back (output) rd, wr, rdwr, rasn, casxxn, csn, wrxx a25, a0, d31Cd0 note: rasn, casxxn, and rdwr are output when the bus is released during self-refreshing. figure 22.8 bus release timing rev. 1.0, 08/99, page 768 of 875 22.3.3 bus timing table 22.6 bus timing (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure address delay time tad 2 * 3 25 ns cs delay time 1 tcsd1 2 * 3 25 ns cs delay time 2 tcsd2 2 * 3 25 ns figure 22.9, figure 22.10, figure 22.12, figure 22.13, figure 22.14, figure 22.15, figure 22.16, figure 22.19, figure 22.20 read strobe delay time 1 trsd1 2 * 3 25 ns read strobe delay time 2 trsd2 2 * 3 25 ns figure 22.9, figure 22.10, figure 22.19, figure 22.20 read data setup time trds * 4 25 ns read data hold time trdh 0 ns figure 22.9, figure 22.10, figure 22.12, figure 22.13, figure 22.14, figure 22.15, figure 22.16, figure 22.19, figure 22.20 write strobe delay time 1 twsd1 2 * 3 25 ns write strobe delay time 2 twsd2 2 * 3 25 ns figure 22.9, figure 22.10, figure 22.19, figure 22.20 write data delay time twdd 25 ns write data hold time twdh 0 25 * 2 ns figure 22.9, figure 22.10, figure 22.12, figure 22.13, figure 22.14, figure 22.15, figure 22.16, figure 22.19, figure 22.20 wait setup time twts 25 ns wait hold time twth 0 ns figure 22.11, figure 22.13, figure 22.20 ras delay time 1 trasd1 2 * 3 25 ns ras delay time 2 trasd2 2 * 3 25 ns figure 22.12, figure 22.13, figure 22.14, figure 22.15, figure 22.16, figure 22.17, figure 22.18 rev. 1.0, 08/99, page 769 of 875 table 22.6 bus timing (cont) (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure cas delay time 1 tcasd1 2 * 3 25 ns cas delay time 2 tcasd2 2 * 3 25 ns figure 22.12, figure 22.13, figure 22.14, figure 22.15, figure 22.16, figure 22.17, figure 22.18 read data access time tacc * 1 t cyc (n+1.5) C 33 ns access time from read strobe toe * 1 t cyc (n+1) C 33 ns figure 22.9, figure 22.10 access time from column address taa * 1 t cyc (n+1.5) C 33 ns access time from ras trac * 1 t cyc (n+rcd+2) C 33 ns access time from cas tcac * 1 t cyc (n+1) C 33 ns row address hold time trah t cyc (rcd+0.5) C 25 ns row address setup time tasr t cyc 0.5 C 16.6 ns data input setup time tds t cyc (m+0.5) C 25 ns data input hold time tdh t cyc + 20 ns figure 22.12, figure 22.15 notes: n is the number of waits. m is 0 when the number of dram write cycle waits is 0, and 1 otherwise. rcd is the set value of the rcd bit in dcr1. 1. the t rds specification need not be met as long as the access time specification is met. 2. t wdh (max) is a reference value. 3. the minimum (min) values for delay times are reference values. 4. t rds is a reference value. rev. 1.0, 08/99, page 770 of 875 table 22.6 bus timing (cont) (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure read/write strobe delay time 1 trwd1 2 * 25 ns read/write strobe delay time 2 trwd2 2 * 25 ns figure 22.12, figure 22.13, figure 22.14, figure 22.15 fast page mode cas precharge time tcp t cyc C 25 ns figure 22.15 ras precharge time trp t cyc (tpc+1.0) C 25 ns figure 22.12, figure 22.15 cas setup time tcsr 10 ns figure 22.17, figure 22.18 ah delay time 1 tahd1 2 * 25 ns ah delay time 2 tahd2 2 * 25 ns multiplex address delay time tmad 2 * 25 ns multiplex address hold time tmah 0 ns figure 22.19, figure 22.20 dack delay time 1 tdackd1 2 * 25 ns figure 22.9, figure 22.10, figure 22.12, figure 22.13, figure 22.14, figure 22.15, figure 22.16, figure 22.19, figure 22.20 an setup time with respect to wrxx fall tas 0 ns an hold time with respect to wrxx rise twr 5 ns dn hold time with respect to wrxx rise twrh 0 ns figure 22.9, figure 22.10 rev. 1.0, 08/99, page 771 of 875 table 22.6 bus timing (cont) (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure bus start delay time 1 tbsd1 2 * 25 ns bus start delay time 2 tbsd2 2 * 25 ns figure 22.9, figure 22.10, figure 22.12, figure 22.13, figure 22.14, figure 22.15, figure 22.16, figure 22.19, figure 22.20 byte strobe delay time 1 txxbsd1 2 * 25 ns byte strobe delay time 2 txxbsd2 2 * 25 ns figure 22.9, figure 22.10 output enable delay time 1 toed1 2 * 25 ns output enable delay time 2 toed2 2 * 25 ns figure 22.14, figure 22.16 column address hold time (read) tcah t cyc (w + 1.5) - 15 ? ns column address hold time (write) tcah t cyc (tcas + 0.5) - 15 ? ns column address setup time (read) tasc t cyc 0.5 - 17.5 ? ns column address setup time (write) tasc t cyc (w + 0.5) - 17.5 ? ns figure 22.12, figure 22.13, figure 22.14, figure 22.15 notes: tpc is the set value of the tpc bit in dcr1. tcas is the set value of the tcas bit in dcr2. w is the dww set number in a write from the cpu, the ddww set number in a dmac single address write, or the number of waits via the wait pin. * the minimum (min) values for delay times are reference values. t cyc is the cke cycle (min. 33.3 ns). rev. 1.0, 08/99, page 772 of 875 cke a25Ca0 csn xxbs bs dackn wr (read) wr (write) wrxx (write) rd (read) d31Cd0 (read) d31Cd0 (write) t1 t2 tad tcsd1 twsd1 tad tcsd2 twsd2 tdackd1 tbsd1 tbsd2 txxbsd1 twdd twsd1 tas twsd1 twsd2 trds trdh trsd2 trsd1 toe tacc twsd2 twr twrh twdh txxbsd2 tdackd1 figure 22.9 basic cycle (no wait) rev. 1.0, 08/99, page 773 of 875 cke a25Ca0 csn xxbs bs dackn wr (read) wr (write) wrxx (write) rd (read) d31Cd0 (read) d31Cd0 (write) t1 tw t2 tad tcsd1 twsd1 tad tcsd2 twsd2 tdackd1 tbsd1 tbsd2 txxbsd1 twdd twsd1 tas twsd1 twsd2 twr twrh trds trdh trsd2 toe tacc trsd1 twsd2 twdh txxbsd2 tdackd1 figure 22.10 basic cycle (software wait) rev. 1.0, 08/99, page 774 of 875 cke a21Ca0 (read) (read) d31Cd0 (read) d31Cd0 (write) t2 thww two tw t1 twts twts twth twth figure 22.11 basic cycle (one software wait + wait signal wait, one software wait after wait signal negation) rev. 1.0, 08/99, page 775 of 875 cke a25Ca0 casxxn rasn bs dackn csn rdwr (read) rdwr (write) d31Cd0 (read) d31Cd0 (write) tr tc1 tc2 (tpc) tad tad trasd1 tasr trah tad trasd2 trp tdackd1 tbsd1 tbsd2 twdd tds tdh trwd1 trwd2 trds tcac taa trac trdh twdh tdackd1 tcsd1 tcsd2 note: trdh: specified from the negation of ras or cas, whichever is first. tcasd2 tcasd1 trwd1 trwd2 row address column address tasc tcah figure 22.12 dram cycle (normal mode, no wait, tpc = 0, rcd = 0) rev. 1.0, 08/99, page 776 of 875 cke a25Ca0 casxxn (read) casxxn (write) rasn bs dackn wait csn rdwr (read) rdwr (write) d31Cd0 (read) d31Cd0 (write) tr two tc1 tc2 (tpc) tad tad trasd1 tad trasd2 tdackd1 tbsd1 tbsd2 twdd trwd1 trwd2 trds twdh tdackd1 tcsd1 tcsd2 note: trdh: specified from the negation of ras or cas, whichever is first. tcasd2 tcasd1 trwd1 tcasd2 tcasd1 twts twth twts twth trwd2 row address column address trdh tasc tcah tasc tcah figure 22.13 dram cycle (normal mode, wait signal wait, tpc = 0, rcd = 0) rev. 1.0, 08/99, page 777 of 875 cke a25Ca0 casxxn rasn bs dackn csn rdwr (read) oen (read) rdwr (write) d31Cd0 (read) d31Cd0 (write) tr tc1 tc2 (tpc) tad tad trasd1 tad trasd2 tdackd1 tbsd1 tbsd2 twdd tds trwd1 trwd2 trds taa trac twdh tdackd1 tcsd1 tcsd2 tcasd2 tcac tcasd1 trwd1 toed2 trdh toed1 trwd2 row address column address note: trdh: specified from the negation of ras or oe, whichever is first. tdh tasc tcah figure 22.14 dram cycle (edo mode) rev. 1.0, 08/99, page 778 of 875 cke dackn a21Ca0 rdwr (read) d31Cd0 (read) rdwr (write) d31Cd0 (write) ras casxx (read) casxx (write) tp tr tad tad tasr trp tc1 tc2 tc1 tc2 note: trdh: specified from the negation of ras or cas, whichever is first. row address trah trac taa taa tcasd1 trwd1 tdackd1 tds tdh twdd tds tdh tdackd1 tdackd1 twdd twdh trwd2 tcasd1 tcasd2 trasd2 tcp trds trds trdh trdh tcac column address column address tcac trasd1 tcasd1 tcasd2 tcp tcasd2 tcasd2 tcasd1 tasc tcah tcah figure 22.15 dram cycle (fast page mode) rev. 1.0, 08/99, page 779 of 875 tr tce1 tce2 tce2 tce2 tce3 (tpc) cke a25Ca0 csn rdwr rasn casxxn oe bs dackn d31Cd0 (read) d31Cd0 (write) row column column column column tad tad tad tcsd2 trasd2 toed2 trdh tbsd2 tbsd1 twdd twdh trds toed1 tcasd1 tcasd2 trasd1 tcsd2 tdackd1 tdackd1 figure 22.16 dram cycle (edo mode, burst access) rev. 1.0, 08/99, page 780 of 875 cke rdwr tcsr trasd1 trasd2 tcasd2 tcasd1 trc trr1 trrw trr2 figure 22.17 cas-before-ras refresh (tras1, tras0 = 0, 0) cke rdwr trp tcsr trasd1 trasd2 tcasd2 tcasd1 trr1 trr2 trc trcc figure 22.18 self-refresh rev. 1.0, 08/99, page 781 of 875 cke a25Ca0 csn ah dackn bs ta1 ta2 ta3 ta4 t2 t1 tad tad tcsd1 tcsd2 tdackd1 trds trdh tmad tmah twdh tmad tmah twdd address address tdackd1 twrd1 twsd2 twsd2 twsd1 twrd1 tbsd1 tbsd2 twsd2 trsd2 trsd1 tahd1 tahd2 wr (read) rd (read) d15Cd0 (read) wrxx (write) wr (write) d15Cd0 (write) figure 22.19 multiplexed address/data i/o space cycle (one software wait + one external wait) rev. 1.0, 08/99, page 782 of 875 cke a25Ca0 wr (read) wr (write) csn ah bs dackn wait rd (read) wrxx (write) d15Cd0 (read) d15Cd0 (write) ta1 ta2 ta3 ta4 two t2 t1 tad tad tcsd1 tcsd2 tdackd1 trds tmad tmah twdh tmad tmah twdd tdackd1 twsd1 twsd2 twsd2 twsd1 twsd1 tbsd2 tbsd1 twth twts twth twts twsd2 trsd2 trsd1 tahd1 tahd2 trdh figure 22.20 multiplexed address/data i/o space cycle (wait signal wait) rev. 1.0, 08/99, page 783 of 875 22.3.4 direct memory access controller timing table 22.7 direct memory access controller timing (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure dreq0, dreq1 setup time tdrqs 16 ns figure 22.21, figure 22.23 dreq0, dreq1 hold time tdrqh 16 ns figure 22.21 dreq0, dreq1 pulse time tdrqw 2.5 tcyc figure 22.22 drak output delay time tdrakd 16 ns figure 22.23, figure 22.24 tend output delay time tted ? 16 ns figure 22.25 cke / level / edge / level clearing (when using 16-stage fifo) tdrqs tdrqs tdrqh tdrqs figure 22.21 dreq0 and dreq1 input timing (1) rev. 1.0, 08/99, page 784 of 875 cke / edge level tdrqw figure 22.22 dreq0 and dreq1 input timing (2) cke / level clearing (when using 1-stage fifo) tdrakd tdrqs figure 22.23 dreq0 and dreq1 input timing (3) rev. 1.0, 08/99, page 785 of 875 cke tdrakd tdrakd figure 22.24 drak output delay time cke tted t1 t2 or t3 tted figure 22.25 tend output delay time rev. 1.0, 08/99, page 786 of 875 22.3.5 16-bit timer pulse unit (tpu) timing table 22.8 16-bit timer pulse unit (tpu) timing (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure output compare output delay time ttocd 100 ns figure 22.26 input capture input setup time ttics 35 ns timer input setup time ttcks 35 ns figure 22.27 timer clock pulse width (single-edge specification) ttckwh/l 1.5 tcyc timer clock pulse width (both-edge specification) ttckwh/l 2.5 tcyc timer clock pulse width (phase counting mode) ttckwh/l 2.5 tcyc p f ttocd ttics output compare output input capture input figure 22.26 tpu input/output timing p f tclkaC tclkd ttcks ttcks ttckwl ttckwh figure 22.27 tpu clock input timing rev. 1.0, 08/99, page 787 of 875 22.3.6 motor management timer (mmt) timing table 22.9 motor management timer (mmt) timing (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure mmt output delay time tmtod 100 ns pci input setup time tpcis 35 ns pci input pulse width tpciw 1.5 tcyc figure 22.28 p f tmtod tpcis tpciw mmt output pci input figure 22.28 mmt input/output timing rev. 1.0, 08/99, page 788 of 875 22.3.7 output enable (poe) timing table 22.10 output enable (poe) timing (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure poe input setup time tpoes 35 ns poe input pulse width tpoew 1.5 tcyc figure 22.29 p f input tpoes tpoew figure 22.29 poe input/output timing rev. 1.0, 08/99, page 789 of 875 22.3.8 i/o port timing table 22.11 i/o port timing (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure port output data delay time tpwd 100 ns figure 22.30 port input hold time tprh 100 ns port input setup time tprs 100 ns cke port (read) port (write) t1 t2 tpwd tprh tprs figure 22.30 i/o port input/output timing rev. 1.0, 08/99, page 790 of 875 22.3.9 watchdog timer timing table 22.12 watchdog timer timing (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure wdtovf delay time twovd 100 ns figure 22.31 m f twovd twovd figure 22.31 watchdog timer timing rev. 1.0, 08/99, page 791 of 875 22.3.10 serial communication interface timing table 22.13 serial communication interface timing (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min max unit figure input clock cycle tscyc 4 p f figure 22.32, figure 22.33 input clock cycle (synchronous) tscyc 6 p f input clock pulse width tsckw 0.4 0.6 p f input clock rise time tsckr 1.5 p f input clock fall time tsckf 1.5 p f transmit data delay time (synchronous) ttxd 100 ns figure 22.33 receive data setup time (synchronous) trxs 100 ns receive data hold time (synchronous) trxh 100 ns note: when the sci output pin is set as an open-drain output, the characteristics depend on the pull-up resistance. sckn tscyc tsckw tsckr tsckf figure 22.32 input clock timing sckn txdn (transmit data) rxdn (receive data) tscyc ttxd trxs trxh figure 22.33 sci input/output timing (synchronous mode) rev. 1.0, 08/99, page 792 of 875 22.3.11 a/d converter timing table 22.14 a/d converter timing (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) item symbol min typ max unit figure external trigger input pulse width ttrgw 2 p f figure 22.34 external trigger input start delay time ttrgs 50 ns cks = 0 td 10 17 p f figure 22.35 a/d conversion start delay time cks = 1 6 9 p f cks = 0 tspl 64 p f input sampling time cks = 1 32 p f cks = 0 tconv 259 266 p f a/d conversion time cks = 1 131 134 p f p f input adst 1 state ttrgw ttrgw ttrgs figure 22.34 external trigger input timing rev. 1.0, 08/99, page 793 of 875 (1) (2) p f adf address write signal input sampling timing t d t spl t conv (1): adcsr write cycle (2): adcsr address t d : a/d conversion start delay time t spl : input sampling time t conv : a/d conversion time figure 22.35 a/d conversion timing rev. 1.0, 08/99, page 794 of 875 22.3.12 a/d converter characteristics table 22.15 a/d converter timing (preliminary) (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) 20 mhz 30 mhz item min typ max min typ max unit resolution 10 10 10 10 10 10 bits conversion time * 2 6.7 (cks = 1) 89 (cks = 0) s analog input capacitance 20 20 pf permissible signal source impedance 1 1 k w nonlinearity error * 2 3.5 * 1 3.5 * 1 lsb offset error * 2 3.5 * 1 3.5 * 1 lsb full-scale error * 2 3.5 * 1 3.5 * 1 lsb quantization error * 2 0.5 * 1 0.5 * 1 lsb absolute accuracy 4 4lsb notes: 1. reference values 2. p f 20 mhz: cks can be set to 0 or 1. p f > 20 mhz: cks can only be set to 0. 22.3.13 d/a converter characteristics table 22.16 d/a converter characteristics (conditions: v cc = pllv cc = 3.0 to 3.6 v, av cc = 3.0 to 3.6 v, av cc = v cc 10%, v ss = pllv ss = pv ss = av ss = 0 v, ta = C20 to +75c) 30 mhz 15 mhz item min typ max min typ max unit test conditions resolution 888 888bits conversion time 10 10 s 20 pf load capacitance 2 4 2 4 lsb 2 m w load resistance absolute accuracy 3 3 3 3 lsb 4 m w load resistance rev. 1.0, 08/99, page 795 of 875 appendix a on-chip peripheral module registers table a.1 on-chip peripheral module registers bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 0080 addra0h ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d h'ffff 0081 addra0l ad1 ad0 h'ffff 0082 addrb0h ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffff 0083 addrb0l ad1 ad0 h'ffff 0084 addrc0h ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffff 0085 addrc0l ad1 ad0 h'ffff 0086 addrd0h ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffff 0087 addrd0l ad1 ad0 h'ffff 0088 to h'ffff 0097 h'ffff 0098 adcsr0 adf adie adst multi cks ch1 ch0 h'ffff 0099 adcr0 trge1 trge0 h'ffff 009a to h'ffff 009f h'ffff 00a0 addra1h ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffff 00a1 addra1l ad1 ad0 h'ffff 00a2 addrb1h ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffff 00a3 addrb1l ad1 ad0 h'ffff 00a4 addrc1h ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffff 00a5 addrc1l ad1 ad0 h'ffff 00a6 addrd1h ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ffff 00a7 addrd1l ad1 ad0 h'ffff 00a8 to h'ffff 00b7 h'ffff 00b8 adcsr1 adf adie adst multi cks ch1 ch0 h'ffff 00b9 adcr1 trge1 trge0 h'ffff 00ba to h'ffff 00bf h'ffff 00c0 dadr0 d/a h'ffff 00c1 dadr1 h'ffff 00c2dacrdaoe1daoe0dae h'ffff 00c3 to h'ffff 03ff rev. 1.0, 08/99, page 796 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 0400 tstr cst5 cst4 cst3 cst2 cst1 cst0 tpu h'ffff 0401 tsyr sync5 sync4 sync3 sync2 sync1 sync0 h'ffff 0402 to h'ffff 040f h'ffff 0410 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff 0411 tmdr0 bfb bfa md3 md2 md1 md0 h'ffff 0412 tior0h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffff 0413 tior0l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'ffff 0414 tier0 ttge tciev tgied tgiec tgieb tgiea h'ffff 0415tsr0tcfvtgfdtgfctgfbtgfa h'ffff 0416 tcnt0 h'ffff 0417 h'ffff 0418 tgr0a h'ffff 0419 h'ffff 041a tgr0b h'ffff 041b h'ffff 041c tgr0c h'ffff 041d h'ffff 041e tgr0d h'ffff 041f h'ffff 0420 tcr1 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff 0421tmdr1md3md2md1md0 h'ffff 0422 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffff 0423 h'ffff 0424 tier1 ttge tcieu tciev tgieb tgiea h'ffff 0425 tsr1 tcfd tcfu tcfv tgfb tgfa h'ffff 0426 tcnt1 h'ffff 0427 h'ffff 0428 tgr1a h'ffff 0429 h'ffff 042a tgr1b h'ffff 042b h'ffff 042c to h'ffff 042f h'ffff 0430 tcr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff 0431tmdr2md3md2md1md0 rev. 1.0, 08/99, page 797 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 0432 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tpu h'ffff 0433 h'ffff 0434 tier2 ttge tcieu tciev tgieb tgiea h'ffff 0435 tsr2 tcfd tcfu tcfv tgfb tgfa h'ffff 0436 tcnt2 h'ffff 0437 h'ffff 0438 tgr2a h'ffff 0439 h'ffff 043a tgr2b h'ffff 043b h'ffff 043c to h'ffff 043f h'ffff 0440 tcr3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff 0441 tmdr3 bfb bfa md3 md2 md1 md0 h'ffff 0442 tior3h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffff 0443 tior3l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'ffff 0444 tier3 ttge tciev tgied tgiec tgieb tgiea h'ffff 0445tsr3tcfvtgfdtgfctgfbtgfa h'ffff 0446 tcnt3 h'ffff 0447 h'ffff 0448 tgr3a h'ffff 0449 h'ffff 044a tgr3b h'ffff 044b h'ffff 044c tgr3c h'ffff 044d h'ffff 044e tgr3d h'ffff 044f h'ffff 0450 tcr4 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff 0451tmdr4md3md2md1md0 h'ffff 0452 tior4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffff 0453 h'ffff 0454 tier4 ttge tcieu tciev tgieb tgiea h'ffff 0455 tsr4 tcfd tcfu tcfv tgfb tgfa h'ffff 0456 tcnt4 h'ffff 0457 rev. 1.0, 08/99, page 798 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 0458 tgr4a tpu h'ffff 0459 h'ffff 045a tgr4b h'ffff 045b h'ffff 045c to h'ffff 045f h'ffff 0460 tcr5 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 h'ffff 0461tmdr5md3md2md1md0 h'ffff 0462 tior5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ffff 0463 h'ffff 0464 tier5 ttge tcieu tciev tgieb tgiea h'ffff 0465 tsr5 tcfd tcfu tcfv tgfb tgfa h'ffff 0466 tcnt5 h'ffff 0467 h'ffff 0468 tgr5a h'ffff 0469 h'ffff 046a tgr5b h'ffff 046b h'ffff 046c to h'ffff 047f h'ffff 0480tmdrolsnolspmd1md0mmt h'ffff 0481 h'ffff 0482tcnrttgecstrprotgientgiem h'ffff 0483 h'ffff 0484tsrtcfdtgfntgfm h'ffff 0485 h'ffff 0486 tcnt h'ffff 0487 h'ffff 0488 tpdr h'ffff 0489 h'ffff 048a tpbr h'ffff 048b h'ffff 048c tddr h'ffff 048d h'ffff 048e h'ffff 048f rev. 1.0, 08/99, page 799 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 0490 tbru mmt h'ffff 0491 h'ffff 0492 tgruu h'ffff 0493 h'ffff 0494 tgru h'ffff 0495 h'ffff 0496 tgrud h'ffff 0497 h'ffff 0498 tdcnt0 h'ffff 0499 h'ffff 049a tdcnt1 h'ffff 049b h'ffff 049c tbru h'ffff 049d h'ffff 049e h'ffff 049f h'ffff 04a0 tbrv h'ffff 04a1 h'ffff 04a2 tgrvu h'ffff 04a3 h'ffff 04a4 tgrv h'ffff 04a5 h'ffff 04a6 tgrvd h'ffff 04a7 h'ffff 04a8 tdcnt2 h'ffff 04a9 h'ffff 04aa tdcnt3 h'ffff 04ab h'ffff 04ac tbrv h'ffff 04ad h'ffff 04ae h'ffff 04af h'ffff 04b0 tbrw h'ffff 04b1 h'ffff 04b2 tgrwu h'ffff 04b3 rev. 1.0, 08/99, page 800 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 04b4 tgrw mmt h'ffff 04b5 h'ffff 04b6 tgrwd h'ffff 04b7 h'ffff 04b8 tdcnt4 h'ffff 04b9 h'ffff 04ba tdcnt5 h'ffff 04bb h'ffff 04bc tbrw h'ffff 04bd h'ffff 04be h'ffff 04bf h'ffff 04c0cmstrcmt h'ffff 04c1 str1str0 h'ffff 04c2cmcsr0 h'ffff 04c3 cmfcmiecks1cks0 h'ffff 04c4 cmcnt0 h'ffff 04c5 h'ffff 04c6 cmcor0 h'ffff 04c7 h'ffff 04c8cmcsr1 h'ffff 04c9 cmfcmiecks1cks0 h'ffff 04ca cmcnt1 h'ffff 04cb h'ffff 04cc cmcor1 h'ffff 04cd h'ffff 04ce to h'ffff 04df h'ffff 04e0icsrpoe3fpoe2fpoe1fpoe0fpiepoe h'ffff 04e1 poe3m1 poe3m0 poe2m1 poe2m0 poe1m1 poe1m0 poe0m1 poe0m0 h'ffff 04e2 to h'ffff 04ff h'ffff 0500 scsmr0 c/a chr/ ick3 pe/ick2 o/e/ick1 stop/ ick0 mp cks1 cks0 sci h'ffff 0501 h'ffff 0502 scbrr0 rev. 1.0, 08/99, page 801 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 0503 sci h'ffff 0504 scscr0 tie rie te re mpie teie cke1 cke0 h'ffff 0505 h'ffff 0506 scftdr0 h'ffff 0507 h'ffff 0508 sc1ssr0 per3 per2 per1 per0 fer3 fer2 fer1 fer0 h'ffff 0509 tdfe rdf orer fer per tend mpb mpbt h'ffff 050a sc2ssr0 tlm rlm n1 n0 brk dr ei er h'ffff 050b h'ffff 050c scfrdr0 h'ffff 050d h'ffff 050e scfcr0 rtrg1 rtrg0 ttrg1 ttrg0 tfrst rfrst loop h'ffff 050f h'ffff 0510scfdr0t4t3t2t1t0 h'ffff 0511 r4r3r2r1r0 h'ffff 0512 scfer0 ed15 ed14 ed13 ed12 ed11 ed10 ed9 ed8 h'ffff 0513 ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 h'ffff 0514 scimr0 irmod psel rivs h'ffff 0515 to h'ffff 051f h'ffff 0520 scsmr1 c/a chr/ ick3 pe/ick2 o/e/ick1 stop/ ick0 mp cks1 cks0 h'ffff 0521 h'ffff 0522 scbrr1 h'ffff 0523 h'ffff 0524 scscr1 tie rie te re mpie teie cke1 cke0 h'ffff 0525 h'ffff 0526 scftdr1 h'ffff 0527 h'ffff 0528 sc1ssr1 per3 per2 per1 per0 fer3 fer2 fer1 fer0 h'ffff 0529 tdfe rdf orer fer per tend mpb mpbt h'ffff 052a sc2ssr1 tlm rlm n1 n0 brk dr ei er h'ffff 052b h'ffff 052c scfrdr1 h'ffff 052d h'ffff 052e scfcr1 rtrg1 rtrg0 ttrg1 ttrg0 tfrst rfrst loop h'ffff 052f rev. 1.0, 08/99, page 802 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 0530scfdr1t4t3t2t1t0sci h'ffff 0531 r4r3r2r1r0 h'ffff 0532 scfer1 ed15 ed14 ed13 ed12 ed11 ed10 ed9 ed8 h'ffff 0533 ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 h'ffff 0534 scimr1 irmod psel rivs h'ffff 0535 to h'ffff 053f h'ffff 0540 scsmr2 c/a chr/ ick3 pe/ick2 o/e/ick1 stop/ ick0 mp cks1 cks0 h'ffff 0541 h'ffff 0542 scbrr2 h'ffff 0543 h'ffff 0544 scscr2 tie rie te re mpie teie cke1 cke0 h'ffff 0545 h'ffff 0546 scftdr2 h'ffff 0547 h'ffff 0548 sc1ssr2 per3 per2 per1 per0 fer3 fer2 fer1 fer0 h'ffff 0549 tdfe rdf orer fer per tend mpb mpbt h'ffff 054a sc2ssr2 tlm rlm n1 n0 brk dr ei er h'ffff 054b h'ffff 054c scfrdr2 h'ffff 054d h'ffff 054e scfdr2 rtrg1 rtrg0 ttrg1 ttrg0 tfrst rfrst loop h'ffff 054f h'ffff 0550scfdr2t4t3t2t1t0 h'ffff 0551 r4r3r2r1r0 h'ffff 0552 scfer2 ed15 ed14 ed13 ed12 ed11 ed10 ed9 ed8 h'ffff 0553 ed7 ed6 ed5 ed4 ed3 ed2 ed1 ed0 h'ffff 0554 scimr2 irmod psel rivs h'ffff 0555 to h'ffff 07ff h'ffff 0800 flmcr1 fwe swe esu psu ev pv e p flash h'ffff 0801flmcr2fler h'ffff 0802 ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 h'ffff 0803ebr2eb11eb10eb9eb8 h'ffff 0804 to h'ffff 0bff rev. 1.0, 08/99, page 803 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 0c00bcrbrqebashizcntbsc h'ffff 0c01 h'ffff 0c02 to h'ffff 0c0f h'ffff 0c10 acr1_0 endian tp1 tp0 exwe sz1 sz0 iw2 h'ffff 0c11 iw1 iw0 swh2 swh1 swh0 swt2 swt1 swt0 h'ffff 0c12 acr1_1 endian tp1 tp0 exwe sz1 sz0 iw2 h'ffff 0c13 iw1 iw0 swh2 swh1 swh0 swt2 swt1 swt0 h'ffff 0c14 acr1_2 endian tp1 tp0 exwe sz1 sz0 iw2 h'ffff 0c15 iw1 iw0 swh2 swh1 swh0 swt2 swt1 swt0 h'ffff 0c16 acr1_3 endian tp1 tp0 exwe sz1 sz0 iw2 h'ffff 0c17 iw1 iw0 swh2 swh1 swh0 swt2 swt1 swt0 h'ffff 0c18 to h'ffff 0c1f h'ffff 0c20acr1_4endianexwe h'ffff 0c21 h'ffff 0c22acr1_5endianexwe h'ffff 0c23 h'ffff 0c24 to h'ffff 0c2f h'ffff 0c30 wcr_0 w3 w2 w1 w0 dsww3 dsww2 dsww1 dsww0 h'ffff 0c31 dswr3 dswr2 dswr1 dswr0 hww2 hww1 hww0 h'ffff 0c32 wcr_1 w3 w2 w1 w0 dsww3 dsww2 dsww1 dsww0 h'ffff 0c33 dswr3 dswr2 dswr1 dswr0 hww2 hww1 hww0 h'ffff 0c34 wcr_2 w3 w2 w1 w0 dsww3 dsww2 dsww1 dsww0 h'ffff 0c35 dswr3 dswr2 dswr1 dswr0 hww2 hww1 hww0 h'ffff 0c36 wcr_3 w3 w2 w1 w0 dsww3 dsww2 dsww1 dsww0 h'ffff 0c37 dswr3 dswr2 dswr1 dswr0 hww2 hww1 hww0 h'ffff 0c38 to h'ffff 0c3f h'ffff 0c40 dcr1 tpc1 tpc0 tpcs2 tpcs1 tpcs0 rcd2 rcd1 rcd0 h'ffff 0c41 dww1 dww0 dwr1 dwr0 h'ffff 0c42 dcr2 diw2 diw1 diw0 ddww3 ddww2 ddww1 ddww0 ddwr3 h'ffff 0c43 ddwr2 ddwr1 ddwr0 rdw tcas h'ffff 0c44 dcr3 be rsd edo dsz1 dsz0 amx2 amx1 amx0 h'ffff 0c45 rfshrmd rev. 1.0, 08/99, page 804 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 0c46 to h'ffff 0c5f bsc h'ffff 0c60 to h'ffff 0c67 h'ffff 0c68 rtcsr cmf cmie cks2 cks1 cks0 ovf ovie lmts1 h'ffff 0c69 lmts0 bref2 bref1 bref0 tras2 tras1 tras0 h'ffff 0c6artcnt h'ffff 0c6b rtcnt7 rtcnt6 rtcnt5 rtcnt4 rtcnt3 rtcnt2 rtcnt1 rtcnt0 h'ffff 0c6crtcor h'ffff 0c6d rtcor7 rtcor6 rtcor5 rtcor4 rtcor3 rtcor2 rtcor1 rtcor0 h'ffff 0c6erfcrrfcr11rfcr10rfcr9rfcr8 h'ffff 0c6f rfcr7 rfcr6 rfcr5 rfcr4 rfcr3 rfcr2 rfcr1 rfcr0 h'ffff 0c70ramerflash h'ffff 0c71 ramasramsram2ram1ram0 h'ffff 0c72 to h'ffff 0c7f h'ffff 0c80 ubarh uba31 uba30 uba29 uba28 uba27 uba26 uba25 uba24 ubc h'ffff 0c81 uba23 uba22 uba21 uba20 uba19 uba18 uba17 uba16 h'ffff 0c82 ubarl uba15 uba14 uba13 uba12 uba11 uba10 uba9 uba8 h'ffff 0c83 uba7 uba6 uba5 uba4 uba3 uba2 uba1 uba0 h'ffff 0c84 ubamrh ubm31 ubm30 ubm29 ubm28 ubm27 ubm26 ubm25 ubm24 h'ffff 0c85 ubm23 ubm22 ubm21 ubm20 ubm19 ubm18 ubm17 ubm16 h'ffff 0c86 ubamrl ubm15 ubm14 ubm13 ubm12 ubm11 ubm10 ubm9 ubm8 h'ffff 0c87 ubm7 ubm6 ubm5 ubm4 ubm3 ubm2 ubm1 ubm0 h'ffff 0c88ubbrubiexyexys h'ffff 0c89 cp1 cp0 id1 id0 rw1 rw0 sz1 sz0 h'ffff 0c8a to h'ffff 0fff rev. 1.0, 08/99, page 805 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 1000 tcsr ovf wt/ it tme cks2 cks1 cks0 wdt h'ffff 1001 tcnt * 1 tcnt7 tcnt6 tcnt5 tcnt4 tcnt3 tcnt2 tcnt1 tcnt0 h'ffff 1002 rstcsr * 2 wovfrste h'ffff 1003 rstcsr * 3 wovfrste h'ffff 1004 sbycr sby hiz h'ffff 1005 to h'ffff 101f h'ffff 1020 msr ?????? sys h'ffff 1021 ?? md5 md4 md3 md2 md1 md0 h'ffff 1022 to h'ffff 1027 h'ffff 1028 frqcr ckiooe ckoe h'ffff 1029 fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 h'ffff 102amodecr h'ffff 102b rommd h'ffff 102c to h'ffff 102f h'ffff 1030 mstpcr1 mstp15 mstp14 mstp13 mstp12 mstp11 mstp10 mstp9 mstp8 h'ffff 1031 mstp7 mstp6 mstp5 mstp4 mstp3 mstp2 mstp1 mstp0 h'ffff 1032 mstpcr2 mstp31 mstp30 mstp29 mstp28 mstp27 mstp26 mstp25 mstp24 h'ffff 1033 mstp23 mstp22 mstp21 mstp20 mstp19 mstp18 mstp17 mstp16 h'ffff 1034 mclkcr1 mclk032 mclk031 mclk030 mclk022 mclk021 mclk020 h'ffff 1035 mclk012 mclk011 mclk010 mclk002 mclk001 mclk000 h'ffff 1036 mclkcr2 mclk072 mclk071 mclk070 mclk062 mclk061 mclk060 h'ffff 1037 mclk052 mclk051 mclk050 mclk042 mclk041 mclk040 h'ffff 1038 mclkcr3 mclk112 mclk111 mclk110 mclk102 mclk101 mclk100 h'ffff 1039 mclk092 mclk091 mclk090 mclk082 mclk081 mclk080 h'ffff 103a mclkcr4 mclk152 mclk151 mclk150 mclk142 mclk141 mclk140 h'ffff 103b mclk132 mclk131 mclk130 mclk122 mclk121 mclk120 h'ffff 103c mclkcr5 mclk191 mclk190 mclk181 mclk180 h'ffff 103d mclk171 mclk170 mclk161 mclk160 h'ffff 103e to h'ffff 104f notes: 1. write address is h'ffff1000; read address is h'ffff1001. 2. write address is h'ffff1002. 3. read address is h'ffff1003. rev. 1.0, 08/99, page 806 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 1050 ipra irq0 irq0 irq0 irq0 irq1 irq1 irq1 irq1 intc h'ffff 1051 irq2 irq2 irq2 irq2 irq3 irq3 irq3 irq3 h'ffff 1052 iprb irq4 irq4 irq4 irq4 irq5 irq5 irq5 irq5 h'ffff 1053 irq6 irq6 irq6 irq6 irq7 irq7 irq7 irq7 h'ffff 1054iprc h'ffff 1055 h'ffff 1056iprd h'ffff 1057 h'ffff 1058 ipre dmac0 dmac0 dmac0 dmac0 dmac1 dmac1 dmac1 dmac1 h'ffff 1059 dmac2 dmac2 dmac2 dmac2 dmac3 dmac3 dmac3 dmac3 h'ffff 105aiprf h'ffff 105b h'ffff 105c iprg bsc bsc bsc bsc bsc bsc bsc bsc h'ffff 105d wdtwdtwdtwdt h'ffff 105e iprh tpu0 tpu0 tpu0 tpu0 tpu0 tpu0 tpu0 tpu0 h'ffff 105f tpu1 tpu1 tpu1 tpu1 tpu1 tpu1 tpu1 tpu1 h'ffff 1060 ipri tpu2 tpu2 tpu2 tpu2 tpu2 tpu2 tpu2 tpu2 h'ffff 1061 tpu3 tpu3 tpu3 tpu3 tpu3 tpu3 tpu3 tpu3 h'ffff 1062 iprj tpu4 tpu4 tpu4 tpu4 tpu4 tpu4 tpu4 tpu4 h'ffff 1063 tpu5 tpu5 tpu5 tpu5 tpu5 tpu5 tpu5 tpu5 h'ffff 1064 iprk sci0 sci0 sci0 sci0 sci1 sci1 sci1 sci1 h'ffff 1065 sci2sci2sci2sci2 h'ffff 1066 iprl cmt cmt cmt cmt a/d a/d a/d a/d h'ffff 1067 mmt mmt mmt mmt poe poe poe poe h'ffff 1068 to h'ffff 106d h'ffff 106eicr1nmileximdnmie h'ffff 106f h'ffff 1070icr2 h'ffff 1071 irq7s irq6s irq5s irq4s irq3s irq2s irq1s irq0s h'ffff 1072isr h'ffff 1073 irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f h'ffff 1074 to h'ffff 10ef rev. 1.0, 08/99, page 807 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 10f0dmaorrc3rc2rc1rc0dma h'ffff 10f1 aenmifdme h'ffff 10f2 to h'ffff 10ff h'ffff 1100 sar0 h'ffff 1101 h'ffff 1102 h'ffff 1103 h'ffff 1104 dar0 h'ffff 1105 h'ffff 1106 h'ffff 1107 h'ffff 1108 dmatcr0 h'ffff 1109 h'ffff 110a h'ffff 110b h'ffff 110c chcr0 rs4rs3rs2rs1rs0 h'ffff 110d fifos ndare nsare fcs tes h'ffff 110e dm1 dm0 sm1 sm0 chne rl am al h'ffff 110f tend ds tm ts1 ts0 ie te de h'ffff 1110 nsar0 h'ffff 1111 h'ffff 1112 h'ffff 1113 h'ffff 1114 ndar0 h'ffff 1115 h'ffff 1116 h'ffff 1117 rev. 1.0, 08/99, page 808 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 1118 ndmatcr0 dma h'ffff 1119 h'ffff 111a h'ffff 111b h'ffff 111c chncnt0 h'ffff 111d h'ffff 111e h'ffff 111f h'ffff 1120 sar1 h'ffff 1121 h'ffff 1122 h'ffff 1123 h'ffff 1124 dar1 h'ffff 1125 h'ffff 1126 h'ffff 1127 h'ffff 1128 dmatcr1 h'ffff 1129 h'ffff 112a h'ffff 112b h'ffff 112c chcr1 rs4rs3rs2rs1rs0 h'ffff 112d fifos ndare nsare fcs tes h'ffff 112e dm1 dm0 sm1 sm0 chne rl am al h'ffff 112f tend ds tm ts1 ts0 ie te de h'ffff 1130 nsar1 h'ffff 1131 h'ffff 1132 h'ffff 1133 h'ffff 1134 ndar1 h'ffff 1135 h'ffff 1136 h'ffff 1137 h'ffff 1138 ndmatcr1 h'ffff 1139 h'ffff 113a h'ffff 113b rev. 1.0, 08/99, page 809 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 113c chncnt1 dma h'ffff 113d h'ffff 113e h'ffff 113f h'ffff 1140 sar2 h'ffff 1141 h'ffff 1142 h'ffff 1143 h'ffff 1144 dar2 h'ffff 1145 h'ffff 1146 h'ffff 1147 h'ffff 1148 dmatcr2 h'ffff 1149 h'ffff 114a h'ffff 114b h'ffff 114c chcr2 rs4rs3rs2rs1rs0 h'ffff 114d fifos ndare nsare fcs tes h'ffff 114e dm1 dm0 sm1 sm0 chne rl am al h'ffff 114f tend ds tm ts1 ts0 ie te de h'ffff 1150 nsar2 h'ffff 1151 h'ffff 1152 h'ffff 1153 h'ffff 1154 ndar2 h'ffff 1155 h'ffff 1156 h'ffff 1157 h'ffff 1158 ndmatcr2 h'ffff 1159 h'ffff 115a h'ffff 115b h'ffff 115c chncnt2 h'ffff 115d h'ffff 115e h'ffff 115f rev. 1.0, 08/99, page 810 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 1160 sar3 dma h'ffff 1161 h'ffff 1162 h'ffff 1163 h'ffff 1164 dar3 h'ffff 1165 h'ffff 1166 h'ffff 1167 h'ffff 1168 dmatcr3 h'ffff 1169 h'ffff 116a h'ffff 116b h'ffff 116c chcr3 rs4rs3rs2rs1rs0 h'ffff 116d fifos ndare nsare fcs tes h'ffff 116e dm1 dm0 sm1 sm0 chne rl am al h'ffff 116f tend ds tm ts1 ts0 ie te de h'ffff 1170 nsar3 h'ffff 1171 h'ffff 1172 h'ffff 1173 h'ffff 1174 ndar3 h'ffff 1175 h'ffff 1176 h'ffff 1177 h'ffff 1178 ndmatcr3 h'ffff 1179 h'ffff 117a h'ffff 117b h'ffff 117c chncnt3 h'ffff 117d h'ffff 117e h'ffff 117f h'ffff 1180 to h'ffff 11ff rev. 1.0, 08/99, page 811 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 1200padrhpa25drpa24drport h'ffff 1201 pa23dr pa22dr pa21dr pa20dr pa19dr pa18dr pa17dr pa16dr h'ffff 1202 padrl pa15dr pa14dr pa13dr pa12dr pa9dr pa8dr h'ffff 1203 pa1drpa0dr h'ffff 1204paiorhpa25iorpa24ior h'ffff 1205 pa23ior pa22ior pa21ior pa20ior pa19ior pa18ior pa17ior pa16ior h'ffff 1206 paiorl pa15ior pa14ior pa13ior pa12ior pa9ior pa8ior h'ffff 1207 pa1iorpa0ior h'ffff 1208 pacrh1 h'ffff 1209 pa25mdpa24md h'ffff 120a pacrh2 pa23md pa22md pa21md pa20md h'ffff 120b pa19md pa18md pa17md pa16md1 pa16md0 h'ffff 120c pacrl1 pa15md1 pa15md0 pa14md pa13md pa12md h'ffff 120d pa9mdpa8md h'ffff 120epacrl2 h'ffff 120f pa1mdpa0md h'ffff 1210pbdrh h'ffff 1211 pb23dr pb22dr pb21dr pb20dr pb19dr pb18dr pb17dr pb16dr h'ffff 1212pbdrlpb13dr h'ffff 1213 pb7drpb6dr h'ffff 1214pbiorh h'ffff 1215 pb23ior pb22ior pb21ior pb20ior pb19ior pb18ior pb17ior pb16ior h'ffff 1216pbiorlpb13ior h'ffff 1217 pb7iorpb6ior h'ffff 1218 pbcrh1 h'ffff 1219 h'ffff 121a pbcrh2 pb23md1 pb23md0 pb22md1 pb22md0 pb21md pb20md h'ffff 121b pb19md1 pb19md0 pb18md1 pb18md0 pb17md pb16md h'ffff 121cpbcrl1pb13md h'ffff 121d h'ffff 121epbcrl2pb7mdpb6md h'ffff 121f h'ffff 1220 pcdrh pc25drpc24dr h'ffff 1221 pc23dr pc22dr pc21dr pc20dr pc19dr pc18dr pc17dr pc16dr h'ffff 1222 pcdrl pc15dr pc14dr pc13dr pc12dr pc11dr pc10dr pc9dr pc8dr h'ffff 1223 pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr rev. 1.0, 08/99, page 812 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 1224pciorhpc25iorpc24iorport h'ffff 1225 pc23ior pc22ior pc21ior pc20ior pc19ior pc18ior pc17ior pc16ior h'ffff 1226 pciorl pc15ior pc14ior pc13ior pc12ior pc11ior pc10ior pc9ior pc8ior h'ffff 1227 pc7ior pc6ior pc5ior pc4ior pc3ior pc2ior pc1ior pc0ior h'ffff 1228 pccrh1 h'ffff 1229 pc25md1pc25md0pc24md1pc24md0 h'ffff 122a pccrh2 pc23md1 pc23md0 pc22md1 pc22md0 pc21md1 pc21md0 pc20md1 pc20md0 h'ffff 122b pc19md1 pc19md0 pc18md1 pc18md0 pc17md1 pc17md0 pc16md1 pc16md0 h'ffff 122c pccrl1 pc15md1 pc15md0 pc14md1 pc14md0 pc13md pc12md h'ffff 122d pc11md pc10md pc9md pc8md h'ffff 122e pccrl2 pc7md pc6md pc5md pc4md h'ffff 122f pc3md pc2md pc1md pc0md h'ffff 1230 pddrh pd31dr pd30dr pd29dr pd28dr pd27dr pd26dr pd25dr pd24dr h'ffff 1231 pd23dr pd22dr pd21dr pd20dr pd19dr pd18dr pd17dr pd16dr h'ffff 1232 pddrl pd15dr pd14dr pd13dr pd12dr pd11dr pd10dr pd9dr pd8dr h'ffff 1233 pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr h'ffff 1234 pdiorh pd31ior pd30ior pd29ior pd28ior pd27ior pd26ior pd25ior pd24ior h'ffff 1235 pd23ior pd22ior pd21ior pd20ior pd19ior pd18ior pd17ior pd16ior h'ffff 1236 pdiorl pd15ior pd14ior pd13ior pd12ior pd11ior pd10ior pd9ior pd8ior h'ffff 1237 pd7ior pd6ior pd5ior pd4ior pd3ior pd2ior pd1ior pd0ior h'ffff 1238 pdcrh1 pd31md1 pd31md0 pd30md1 pd30md0 pd29md1 pd29md0 pd28md1 pd28md0 h'ffff 1239 pd27md1 pd27md0 pd26md1 pd26md0 pd25md1 pd25md0 pd24md1 pd24md0 h'ffff 123a pdcrh2 pd23md1 pd23md0 pd22md1 pd22md0 pd21md1 pd21md0 pd20md1 pd20md0 h'ffff 123b pd19md1 pd19md0 pd18md1 pd18md0 pd17md1 pd17md0 pd16md1 pd16md0 h'ffff 123c pdcrl1 pd15md1 pd15md0 pd14md1 pd14md0 pd13md1 pd13md0 pd12md1 pd12md0 h'ffff 123d pd11md1 pd11md0 pd10md1 pd10md0 pd9md1 pd9md0 pd8md1 pd8md0 h'ffff 123e pdcrl2 pd7md pd6md pd5md pd4md h'ffff 123f pd3md pd2md pd1md pd0md h'ffff 1240pedrh h'ffff 1241 pe23dr pe22dr pe21dr pe20dr pe19dr pe18dr pe17dr pe16dr h'ffff 1242pedrlpe15drpe14drpe13drpe12dr h'ffff 1243 h'ffff 1244peiorh h'ffff 1245 pe23ior pe22ior pe21ior pe20ior pe19ior pe18ior pe17ior pe16ior h'ffff 1246peiorlpe15iorpe14iorpe13iorpe12ior h'ffff 1247 rev. 1.0, 08/99, page 813 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 1248 pecrh1 port h'ffff 1249 h'ffff 124a pecrh2 pe23md1 pe23md0 pe22md1 pe22md0 pe21md1 pe21md0 pe20md1 pe20md0 h'ffff 124b pe19md1 pe19md0 pe18md1 pe18md0 pe17md1 pe17md0 pe16md1 pe16md0 h'ffff 124c pecrl pe15md pe14md pe13md pe12md h'ffff 124d h'ffff 124e h'ffff 124f h'ffff 1250fcr h'ffff 1251 scimdirqmd1irqmd0 h'ffff 1252 to h'ffff 1261 h'ffff 1262pfdrl h'ffff 1263 pf7dr pf6dr pf5dr pf3dr pf2dr pf1dr h'ffff 1264 h'ffff 1265 h'ffff 1266pfiorl h'ffff 1267 pf7ior pf6ior pf5ior pf3ior pf2ior pf1ior h'ffff 1268 to h'ffff 126b h'ffff 126cpfcrl1 h'ffff 126d h'ffff 126e pfcrl2 pf7md1 pf7md0 pf6md1 pf6md0 pf5md1 pf5md0 h'ffff 126f pf3md1 pf3md0 pf2md1 pf2md0 pf1md1 pf1md0 h'ffff 1270pgdrpg31drpg30drpg29dr h'ffff 1271 h'ffff 1272 h'ffff 1273 h'ffff 1274 pgior pg31ior pg30ior pg29ior h'ffff 1275 h'ffff 1276 h'ffff 1277 h'ffff 1278 pgcrh1 pg31md pg30md pg29md h'ffff 1279 h'ffff 127a pgcrh2 h'ffff 127b rev. 1.0, 08/99, page 814 of 875 table a.1 on-chip peripheral module registers (cont) bit names address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module h'ffff 127c to h'ffff 1281 port h'ffff 1282phdrph1drph0dr h'ffff 1283 to h'ffff 1285 h'ffff 1286phior h'ffff 1287 ph1iorph0ior h'ffff 1288 to h'ffff 128d h'ffff 128ephcr h'ffff 128f ph1mdph0md h'ffff 1290 pidr pi7dr pi6dr pi5dr pi4dr pi3dr pi2dr pi1dr pi0dr h'ffff 1291 to h'ffff 12ff rev. 1.0, 08/99, page 815 of 875 appendix b pin states b.1 pin states in reset, power-down state, and bus-released state table b.1 pin states in reset, power-down state, and bus-released state pin function pin state power-down state type pin name reset state software standby hardware standby * 7 sleep bus- released state software standby in bus- released state hardware standby in bus- released state ckio i/o/z * 1, * 2 i/l/z * 1, * 2 i/l/z * 1, * 2 i/o/z * 1 * 2 i/o/z * 1, * 2 i/l/z * 1 * 2 i/l/z * 1, * 2 extal i * 1 i * 1 i * 1 i * 1 i * 1 i * 1 i * 1 xtal o * 1 o * 1 o * 1 o * 1 o * 1 o * 1 o * 1 ck o/z * 1, * 2 l/z * 1, * 2 l/z * 1, * 2 o/z * 1, * 2 o/z * 1, * 2 l/z * 1, * 2 l/z * 1, * 2 clock pllcap1C pllcap2 i/o i/o i/o i/o i/o i/o i/o res i iiiiii wdtovf hhzoohz breq zzziiiz back z zzollz system control hstby i iiiiii md0Cmd5i iiiiii operating mode control fwe i iiiiii nmi i iziiiz irq0 C irq7 ziziiiz interrupt irqout zh * 4 zooh * 4 z address bus a0C25 o z z o z z z data bus d0C31 z z z i/o z z z bs h * 5 zzozzz cs0 h * 5 zzozzz cs1 C cs5 z zzozzz rd h * 5 zzozzz bus control rdwr z z z o z z z rev. 1.0, 08/99, page 816 of 875 table b.1 pin states in reset, power-down state, and bus-released state (cont) pin function pin state power-down state type pin name reset state software standby hardware standby * 7 sleep bus- released state software standby in bus- released state hardware standby in bus- released state bus control wrll C hh / llbs C hhbs h * 5 zzozzz wait z zzizzz wr z zzozzz ras0 C ras1 zz/o * 3 zoz/o * 3 z/o * 3 z oe0 C oe1 zz/o * 3 zoz/o * 3 z/o * 3 z ah z zzozzz dmac dreq0 C dreq1 zzziizz drak0 C drak1 zo * 4 zooo * 4 z dack0 C dack1 zo * 4 zooo * 4 z tend0 C tend1 zo * 4 zooo * 4 z tpu tclkaCtclkd z z z i i z z tioc0aCtioc0d z k * 4 z i/o i/o k * 4 z tioc1aCtioc1b z k * 4 z i/o i/o k * 4 z tioc2aCtioc2b z k * 4 z i/o i/o k * 4 z tioc3aCtioc3d z k * 4 z i/o i/o k * 4 z tioc4aCtioc4b z k * 4 z i/o i/o k * 4 z tioc5aCtioc5b z k * 4 z i/o i/o k * 4 z mmt pcio z k * 4 z i/o i/o k * 4 z puoaCpuob z z * 6 z * 6 oo z * 6 z * 6 pvoaCpvob z z * 6 z * 6 oo z * 6 z * 6 pwoaCpwob z z * 6 z * 6 oo z * 6 z * 6 poe0 C poe3 zzziizz sci txd0Ctxd2 z o * 4 zooo * 4 z rxd0Crxd2 z z z i i z z sck0Csck2 z z z i/o i/o z z an0Can7 z z z i i z z a/d converter adtrg zzziizz d/a converter da0Cda1 z o * 4 zooo * 4 z rev. 1.0, 08/99, page 817 of 875 table b.1 pin states in reset, power-down state, and bus-released state (cont) pin function pin state power-down state type pin name reset state software standby hardware standby * 7 sleep bus- released state software standby in bus- released state hardware standby in bus- released state i/o ports pan z k * 4 z k i/o k * 4 z pbn z k * 4 z k i/o k * 4 z pcn z k * 4 z k i/o k * 4 z pdn z k * 4 z k i/o k * 4 z pen z k * 4 z k i/o k * 4 z pfn z k * 4 z k i/o k * 4 z pgn z k * 4 z k i/o k * 4 z phn z k * 4 z k i/o k * 4 z pin z z z i i z z i: input o: output h: high-level output l: low-level output z: high-impedance state k: input pins are in the high-impedance state; output pins maintain their previous state. notes: 1. depends on the clock mode. 2. z or o depending on register setting. 3. z or o depending on bus control register setting. 4. z or o depending on standby control register setting. 5. z in on-chip rom enabled modes and single-chip mode. 6. z for all pins when puoa, pvoa, pwoa, puob, pvob, and pwob are multiplexed. rev. 1.0, 08/99, page 818 of 875 b.2 bus-related signal pin states table b.2 bus-related signal pin states on-chip supporting modules 16-bit space pin on-chip rom space on-chip ram space 8-bit space upper byte lower byte word/ longword cs0 C cs5 hhhhhh ras0 , ras1 * 1 hhhhhh cashh0 , cashh1 * 2 hhhhhh cashl0 , cashl1 * 2 hhhhhh caslh0 , caslh1 * 2 hhhhhh casll0 , casll1 * 2 hhhhhh oe0 , oe1 hhhhhh rdwr rhhhhhh whhhhhh ah llllll bs hhhhhh rd rhhhhhh whhhhh wr rhhhhhh whhhhh wrhh rhhhhhh whhhhh wrhl rhhhhhh whhhhh wrlh rhhhhhh whhhhh wrll rhhhhhh whhhhh hhbs rhhhhhh whhhhh hlbs rhhhhhh whhhhh lhbs rhhhhhh whhhhh llbs rhhhhhh whhhhh a25Ca0 address * 3 address * 3 address * 3 address * 3 address * 3 address * 3 d31Cd24 high-z high-z high-z high-z high-z high-z d23Cd16 high-z high-z high-z high-z high-z high-z d15Cd8 high-z high-z high-z high-z high-z high-z d7Cd0 high-z high-z high-z high-z high-z high-z r: read w: write notes: 1. asserted low in ras down or refresh state. 2. asserted low in refresh state. 3. previously accessed external space address value is retained. rev. 1.0, 08/99, page 819 of 875 table b.2 bus-related signal pin states (cont) external normal space 16-bit space big-endian little-endian pin 8-bit space upper byte lower byte upper byte lower byte word/ longword cs0 C cs3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 cs4 , cs5 hhh hhh ras0 , ras1 * 1 hhh hhh cashh0 , cashh1 * 2 hhh hhh cashl0 , cashl1 * 2 hhh hhh caslh0 , caslh1 * 2 hhh hhh casll0 , c asll1 * 2 hhh hhh oe0 , oe1 hhh hhh rdwr r h h h h h h whhh hhh ah lll lll bs enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 rd rlll lll whhh hhh wr rhhh hhh wlll lll wrhh rhhh hhh whhh hhh wrhl rhhh hhh whhh hhh wrlh rhhh hhh wh l h h l l wrll rhhh hhh wl h l l h l hhbs rhhh hhh whhh hhh hlbs rhhh hhh whhh hhh lhbs rh l h h l l wh l h h l l llbs rl h l l h l wl h l l h l a25Ca0 address address address address address address d31Cd24 high-z high-z high-z high-z high-z high-z d23Cd16 high-z high-z high-z high-z high-z high-z d15Cd8 high-z data high-z high-z data data d7Cd0 data high-z data data high-z data r: read w: write notes: 1. asserted low in ras down or refresh state. 2. asserted low in refresh state. 3. chip select signal for accessed area is low, other chip select signals are high. 4. asserted low in accordance with bs timing. rev. 1.0, 08/99, page 820 of 875 table b.2 bus-related signal pin states (cont) external normal space 32-bit space big-endian little-endian pin most sig- nificant byte byte 1 byte 2 least sig- nificant byte most sig- nificant byte byte 1 byte 2 least sig- nificant byte cs0 C cs3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 cs4 , cs5 hhhh hhhh ras0 , ras1 * 1 hhhh hhhh cashh0 , cashh1 * 2 hhhh hhhh cashl0 , cashl1 * 2 hhhh hhhh caslh0 , caslh1 * 2 hhhh hhhh casll0 , casll1 * 2 hhhh hhhh oe0 , oe1 hhhh hhhh rdwr rhhhh hhhh whhhh hhhh ah llll llll bs enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 rd rllll llll whhhh hhhh wr rhhhh hhhh wllll llll wrhh rhhhh hhhh wl hhh hhhl wrhl rhhhh hhhh whl hh hhl h wrlh rhhhh hhhh wh h l h h l h h wrll rhhhh hhhh whhhl l hhh hhbs rl hhh hhhl wl hhh hhhl hlbs rhl hh hhl h whl hh hhl h lhbs rh h l h h l h h wh h l h h l h h llbs rhhhl l hhh whhhl l hhh a25Ca0 address address address address address address address address d31Cd24 data high-z high-z high-z high-z high-z high-z data d23Cd16 high-z data high-z high-z high-z high-z data high-z d15Cd8 high-z high-z data high-z high-z data high-z high-z d7Cd0 high-z high-z high-z data data high-z high-z high-z r: read w: write notes: 1. asserted low in ras down or refresh state. 2. asserted low in refresh state. 3. chip select signal for accessed area is low, other chip select signals are high. 4. asserted low in accordance with bs timing. rev. 1.0, 08/99, page 821 of 875 table b.2 bus-related signal pin states (cont) external normal space 32-bit space big-endian little-endian pin upper byte lower byte upper byte lower byte longword cs0 C cs3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 cs4 , cs5 hh hhh ras0 , ras1 * 1 hh hhh cashh0 , cashh1 * 2 hh hhh cashl0 , cashl1 * 2 hh hhh caslh0 , caslh1 * 2 hh hhh casll0 , casll1 * 2 hh hhh oe0 , oe1 hh hhh rdwr r h h h h h whh hhh ah ll lll bs enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 rd rll lll whh hhh wr rhh hhh wll lll wrhh rhh hhh wl h h l l wrhl rhh hhh wl h h l l wrlh rhh hhh wh l l h l wrll rhh hhh wh l l h l hhbs rl h h l l wl h h l l hlbs rl h h l l wl h h l l lhbs rh l l h l wh l l h l llbs rh l l h l wh l l h l a25Ca0 address address address address address d31Cd24 data high-z high-z data data d23Cd16 data high-z high-z data data d15Cd8 high-z data data high-z data d7Cd0 high-z data data high-z data r: read w: write notes: 1. asserted low in ras down or refresh state. 2. asserted low in refresh state. 3. chip select signal for accessed area is low, other chip select signals are high. 4. asserted low in accordance with bs timing. rev. 1.0, 08/99, page 822 of 875 table b.2 bus-related signal pin states (cont) multiplexed i/o space 16-bit space big-endian little-endian pin 8-bit space upper byte lower byte upper byte lower byte word/ longword cs0 hhh hhh cs1 C cs3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 cs4 , cs5 hhh hhh ras0 , ras1 * 1 hhh hhh cashh0 , cashh1 * 2 hhh hhh cashl0 , c ashl1 * 2 hhh hhh caslh0 , caslh1 * 2 hhh hhh casll0 , casll1 * 2 hhh hhh oe0 , oe1 hhh hhh rdwr r h h h h h h whhh hhh ah enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 bs enabled * 5 enabled * 5 enabled * 5 enabled * 5 enabled * 5 enabled * 5 rd rlll lll whhh hhh wr rhhh hhh wlll lll wrhh rhhh hhh whhh hhh wrhl rhhh hhh whhh hhh wrlh rhhh hhh wh l h h l l wrll rhhh hhh wl h l l h l hhbs rhhh hhh whhh hhh hlbs rhhh hhh whhh hhh lhbs rhhh hhh whhh hhh llbs rhhh hhh whhh hhh a25Ca0 address address address address address address d31Cd24 high-z high-z high-z high-z high-z high-z d23Cd16 high-z high-z high-z high-z high-z high-z d15Cd8 high-z address/data address address address/data address/data d7Cd0 address/data address address/data address/data address address/data r: read w: write notes: 1. asserted low in ras down or refresh state. 2. asserted low in refresh state. 3. chip select signal for accessed area is low, other chip select signals are high. 4. output at high level in accordance with ah timing. 5. asserted low in accordance with bs timing. rev. 1.0, 08/99, page 823 of 875 table b.2 bus-related signal pin states (cont) dram space 16-bit space big-endian little-endian pin 8-bit space upper byte lower byte upper byte lower byte word/ longword cs0 C cs3 hhh hhh cs4 , cs5 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 ras0 , ras1 * 1 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 cashh0 , cashh1 * 2 hhh hhh cashl0 , cashl1 * 2 hhh hhh caslh0 , caslh1 * 2 h enabled * 4 h h enabled * 4 enabled * 4 casll0 , casll1 * 2 enabled * 4 h enabled * 4 enabled * 4 h enabled * 4 oe0 , oe1 enabled * 5 enabled * 5 enabled * 5 enabled * 5 enabled * 5 enabled * 5 rdwr r h h h h h h wlll lll ah lll lll bs enabled * 6 enabled * 6 enabled * 6 enabled * 6 enabled * 6 enabled * 6 rd rhhh hhh whhh hhh wr rhhh hhh whhh hhh wrhh rhhh hhh whhh hhh wrhl rhhh hhh whhh hhh wrlh rhhh hhh whhh hhh wrll rhhh hhh whhh hhh hhbs rhhh hhh whhh hhh hlbs rhhh hhh whhh hhh lhbs rhhh hhh whhh hhh llbs rhhh hhh whhh hhh a25Ca0 address address address address address address d31Cd24 high-z high-z high-z high-z high-z high-z d23Cd16 high-z high-z high-z high-z high-z high-z d15Cd8 high-z data high-z high-z data data d7Cd0 data high-z data data high-z data r: read w: write notes: 1. asserted low in ras down or refresh state. 2. asserted low in refresh state. 3. chip select signal for accessed area is low, other chip select signals are high. 4. signal for accessed area is asserted low, and other signals go high, at timing in accordance with dram access strobe waveform. 5. in edo mode only, asserted low in accordance with oe timing. 6. asserted low in accordance with bs timing. rev. 1.0, 08/99, page 824 of 875 table b.2 bus-related signal pin states (cont) dram space 32-bit space big-endian little-endian pin most sig- nificant byte byte 1 byte 2 least sig- nificant byte most sig- nificant byte byte 1 byte 2 least sig- nificant byte cs0 C cs3 hhhh hhhh cs4 , cs5 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 ras0 , ras1 * 1 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 cashh0 , cashh1 * 2 enabled * 4 hhh hhhe nabled * 4 cashl0 , cashl1 * 2 h enabled * 4 h h h h enabled * 4 h caslh0 , caslh1 * 2 h h enabled * 4 h h enabled * 4 hh casll0 , casll1 * 2 h h h enabled * 4 enabled * 4 hhh oe0 , oe1 enabled * 5 enabled * 5 enabled * 5 enabled * 5 enabled * 5 enabled * 5 enabled * 5 enabled * 5 rdwr rhhhh hhhh wllll llll ah llll llll bs enabled * 6 enabled * 6 enabled * 6 enabled * 6 enabled * 6 enabled * 6 enabled * 6 enabled * 6 rd rhhhh hhhh whhhh hhhh wr rhhhh hhhh whhhh hhhh wrhh rhhhh hhhh whhhh hhhh wrhl rhhhh hhhh whhhh hhhh wrlh rhhhh hhhh whhhh hhhh wrll rhhhh hhhh whhhh hhhh hhbs rhhhh hhhh whhhh hhhh hlbs rhhhh hhhh whhhh hhhh lhbs rhhhh hhhh whhhh hhhh llbs rhhhh hhhh whhhh hhhh a25Ca0 address address address address address address address address d31Cd24 data high-z high-z high-z high-z high-z high-z data d23Cd16 high-z data high-z high-z high-z high-z data high-z d15Cd8 high-z high-z data high-z high-z data high-z high-z d7Cd0 high-z high-z high-z data data high-z high-z high-z r: read w: write notes: 1. asserted low in ras down or refresh state. 2. asserted low in refresh state. 3. chip select signal for accessed area is low, other chip select signals are high. 4. signal for accessed area is asserted low, and other signals go high, at timing in accordance with dram access strobe waveform. 5. in edo mode only, asserted low in accordance with oe timing. 6. asserted low in accordance with bs timing. rev. 1.0, 08/99, page 825 of 875 table b.2 bus-related signal pin states (cont) dram space 32-bit space big-endian little-endian pin upper byte lower byte upper byte lower byte longword cs0 C cs3 hh hhh cs4 , cs5 enabled * 3 enabled * 3 enabled * 3 enabled * 3 enabled * 3 ras0 , ras1 * 1 enabled * 4 enabled * 4 enabled * 4 enabled * 4 enabled * 4 cashh0 , cashh1 * 2 enabled * 4 h h enabled * 4 enabled * 4 cashl0 , cashl1 * 2 enabled * 4 h h enabled * 4 enabled * 4 caslh0 , caslh1 * 2 h enabled * 4 enabled * 4 h enabled * 4 casll0 , casll1 * 2 h enabled * 4 enabled * 4 h enabled * 4 oe0 , oe1 enabled * 5 enabled * 5 enabled * 5 enabled * 5 enabled * 5 rdwr r h h h h h wll lll ah ll lll bs enabled * 6 enabled * 6 enabled * 6 enabled * 6 enabled * 6 rd rhh hhh whh hhh wr rhh hhh whh hhh wrhh rhh hhh whh hhh wrhl rhh hhh whh hhh wrlh rhh hhh whh hhh wrll rhh hhh whh hhh hhbs rhh hhh whh hhh hlbs rhh hhh whh hhh lhbs rhh hhh whh hhh llbs rhh hhh whh hhh a25Ca0 address address address address address d31Cd24 data high-z high-z data data d23Cd16 data high-z high-z data data d15Cd8 high-z data data high-z data d7Cd0 high-z data data high-z data r: read w: write notes: 1. asserted low in ras down or refresh state. 2. asserted low in refresh state. 3. chip select signal for accessed area is low, other chip select signals are high. 4. signal for accessed area is asserted low, and other signals go high, at timing in accordance with dram access strobe waveform. 5. in edo mode only, asserted low in accordance with oe timing. 6. asserted low in accordance with bs timing. rev. 1.0, 08/99, page 826 of 875 appendix c i/o port block diagrams pa r res paw pandr internal data bus oe0/1, ras0/1 wr, cs1/2/3/4/5 single-chip mode pfc panmd panior hiz sbycr standby bus released par: port a read signal paw: port a write signal res: reset signal n = 0, 1, 8, 9, 17, or 21 to 25 figure c.1 pan/xxxx block diagram rev. 1.0, 08/99, page 827 of 875 pa r res paw pandr pfc panmd panior sbycr hiz bsc wait standby bus released single-chip mode internal data bus par: port a read signal paw: port a write signal res: reset signal n = 12 figure c.2 pa12/wait block diagram rev. 1.0, 08/99, page 828 of 875 pa r res pandr paw wrlh, lhbs wrll, llbs pfc panmd panior sbycr hiz standby mode 2/3/4 single-chip mode mode 1 bus released par: port a read signal paw: port a write signal res: reset signal n = 13, 14 internal data bus figure c.3 pa13/wrll/llbs, pa14/wrlh/lhbs block diagram rev. 1.0, 08/99, page 829 of 875 pa r res pandr paw internal data bus , , , tioc3b, tioc3a single-chip mode pfc panmd0 panmd1 panior sbycr hiz standby tpu tioc3b/ tioc3a tclkd/ tclkc mode 2/3/4 bus released par: port a read signal paw: port a write signal res: reset signal n = 15, 16 figure c.4 pa15/wrhl/hlbs/tclkd/tioc3b, pa16/wrhh/hhbs/tclkc/tioc3a block diagram rev. 1.0, 08/99, page 830 of 875 pa r res pandr paw internal data bus cs0, bs, rd single-chip mode mode 1 mode 2/3/4 bus released pfc panmd panior sbycr hiz standby par: port a read signal paw: port a write signal res: reset signal n = 18 to 20 figure c.5 pa18/rd, pa19/bs, pa20/cs0 block diagram rev. 1.0, 08/99, page 831 of 875 pbr res pbndr pbw internal data bus single-chip mode pfc pbnmd pbnior sbycr hiz bsc breq standby bus released pbr: port b read signal pbw: port b write signal res: reset signal n = 6 figure c.6 pb6/breq block diagram rev. 1.0, 08/99, page 832 of 875 pbr res pbndr pbw internal data bus back, rdwr, casll0, caslh0, casll1, caslh1 single-chip mode pfc pbnmd0 pbnior sbycr hiz standby pbr: port b read signal pbw: port b write signal res: reset signal n = 7, 13, 16, 17, 20, 21 figure c.7 pbn/xxxx block diagram rev. 1.0, 08/99, page 833 of 875 pbr res pbndr pbw internal data bus cashl0 single-chip mode pfc pbnmd0 pbnmd1 pbnior sbycr hiz standby sci rxd0 pbr: port b read signal pbw: port b write signal res: reset signal n = 18 figure c.8 pb18/cashl0/rxd0 block diagram rev. 1.0, 08/99, page 834 of 875 pbr res pbndr pbw internal data bus cashh0 txd0 single-chip mode pfc pbnmd0 pbnmd1 pbnior sbycr hiz standby pbr: port b read signal pbw: port b write signal res: reset signal n = 19 figure c.9 pb19/cashh0/txd0 block diagram rev. 1.0, 08/99, page 835 of 875 pbr res pbndr pbw internal data bus cashl1 tend1 single-chip mode pfc pbnmd0 pbnmd1 pbnior sbycr hiz sci rxd1 standby pbr: port b read signal pbw: port b write signal res: reset signal n = 22 figure c.10 pb22/cashl1/rxd1/tend1 block diagram rev. 1.0, 08/99, page 836 of 875 pbr res pbw internal data bus txd1 single-chip mode pfc pbnmd0 pbnmd1 pbnior sbycr hiz standby pbndr pbr: port b read signal pbw: port b write signal res: reset signal n = 23 figure c.11 pb23/cashh1/txd1/tend0 block diagram rev. 1.0, 08/99, page 837 of 875 pcr res pcndr pcw an on-chip flash memory internal data bus an single-chip mode pfc pcnmd pcnior sbycr hiz standby mode 2/3/4 mode 1 bus released writer mode pcr: port c read signal pcw: port c write signal res: reset signal n = 0 to 13 figure c.12 pcn/an block diagram (for f-ztat) rev. 1.0, 08/99, page 838 of 875 pcr res pcw pcndr internal data bus an single-chip mode pfc pcnmd pcnior sbycr hiz standby pcr: port c read signal pcw: port c write signal res: reset signal n = 0 to 13 bus released mode 2/3/4 mode 1 figure c.13 pcn/an block diagram (for mask) rev. 1.0, 08/99, page 839 of 875 pcr res pcndr pcw internal data bus an on-chip flash memory an tioc3c/ 3d/3a/3b single-chip mode pfc pcnmd0 pcnmd1 pcnior sbycr hiz tpu tioc3c/ 3d/3a/3b standby mode 2/3/4 bus released writer mode pcr: port c read signal pcw: port c write signal res: reset signal n = 14 to 17 figure c.14 pc14/a14/tioc3c, pc15/a15/tioc3d, pc16/a16/tioc3a, pc17/a17/tioc3b block diagram (for f-ztat) rev. 1.0, 08/99, page 840 of 875 pcr res pcw pcndr internal data bus an tioc3c/ 3d/3a/3b single-chip mode pfc pcnmd0 pcnmd1 pcnior sbycr hiz tpu tioc3c/ 3d/3a/3b standby mode 2/3/4 bus released pcr: port c read signal pcw: port c write signal res: reset signal n = 14 to 17 figure c.15 pc14/a14/tioc3c, pc15/a15/tioc3d, pc16/a16/tioc3a, pc17/a17/tioc3b block diagram (for mask) rev. 1.0, 08/99, page 841 of 875 pcr res pcw pcndr internal data bus an tioc4a/ 4b/5a/5b single-chip mode pfc pcnmd0 pcnmd1 pcnior sbycr hiz tpu tioc4a/ 4b/5a/5b standby mode 2/3/4 bus released pcr: port c read signal pcw: port c write signal res: reset signal n = 18 to 21 figure c.16 pc18/a18/tioc4a, pc19/a19/tioc4b, pc20/a20/tioc5a, pc21/a21/tioc5b block diagram rev. 1.0, 08/99, page 842 of 875 pcr res pcw pcndr internal data bus an tioc1a/ 1b/3a/3b single-chip mode pfc pcnmd0 pcnmd1 pcnior sbycr hiz tpu tioc1a/ 1b/3a/3b tclka/b/c/d standby mode 2/3/4 bus released pcr: port c read signal pcw: port c write signal res: reset signal n = 22 to 25 figure c.17 pc22/a22/tioc1a/tclka, pc23/a23/tioc1b/tclkb, pc24/a24/tioc3a/tclkc, pc25/a25/tioc3b/tclkd block diagram rev. 1.0, 08/99, page 843 of 875 pdr res pdndr pdw internal data bus dn on-chip flash memory dn single-chip mode pfc pdnmd pdnior sbycr hiz standby din mode 2/3/4 mode 1 bus released writer mode dout pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 0 to 7 figure c.18 pdn/dn block diagram (for f-ztat) rev. 1.0, 08/99, page 844 of 875 pdr res pdndr pdw internal data bus dn dout single-chip mode pfc pdnmd pdnior sbycr hiz standby din mode 2/3/4 mode 1 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 0 to 7 figure c.19 pdn/dn block diagram (for mask) rev. 1.0, 08/99, page 845 of 875 pdr res pdndr pdw , , on-chip flash memory writer mode internal data bus dout dn tioc1a, tioc1b, tioc2a single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz tpu tioc1a, tioc1b, tioc2a standby din mode 2/3 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 8 to 10 figure c.20 pd8/d8/tioc1a, pd9/d9/tioc1b, pd10/d10/tioc2a block diagram (for f-ztat) rev. 1.0, 08/99, page 846 of 875 pdr res pdndr pdw internal data bus dn tioc1a, tioc1b, tioc2a single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz tpu tioc1a, tioc1b, tioc2a standby din dout bus released mode 2/3 pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 8 to 10 figure c.21 pd8/d8/tioc1a, pd9/d9/tioc1b, pd10/d10/tioc2a block diagram (for mask) rev. 1.0, 08/99, page 847 of 875 pdr res pdndr pdw dout internal data bus dn tioc2b, tioc4a, tioc4b, tioc5a, tioc5b tioc2b, tioc4a, tioc4b, tioc5a, tioc5b single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz tpu standby din mode 2/3 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 11 to 15 figure c.22 pd11/d11/tioc2b, pd12/d12/tioc4a, pd13/d13/tioc4b, pd14/d14/tioc5a, pd15/d15/tioc5b block diagram rev. 1.0, 08/99, page 848 of 875 pdr res pdndr pdw dout internal data bus dn poe0 single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz mmt standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 16 figure c.23 pd16/d16/poe0 block diagram rev. 1.0, 08/99, page 849 of 875 pdr res pdndr pdw internal data bus dout dn single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz mmt poe1 ad0/1 adtrg standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 17 figure c.24 pd17/d17/poe1/adtrg block diagram rev. 1.0, 08/99, page 850 of 875 pdr res pdndr pdw internal data bus dout dn single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz mmt poe2, poe3 intc irq4, irq5 standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 18, 19 figure c.25 pd18/d18/poe2/irq4, pd19/d19/poe3/irq5 block diagram rev. 1.0, 08/99, page 851 of 875 pdr res pdndr pdw dout internal data bus dn puoa, pvoa irqm single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz intc standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 20, 21 m = 6, 7 figure c.26 pd20/d20/puoa/irq6, pd21/d21/pvoa/irq7 block diagram rev. 1.0, 08/99, page 852 of 875 pdr res pdndr pdw dout internal data bus dn pwoa sck0 sck0 single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz sci standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 22 figure c.27 pd22/d22/pwoa/sck0 block diagram rev. 1.0, 08/99, page 853 of 875 pdr res pdndr pdw internal data bus dout dn pco sck1 single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz mmt pci sci sck1 standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 23 figure c.28 pd23/d23/pco/pci/sck1 block diagram rev. 1.0, 08/99, page 854 of 875 pdr res pdndr pdw dout internal data bus dn puob, pvob, pwob single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 24 to 26 figure c.29 pd24/d24/puob, pd25/d25/pvob, pd26/d26/pwob block diagram rev. 1.0, 08/99, page 855 of 875 pdr res pdndr pdw internal data bus dout dn tioc3c/3d single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz tpu tclka, tclkb tioc3c, tioc3d standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 27, 28 figure c.30 pd27/d27/tclka/tioc3c, pd28/d28/tclkb/tioc3d block diagram rev. 1.0, 08/99, page 856 of 875 pdr res pdndr pdw internal data bus dout dn sck2 tioc4a single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz sci sck2 tpu tioc4a standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 29 figure c.31 pd29/d29/sck2/tioc4a block diagram rev. 1.0, 08/99, page 857 of 875 pdr res pdndr pdw dout internal data bus dn txd2 tioc4b tioc4b single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz tpu standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 30 figure c.32 pd30/d30/txd2/tioc4b block diagram rev. 1.0, 08/99, page 858 of 875 pdr res pdndr pdw internal data bus dout dn tioc5a single-chip mode pfc pdnmd0 pdnmd1 pdnior sbycr hiz sci tpu rxd2 tioc5a standby din mode 2 bus released pdr: port d read signal pdw: port d write signal res: reset signal dout: data bus output timing signal din: data bus input timing signal n = 31 figure c.33 pd31/d31/rxd2/tioc5a block diagram rev. 1.0, 08/99, page 859 of 875 per res pendr pew internal data bus pfc penmd penior sbycr hiz intc irqm standby per: port e read signal pew: port e write signal res: reset signal n = 12 to 15 m = 4 to 7 figure c.34 pen/irqm block diagram rev. 1.0, 08/99, page 860 of 875 per res pendr pew internal data bus sck1 ah single-chip mode pfc penmd0 penmd1 penior sbycr hiz sci intc sck1 irq0 standby per: port e read signal pew: port e write signal res: reset signal n = 16 figure c.35 pe16/irq0/sck1/ah block diagram rev. 1.0, 08/99, page 861 of 875 per res pendr pew internal data bus puoa sck0 pfc penmd0 penmd1 penior sbycr hiz sci intc sck0 irq1 standby per: port e read signal pew: port e write signal res: reset signal n = 17 figure c.36 pe17/irq1/puoa/sck0 block diagram rev. 1.0, 08/99, page 862 of 875 per res pendr pew internal data bus pvoa, pwoa, puob, pvob, pwob irqm pfc penmd0 penmd1 penior sbycr hiz intc standby per: port e read signal pew: port e write signal res: reset signal n = 18, 19, or 21 to 23 m = 2, 3, or 5 to 7 figure c.37 pe18/irq2/pvoa, pe19/irq3/pwoa, pe21/irq5/puob, pe22/irq6/pvob, pe23/irq7/pwob block diagram rev. 1.0, 08/99, page 863 of 875 per res pendr pew internal data bus pco pfc penmd0 penmd1 penior sbycr hiz mmt intc pci irq4 standby per: port e read signal pew: port e write signal res: reset signal n = 20 figure c.38 pe20/irq4/pco/pci block diagram rev. 1.0, 08/99, page 864 of 875 pfr res pfndr pfw internal data bus , tioc0b, tioc0c tioc0b, tioc0c single-chip mode pfc pfnmd0 pfnmd1 pfnior sbycr hiz tpu standby pfr: port f read signal pfw: port f write signal res: reset signal n = 1, 2 figure c.39 pf1/dack0/tioc0b, pf2/drak0/tioc0c block diagram rev. 1.0, 08/99, page 865 of 875 pfr res pfndr pfw internal data bus single-chip mode tioc0a pfc pfnmd0 pfnmd1 pfnior sbycr hiz tpu dmac tioc0a dreq0 standby pfr: port f read signal pfw: port f write signal res: reset signal n = 3 figure c.40 pf3/dreq0/tioc0a block diagram rev. 1.0, 08/99, page 866 of 875 pfr res pfndr pfw internal data bus single-chip mode dack1 tioc2b pfc pfnmd0 pfnmd1 pfnior sbycr hiz tpu sci tioc2b rxd1 standby pfr: port f read signal pfw: port f write signal res: reset signal n = 5 figure c.41 pf5/dack1/rxd1/tioc2b block diagram rev. 1.0, 08/99, page 867 of 875 pfr res pfndr pfw internal data bus drak1 txd1 tioc2a tioc2a single-chip mode pfc pfnmd0 pfnmd1 pfnior sbycr hiz tpu standby pfr: port f read signal pfw: port f write signal res: reset signal n = 6 figure c.42 pf6/drak1/txd1/tioc2a block diagram rev. 1.0, 08/99, page 868 of 875 pfr res pfndr pfw internal data bus single-chip mode irqout tioc0d pfc pfnmd0 pfnmd1 pfnior sbycr hiz tpu dmac tioc0d dreq1 standby pfr: port f read signal pfw: port f write signal res: reset signal n = 7 figure c.43 pf7/dreq1/irqout/tioc0d block diagram rev. 1.0, 08/99, page 869 of 875 pgr res pgndr pgw internal data bus sck2 sck2 pfc pgnmd0 pgnior sbycr hiz sci standby pgr: port g read signal pgw: port g write signal res: reset signal n = 29 figure c.44 pg29/sck2 block diagram rev. 1.0, 08/99, page 870 of 875 pgr res pgndr pgw internal data bus txd2 pfc pgnmd0 pgnior sbycr hiz standby pgr: port g read signal pgw: port g write signal res: reset signal n = 30 figure c.45 pg30/txd2 block diagram rev. 1.0, 08/99, page 871 of 875 pgr res pgndr pgw internal data bus pfc pgnmd pgnior sbycr hiz sci rxd2 standby pgr: port g read signal pgw: port g write signal res: reset signal n = 31 figure c.46 pg31/rxd2 block diagram rev. 1.0, 08/99, page 872 of 875 phr res phndr phw internal data bus pfc phnmd0 phnior sbycr da hiz dacn dan standby phr: port h read signal phw: port h write signal res: reset signal n = 0, 1 figure c.47 phn/dan block diagram rev. 1.0, 08/99, page 873 of 875 internal data bus standby idle sbycr hiz ad0/1 ann pir: port i read signal n = 0 to 7 pir figure c.48 pin/ann block diagram rev. 1.0, 08/99, page 874 of 875 appendix d package dimensions figure d.1 shows the sh7065 package dimensions (fp-176). hitachi code jedec eiaj weight (reference value) fp-176 conforms 1.9 g unit: mm *dimension including the plating thickness base material dimension 26.0 0.2 24 0.10 133 176 45 88 132 89 144 0.10 m 0.5 26.0 0.2 1.70 max 1.40 *0.17 0.05 0 ? C 8 ? 1.0 0.5 0.1 0.10 0.05 *0.22 0.05 1.25 0.20 0.04 0.15 0.04 figure d.1 package dimensions (fp-176) rev. 1.0, 08/99, page 875 of 875 appendix e product lineup table e.1 sh7065 series product lineup product type model model marking package mask rom version hd6437065s hd6437065s(***)f 176-pin qfp (fp-176) sh7065 f-ztat version hd64f7065s hf64f7065sf60 176-pin qfp (fp-176) note: (***) is the rom code. sh7065 hardware manual publication date: 1st edition, august 1999 published by: electronic devices sales & marketing group semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group ul media co., ltd. copyright ? hitachi, ltd., 1999. all rights reserved. printed in japan. |
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