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products and specifications discussed herein ar e subject to change by micron without notice. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm features pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 1 ?2003 micron technology, inc. all rights reserved. synchronous dram module mt36lsdf6472 ? 512mb mt36lsdf12872 ? 1gb for the latest data sheet, refer to micron?s web site: www.micron.com/modules features ? 168-pin, dual in-line memory module (dimm) ? pc133-compliant ? registered inputs with one-clock delay ? phase-lock loop (pll) clock driver to reduce loading ? utilizes 133 mhz sdram components ? supports ecc error detection and correction ? 512mb (64 meg x 72) and 1gb (128 meg x 72) ? single +3.3v power supply ? fully synchronous; all signals registered on positive edge of pll clock ? internal pipelined operat ion; column address can be changed every clock cycle ? internal sdram banks for hiding row access/ precharge ? programmable burst lengths: 1, 2, 4, 8, or full page ? auto precharge, includes concurrent auto precharge ?auto refresh mode ? self refresh mode: 64ms, 4,096-cycle refresh (512mb) or 8,192-cycle refresh (1gb) ? lvttl-compatible inputs and outputs ? serial presence-detect (spd) ? gold edge contacts table 1: timing parameters cl = cas (read) latency module marking clock frequency access time setup time hold time cl = 2 cl = 3 -13e 133 mhz 5.4ns ? 1.5 0.8 -133 133 mhz ? 5.4ns 1.5 0.8 figure 1: 168-pin dimm (mo-161) notes:1. contact micron for product availability. 2. registered mode adds one clock cycle to cl. 3. available on the 1gb device only. options marking ?package 168-pin dimm (standard) g 168-pin dimm (lead-free) 1 y ? standard or low-profile pcb see note on page 2 ?frequency/cas latency 2 133 mhz/cl = 2 3 -13e 133 mhz/cl = 3 -133 ? pcb height standard 1.70in. (43.18mm) see page 2 note hei g ht s tan d ar d 1.70in. (43.18mm) table 2: address table parameter 512mb 1gb refresh count 4k 8k device banks 4 (ba0, ba1) 4 (ba0, ba1) device configuration 128mb (32 meg x 4) 256mb (64 meg x 4) row addressing 4k (a0?a11) 8k (a0?a12) column addressing 2k (a0?a9, a11) 2k (a0?a9, a11) module ranks 2 (s0#, s2#; s1#, s3#) 2 (s0#, s2#; s1#, s3#)
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 2 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm features note: the designators for component and pcb revi sion are the last two ch aracters of each part number. consult factory for current revisi on codes. example: MT36LSDF12872G-133D1 . table 3: part numbers part number module density configuration system bus speed mt36lsdf6472g-133__ 512mb 64 meg x 72 133 mhz mt36lsdf6472y-133__ 512mb 64 meg x 72 133 mhz mt36lsdf12872g-13e__ 1gb 128 meg x 72 133 mhz mt36lsdf12872y-13e__ 1gb 128 meg x 72 133 mhz mt36lsdf12872g-133__ 1gb 128 meg x 72 133 mhz mt36lsdf12872y-133__ 1gb 128 meg x 72 133 mhz
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 3 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm pin assignments and descriptions pin assignments and descriptions notes: 1. pin 126 is nc for 512mb, a12 for 1gb. figure 2: 168-pin dimm pin locations table 4: pin assignment 168-pin dimm front 168-pin dimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1v ss 22 cb1 43 v ss 64 v ss 85 v ss 106 cb5 127 v ss 148 v ss 2dq0 23 v ss 44 nc 65 dq21 86 dq32 107 v ss 128 cke0 149 dq53 3dq1 24 nc 45 s2# 66 dq22 87 dq33 108 nc 129 s3# 150 dq54 4dq2 25 nc 46 dqmb2 67 dq23 88 dq34 109 nc 130 dqmb6 151 dq55 5dq3 26 v dd 47 dqmb3 68 v ss 89 dq35 110 v dd 131 dqmb7 152 v ss 6v dd 27 we# 48 nc 69 dq24 90 v dd 111cas#132 nc 153 dq56 7dq4 28 dqmb0 49 v dd 70 dq25 91 dq36 112 dqmb4 133 v dd 154 dq57 8dq5 29 dqmb1 50 nc 71 dq26 92 dq37 113 dqmb5 134 nc 155 dq58 9dq6 30 s0# 51 nc 72 dq27 93 dq38 114 s1# 135 nc 156 dq59 10 dq7 31 nc 52 cb2 73 v dd 94 dq39 115 ras# 136 cb6 157 v dd 11 dq8 32 v ss 53 cb3 74 dq28 95 dq40 116 v ss 137 cb7 158 dq60 12 v ss 33 a0 54 v ss 75 dq29 96 v ss 117 a1 138 v ss 159 dq61 13 dq9 34 a2 55 dq16 76 dq30 97 dq41 118 a3 139dq48160dq62 14 dq10 35 a4 56 dq17 77 dq31 98 dq42 119 a5 140dq49161dq63 15 dq11 36 a6 57 dq18 78 v ss 99 dq43 120 a7 141 dq50 162 v ss 16 dq12 37 a8 58 dq19 79 ck2 100 dq44 121 a9 142 dq51 163 ck3 17 dq13 38 a10 59 v dd 80 nc 101 dq45 122 ba0 143 v dd 164 nc 18 v dd 39 ba1 60 dq20 81 nc 102 v dd 123 a11 144 dq52 165 sa0 19 dq14 40 v dd 61 nc 82 sda 103 dq46 124 v dd 145 nc 166 sa1 20 dq15 41 v dd 62 nc 83 scl 104 dq47 125 ck1 146 nc 167 sa2 21 cb0 42 ck0 63 nc 84 v dd 105 cb4 126 nc/ a12 1 147 rege 168 v dd u1 u2 u3 u4 u5 u 6 u7 u8 u9 u10 u11 u12 u13 u14 u39 u37 u38 u15 u1 6 u17 u18 u28 u27 u2 6 u25 u24 u23 u22 u21 u20 u19 u3 6 u35 u34 u33 u40 u32 u31 u30 u29 u42 in d i c ates a v dd or v dd q pin in d i c ates a v ss pin pin 1 pin 41 pin 84 pin 85 pin125 pin 1 6 8 front view ba c k view
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 4 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm pin assignments and descriptions table 5: pin descriptions pin numbers may not correl ate with symbol order; refer to pin assignment table on page 3 for more information pin number symbol type description 27, 111, 115 ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. 42, 79, 125, 163 ck0?ck3 input clock: ck0 is distributed through an on-board pll to all devices. ck1?ck3 are terminated. 128 cke0?1 input clock enable: cke activates (high) and deactivates (low) the ck0 signal. deactivati ng the clock provid es power-down and self refresh operatio ns (all device banks idle) or clock suspend operation (burst ac cess in progress). cke is synchronous except after the devi ce enters power-down and self refresh modes, where cke beco mes asynchronous until after exiting the same mode . the input buffers, including ck, are disabled during power-down and self refresh modes, providing low standby power. 30, 45, 114, 129 s0#?s3# input chip select: s# enable (registe red low) and disable (registered high) the command decoder. al l commands are masked when s# are registered high. s# are considered part of the command code. 28, 29, 46, 47, 112, 113, 130, 131 dqmb0? dqmb7 input input/output mask: dqmb is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when dqmb is sampled high during a read cycle. 39, 122 ba0, ba1 input bank address: ba0 and ba1 defi ne to which device bank the active, read, write, or precharge command is being applied. 33-38, 117-121, 123, 126 (1gb) a0?a11 (512mb) a0?a12 (1gb) input address inputs: provide the row address for active commands, and the column address and auto precharge bit (a10) for read/ write commands, to select one location out of the memory array in the respective device bank. a10 sampled during a precharge command determine s whether the precharge applies to one device bank (a10 low, device bank selected by ba0, ba1) or all device bank s (a10 high). the address inputs also provide the op-code du ring a mode register set command. 83 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfe r to and from the module. 165-167 sa0?sa2 input presence-detect address inputs: th ese pins are used to configure the presence-detect device. 147 rege input register enable: rege permi ts the dimm to operate in ?buffered? mode (low) or ?registered? mode (high). 2?5, 7?11, 13?17, 19?20, 55?58, 60, 65?67, 69?72, 74?77, 86?89, 91?95, 97? 101, 103?104, 139?142, 144, 149?151, 153?156, 158?161 dq0?dq63 input/ output data i/os: data bus. 21, 22, 52, 53, 105, 106, 136, 137 cb0?cb7 input/ output check bits.
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 5 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm functional block diagram functional block diagram per industry standard, micron modules utilize various component speed grades, as ref- erenced in the module part number guide at www.micron.com/numberguide . standard modules use the following sd ram devices: mt48lc32m4a2fb (512mb); mt48lc64m4a2fb (1gb). lead-free module s use the following sdram devices: mt48lc32m4a2bb (512mb); mt48lc64m4a2bb (1gb). 82 sda input/ output serial presence-detect data: sda is a bidirectional pin used to transfer addresses and data into and data out of the presence- detect portion of the module. 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 v dd supply power supply: +3.3v 0.3v. 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 v ss supply ground. 24, 25, 31, 44, 48, 50, 51 61 ? 63, 80, 81, 108, 109, 126 (512mb), 132, 134, 135, 145, 146, 164 nc ? not connected: listed pins are not connecte d on these modules. table 5: pin descriptions (continued) pin numbers may not correl ate with symbol order; refer to pin assignment table on page 3 for more information pin number symbol type description
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 6 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm functional block diagram figure 3: functional block diagram note: all resistor values are 10 unless otherwise specified. a0 sa0 spd scl sda a1 sa1 a2 sa2 rs1# v dd v ss sdrams sdrams 12pf ck1?ck3 pll sdram x 4 sdram x 4 sdram x 4 sdram x 4 sdram x 4 sdram x 4 sdram x 4 sdram x 4 sdram x 4 register x 3 ck0 12pf dqm cs# u11 dq dq dq dq dq0 dq1 dq2 dq3 rdqmb0 dqm cs# u29 dq dq dq dq dqm cs# u12 dq dq dq dq dq4 dq5 dq6 dq7 dqm cs# u30 dq dq dq dq dqm cs# u13 dq dq dq dq dq8 dq9 dq10 dq11 rdqmb1 dqm cs# u31 dq dq dq dq dqm cs# u5 dq dq dq dq cb0 cb1 cb2 cb3 dqm cs# u23 dq dq dq dq rs3# rdqmb6 dqm cs# u15 dq dq dq dq dq16 dq17 dq18 dq19 rdqmb2 dqm cs# u7 dq dq dq dq dq48 dq49 dq50 dq51 dqm cs# u16 dq dq dq dq dq20 dq21 dq22 dq23 dqm cs# u8 dq dq dq dq dq52 dq53 dq54 dq55 rdqmb7 dqm cs# u17 dq dq dq dq dq24 dq25 dq26 dq27 rdqmb3 dqm cs# u9 dq dq dq dq dq56 dq57 dq58 dq59 dqm cs# u18 dq dq dq dq dq28 dq29 dq30 dq31 dqm cs# u10 dq dq dq dq dq60 dq61 dq62 dq63 ras# cas# we# cke0 cke1 a0?a11 (512mb) a0?a12 (1gb) ba0 ba1 s0#?s3# dqmb0?dqmb7 rras#: sdrams rcas#: sdrams rwe#: sdrams rcke0: sdrams fa rcke1: sdrams fa ra0?ra11fa: sdrams ra0?ra12: sdrams rba0: sdrams rba1: sdrams rs0#?rs3# rdqmb0?rdqmb7 v dd rege 10k wp dqm cs# u14 dq dq dq dq dq12 dq13 dq14 dq15 dqm cs# u32 dq dq dq dq dqm cs# u1 dq dq dq dq dq32 dq33 dq34 dq35 rdqmb4 dqm cs# u19 dq dq dq dq dqm cs# u2 dq dq dq dq dq36 dq37 dq38 dq39 dqm cs# u20 dq dq dq dq dqm cs# u3 dq dq dq dq dq40 dq41 dq42 dq43 rdqmb5 dqm cs# u21 dq dq dq dq dqm u6 dq dq dq dq cb4 cb5 cb6 cb7 dqm u24 dq dq dq dq dqm cs# u4 dq dq dq dq dq44 dq45 dq46 dq47 dqm cs# u22 dq dq dq dq rs0# dqm cs# u33 dq dq dq dq dqm cs# u34 dq dq dq dq dqm cs# u35 dq dq dq dq dqm cs# u36 dq dq dq dq dqm cs# u25 dq dq dq dq dqm cs# u26 dq dq dq dq dqm cs# u27 dq dq dq dq dqm cs# u28 dq dq dq dq rs2# r e g i s t e r s u39 u41 u42 u37, u38, u40 cs# cs# pll clk cke0
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 7 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm general description general description the mt36lsdf6472 and mt36lsdf12872 are high-speed cmos, dynamic random- access, 512mb and 1gb memory modules or ganized in x72 (ecc) configurations. sdram modules use internally configured quad-bank sdram devices with a synchro- nous interface (all signals are registered on the positive edge of clock signal ck). read and write accesses to sdram module s are burst oriented; accesses start at a selected location and continue for a prog rammed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the devi ce bank and row to be accessed (ba0, ba1 select the device bank; a0?a11 [512mb] or a0?a12 [1gb], select the device row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. sdram modules provide for programmable read or write bl of 1, 2, 4, or 8 locations, or full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. sdram modules use an internal pipelined architecture to achieve high-speed opera- tion. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, ran- dom-access operation. sdram modules are designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a powe r-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic column- address generation, the ability to interleave between device banks in order to hide pre- charge time, and the capability to randomly change column addresses on each clock cycle during a burst access. for more inform ation regarding sdram operation, refer to the 128mb or 256mb sdram component data sheets. prior to normal operation, the sdram must be initialized. the following sections pro- vide detailed information covering device initialization, register definition, command descriptions and device operation. pll and register operation these modules can be operated in either re gistered mode (rege pin high), where the control/address input signals are latched in the register on one rising clock edge and sent to the sdram devices on the following rising clock edge (data access is delayed by one clock), or in buffered mode (rege pin low) where the input signals pass through the register/buffer to the sdram devices on the same clock. a phase-lock loop (pll) on the modules is used to redrive the clock to the sdram devices to minimize system clock loading. (ck0 is connected to the pll, and ck1, ck2, and ck3 are terminated.) serial presence-detect operation these modules incorporate serial presence-d etect (spd). the spd function is imple- mented using a 2,048-bit eeprom. this nonvol atile storage de vice contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and vari- ous sdram organizations and timing parameters. the remaining 128 bytes of storage
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 8 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm initialization are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard i 2 c bus using the dimm?s scl (clock) and sda (dat a) signals, together with sa (2:0), which provide eight unique dimm/eeprom addresses. wr ite protect (wp) is tied to ground on the module, permanently disabling hardware write protect. initialization sdrams must be powered up and initialized in a predefined manner. operational pro- cedures other than those specified may result in undefined operation. once power is applied to v dd and v dd q (simultaneously) and the cloc k is stable (stable clock is defined as a signal cycling wi thin timing constraints specified for the clock pin), the sdram requires a 100s delay prior to is suing any command other than a command inhibit or nop. starting at some point during this 100s period and continuing at least through the end of this period, comman d inhibit or nop commands should be applied. once the 100s delay has been satisfied wi th at least one command inhibit or nop command having been applied, a precharge command should be applied. all device banks must then be precharged, thereby placing the device in the all device banks idle state. once in the idle state, two auto refresh cy cles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register programming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. mode register definition the mode register is used to define the spec ific mode of operation of the sdram. this definition includes the selection of bl, a bu rst type, cl, an operating mode, and a write burst mode, as shown in figure 4 on page 9. the mode register is programmed via the load mode register command and will retain the stored information until it is pro- grammed again or the device loses power. mode register bits m0?m2 specify bl, m3 specifies the type of burst (sequential or inter- leaved), m4?m6 specify cl, m7 and m8 spec ify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. address a12 (m12) is undefined but should be driven low during loading of the mode register. the mode register must be loaded when all device banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating either of these requirements will resu lt in unspecified operation. burst length read and write accesses to the sdram are burst oriented, with bl being programmable, as shown in figure 4. bl determines the ma ximum number of column locations that can be accessed for a given read or write comma nd. bl of 1, 2, 4, or 8 locations are avail- able for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate command to generate arbitrary bl. reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to bl is effectively selected. all accesses for that burst take pl ace within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in table 6 on page 10. the
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 9 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm mode register definition block is uniquely selected by a1?a9, a11 wh en bl = 2; a2?a9, a11 when bl = 4; and by a3?a9, a11 when bl = 8. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached, as shown in table 6 on page 10. figure 4: mode register definition diagram burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 op mode a10 a11 10 11 reserved wb 512mb module address bus m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 ? 0 ? defined ? 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 op mode a10 a11 10 11 reserved wb 0 1 write burst mode programmed burst length single location access m9 program m12, m11, m10 = ?0, 0, 0? to ensure compatibility with future devices. program m11, m10 = ?0, 0, 0? to ensure compatibility with future devices. a12 12 1gb module address bus
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 10 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm mode register definition notes: 1. for full-page accesses: y = 2,048. 2. for bl = 2, a0?a9, a11 will select the bloc k of two burst; a0 sele cts the starting column within the block. 3. for bl = 4, a0?a9, a11 will select the block of four burst; a0?a1 select the starting column within the block. 4. for bl = 8, a0?a9, a11 will select the block of eight burst; a0?a2 select the starting col- umn within the block. 5. for a full-page burst, the full row is selected and i will select the starting column. 6. whenever a boundary of the block is reache d within a given sequence above, the follow- ing access wraps within the block. 7. for bl = 1, a0?a9, a11 will select the unique column to be accessed, and mode register bit m3 is ignored. table 6: burst definition table bl starting column address order of accesses within a burst type = sequential type = interleaved 2 a0 00-1 0-1 11-0 1-0 4 a1 a0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full page (y) n = a0?a9, a11 (location 0-y) cn, cn+1, cn+2, cn+3, cn+4..., ...cn-1, cn... not supported
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 11 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm mode register definition figure 5: cas latency diagram burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses with in a burst is determined by bl, the burst type, and the starting column address, as shown in table 6 on page 10. cas latency cl is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to two or three clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dq will start driving as a result of the clock edge one cycle earlier ( n + m - 1), and provided that the re levant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0 and the latency is programmed to two clocks, the dq will start driving after t1 and the data will be valid by t2, as shown in figure 5. table 7 on page 12 indicates the operating frequencies at which each cl setting can be used. reserved states should not be used as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by se tting m7 and m8 to zero; the other combi- nations of values for m7 and m8 are reserved for future use and/or test modes. the pro- grammed bl applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. clk dq t2 t1 t3 t0 cl = 3 lz d out t oh t command nop read t ac nop t4 nop don?t care undefined clk dq t2 t1 t3 t0 cl = 2 lz d out t oh t command nop read t ac nop
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 12 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm commands write burst mode when m9 = 0, bl programmed via m0?m2 applies to both read and write bursts; when m9 = 1, the programmed bl applies to read bursts, but write accesses are single- location (nonburst) accesses. commands table 8, provides a quick reference of availabl e commands. this is followed by a written description of each command. for a more de tailed description of commands and opera- tions, refer to 128mb or 256mb sdram component data sheet. notes: 1. a0?a12 provide device row address. ba0, ba1 determine which device bank is made active. 2. a0?a9, a11 provide device column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which device bank is being read from or written to. 3. a10 low: ba0, ba1 determine which device bank is being precharged. a10 high: both device banks are precharged and ba0, ba1 are ?don?t care.? 4. this command is auto refresh if cke is high, self refresh if cke is low. 5. internal refresh counter controls row addr essing; all inputs and i/os are ?don?t care? except for cke. 6. a0?a11 (512mb) or a0?a12 (1gb) define the op-code written to the mode register, and should be driven low. 7. activates or deactivates the dqs during wri tes (zero-clock delay) and reads (two-clock delay). table 7: cas latency table input register adds one cl ock in registered mode speed allowable operating clock frequency (mhz) cl = 2 cl = 3 -13e 133 143 -133 100 133 table 8: sdram command and dqmb operation truth table cke is high for all commands shown except self refresh name (function) cs# ras# cas# we# dqmb addr dq notes command inhibit (nop) hxxx x x x no operation (nop) l hhh x x x active (select bank and activate row) l l h h x bank/row x 1 read (select bank and column, and start read burst) lhlhl/h 7 bank/col x 2 write (select bank and colu mn, and start write burst) l h l l l/h 7 bank/col valid 2 burst terminate lhhl x xactive precharge (deactivate row in bank or banks) llhl x code x 3 auto refresh or self refresh (enter self refresh mode) lllh x x x4, 5 load mode register llll xop-codex 6 write enable/output enable ???? l ?active7 write inhibit/output high-z ???? h ?high-z7
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 13 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm electrical specifications electrical specifications stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. table 9: absolute maximum ratings parameter min max units voltage on v dd supply relative to vss -1 +4.6 v voltage on inputs, nc or i/o pins relative to vss -1 +4.6 v operating temperature t opr (commercial - ambient) 0 +65 c storage temperature t stg (plastic) -55 +150 c table 10: dc electrical characteristics and operating conditions notes: 1, 5, 6; notes ap pear on pages 17 and 18; v dd = v dd q = +3.3v 0.3v parameter/condition symbol min max units notes supply voltage v dd , v dd q3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v22 input low voltage: logic 0; all inputs v il -0.3 0.8 v 22 input leakage current: any input: 0v v in v dd (all other pins not under test = 0v) command and address, cke, s# i i -10 10 a 33 dqmb -5 5 output leakage current: dqs are disabled; 0v v in v dd dq i oz -10 10 a 33 output levels: output high voltage (i out = -4ma) v oh 2.4 ? v output low voltage (i out = 4ma) v ol ?0.4v
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 14 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm electrical specifications table 11: i dd specifications and conditions ? 512mb sdram components only; notes: 1, 5, 6, 11, 13; notes appear on pages 17 and 18; v dd = v dd q = +3.3v 0.3v parameter/condition symbol max units notes -133 operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 a 2,736 ma 3, 18, 19, 30 standby current: power-down mode; all device banks idle; cke = low i dd 2 b 72 ma 30 standby current: active mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 a 936 ma 3, 12, 19, 30 operating current: burst mode; continuous burst; read or write; all device banks active i dd 4 a 2,736 ma 3, 18, 19, 30 auto refresh current cs# = high; cke = high t rfc = t rfc (min) i dd 5 b 11,160 ma 3, 12, 18, 19, 30, 31 t rfc = 15.625s i dd 6 b 108 ma self refresh current: cke 0.2v i dd 7 b 72 ma 4 note: a - value calculated as one module rank in this operating condition, and all other module ranks in power-down (i dd 2) mode. b - value calculated reflects all module ranks in this operating condition. table 12: i dd specifications an d conditions ? 1gb sdram components only; notes: 1, 5, 6, 11, 13; notes appear on pages 17 and 18; v dd = v dd q = +3.3v 0.3v parameter/condition symbol max units notes -13e -133 operating current: active mode; burst = 2; read or write; t rc = t rc (min) i dd 1 a 2,466 2,286 ma 3, 18, 19, 30 standby current: power-down mode; all device banks idle; cke = low i dd 2 b 72 72 ma 30 standby current: aactive mode; cke = high; cs# = high; all device banks active after t rcd met; no accesses in progress i dd 3 a 756 756 ma 3, 12, 19, 30 operating current: burst mode; cont inuous burst; read or write; all device banks active i dd 4 a 2,466 2,466 ma 3, 18, 19, 30 auto refresh current cs# = high; cke = high t rfc = t rfc (min) i dd 5 b 10,260 9,720 ma 3, 12, 18, 19, 30, 31 t rfc = 7.8125s i dd 6 b 126 126 ma self refresh current: cke 0.2v i dd 7 b 90 90 ma 4 note: a - value calculated as one module rank in this operating condition, and all other module ranks in power-down (i dd 2) mode. b - value calculated reflects all module ranks in this operating condition. table 13: capacitance note: 2; notes begin on page 17 parameter symbol min typ max units input capacitance: ad dress and command, s# c i 1 ?10 pf input capacitance: cke c i 1 a ?20 pf input capacitance: ck0 c i 2 ?17?pf input capacitance: ck1?ck3 c i 3 ?12?pf input capacitance: dqmb c i 4 6?22.8pf input/output capacitance: dq c io 6?12pf
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 15 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm electrical specifications table 14: sdram component electrical charact eristics and recommended ac operating conditions notes: 5, 6, 8, 9, 11, 32; notes appear on pages 17 and 18 ac characteristics -13e -133 units notes parameter symbol min max min max access time from clk (positive edge) cl = 3 t ac(3) 5.4 5.4 ns 27 cl = 2 t ac(2) 5.4 6 ns address hold time t ah 0.8 0.8 ns address setup time t as 1.5 1.5 ns clk high-level width t ch 2.5 2.5 ns clk low-level width t cl 2.5 2.5 ns clock cycle time cl = 3 t ck(3) 7 7.5 ns 23 cl = 2 t ck(2) 7.5 10 ns 23 cke hold time t ckh 0.8 0.8 ns cke setup time t cks 1.5 1.5 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 ns data-in hold time t dh 0.8 0.8 ns data-in setup time t ds 1.5 1.5 ns data-out high-z time cl = 3 t hz(3) 5.4 5.4 ns 10 cl = 2 t hz(2) 5.4 6 ns 10 data-out low-z time t lz 1 1 ns data-out hold time (load) t oh 3 3 ns data-out hold time (no load) t oh n 1.8 1.8 ns 28 active-to-precharge command t ras 37 120,000 44 120,000 ns 32 active-to-active command period t rc 60 66 ns active-to-read or write delay t rcd 15 20 ns refresh period t ref 64 64 ms auto refresh period t rfc 66 66 ns precharge command period t rp 15 20 ns active bank a to active bank b command t rrd 14 15 ns transition time t t 0.3 1.2 0.3 1.2 ns 7 write recovery time t wr 1 clk + 7ns 1 clk + 7.5ns ns 24 14 15 ns 25 exit self refresh-to-active command t xsr 67 75 ns 20
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 16 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm electrical specifications table 15: ac functional characteristics notes: 5, 6, 7, 8, 9, 11; notes appear on pages 17 and 18 parameter symbol -13e -133 units notes read/write command to read/write command t ccd 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 t ck 14, 32 cke to clock enable or power-down exit setup mode t ped 1 1 t ck 14, 32 dqm to input data delay t dqd 0 0 t ck 17, 32 dqm to data mask during writes t dqm 0 0 t ck 17, 32 dqm to data high-z during reads t dqz 2 2 t ck 17, 32 write command to input data delay t dwd 0 0 t ck 17, 32 data-in to active command t dal 4 5 t ck 15, 21, 32 data-in to precharge command t dpl 2 2 t ck 16, 21, 32 last data-in to burst stop command t bdl 1 1 t ck 17, 32 last data-in to ne w read/write command t cdl 1 1 t ck 17, 32 last data-in to precharge command t rdl 2 2 t ck 16, 21, 32 load mode register command to active or refresh command t mrd 2 2 t ck 26 data-out to high-z from precharge command cl = 3 t roh(3) 3 3 t ck 17, 32 cl = 2 t roh(2) 2 2 t ck 17, 32
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 17 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm notes notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd = v dd q = +3.3v 0.3v; f = 1 mhz, t a = 25c; pin under test biased at 1.4v. 3. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured; (0c t a +70c). 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be pow- ered up simultaneously. vss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh require- ment is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specification, the cl ock and cke must tran- sit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5 v with equivalent load: 10. t hz defines the time at which the output achi eves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd tests have v il = 0v and v ih = 3v, using a measurement reference level of 1.5v. if the input transition time is longer than 1ns, then the timing is mea- sured from v il (max) and v ih (min) and no longer at th e 1.5v midpoint. clk should always be referenced to crossover. refer to micron technical note tn-48-09. 12. other input signals are allowed to transiti on no more than once every two clocks and are otherwise at valid v ih or v il levels. 13. i dd specifications are tested after th e device is properly initialized. 14. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 15. timing actually specified by t wr + t rp; clock(s) specified as a reference only at mini- mum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 18. the i dd current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. address transitions average on e transition every two clocks. 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 7.5ns for -133 and -13e. 22. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 3ns. q 50pf
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 18 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm notes 23. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for th e clock pin) during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 24. auto precharge mode only. the precharge timing budget ( t rp) begins at 7ns for -13e; and 7.5ns for -133 after the first clock de lay, after the last write is executed. 25. precharge mode only. 26. jedec specifies three clocks. 27. t ac for -133/-13e at cl = 3 with no load is 4.6ns and is guaranteed by design. 28. parameter guaranteed by design. 29. for -133, cl = 3 and t ck = 7.5ns; for -13e, cl = 2 and t ck = 7.5ns. 30. cke is high during refresh command period t rfc (min) else cke is low. the i dd 6 limit is actually a nominal value and does not result in a fail value. 31. refer to device data sheet for timing waveforms. 32. the value for t ras used in -13e speed grade modules is calculated from t rc - t rp. 33. this ac timing function will show an extra clock cycle when in registered mode. 34. leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes.
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 19 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm pll and register specifications pll and register specifications notes: 1. ssc = spread spectrum clock. the use of ssc synthesizers on th e system motherboard will reduce emi. 2. skew is defined as the total clock skew be tween any two outputs and is therefore speci- fied as a maximum only. table 16: register timing requirements and switching characteristics register symbol parameter condition 0c t a 65c v dd = +3.3v 0.3v units min max sstl bit pattern by jesd82-2 f clock clock frequency 150 240 mhz t pd1 propagation delay, single rank (ck to output) 50pf to gnd and 50 to v tt 1.4 3.5 ns t pd2 propagation delay, dual rank (ck to output) 30pf to gnd and 50 to v tt 0.7 2.4 ns t w pulse duration ck, high or low 3.3 ? ns t su setup time data before ck high 0.75 ? ns t h hold time data after ck high 0.75 ? ns table 17: pll clock driver timing requirements and switching characteristics parameter symbol 0c t a 65c v dd = +3.3v 0.3v units notes min max operating clock frequency f ck 50 140 mhz input duty cycle t dc 44 55 % cycle to cycle jitter t jit cc -75 75 ps static phase offset t ? -150 150 ps ssc induced skew t ssc ? 150 ps 1, 2 output to output skew t sk o ? 150 ps
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 20 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm pll and register specifications figure 6: component case temperature vs. airflow notes: 1. micron technology, inc. recommends a minimum air flow of 1 meter/second (~197 lfm) across all module s when installed in a system. 2. the component case temperature measurem ents shown above are obtained experimen- tally. the system used for experimental purposes is a dual-processor 600 mhz work station, fully loaded with four mt36lsdt12872g modul es. case temperatures charted represent worst-case component locations on modules installed in the internal slots of the system. 3. temperature versus air speed data is obtain ed by performing experiments with the system motherboard removed from its case and mounted in a eiffel -type low air speed wind tun- nel. peripheral devices installed on the syste m motherboard for testing are the processor(s) and video card, all other periph eral devices are mounted outs ide of the wind tunnel test chamber. 4. the memory diagnosti c software used for determining worst-case component tempera- tures is a memory diag nostic software appl ication developed for in ternal use by micron technology, inc. 20 30 40 50 60 70 80 90 100 0.0 0.5 1.0 2.0 air flow (meters/sec) degrees celsius ambient temperature = 25o c t max - memory stress software t ave - 3d gaming software t ave - memory stress software minimum air flow
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 21 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm serial presence-detect serial presence-detect spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (as shown in figure 7, and figure 8 on page 22). spd start condition all commands are preceded by the start cond ition, which is a hi gh-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not re spond to any command until this condition has been met. spd stop condition all communications are terminated by a stop condition, which is a low-to-high tran- sition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting 8 bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the 8 bits of data (as shown in figure 9 on page 22). the spd device will always respond with an acknowledge after recognition of a start condition and its slave address. if both th e device and a write operation have been selected, the spd device will respond with an acknowledge after the receipt of each sub- sequent 8-bit word. in the read mode the spd de vice will transmit 8 bits of data, release the sda line and monitor the line for an ackn owledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave wi ll terminate further data transmissions and await the stop condition to return to standby power mode. figure 7: data validity scl sda data stable data stable data change
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 22 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm serial presence-detect figure 8: definition of start and stop figure 9: acknowledge response from receiver table 18: eeprom device select code the most significant bit (b7) is sent first select code device type identifier chip enable rw b7 b6 b5 b4 b3 b2 b1 b0 memory area select code (two arrays) 1 0 1 0 sa2 sa1 sa0 rw protection register select code 0 1 1 0 sa2 sa1 sa0 rw table 19: eeprom operating modes mode rw bit w c bytes initial sequence current address read 1 v ih or v il 1 start, device select, rw = 1 random address read 0 v ih or v il 1 start, device select, rw = 0, address 1v ih or v il restart, device select, rw = 1 sequential read 1v ih or v il 1 similar to current or random address read byte write 0 v il 1 start, device select, rw = 0 page write 0 v il 16 start, device select, rw = 0 scl sda start bit stop bit scl from master data output from transmitter data output from receiver 9 8 acknowledge
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 23 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm serial presence-detect figure 10: spd eeprom timing diagram scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 24 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm serial presence-detect notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition, or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/progra m cycle. during the write cycle, the eepro m bus interface circuit is disa bled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address. table 20: serial presence-detec t eeprom dc operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units supply voltage v dd 33.6v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ?0.4v input leakage current: v in = gnd to v dd i li -10 10 a output leakage current: v out = gnd to v dd i lo -10 10 a standby current: scl = sda = v dd - 0.3v; all other inputs = v ss or v dd i ccs ?30a power supply current: scl clock frequency = 100 khz i cc write ? 3 ma i cc read ? 1 ma table 21: serial presence-detec t eeprom ac operating conditions all voltages referenced to v ss ; v ddspd = +2.3v to +3.6v parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time the bus must be free before a new transition can start t buf 1.3 s data-out hold time t dh 200 ns sda and scl fall time t f300ns2 data-in hold time t hd:dat 0 s start condition hold time t hd:sta 0.6 s clock high period t high 0.6 s noise suppression time con stant at scl, sda inputs t i50ns clock low period t low 1.3 s sda and scl rise time t r0.3s2 scl clock frequency f scl 400 khz data-in setup time t su:dat 100 ns start condition setup time t su:sta 0.6 s 3 stop condition setup time t su:sto 0.6 s write cycle time t wrc 10 ms 4
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 25 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm serial presence-detect table 22: serial presence-detect matrix ?1?/?0?: serial data , ?driven to high?/?driven to low?; v dd = +3.3v 0.3v byte description entry (version) mt36lsdf6472 mt36lsdf12872 0 number of bytes used by micron 128 80 80 1 total number of spd memory bytes 256 08 08 2 memory type sdram 04 04 3 number of row addresses 12 or 13 0c 0d 4 number of column addresses 11 0b 0b 5 number of module ranks 20202 6 module data width 72 48 48 7 module data width (continued) 00000 8 module voltage interface levels lvttl 01 01 9 sdram cycle time, t ck (cl = 3) 7ns (-13e) 7.5ns (-133) 70 75 70 75 10 sdram access from clk, t ac (cl = 3) 5.4ns (-13e/-133) 54 54 11 module configuration type ecc 02 02 12 refresh rate/type 15.6s or 7.81s/ self 80 82 13 sdram width (primary sdram) 40404 14 error-checking sdram data width 40404 15 minimum clock delay from back-to-back random column addresses, t ccd 10101 16 burst lengths supported 1, 2, 4, 8, page 8f 8f 17 number of banks on sdram device 40404 18 cas latencies supported 2, 3 06 06 19 cs latency 00101 20 we latency 00101 21 sdram module attributes -13e/-133 1f 1f 22 sdram device attributes: general 0e 0e 0e 23 sdram cycle time, t ck (cl = 2) 7.5ns (-13e) 10ns (-133) 75 a0 75 a0 24 sdram access from clk, t ac (cl = 2) 5.4ns (-13e) 6ns (-133) 54 60 54 60 25 sdram cycle time, t ck (cl = 1) ?0000 26 sdram access from clk, t ac (cl = 1) ?0000 27 minimum row precharge time, t rp 15ns (-13e) 20ns (-133) 0f 14 0f 14 28 minimum row active to row active, t rrd 14ns (-13e) 15ns (-133) 0e 0f 0e 0f 29 minimum ras# to cas# delay, t rcd 15ns (-13e) 20ns (-133) 0f 14 0f 14 30 minimum ras# pulse width, t ras (see note 1) 45ns (-13e) 44ns (-133) 2d 2c 2d 2c 31 module rank density 256mb / 512mb 40 80 32 command and address setup time, t as, t cms 1.5ns (-13e/-133) 15 15 33 command and aaddress hold time, t ah, t cmh 0.8ns (-13e/-133) 08 08 34 data signal input setup time, t ds 1.5ns (-13e/-133) 15 15 35 data signal input hold time, t dh 0.8ns (-13e/-133) 08 08 36?40 reserved 00 00
pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 26 ?2003 micron technology, inc. all rights reserved. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm serial presence-detect notes: 1. the value of t ras used for the -13e modu le is calculated from t rc - t rp. actual device spec- ification value is 37ns. 41 device minimum active/auto refresh time, t rc 66ns (-13e) 71ns (-133) 3c 42 3c 42 42?61 reserved 00 00 62 spd revision rev. 2.0 02 02 63 checksum for bytes 0?62 -13e -133 df 2b 22 6e 64 manufacturer?s jedec id code micron 2c 2c 65-71 manufacturer?s jedec id code (continued) ff ff 72 manufacturing location 1?9 01?09 01?09 73-90 module part number (ascii) variable data variable data 91 pcb identification code 1?11 01?0b 01?0b 92 identification code (continued) 00000 93 year of manufacture in bcd variable data variable data 94 week of manufacture in bcd variable data variable data 95-98 module serial nnumber variable data variable data 99-125 manufacturer-specific data (rsvd) ?? 126 system frequency 100/133 mhz 64 64 127 sdram component and clock detail 8f 8f table 22: serial presence-detect matrix (continued) ?1?/?0?: serial data , ?driven to high?/?driven to low?; v dd = +3.3v 0.3v byte description entry (version) mt36lsdf6472 mt36lsdf12872
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are tr ademarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. this data sheet contains minimum and maximum limits specified ov er the complete power supply and temperature range for production devices. althou gh considered final, these specifications are subject to change, as further product development and data characte rization sometimes occur. 512mb, 1gb (x72, ecc, dr): 168-pin sdram rdimm module dimensions pdf: 09005aef807da15c/source: 09005aef80f69382 micron technology, inc., reserves the right to change products or specifications without notice. sdf36c64_128x72g.fm - rev. e 10/05 en 27 ?2003 micron technology, inc. all rights reserved. module dimensions all dimensions are in inches (millimeters); or typical where noted. figure 11: 168-pin dimm dimensions max min 1.705 (43.31) 1. 6 95 (43.05) 0.128 (3.25) 0.118 (3.00) (2x) pin 1 0.700 (17.78) typ 0.118 (3.00) (2x) 0.118 (3.00) typ 0.250 ( 6 .35) typ 4.550 (115.57) 0.050 (1.27) typ 0.118 (3.00) typ 0.040 (1.02) typ 0.079 (2.00) r (2x) 0.039 (1.00) r(2x) pin 84 front view ba c k view pin 1 6 8 pin 85 2. 6 25 ( 66 . 6 8) 1. 66 1 (42.18) 0.157 (3.99) max 0.054 (1.37) 0.04 6 (1.17) 5.25 6 (133.50) 5.244 (133.20) u1 u2 u3 u4 u5 u 6 u7 u8 u9 u10 u11 u12 u13 u14 u39 u37 u38 u15 u1 6 u17 u18 u28 u27 u2 6 u25 u24 u23 u22 u21 u20 u19 u3 6 u35 u34 u33 u40 u32 u31 u30 u29 u42

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