mitsumi ic for cmos system reset pst81xx, 82xx series ic for cmos system reset monolithic ic pst81xx, 82xx series outline this ic functions in a variety of cpu systems and other logic systems, to detect supply voltage and reset the system accurately when the power is turned on or interrupted. to ?.5% of detection voltage accuracy of the conventional models, a maximum of ?.5% of super-high precision is realized, and it is more suitable for battery detection etc. moreover, the mounting area significantly contributes to space saving using the sson package. features 1. ultra-high accuracy v th ?.5%/2.0~6.0v v th ?.8%/0.8~1.9v 2. ultra-low current consumption 0.25? typ. 3. ultra-small package 1.10 1.40mm (sson-4a) 4. operating temperature range -40~+105 c 5. detecting voltage rank 0.8~6.0v (0.1v step) 6. output configuration pst81xx series cmos output pst82xx series open drain output packages sot-25a sc-82aba sc-82abb sson-4a applications 1. reset circuits for microcomputers, cpus and mpus 2. reset circuits for logic circuits 3. battery voltage check circuits 4. back-up power supply switching circuits 5. level detection circuits
mitsumi ic for cmos system reset pst81xx, 82xx series block diagram 1 3 2 vref v dd gnd out pst81xxnx, pst81xxrx, pst81xxux (sot-25a) (sson-4a) (sc-82aba/-82abb) 1 3 2 vref v dd gnd out pst82xxnx, pst82xxrx, pst82xxux (sot-25a) (sson-4a) (sc-82aba/-82abb)
mitsumi ic for cmos system reset pst81xx, 82xx series pin assignment 123 54 sot-25a (top view) 12 43 sc-82aba sc-82abb (top view) 12 43 sson-4a (top view) 1 out 2 v dd 3 gnd 4 n.c 5 n.c 1 out 2 gnd 3 n.c 4 v dd 1 out 2 v dd 3 n.c 4 gnd pst81xx, pst82xx pin description pin no. pin name functions 1 out reset signal output pin 2 v dd v dd pin / voltage detect pin 3 gnd gnd pin 4 n.c no connection 5 n.c no connection pst81xxnx, pst82xxnx (sot-25a) pin no. pin name functions 1 out reset signal output pin 2 gnd gnd pin 3 n.c no connection 4 v dd v dd pin / voltage detect pin pst81xxrx, pst82xxrx (sson-4a) pin no. pin name functions 1 out reset signal output pin 2 v dd v dd pin / voltage detect pin 3 n.c no connection 4 gnd gnd pin pst81xxux, pst82xxux (sc-82aba/-82abb)
mitsumi ic for cmos system reset pst81xx, 82xx series absolute maximum ratings item symbol ratings units supply voltage v dd max - 0.3~+12.0 v output voltage out - 0.3~(v dd +0.3) v input current (v dd ) i dd 20 ma output current (reset, reset) i out 20 ma operating temperature t opr - 40~+105 c storage temperature t stg - 65~+150 c pst81xx item symbol ratings units supply voltage v dd max - 0.3~+12.0 v output voltage out - 0.3~+12.0 v input current (v dd ) i dd 20 ma output current (reset, reset) i out 20 ma operating temperature t opr - 40~+105 c storage temperature t stg - 65~+150 c pst82xx recommended operating conditions item symbol ratings units operating temperature t opr - 40~+105 c supply voltage v dd +0.7~+10.0 v
mitsumi ic for cmos system reset pst81xx, 82xx series electrical characteristics (except where noted otherwise ta=25?) note1 : this device is tested at ta=25 c, over temperature limits guaranteed by design only. note2 : the parameter is guaranteed by design. pst81xx item symbol measurement conditions min. typ. max. units circuit supply current i dd v dd =v th +1v 0.25 1.0 ? (1) ta=+25 c v th < = 1.9v v th - 0.8% v th v th +0.8% reset threshold v th ta=-40~+85 c (note1) v th - 2.5% 0.8~ v th +2.5% v (2) ta=+25 c v th > = 2.0v v th v0.5% 6.0v v th +0.5% ta= - 40~+85 c (note1) v th - 2.5% (0.1vstep) v th +2.5% reset threshold hysteresis v th v dd =0v v th +1v 0v v th 0.03 v th 0.08 v (2) reset threshold temp. coefficient v th / c ta= - 40~+85 c (note1) ?00 ppm/ c (2) l transfer delay time t phl v dd =v th +0.4v v th - 0.4v (note2) 100 ? (5) h transfer delay time t plh v dd =v th - 0.4v v th +0.4v (note2) 100 ? (5) i ol1 v dd =0.7v, v ds =0.05v 0.01 0.10 i ol2 v dd =1.2v, v ds =0.5v v th > 1.3v 0.23 2.00 "l" output curren i ol3 v dd =2.4v, v ds =0.5v ma (3) v th > 2.5v 1.60 8.00 i ol4 v dd =3.6v, v ds =0.5v 3.20 12.0 v th > 3.7v "h" output current i oh1 v dd =4.8v, v ds =0.5v, v th < 4.7v 0.36 0.62 ma (4) i oh2 v dd =6.1v, v ds =0.5v, v th < 5.9v 0.46 0.75 note1 : this device is tested at ta=25 c, over temperature limits guaranteed by design only. note2 : the parameter is guaranteed by design. pst82xx item symbol measurement conditions min. typ. max. units circuit supply current i dd v dd =v th +1v 0.25 1.0 ? (1) ta=+25 c v th < = 1.9v v th - 0.8% v th v th +0.8% reset threshold v th ta= - 40~+85 c (note1) v th - 2.5% 0.8~ v th +2.5% v (2) ta=+25 c v th > = 2.0v v th - 0.5% 6.0v v th +0.5% ta= - 40~+85 c (note1) v th - 2.5% (0.1vstep) v th +2.5% reset threshold hysteresis v th v dd =0v v th +1v 0v v th 0.03 v th 0.08 v (2) reset threshold temp. coefficient v th / c ta= - 40~+85 c (note1) ?00 ppm/ c (2) l transfer delay time t phl v dd =v th +0.4v v th - 0.4v (note2) 100 ? (4) h transfer delay time t plh v dd =v th - 0.4v v th +0.4v (note2) 100 ? (4) i ol1 v dd =0.7v, v ds =0.05v 0.01 0.10 i ol2 v dd =1.2v, v ds =0.5v v th > 1.3v 0.23 2.00 "l" output curren i ol3 v dd =2.4v, v ds =0.5v ma (3) v th > 2.5v 1.60 8.00 i ol4 v dd =3.6v, v ds =0.5v v th > 3.7v 3.20 12.0 output leakage current ireak v dd =10v, out=10v 0.1 ? (3)
mitsumi ic for cmos system reset pst81xx, 82xx series measuring circuit (1) i dd pst81xx * 1 - 3 in the circuit diagram is pin number for the sot-25a package. pst 81xx 2 v dd gnd v in i ss 1 3 (2) v th , v th , v th /? v dd gnd v in out pst 81xx 2 1 3 (3) i ol1 , i ol2 , i ol3 , i ol4 v dd gnd v in out v ds i out pst 81xx 2 1 3 (4) i oh1 , i oh2 v dd gnd v in out v dd -v ds i out pst 81xx 2 1 3 (5) t plh , t phl v dd gnd v in out pst 81xx 2 1 3 v th +0.4v gnd 100% 50% gnd input voltage output voltage v th +0.4v v th
mitsumi ic for cmos system reset pst81xx, 82xx series (1) i dd pst 82xx 2 v dd gnd v in i ss 1 3 (2) v th , v th , v th /? 470k ? v dd gnd v in out pst 82xx 2 1 3 (3) i ol1 , i ol2 , i ol3 , i ol4 , ireak v dd gnd v in out v ds i out pst 82xx 2 1 3 (4) t plh , t phl 470k ? v dd gnd v in out pst 82xx 2 1 3 v th +0.4v gnd 100% 50% gnd input voltage output voltage v th +0.4v v th pst81xx * 1 - 3 in the circuit diagram is pin number for the sot-25a package.
mitsumi ic for cmos system reset pst81xx, 82xx series timing chart v v dd t v out t v th v th t plh v th + v th t phl application circuit pst 81xx logic system 2 1 3 reset out v dd gnd v dd v in pst81xx
mitsumi ic for cmos system reset pst81xx, 82xx series ?we shall not be liable for any trouble or damage caused by using this circuit. ?in the event a problem which may affect industrial property or any other rights of us or a third party is encountered during the use of information described in these circuit, mitsumi electric co., ltd. shall not be liable for any such problem, nor grant a license therefore. ?please note that there is any possibility of circuit oscillation when resistance put in the line v in . ?please do not put resistance for pst81xx. ?recommend 15k ? or less for pst82xx. pst 81xx 2 out v dd gnd v in 1 3 pst 82xx 2 out v dd gnd v in 1 3 pst 82xx logic system 2 reset out v dd gnd v dd v in 1 3 pst82xx
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