exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr xrk39653 3.3v, 8-output zero delay buffer november 2006 rev. 1.0.0 xrk39653 general description the xrk39653 is a low voltage high performance pll based zero delay buffer/clock generator designed for high speed clock distribution applications. it provides 9 low skew, low jitter outputs ideal for networking, computing and telecom applications. the pll based design allows the 9 outputs (8 clock outputs and 1 feedback output) to be phase aligned to the input ref - erence clock. the outputs source lvcmos compatible lev - els and can drive 50 transmission lines. if series termination is used, each output can drive up to 2 lines pro - viding effectively a fanout of 1:16. the xrk39653?s refer - ence input accepts a lvpecl clock source. for normal operation (pll used to source the outputs), the feedback output (qfb) is connected to the feedback input (fb_in). the vco range of operation is 200 to 500mhz. this means that the input/output ranges are determined by the divider setting. if 4 is used, the input/output range is 50 to 125mhz (high range), if 8 is used the input/output range is 25 to 62.5mhz (low range). for testing purposes two pll bypass modes are provided. the first simply replaces the pll output with the reference clock (pll_en=0, bypass =1). the dividers are still in use. the second is a full bypass mode that has the pll and divider operation removed ( bypass =0). in this mode the reference clock directly sources the outputs drivers. features ? 8 lvcmos clock outputs ? 1 feedback output ? lvpecl reference clock input ? 25-125 mhz input/output frequency range input/output range ( 4): 50-125mhz input/output range ( 8): 25-62.5mhz ? 150ps max output to output skew ? two bypass test mode options ? fully integrated pll ? 3.3v operation ? pin compatible with mpc9653 ? industrial temp range: -40c to +85c ? 32-lead tqfp packaging f igure 1. b lock d iagram of the xrk39653 pll ref fb 1 0 1 0 1 0 fb_in pll_en oe pecl pecl q5 q6 q7 qf b 2 4 q4 q0 q1 q2 q3 v co_sel bypass vdd vdd
xrk39653 xr 3.3v, 8-output zero delay buffer rev. 1.0.0 2 product ordering information p roduct n umber p ackage t ype o perating t emperature r ange xrk39653cq 32-lead tqfp 0c to +70c xrk39653iq 32-lead tqfp -40c to +85c f igure 2. p in o ut of the xrk39653 1 2 3 4 5 6 7 8 9 10111213141516 25 24 23 22 21 20 19 18 32 31 30 29 28 27 26 17 xrk39653 vco_se l nc nc nc oe pecl agnd fb_in pll_en avdd vdd q7 gnd q6 q5 vdd gn d q1 q2 vd d vd d q3 q4 gn d bypass gnd gnd qfb q0 vdd nc pecl
xr xrk39653 rev. 1.0.0 3.3v, 8-output zero delay buffer 3 pin descriptions n umber n ame t ype d escription 1 avdd power power supply for pll 2 fb_in input pull-up external pll feedback clock input 3, 4, 5, 6 nc 7 agnd power pll ground 8 pecl input lvpecl - pos differential reference clock 9 pecl input lvpecl - neg differential reference clock 10 oe input pull-down output enable/disable and device reset 11,15, 19, 23, 27, vdd power power supply 12, 14, 16, 18, 20, 22, 24, 26 q[7:0] output clock outputs 13, 17, 21, 25, 29 gnd power ground 28 qfb output feedback output for pll 30 pll_en input pull-up pll enable/disable select 31 bypass input pull-up pll and output divider bypass select 32 vco_sel input pull-up vco divider select t able 1: control input function table pin name 0 1 default vco_sel system divide = 4 of vco output system divide = 8 of vco output 1 pll_en pll is bypassed and disabled. the pecl clock reference source drives the outputs through the divider blocks pll enabled. normal operation. vco out - put drives the outputs through the divider blocks 1 bypass complete bypass of the pll and divider blocks. pecl reference clocks the outputs. normal operation. dividers selected. 1 oe outputs enabled outputs tri-stated and device reset. vco running at minimum frequency 0
xrk39653 xr 3.3v, 8-output zero delay buffer rev. 1.0.0 4 a. vcmr is the cross point of the differential input signal. . dc c haracteristics (v cc = 3.3 + 5%, t a = -40 c to +85 c) s ymbol c haracteristics m in t yp m ax u nit c ondition v cmr a pecl clock inputs common mode range 1.0 v dd -0.6 v lvpecl v pp pecl clock peak-to-peak input voltage 300 1000 mv lvpecl v ih input voltage high 2.0 v dd +0.3 v lvcm os v il input voltage low 0.8 v lvcm os v oh output high voltage a 2.4 v i oh =-24ma v ol output low voltage a 0.55 0.30 v v i ol =24ma i ol =12ma z out output impedance 14-17 i in input leakage current + 200 ? v in =v dd or v in =gnd i cc_pll maximum pll supply current 5.0 10.0 ma av dd pin i ccq maximum quiescent supply current 10.0 ma all v dd pins, oe =1 v tt output termination voltage v cc 2 v ac c haracteristics (v cc = 3.3 + 5%, t a = -40 c to +85 c) a s ymbol p arameter m in t yp m ax u nit c ondition f vco vco frequency 200 500 mhz f ref input reference frequency 4 feedback 8 feedback pll bypass 50 25 0 125 62.5 200 mhz pll locked pll locked bypass mode f max max output frequency 4 feedback 8 feedback 50 25 125 62.5 mhz pll locked pll locked v pp pecl clock peak-to-peak input voltage 450 1000 mv lvpecl v cmr pecl input common mode range 1.2 v dd -0.75 v lvpecl t pw min input reference clock minimum pulse width 2 ns t spo propagation delay - static phase offset (pecl to fb_in) -75 125 ps pll locked t pd propagation delay - pll bypassed bypass mode 1 ( bypass = 0) bypass mode 2, ( bypass = 1, pll_en = 0) 1.2 3.0 3.3 7.0 ns ns t skew(o) output-to-output skew 150 ps t skew(pp) part to part skew (bypass pll & divider) 1.5 ns bypass =0 t jit(cc) cycle-to-cycle jitter 100 ps
xr xrk39653 rev. 1.0.0 3.3v, 8-output zero delay buffer 5 a. ac characteristics apply for parallel output termination of 50 to v tt . a. absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. t jit(per) period jitter 100 ps t jit(i/o) i/o phase jitter (rms) 25 ps bw pll bandwidth 4 feedback 8 feedback 0.8 - 4 0.5 - 1.3 mhz mhz dc output duty cycle 45 50 55 % pll locked t lock maximum pll lock time 10.0 ms t or /t of output rise/fall time 100 1000 ps 0.55 to 2.4v t plz,hz output disable time 7 ns t phz,lz output enable time 6 ns maximum ratings a s ymbol characteristics m in m ax u nit c ondition v dd supply voltage -0.3 3.9 v v in dc input voltage -0.3 v dd +0.3 v v out dc output voltage -0.3 v dd +0.3 v i in dc input current + 20 ma i out dc output current + 50 ma t s storage temperature -65 125 c general specifications s ymbol c haracteristics m in t yp m ax u nit c ondition v tt output termination voltage v cc 2 v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c in input capacitance 4.0 pf inputs ac c haracteristics (v cc = 3.3 + 5%, t a = -40 c to +85 c) a s ymbol p arameter m in t yp m ax u nit c ondition
xrk39653 xr 3.3v, 8-output zero delay buffer rev. 1.0.0 6 f igure 3. o utput - to - output s kew t sk(o) f igure 4. p ropogation delay (t (?) , static phase offset ) test reference f igure 5. o utput d uty c ycle (dc) f igure 6. i/o j itter the pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. v cc v cc 2 gnd v cc v cc 2 gnd t sk(o) fb_in t (?) cclkx v cc v cc 2 gnd v cc v cc 2 gnd tp t 0 dc=t p /t 0 x 100% the time from the pll controlled edge to the non controlled edge, divided by the time between pll controlled edges, expressed as a percentage v cc v cc 2 gnd fb_in cclkx t jit(i/o) = |t 0 -t 1 mean | the deviation in t 0 for a controlled edge with respect to a t 0 mean in a random sample of cycles
xr xrk39653 rev. 1.0.0 3.3v, 8-output zero delay buffer 7 f igure 7. c ycle - to - cycle j itter f igure 8. p eriod j itter f igure 9. o utput t ransition t ime t est r eference the variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs t n t n+1 t jit(cc) = |t n -t n+1 | the deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles t 0 t jit(per) = |t n -1/f 0 | v cc =3.3v t of t or 2.4 0.55
xrk39653 xr 3.3v, 8-output zero delay buffer rev. 1.0.0 8 package dimensions [ note: the control dimension is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.012 0.018 0.30 0.45 c 0.004 0.008 0.09 0.20 d 0.346 0.362 8.80 9.20 d 1 0.272 0.280 6.90 7.10 e 0.0315 bsc 0.80 bsc l 0.018 0.030 0.45 0.75 0 7 0 7 24 17 16 9 18 25 32 d d 1 d d 1 b e a 2 a 1 a seating plane l c 32 lead thin quad flat pack (7 x 7 x 1.4 mm tqfp) rev. 2.00
xr xrk39653 rev. 1.0.0 3.3v, 8-output zero delay buffer 9 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the li fe support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c ) potential liability of exar corporation is adequately protected under the circumstances. copyright 2006 exar corporation datasheet november 2006. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history r evision # d ate d escription 1.0.0 november 2006 initial final release.
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