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rev. 1.0 7/03 copyright ? 2003 by silicon laboratories si3052-ds10 si3052 si3017/11/18 g lobal pci daa c hipset features applications description the si3052 is a system-side silicon direct access arrangement (daa) device that integrates a 32-bit, 33 mhz pci bus interface. the si3052 is paired with the si3018 global line- side device, si3011 fcc/tbr21 line- side device, or si3017 fcc line-side device. the pci daa chipset is compliant with global standards and includes a v.92 quality codec (80 db snr, ?75 db thd), dc termination (50 ? , current limiting) , ac termination (600 ? , complex impedance), and an integrated hybrid. functional block diagram ! si3052 pci daa and si3018 global, si3011 tbr21, or si3017 fcc line-side daa ! 32-bit, 33 mhz, pci 2.3 compliant interface ! ppmi 1.1 and wake support with pme and vaux ! bus master and target operation, dma controller ! 16 x 8 fifo on dma paths ! interrupt controller ! lowest cost external bill-of- material (bom) ! watchdog timer ! external eprom interface ! compliant with fcc, tbr21, jate, and other ptts ! 80 db dynamic range tx/rx path ! 2- to 4-wire hybrid ! patented isocap? technology ! >5000 v isolation ! wake-on-ring and ring validation ! 3.3 v digital power supply ! 64-pin tqfp, 0 to 70 c ! v.92 soft data/fax modems pci interface with fifos pci addr/data pci control vd vaux gnd eprom bom si3018 daa daa control dma control interrupt control id/rom interface aout call progress speaker tip ring us patent # 5,870,046 us patent # 6,061,009 patents pending ordering information see page 97. pin assignments si3052 64-lead tqfp (epad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 20 19 18 24 23 22 21 31 30 29 28 27 26 25 32 64 61 62 63 57 58 59 60 50 51 52 53 54 55 56 49 qe dct rx ib c1b c2b vreg dct2 ignd dct3 qb qe2 sc vreg2 rng2 rng1 si3017/11/18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
si3052/17/11/18 2 rev. 1.0
si3052/17/11/18 rev. 1.0 3 t able of c ontents section page electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 aout pwm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 pci functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 dma bus master operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 1 daa control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 fifo buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 telephone line interface functional d escription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 isolation barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 parallel handset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 loop current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 off-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 dc termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 ac termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 transhybrid balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 ring detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 ring validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 ringer impedance and threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 dtmf dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 pulse dialing and spark quenching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 billing tone detection and receive overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 billing tone filter (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 on-hook line monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 caller id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 filter selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 in-circuit testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 revision identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 pci configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 pci and daa control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 pin descriptions: si3052 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 pin descriptions: si3017/11/18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 package outline: 64-pin tqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 package outline: 16-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 02
si3052/17/11/18 4 rev. 1.0 electrical specifications table 1. recommended operating conditions parameter 1 symbol test condition min 2 typ max 2 unit ambient temperature t a k-grade 0 25 70 c si3052 supply voltage, core vd 3.0 3.3 3.6 v si3052 io supply voltage v io 3.3 v signaling 3.0 3.3 3.6 v si3052 io supply voltage v io 5 v signaling 4.75 5.0 5.25 v note: 1. the si3052 specifications are guaranteed when the typical ap plication circuit (including component tolerance) and si3052 and si3017/11/18 are used. refer to figure 13 on page 16 for the typical application schematic. 2. all minimum and maximum specificatio ns are guaranteed and apply across t he recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise stated.
si3052/17/11/18 rev. 1.0 5 table 2. pci interface dc characteristics for 5 v io 1 (v io = 4.75 to 5.25 v, t a = 0 to 70 c) parameter symbol test condition min typ max unit power supply cu rrent, core i d,vd d0 uninitialized 2 ?2021ma d0 initialized 3 ?2028ma d3 wake-on-ring 4 ?1215ma d3 deep sleep 5 ?1 ?ma power supply current, io i d,vio d0 uninitialized 2 ?0.3552 ma d0 initialized 3 ?0.3547 ma d3 4,5 ?0.35 ? ma high level input voltage v ih 2.0 ? v io +0.5 v low level input voltage v il ?0.5 ? 0.8 v input/hi-z leakage current i il 0 si3052/17/11/18 6 rev. 1.0 table 3. pci interface dc characteristics for 3.3 v io 1 (v io = 3.0 to 3.6 v, t a = 0 to 70 c) parameter symbol test condition min typ max unit power supply cu rrent, core i d,vd d0 unitialized 2 ?2021ma d0 initialized 3 ?2028ma d3 wake-on-ring 4 ?1215ma d3 deep sleep 5 ?1 ?ma power supply current, io i d,vio d0 unitialized 2 ?0.3536 ma d0 initialized 3 ?0.3535 ma d3 4,5 ?0.35 ? ma high level input voltage v ih 0.5 v io ?v io +0.5 v low level input voltage v il ?0.5 ? 0.3 v io v input leakage current i il 0 si3052/17/11/18 rev. 1.0 7 table 4. dc characteristics for non-pci pins 1 (vd = 3.0 to 3.6 v, t a = 0 to 70 c) parameter symbol test condition min max unit high level input voltage 2 v ih 2.0 ? v low level input voltage 2 v il ?0.8 v input leakage current 2 i il,1 0 si3052/17/11/18 8 rev. 1.0 table 5. pci interface ac characteristics for 5v io 1 (v io = 4.75 to 5.25 v, t a = 0 to 70 c) parameter symbol test condition min max unit switching current, high 2 i oh(ac) 0 v out >0.55 3 v out /0.023 ? ma 0.71>v out >0 3 ?78.5xv out x (4.4 ? v out ) ma v out =0.71 (test point) ? 206 ma low clamp current i cl -5 si3052/17/11/18 rev. 1.0 9 table 6. pci interface ac characteristics for 3.3v io 1 (v io = 3.0 to 3.6 v, t a = 0 to 70 c) parameter symbo l test condition min max unit switching current, high 2 i oh(ac) 0< v out <0.3v io 3 ?12 v io ? ma 0.3 v io < v out <0.9v io 3 ?17.1(v io ? v out ) ? ma 0.7 v io < v out v out 0.6v io 3 16 v io ? ma 0.6 > v out >0.1v io 3 26.7 v out ? ma 0.18 v io > v out >0 3 ? (256/v io )x v out x (v io ? v out ) ma v out =0.71 (test point) ? 38xv io ma low clamp current i cl ?3 < v in 1 ?25 + ( v in + 1)/0.015 ? ma high clamp current i ch v io +1 v in si3052/17/11/18 10 rev. 1.0 figure 1. pci timing table 7. pci interface timing characteristics (v d = 3.0 to 3.6 v, v io = 3.0 to 5.25 v, t a = 0 to 70 c, see figure 1) parameter symbol test condition min typ max unit pciclk cycle time t cyc 30 ? ? ns pciclk high time t high 11 ? ? ns pciclk low time t low 11 ? ? ns pciclk to signal valid delay? bused signals 1 t val 2?11ns pciclk to signal valid delay? point to point 1,3 t val(ptp) 2 ? 12 ns float to active delay 2 t on 2??ns active to float delay 2 t off ? ? 28 ns input setup time to pciclk? bused signals t su 7??ns input setup time to pciclk? point to point 3 t su(ptp) 10 ? ? ns input hold time for pciclk t h 0??ns reset active to ou tput float delay 2 t rst-off ? ? 30 ns notes: 1. for 5 v signaling, t val is evaluated with 50 pf load to ground. for 3.3 v signaling, t val is evaluated with 25 ? in parallel with 10 pf to ground (rising) or 25 ? to v io with 10 pf to ground (falling). 2. for purposes of identifying float timing measurements, the hi-z or off state is defined to be when the total current is less than or equal to the leak age current specification. 3. the point-to-point signals are req and gnt . valid input pciclk reset outputs hi-z outputs valid inputs t su t h t on t off t rst-off t val t cyc t high t low
si3052/17/11/18 rev. 1.0 11 figure 2. test circuit for loop characteristics table 8. daa loop characteristics 1 (v d = 3.0 to 3.6 v, t a = 0 to 70 c, see figure 2) parameter symbol test condition min typ max unit dc termination voltage v tr i l = 20 ma, ilim = 0 dcv = 00, mini = 11, dcr = 0 ??6.0v dc termination voltage v tr i l = 120 ma, ilim = 0 dcv = 00, mini = 11, dcr = 0 9??v dc termination voltage 2 v tr i l = 20 ma, ilim = 0 dcv = 11, mini = 00, dcr = 0 ??7.5v dc termination voltage 2 v tr i l = 120 ma, ilim = 0 dcv = 11, mini = 00, dcr = 0 9??v dc termination voltage v tr i l = 20 ma, ilim = 1 dcv = 11, mini = 00, dcr = 0 ??7.5v dc termination voltage v tr i l = 60 ma, ilim = 1 dcv = 11, mini = 00, dcr = 0 40 ? ? v dc termination voltage v tr i l = 50 ma, ilim = 1 dcv = 11, mini = 00, dcr = 0 ??40 v dc termination voltage v tr i l = 20 ma, ilim = 0 dcv = 11, mini = 00, dcr = 1 ??16 v dc termination voltage v tr i l = 60 ma, ilim = 0 dcv = 11, mini = 00, dcr = 1 40 ? ? v on-hook leakage current 2 i lk v tr =?48v ? ? 5 a operating loop current 2 i lp mini = 00, ilim = 0 10 ? 120 ma operating loop current i lp mini = 00, ilim = 1 10 ? 60 ma dc ring current 2 dc current flowing through ring detection circuitry ?1.5 3 a ring detect voltage 2,3 v rd rt = 0 12 15 18 v rms ring detect voltage 3 v rd rt = 1 18 21 25 v rms ring frequency 2 f r 13 ? 68 hz ringer equivalence number 2 ren ? ? 0.2 notes: 1. all parameters apply to si3018 global and si3011 tbr21 line-side devices. 2. parameter applies to si3017 fcc line-side device. 3. the ring signal is guaranteed to not be detected below the minimum. the ring signal is guaranteed to be detected above the maximum. tip ring + ? si3017/11/18 v tr 600 ? 10 f i l
si3052/17/11/18 12 rev. 1.0 table 9. daa ac characteristics 1 (v d = 3.0 to 3.6 v, t a = 0 to 70 c, fs = 8 khz) parameter symbol test condition min typ max unit sample rate 2 fs 7.2 ? 16 khz receive frequency response 2 low ?3 dbfs corner ? 5 ? hz transmit full scale level 2,3 v fs 0dbm ? 1.1 ? v peak receive full scale level 2,3,4 v fs 0dbm ? 1.1 ? v peak dynamic range 2,5,6,7 dr ilim = 0, dcv = 11, mini = 00 dcr = 0, i l =100ma ?78? db dynamic range 5,6,8 dr ilim = 0, dcv = 00, mini = 11 dcr = 0, i l =20ma ?79? db dynamic range 5,6,9 dr ilim = 1, dcv = 11, mini = 00 dcr = 0, i l =50ma ?78? db transmit total harmonic distortion 7,8 thd ilim = 0, dcv = 11, mini = 00 dcr = 0, i l =100ma ??72? db transmit total harmonic distortion 2,7,8 thd ilim = 0, dcv = 00, mini = 11 dcr = 0, i l =20ma ??78? db receive total harmonic distortion 7,8 thd ilim = 0, dcv = 00, mini = 11 dcr = 0, i l =20ma ??78? db receive total harmonic distortion 7,8 thd ilim = 1,dcv = 11, mini = 00 dcr = 0, i l =50ma ??78? db dynamic range (caller id mode) 2,7 dr cid v in = 1 khz, ?13 dbm ? 50 ? db caller id full scale level 2 v cid ?6? v pp notes: 1. all parameters apply to si3018 global and si3011 tbr21 line-side devices. 2. parameter applies to si3017 fcc line-side device. 3. measured at tip and ring with 600 ? . termination at 1 khz, as shown in figure 2. 4. receive full scale level produces ?0.9 dbfs. 5. dr = 20 x log (rms v fs /rms v in )+ 20 x log (rms v in /rms noise). v fs is the 0 dbm full-scale level. 6. measurement is 300 to 3400 hz. applie s to both transmit and receive paths. 7. v in = 1 khz, ?3 dbfs 8. thd = 20 x log (rms distortion / rms signal). 9. dr cid = 20 x log (rms v cid /rms v in )+ 20 x log (rms v in /rms noise). v cid is the 6 v full-scale level.
si3052/17/11/18 rev. 1.0 13 table 10. digital fir filter characteristics?transmit and receive (v d = 3.0 to 3.6 v, sample rate = 8 khz, t a = 0 to 70 c) parameter symbol min typ max unit passband (0.1 db) f (0.1 db) 0?3.3khz passband (3 db) f (3 db) 0?3.6khz passband ripple peak-to-peak ?0.1 ? 0.1 db stopband ? 4.4 ? khz stopband attenuation ?74 ? ? db group delay t gd ? 12/fs ? s note: typical fir filter characteristics for fs = 8000 hz are shown in figures 3, 4, 5, and 6. table 11. digital iir filter characteristics?transmit and receive (v d = 3.0 to 3.6 v, sample rate = 8khz, t a = 0 to 70 c) parameter symbol min typ max unit passband (3 db) f (3 db) 0?3.6khz passband ripple peak-to-peak ?0.2 ? 0.2 db stopband ? 4.4 ? khz stopband attenuation ?40 ? ? db group delay t gd ? 1.6/fs ? s note: typical iir filter characteristics for fs = 8000 hz are shown in figures 7, 8, 9, and 10. figures 11 and 12 show group delay versus input frequency.
si3052/17/11/18 14 rev. 1.0 figure 3. fir receive filter response figure 4. fir receive filter passband ripple figure 5. fir transmit filter response figure 6. fir transmit filter passband ripple for figures 3?6, all filter plots apply to a sample rate of fs = 8 khz. the filters scale with the sample rate as follows: f (0.1 db) = 0.4125 fs f (?3 db) =0.45fs where fs is the sample frequency. for figures 7?10, all filter plots apply to a sample rate of fs = 8 khz. the filters scale with the sample rate as follows: f (?3 db) =0.45fs where fs is the sample frequency. input frequency?hz attenuation?db input frequency?hz attenuation?db attenuation?db input frequency?hz input frequency?hz attenuation?db
si3052/17/11/18 rev. 1.0 15 figure 7. iir receive filter response figure 8. iir receive filter passband ripple figure 9. iir transmit filter response figure 10. iir transmit filter passband ripple figure 11. iir receive group delay figure 12. iir transmit group delay input frequency?hz attenuation?db input frequency?hz attenuation?db input frequency?hz attenuation?db input frequency?hz attenuation?db input frequency?hz delay?s input frequency?hz delay?s
si3052/17/11/18 16 rev. 1.0 typical application schematic c1a tip c2a ring no ground plane in daa section r63 q3 r16 d1 rv1 r11 r61 r12 r62 r3 u2 lineside qe 1 dct 2 rx 3 ib (vreg) 4 c1b 5 c2b 6 vreg 7 rng1 8 dct2 16 ignd 15 dct3 14 qb 13 qe2 12 sc (ignd) 11 vreg2 10 rng2 9 fb1 fb2 c9 + c4 r9 q4 c1 r6 c6 q1 d2 r5 r65 r15 r10 r13 q5 r60 q2 z1 r64 c7 r8 r2 r4 c3 c10 c8 c2 r7 r1 c5 figure 13. si3052 and si3017/11/18 typical application schematic (1 of 2)
si3052/17/11/18 rev. 1.0 17 ad12 ad30 ad21 3.3vaux ad27 5vb6 pci_tdd ad6 5vb5 ad3 ad28 ad26 5vb61 ad23 ad8 ad2 3.3va33 5va5 ad25 5vb62 vioa59 ad24 ad13 ad4 3.3vb36 5va8 3.3va27 ad18 ad0 ad20 3.3vb25 3.3vb43 vioa16 ad10 ad19 ad16 3.3vb54 3.3va21 ad1 ad17 3.3vb41 ad5 ad7 3.3vb31 5va62 ad14 ad9 ad29 ad11 3.3va39 viob59 5va61 ad15 ad31 ad22 viob19 3.3va45 vioa10 ad[0:31] 3.3va53 3.3vb31 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 vio1 vio16 vio25 vio55 5vb61 5vb6 5va62 5va5 5vb5 5va8 5va61 5vb62 vio55 viob19 3.3va53 3.3va21 3.3vaux 3.3va33 3.3vb36 3.3vb43 3.3vb41 3.3va45 3.3vb25 3.3va27 3.3vb54 3.3va39 3.3vaux vioa10 vio25 vioa59 vioa16 vio viob59 vio16 vio1 3.3vccbus 5vcc vio 12v vio 3.3vccbus 3.3vaux 3.3vaux 3.3vccbus c/be0_l c/be3_l stop_l irdy_l serr_l c/be1_l devsel_l frame_l req_l idsel trdy_l clk c/be2_l pme_l gnt_l rst_l inta_l perr_l par c/be0_l c/be1_l c/be2_l c/be3_l clk devsel_l frame_l gnt_l idsel irdy_l par perr_l req_l rst_l serr_l stop_l trdy_l pin_a c1a c2a pme_l pin_b inta_l va c50 should be located close to u1 y1 or y2 should be used. note: r40 should be installed if pci 2.2 compliant r41 should be installed if not pci 2.2 compliant c110 c118 c107 c60 c82 c104 c57 c117 u1 si3052 ad[18] 64 ad[17] 2 ad[16] 3 c/be[2] 4 frame 5 irdy 6 trdy 7 devsel 8 vio 25 stop 9 perr 10 serr 11 par 12 c/be[1] 13 ad[15] 14 ad[14] 15 ad[13] 17 ad[12] 18 ad[11] 19 ad[10] 20 ad[09] 21 ad[08] 22 c/be[0] 23 ad[07] 24 ad[06] 26 ad[05] 27 ad[04] 28 ad[03] 29 ad[02] 30 ad[01] 31 ad[00] 32 vd 44 xin 36 xout 35 c2a 41 c1a 42 pin_b 39 pme 40 pin_a 38 inta 33 rst 37 clk 45 gnt 46 req 47 ad[31] 48 ad[30] 49 ad[29] 50 ad[28] 51 ad[27] 52 ad[26] 53 ad[25] 54 ad[24] 56 vaux_sense 34 c/be[3] 57 idsel 58 ad[23] 59 ad[22] 60 ad[21] 61 ad[20] 62 ad[19] 63 vio 55 vio 16 vio 1 va 43 gnd c56 c51 c87 j2 pciconunv trst# a1 -12v b1 +12v a2 tck b2 tms a3 gnd b3 tdi a4 tdo b4 +5v a5 +5v b5 inta# a6 +5v b6 intc# a7 intb# b7 +5v a8 intd# b8 reserved a9 prsnt1# b9 vio a10 reserved b10 reserved a11 prsnt2# b11 3.3vaux a14 reserved b14 rst# a15 gnd b15 vio a16 clk b16 gnt# a17 gnd b17 gnd a18 req# b18 pme# a19 vio b19 ad30 a20 ad31 b20 +3.3v a21 ad29 b21 ad28 a22 gnd b22 ad26 a23 ad27 b23 gnd a24 ad25 b24 ad24 a25 +3.3v b25 idsel a26 c/be3# b26 +3.3v a27 ad23 b27 ad22 a28 gnd b28 ad20 a29 ad21 b29 gnd a30 ad19 b30 ad18 a31 +3.3v b31 ad16 a32 ad17 b32 +3.3v a33 c/be2# b33 frame# a34 gnd b34 gnd a35 irdy# b35 trdy# a36 +3.3v b36 gnd a37 devsel# b37 stop# a38 gnd b38 +3.3v a39 lock# b39 reserved a40 perr# b40 reserved a41 +3.3v b41 gnd a42 serr# b42 par a43 +3.3v b43 ad15 a44 c/be1# b44 +3.3v a45 ad14 b45 ad13 a46 gnd b46 ad11 a47 ad12 b47 gnd a48 ad10 b48 ad9 a49 m66en b49 c/be0# a52 ad8 b52 +3.3v a53 ad7 b53 ad6 a54 +3.3v b54 ad4 a55 ad5 b55 gnd a56 ad3 b56 ad2 a57 gnd b57 ad0 a58 ad1 b58 vio a59 vio b59 req64# a60 ack64# b60 +5v a61 +5v b61 +5v a62 +5v b62 y1 c106 c84 c103 c55 c53 c85 c115 c52 c40 c83 c125 c86 c114 y2 r51 r40 c124 c109 r52 c58 c108 c113 c121 c105 c50 c123 c81 c41 r41 c59 c112 c120 c122 c111 c54 c119 c80 c88 c116 figure 14. si3052 and si3017/11/18 typical application schematic (2 of 2)
si3052/17/11/18 18 rev. 1.0 bill of materials component(s) value supplier(s) c1, c2 33pf, y2, x7r, 20% panasonic, murata, vishay c3 10 nf, 250 v, x7r, 20% venkel, smec c4 1.0 f, 35 v, elec/tant, 20% panasonic c5, c6, c50, c117 1 0.1 f, 16 v, x7r, 20% venkel, smec c7 2.7 nf, 50 v, x7r, 20% venkel, smec c8, c9 680 pf, y2, x7r, 10% panasonic, murata, vishay c10, c52-c53, c56?c57, c60, c81, c84?c87, c103?c115, c123?c125 1 0.01 f, 16 v, x7r, 20% venkel, smec c40?41 22 pf, 50 v, cog, 5% venkel, smec c51,c54,c55,c58,c59 1 1.0 f, 16 v, x7r, 20% venkel, smec c81-c82, c8 5-c86, c88 1 1.0uf, 16v, x7r, 20% venkel, smec c80, c82, c88, c116 1 10 f, 16 v, elec, 20% panasonic c83, c118, c119, c120, c121 1 0.047 f, 16 v, x7r, 20% venkel, smec d1, d2 2 dual diode, 225 ma, 300 v, cmpd2004s central semiconductor fb1, fb2 ferrite bead, blm21aj601s murata q1, q3 npn, 300 v, mmbta42 fair child, onsemi, central semi q2 pnp, 300 v, mmbta92 fairchild, onsemi, central semi q4, q5 npn, 80 v, 330 mw, mmbta06 fairchild, onsemi, central semi rv1 sidactor, 275 v, 100 a teccor, protek, st micro r1 1.07 k ? , 1/2 w, 1% venkel, smec, panasonic r2 150 ? , 1/16 w, 5% venkel, smec, panasonic r3 3.65 k ? , 1/2 w, 1% venkel, smec, panasonic r4 2.49 k ? , 1/2 w, 1% venkel, smec, panasonic r5, r6 100 k ? , 1/16 w, 5% venkel, smec, panasonic r7, r8 20 m ? , 1/16 w, 5% venkel, smec, panasonic r9 1 m ? , 1/16 w, 1% venkel, smec, panasonic r10 536 ? , 1/4 w, 1% venkel, smec, panasonic notes: 1. decoupling capacitors based on pci specification rev 2.2. 2. several diode bridge configurations are acceptable; parts, such as a single df-04s or four 1n4004 diodes, may be used (suppliers include general semiconductor, diodes inc., etc.). 3. a 56 ? , 1%, 1/16 w resistor may be used if needed for r12?r13 (0 ?) to decrease emissions. 4. murata blm21aj601s may be used if needed for r15?r16 (0 ?) to decrease emissions. 5. r40 should be populated with a 0 ? resistor if 3.3 v aux is present; otherwise, r41 should be populated with a 0 ? resistor. 6. required for compatibility with future line-side devices.
si3052/17/11/18 rev. 1.0 19 r11 73.2 ? , 1/2 w, 1% venkel, smec, panasonic r12, r13 3 0 ? , 1/16 w venkel, smec, panasonic r15, r16 5 0 ? , 1/16 w venkel, smec, panasonic r40 5 0 ? , 1/16 w venkel, smec, panasonic r41 5 , r60?r64 6 ni venkel, smec, panasonic r51, r52 20 m ? , 1/16 w, 5% venkel, smec, panasonic u1 si3052 silicon labs u2 si3017/11/18 silicon labs y1 32.768 khz, 50 ppm ecs, epson, cts z1 zener diode, 43 v, 1/2 w general semiconductor, diodes inc. component(s) value supplier(s) notes: 1. decoupling capacitors based on pci specification rev 2.2. 2. several diode bridge configurations are acceptable; parts, such as a single df-04s or four 1n4004 diodes, may be used (suppliers include general semiconductor, diodes inc., etc.). 3. a 56 ? , 1%, 1/16 w resistor may be used if needed for r12?r13 (0 ?) to decrease emissions. 4. murata blm21aj601s may be used if needed for r15?r16 (0 ?) to decrease emissions. 5. r40 should be populated with a 0 ? resistor if 3.3 v aux is present; otherwise, r41 should be populated with a 0 ? resistor. 6. required for compatibility with future line-side devices.
si3052/17/11/18 20 rev. 1.0 aout pwm output figure 15 illustrates an opti onal circuit to support the pulse-width modulation (pwm ) output capability of the si3052 for call progress monitoring. this mode is enabled by setting the pwme bit (offset 0x31). the aout signal is a standard digital output from pin_39, which represents the sum of independently- scalable receive and transm it call progress contents in pulse-width modulation (pwm) form. the sampling rate of the audio path signals is 32 khz. the format of the pwm is configurable by the pwmm bits (offset 0x31). arm[1:0] and atm[1:0] (off set 0x36) control receive and transmit gains in 6 db steps and receive and transmit muting. alternativ ely, arm[7:0] and atm[7:0] (offset 0x44 and 0x45) control gains and muting with finer resolution. these registers allow the receive and transmit paths to be independently controlled and attenuated linearly. setting these 8-bit registers to all 0s mutes the receive and transmit paths. these registers affect the call progress ou tput only and do not affect transmit and receive operations on the telephone line. figure 15. aout pwm circuit for call progress table 12. component values?aout pwm component value supplier(s) c101 1 nf, 16 v, x7r, 20% venkel, smec ls1 brt1209pf-06 intervox q10 mosfet n gsd, fdv301n fairchild r60 15 k ? , 1/10 w, 5% venkel, smec, panasonic r61 0 ? , 1/10 w, 5% venkel, smec, panasonic r62, r63 ni pin_39 speaker 3.3 vccbus 5 vcc 12 v r61 r62 r63 ls1 q10 1 23 c101 r60 only install one
si3052/17/11/18 rev. 1.0 21 pci functional description the si3052 provides the interface between a pci 2.3- compliant bus and the si3018 using the silicon laboratories? proprietary isocap? technology. the si3052 has several major functional blocks including dma, bus mastering, daa control/status, power management, pnp configuration, eprom interface, interrupt control/status, fifo buffering, and a watchdog timer. table 13 on page 23 indicates which pci commands are supported and the method of implementation. the pci timing for write, read, and arbitration operations is shown in figures 15 through 17. dma bus master operation the si3052 supports dma bus master for write and read operations to memory. a dma write is a data transfer from memory to the si3052 fifo buffers. a dma read is a data transfer from the si3052 fifo buffers to memory. separate registers are defined and configured for independent operation of dma read and dma write. dma master transfer setup a dma transfer is set up by programming the dma start address register (read or write) and dma end address register (read or write) to physical memory locations. the size of the data transfer is calculated as the difference between the dma start and end memory address locations. the dma start and end memory addresses must be on a double-word (4-byte) boundary. a programming sequence for a dma write is as follows: 1. allocate dma memory buffer (non-cacheable, continuous). 2. set dma write start address register to physical memory address. 3. set dma write end address register to physical memory address. 4. fill dma write fifo buffer. 5. set dma control register start bit. to start the dma operation, set the dma enable bit (offset 0x00, bit 8). to stop the dma operation, clear this bit. dma restart bit (offset 0x00, bit 9) restarts the dma operation in single mode but is ignored in multiple mode. when the dma is setup, th e processor can use a polling routine to monitor the current dma status and process the fifo read and fifo writ e buffers. base the polling interval on the size of the allocated dma memory buffer. dma master status dma status is monitored by reading the current dma address (offset 0x14 read and 0x24 write) or by programming the dma interrupt address register (offset 0x10 read and 0x20 write). the current dma address register (read or write) c ontains the physical memory address of the dma operation in progress. if the dma interrupt address register (read or write) is programmed, an interrupt is generated and the interrupt status register flag (offset 0x04) is set when the dma transfer reaches the interrupt address. when the flag is set, it is cleared by setting the interrupt status register flag. the dma status register (offset 0x04, bits 3:0) contains the status of the current dma operation. each bit generates an interrupt if the corresponding mask bit is set. if the pci bus master logic detects an abort condition, the dma status register (offset 0x04, bits 5:4) is set based on the abort condition. the dma status register is cleared by reading the register value. to recover the pci bus master state machine, clear the dma reset bit in the dma control register (offset 0x00, bit 1) and enable dma operation by setting the dma enable bit in the dma control register (offset 0x00, bit 8). dma master control the dma interrupt mode bit (offset 0x00, bit 6) configures the interrupt mode. for level trigger mode, the interrupt occurs when the event happens and the status bit remains set as long as the conditions that created the interrupt remain active. in level trigger mode, the status bit is non-sticky. for edge trigger mode, the interrupt occurs when the event happens and the status bit remains set until cleared by setting the dma status register. in edge trigger mode, the status bit is sticky. the dma master mode bit (offset 0x00, bit 7) configures the dma operation mode. in multiple mode, the dma address wraps around to the starting address when the ending address is reached. in single mode, the dma stops when it reaches the end address. the advantage of multiple dma mode over single dma mode is that the si3052 continuously transfers data without processor intervention. the single dma mode has a control flow similar to the pc core logic dma controller. daa control the daa registers are accessed by either direct or indirect methods. the access mode is selected by the data mode bits (offset 0x00, bits 11, 12). direct daa register access the daa registers are accessed directly through either memory or i/o cycles. for memory accesses, the base address is set in pci configuration register 10h. for i/o
si3052/17/11/18 22 rev. 1.0 accesses, the base address is set in pci configuration register 14h. memory and i/o cycles are used interchangeably to acce ss internal registers. indirect daa register access the daa registers can be indirectly accessed through the dma master write buffer . the dma write buffer can contain daa control and data. this is equivalent to having a primary timeslot for modem data and a secondary timeslot for control data. if data mode (offset 0x00, bits 12:11) is set to indirect, the lsb of the 16-bit transmit word is used as a flag to indicate control address/data in the dma write buffer. if the lsb is 1, the transmit word is interpreted as control address/data and written to the corresponding control register. only 15-bit data is transmitted result ing in a loss of snr but allowing efficient access to daa control registers. figure 16. indirect daa register access core logic (pci target) si3052 (pci master) daa registers 1 1 0 data data control (read command) control (write command) data data data data control (all 0s) control (register data) dma write buffer dma read buffer pci bus signaling bits interleaved data and control words
si3052/17/11/18 rev. 1.0 23 figure 17. pci write operation table 13. pci command summary c/be [3:0] command type implementation 0000 interrupt acknowledge not supported 0001 special cycle not supported 0010 i/o read supported 0011 i/o write supported 0100 reserved 0101 reserved 0110 memory read support only linear addressing mode 0111 memory write support only linear addressing mode 1000 reserved 1001 reserved 1010 configuration read supported 1011 configuration write supported 1100 memory read multiple aliases to memory read 1101 dual address cycle not supported 1110 memory ready line aliases to memory read 1111 memory write and invalidate aliases to memory write bus cmd be-1 be-2 pciclk frame address data-1 data-2 data-3 ad c/be be-3 irdy data transfer data transfer data transfer wait wait wait trdy devsel address phase data phase data phase data phase bus transaction 5 4 6 7 3 2 1 8 9
si3052/17/11/18 24 rev. 1.0 figure 18. pci read operation figure 19. pci arbitration bus cmd address data-2 wait data transfer wait address phase data phase data phase data phase bus transaction 5 4 6 7 3 2 1 8 9 data-3 be data transfer data transfer wait data-1 pciclk frame ad c/be irdy trdy devsel pciclk req-a req-b gnt-a frame ad 5 4 6 7 3 2 1 gnt-b address data address data access - a access - b
si3052/17/11/18 rev. 1.0 25 power management the si3052 conforms to the pci bus power management specification, revision 1.1. the pci functions operate between the d0 and d3 power states. the pci bus controller operates between the b0 and b3 bus power states. d0 uninitia lized state d0 uninitialized is the defaul t condition after either a warm or a cold reset. 3.3 v is available from the pci power bus to power all pci i/o pads and non-vaux pci core logic. 3.3 v vaux is available for all vaux-power i/o and logic. powerdown (offset 0x36, bit 3) defaults low (inactive) and powerdown link (offset 0x36, bit 4) defaults high (active), meaning that the system-side device is fully operational except for the isocap, and the line-side device has no communication or power. pme-related logic is not cleared by reset. d0 active state d0 active is the fully-active condition arrived at from d0 uninitialized after software configuration. 3.3 v is available from the pci power bus to power all pci i/o pads and non-vaux pci core logic. 3.3 v vaux is available for all vaux-power i/o and logic. d3 hot state d3 (hot) is the powered-up idle condition. 3.3 v is available from the pci power bus to power all pci i/o pads and non-vaux pci core logic; however, pciclk can be stopped for minimal power consumption. pci bus signals are guaranteed to be held low during d3 (hot). 3.3 v vaux is available for all vaux-power i/o and logic at a max current draw of 20 ma per card if wake- on-ring is not enabled or 375 ma per card if wake-on- ring is enabled. d3 cold state d3 (cold) is the powered-dow n idle condition. the 3.3 v pci power bus is removed so there is no power to all pci i/o pads and non-vaux pci core logic. pci bus signals are guaranteed to be held low during d3 (cold). vaux is available for all vaux-power i/o and logic at a max current draw of 20 ma per card if wake-on-ring is not enabled, or 375 ma per card if wake-on-ring is enabled. b0 state b0 is the fully-active bus power condition. 3.3 v is available from the pci power bus to power to all pci i/o pads and non-vaux pci core logic. 3.3 v vaux is available for all vaux-power i/o and logic. the pciclk is active, and all bus transactions are available. b3 state b3 is the powerdown condition. the 3.3 v pci power bus is removed so there is no power to any pci i/o pads and non-vaux pci core logic. no pci bus activity is allowed. all pci bus signals are guaranteed to be held static, with the exception of pme . vaux is available for all pme-related logic and i/o. exit from b3 requires application of supply and is always accompanied by an active reset . software must guarantee that the daa pci function enters d3 before placing the pci bus in b3. eprom interface during si3052 initialization, the ee_sd and ee_sc pins are examined to determine if an external eprom is present. a pullup resistor on ee_sc and a logic high on ee_sd indicate this condition. the eprom load sequence reads six data bytes immediately after a cold reset. the first data byte is a header of 95h. the next four data bytes are the pci subsystem vendor id (svid) and the subsystem id (ssid) values. the final data byte is a cyclic red undancy check (crc) code. the eprom map is shown in figure 20. . figure 20. eprom map the 8-bit crc code indicates error detection in a faulty eprom. the crc is calcul ated using the following generator polynomial: the crc byte is calculated by appending an all-zero byte to the end of the data bytes and dividing the string by the generator polynomial in modulo-2 fashion. the remainder of the division is the crc byte value. an example calculation follows. bits bytes 0x05 0x04 0x03 0x02 0x01 0x00 7654 3210 ssid(15:8) ssid(7:0) svid(15:8) svid(7:0) eprom id(0x95) crc gx () x 8 x 2 x 1 1 +++ =
si3052/17/11/18 26 rev. 1.0 data bytes: 0x95 header byte 0x43 svid[7:0] 0x15 svid[15:8] 0x52 ssid[7:0] 0x30 ssid[15:8] 0x00 all zero byte eprom bytes: 0x95 header byte 0x43 svid[7:0] 0x15 svid[15:8] 0x52 ssid[7:0] 0x30 ssid[15:8] 0x3d crc byte figure 21. eprom circuit 3.3 vcc bus pin_ 39 pin_ 38 va option pin_38 pin_39 pin_38 function pin_39 function 0 x 0 clkrun aout 1 x a clkrun pnpid 2 x 1 clkrun aout 3a 0 pnpid aout 4a a pnpid pnpid 5a 1 pnpid aout 6 1 0 sda scl/ aout 7 1 a --- pnpid 8 1 1 sda scl/aout r55 c100 u3 nc 1 a1 2 a2 3 vss 4 vcc 8 sda 5 scl 6 nc 7 r62 r60 r57 r59 r56 r58 note: x = no install 1 = 4.7 kw pullup to 3.3 v 0 = 4.7 kw pulldown to gnd a = voltage divider between v a and gnd
si3052/17/11/18 rev. 1.0 27 interrupt sources inta is a level triggered interrupt pin for si3052 interrupt sources. the sources for the inta interrupt are as follows: ! ring detect ! pci target abort ! pci master abort ! dma read end of buffer ! dma read interrupt address ! dma write end of buffer ! dma write interrupt address ! interrupt counter ! isocap frame detect ! receive overload ! billing tone detect ! drop out detect ! overload detect pme is a level triggered interrupt pin for pci power management events. the source for the pme interrupt is ring detect with or without ring validation. fifo buffers the fifo buffers are fixed as 16 bits wide by 8 samples deep for dma master read and write. the sample data is contained in the lowest 16 bits of a 32-bit word. the fifo buffers do not support dma target operations. the fifo buffers are not memory mapped and cannot be accessed directly.
si3052/17/11/18 28 rev. 1.0 telephone line interface functional description together, the si3052 and si3017/11/18 comprise an integrated direct access arrangement (daa) that provides a programmable line interface to meet global telephone line interface requirements. the device implements silicon laborator ies? proprietary isocap? technology, which offers the highest level of integration by replacing an analog front end (afe), an isolation transformer, relays, opto-isolators, a 2- to 4-wire hybrid, and other circuitry. the si3018 can be fully programmed to meet international requirements and is compliant with fcc, tbr21, jate, and other country-specific ptt specifications as shown in table 14. also, the si3018 meets the most stringent global requirements for out-of- band energy, emissions, immunity, lightning surges, and safety. the si3011 meets all tbr21 and fcc requirements. the si3017 meets all fcc requirements. table 14. country specific register settings offset 0x40 line-side country ohs act2,act dct[1:0] rz rt 3018 3011 3017 argentina 0 00 10 0 0 !!! australia 1 10 01 0 0 ! austria 1 010 1100 !! bahrain 0 10 11 0 0 !! belgium 1 010 1100 !! brazil 0 00 01 0 0 ! bulgaria 0 10 11 0 0 !! canada 0 00 10 0 0 !!! chile 0 00 10 0 0 !!! china 0 00 10 0 0 !!! colombia 0 00 10 0 0 !!! croatia 0 10 11 0 0 !! cyprus 0 10 11 0 0 !! czech republic 0 10 11 0 0 !! denmark 1 010 1100 !! ecuador 0 00 10 0 0 !!! egypt 0 00 01 0 0 ! el salvador 0 00 10 0 0 !!! finland 1 010 1100 !! france 1 010 1100 !! germany 1 010 1100 !! greece 1 010 1100 ! ! guam 0 00 10 0 0 !!! hong kong 0 00 10 0 0 !!! hungary 0 00 10 0 0 !!! iceland 1 010 1100 !! notes: 1. tbr21 includes the following countries: austria, belgium, denmark, finland, france, germany, greece, iceland, ireland, italy, luxembourg, netherlands, norway, portugal, spain, sweden, switzerland, and the united kingdom. 2. supported for loop currents 20 ma. 3. products using the si3011/17 which have been submitted fo r jate approval should document a waiver for the jate dc termination specification. this specification is met in the si3018 global line-side device.
si3052/17/11/18 rev. 1.0 29 india 0 00 10 0 0 !!! indonesia 0 00 10 0 0 !!! ireland 1 010 1100 !! israel 0 10 11 0 0 !! italy 1 010 1100 !! japan 0 00 01 0 0 !! 3 ! 3 jordan 0 00 01 0 0 ! kazakhstan 0 00 01 0 0 ! kuwait 0 00 10 0 0 !!! latvia 0 10 11 0 0 !! lebanon 0 10 11 0 0 !! luxembourg 1 010 1100 !! macao 0 00 10 0 0 !!! malaysia 2 000 0100 ! malta 0 10 11 0 0 !! mexico 0 00 10 0 0 !!! morocco 0 10 11 0 0 !! netherlands 1 010 1100 !! new zealand 0 11 10 0 0 ! nigeria 0 10 11 0 0 !! norway 1 010 1100 !! oman 0 00 01 0 0 ! pakistan 0 00 01 0 0 ! peru 0 00 10 0 0 !!! philippines 0 00 01 0 0 ! poland 0 00 10 1 1 ! portugal 1 010 1100 !! romania 0 00 10 0 0 !!! russia 0 00 01 0 0 ! saudi arabia 0 00 10 0 0 !!! singapore 0 00 10 0 0 !!! slovakia 0 00 10 0 0 !!! slovenia 0 10 11 0 0 !! south africa 1 00 10 1 0 ! south korea 0 00 10 1 0 ! table 14. country specific register settings (continued) offset 0x40 line-side country ohs act2,act dct[1:0] rz rt 3018 3011 3017 notes: 1. tbr21 includes the following countries: austria, belgium, denmark, finland, france, germany, greece, iceland, ireland, italy, luxembourg, netherlands, norway, portugal, spain, sweden, switzerland, and the united kingdom. 2. supported for loop currents 20 ma. 3. products using the si3011/17 which have been submitted fo r jate approval should document a waiver for the jate dc termination specification. this specification is met in the si3018 global line-side device.
si3052/17/11/18 30 rev. 1.0 initialization when the si3052 is initia lly powered up, the reset pin must be asserted. when the reset pin is de-asserted, the registers have their default values. the daa registers cannot be accessed during the crystal warm- up period. the following is an example initialization procedure: 1. select the crystal frequency using the xtal bit (offset0x28, bit24). 2. poll the daa status bit (offset 0x4, bit 23) until it indicates the daa is ready. 3. select the desired sample rate using the src bits (offset 0x37, bits 3:0). 4. power up the line side by clearing the pdl bit (offset0x36, bit4). 5. enable aout by setting arm[1:0] (offset 0x36, bits 5:0) and atm[1:0] (offset 36, bits 6:1) to the desired level. 6. set the required line interfac e parameters (i.e., dct[1:0], act, ohs, and rt) as defined in table 14. 7. prior to receiving or transmitting data, ensure fdt (offset 3c, bit 6) is set indicating the si3018 is ready for normal operation. after the procedure is complete, the daa is ready for off-hook, on-hook line monito ring, and ring detection. isolation barrier the si3052 achieves an isolation barrier through low- cost, high-voltage capacitors in conjunction with silicon laboratories? proprietary isocap? signal processing techniques. these techniques eliminate signal degradation from capacitor mismatches, common mode interference, or noise coupling. the c1, c2, c8, and c9 capacitors isolate the si3052 system-side device from the si3017/11/18 line-side device. all transmit, receive, control, ring detect, and caller id data are communicated through this barrier. y2 class capacitors can be used to achieve surge performance of 5 kv or greater. the isocap communications link is disabled by default. to enable it, the pdl bit (offset 0x36, bit 4) must be cleared. no communication between the si3052 and si3017/11/18 can occur until this bit is cleared and the fdt bit (offset 0x3c, bit 6) is high. parallel handset detection the si3052 can detect a parallel handset going off- hook. when the si3052 is off-hook, the loop current can be monitored via the lcs bits (offset 0x3c, bits 4:0). a significant drop in loop current can signal a parallel handset going off-hook. if a parallel handset causes the lcs bits to read 0s, the dropout detect interrupt bit (offset 0x34, bit 3) can be checked to verify that a valid line still exists. spain 1 010 1100 !! sweden 1 010 1100 !! switzerland 1 010 1100 !! syria 0 00 01 0 0 ! taiwan 0 00 10 0 0 !!! thailand 0 00 01 0 0 ! uae 0 00 10 0 0 !!! united kingdom 1 010 1100 !! usa 0 00 10 0 0 !!! yemen 0 00 10 0 0 !!! table 14. country specific register settings (continued) offset 0x40 line-side country ohs act2,act dct[1:0] rz rt 3018 3011 3017 notes: 1. tbr21 includes the following countries: austria, belgium, denmark, finland, france, germany, greece, iceland, ireland, italy, luxembourg, netherlands, norway, portugal, spain, sweden, switzerland, and the united kingdom. 2. supported for loop currents 20 ma. 3. products using the si3011/17 which have been submitted fo r jate approval should document a waiver for the jate dc termination specification. this specification is met in the si3018 global line-side device.
si3052/17/11/18 rev. 1.0 31 for the si3052 to operate in parallel with another handset, the parallel handset must have a sufficiently high dc termination to support two daas off-hook on the same line. improved parallel handset operation can be achieved by changing the dc impedance from 50 to 800 ? by setting the dcr bit (offset 0x4a, bit 0) and setting dcv[1:0] (offset 0x4a, bits 7:6) to 00b. map = 1 is necessary to access the dcr and dcv bits. loop current sensing the si3052 measures loop cu rrent. the lcs[4:0] bits (offset 0x3c, bits 4:0) report loop current measurements when off-hook. the following can be determined with the lcs bits: ! when off-hook, detect if a parallel phone goes on- or off-hook. ! determine if sufficient loop current is available to operate. ! detect if there is an overload condition (see "overload detection" on page 37). loop current measurement when the si3052 is off-hook, the lcs bits measure loop current in 3.3 ma/bit resolution. these bits detect another phone going off-hook by monitoring the dc loop current. the line current sense transfer function is shown in figure 22 and is detailed in table 15. the lcs bits display loop current down to the minimum operation loop current for the daa, wh ich is set by the mini[1:0] bits. when the lcs bits have reached their maximum value, the loop current sense overload interrupt bit fires; however, lcsi firing does not necessarily guarantee that an overload situation has occurred. an overload situation in the daa is determined by the status of the opd bit. after the lcsi interrupt fires, the opd bit should be checked to determine if an overload situation exists. the opd bit indicates an overload situation when loop current exceeds either 160 ma (ilim = 0) or 60 ma (ilim = 1). figure 22. typical lcs transfer function (ilim = 0) 0 3.3 6.6 9.9 13.2 16.5 19.8 23.1 26.4 33 36.3 39.6 42.9 46.2 49.5 52.8 56.1 59.7 62.7 66 69.3 72.6 75.9 79.2 127 82.5 85.8 89.1 92.4 95.7 99 102.3 loop current (ma) lcs bits 29.7 0 5 10 15 20 25 30 overload table 15. loop current transfer function lcs[4:0] condition 00000 insufficient line current for normal operat ion. use the dodi bit (offset 0x34, bit 3) to determine if a line is still connected. 00100 minimum line current for normal operation. (mini[1:0] = 01) 11111 loop current may be excessive. for fcc, low voltage, and jate termination, cur- rent may be >120 ma. for tbr21, current may be >60 ma. use the opd bit (offset 0x43, bit 1) to determine if an overload condition exists.
si3052/17/11/18 32 rev. 1.0 off-hook the software generates an off-hook command by setting the oh bit (offset 0x35, bit 0). this state seizes the line for incoming/outgoing calls and can also be used for pulse dialing. when on-hook, negligible dc current flows through the hookswitch. when off-hook, the hookswitch transistor pair, q1 and q2, turn on. a termination impedance is applied across tip and ring and causes dc loop current to flow. the termination impedance has an ac and dc component. several events occur internally to the daa when the oh bit is set. there is a 250 s latency for the off-hook command to communicate to the line-side device. when the line-side device goes off-hook, an off-hook counter forces a delay before transmission or reception can occur. this off-hook counter time is controlled by the foh[1:0] bits (offset 0x4f, bits 6:5). the default setting for the off-hook counter time is 128 ms, but can be adjusted up to 512 ms or down to either 64 or 8 ms. after the off-hook counter expires, a resistor calibration is performed for 17 ms. the resistor calibration can be disabled by setting the rcald bit (offset 0x49, bit 5). after the resistor calibration is performed, an adc calibration is performed for 256 ms. the adc calibration can be disabled by setting the cald bit (offset 0x41, bit 5). refer to "calibration" on page 37 for information on automatic and manual calibration. disabling the resistor and the adc calibrations should only be done when a fast response is needed after going off-hook, such as when responding to a type ii caller-id signal. see "caller id" on page 36. to calculate the total time required to go off-hook and start transmission or reception, the digital filter delay (typically 1.5 ms with the fi r filter) should be included in the calculation. dc termination the si3052 has four programmable dc termination modes that are selected with the dct[1:0] bits (offset 0x40, bits 3:2). fcc mode (dct[1:0] = 10 b ), shown in figure 23, is the default dc termination mode and supports a transmit full scale level of ?0.5 dbm at tip and ring. this mode meets fcc requirements and the requirements of many other countries. figure 23. fcc mode i/v characteristics tbr21 mode (dct[1:0] = 11 b ), shown in figure 24, provides current limiting wh ile maintaining a transmit full-scale level of ?0.5 dbm at tip and ring. the dc termination current limits before reaching 60 ma. figure 24. tbr21 mode i/v characteristics japan mode (dct[1:0] = 01 b ), shown in figure 25, is a lower voltage mode and supports a transmit full-scale level of ?0.5 dbm. the lo w voltage requirement is dictated by countries, such as japan and malaysia. 12 11 10 9 8 7 6 fcc dct mode .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 loop c urrent (a) voltage across d aa (v) ctr21 dct mode loop current (a) voltage across daa (v) 0.15 0.2 0.25 0.3 0.4 0.45 0.5 0.55 0.6 5 10 15 25 25 30 35 40 45 0.35
si3052/17/11/18 rev. 1.0 33 figure 25. japan mode i/v characteristics low-voltage mode (dct[1:0] = 00 b ), shown in figure 26, is the lowest line voltage mode supported on the si3052, with a transmit full-scale level of ?0.5 dbm. this low-voltage mode is offered for situations that require low line voltage operation. figure 26. low-voltage mode i/v characteristics ac termination the si3052 has four ac termination impedance settings. the act and act2 bits select the ac impedance. the available ac termination settings are listed in table 16. transhybrid balance the si3052 contains an on-chip analog hybrid that performs the 2- to 4-wire conversion and near-end echo cancellation. this hybrid circ uit is adjusted for each ac termination setting selected. the si3052 also offers a digital hybrid for additional near-end echo cancellation. for each ac termination setting selected, the eight programmable hybrid registers (offsets 0x5d?0x64) can be programmed with coefficients to increase cancellation of real-world line characteristics. the digital filter can produce 10 db or greater of near-end echo cancellation in addition to the echo cancellation provided by the analog hybrid circuitry. ring detection the ring signal is connected from tip and ring to the rng1 and rng2 pins. the si3052 supports either full- or half-wave ring detection. full-wave ring detection detects a polarity reversal and the ring signal. see ?caller id? on page 36. the ring detection threshold is programmable with the rt bit (offset 0x40, bit 0). the ring detector output can be monitored with the register bits rdtp, rdtn, and rdt (offset 0x35, bits 6, 5, and 2). software must dete ct the frequency of the ring signal to distinguish a ring from pulse dialing by telephone equipment connected in parallel. alternatively, hardware ring validation can be used. see "ring validation" on page 34. the ring detector mode is controlled by the rfwe bit (offset 0x42, bit 1). when the rfwe bit is 0 (default mode), the ring detector operates in half-wave rectifier mode. only positive ring si gnals are detected. a positive ring signal is defined as a voltage greater than the ring threshold across rng1-rng2. conversely, a negative japan dct mode loop current (a) voltage across daa (v) 10.5 10 8.5 9 8 7.5 7 6.5 6 5.5 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 9.5 low voltage mode loop current (a) voltage across daa (v) 10.5 10 8.5 9 8 7.5 7 6.5 6 5.5 .01 .02 .03 .04 .05 .06 .07 .08 .09 .1 .11 9.5 table 16. ac termination settings act2 act ac termination 0 0 real, nominal 600 ? termination that satisfies the impedance requirements of fcc part 68, jate, and other countries. 0 1 complex impedance that satisfies global complex impedance requirements. 1 0 complex impedance that satisfies global complex impedance requirements except new zealand. achieves higher return loss for some complex ac termi- nation. 1 1 complex impedance for use in new zealand.
si3052/17/11/18 34 rev. 1.0 ring signal is defined as a voltage less than the negative ring threshold across rng1-rng2. when the rfwe bit is 1, the ring detector operates in full-wave rectifier mode. po sitive and negative ring signals are detected. the rdtp and rdtn behavior is based on the rng1- rng2 voltage. when the signal on rng1-rng2 is above the positive ring thre shold, the rdtp bit is set. when the signal on rng1-rng2 is below the negative ring threshold, the rdtn bi t is set. when the signal on rng1-rng2 is between these thresholds, neither bit is set. the rdt behavior is also based on the rng1-rng2 voltage. when the rfwe bit is 0, a positive ring signal sets the rdt bit for a period of time. when the rfwe bit is 1, either a positive or negative ring signal sets the rdt bit. the rdt bit acts like a one shot. when a new ring signal is detected, the one shot is reset. if no new ring signals are detected before the one shot counter reaches 0, the rdt bit returns to 0. the length of this count (in seconds) is 65536 divided by the sample rate. the rdt bit is also reset to 0 by an off-hook event. ring validation this feature prevents false triggering of a ring detection by validating the ring parame ters. invalid signals, such as line-voltage changes when a parallel handset goes off-hook, pulse dialing, and high-voltage line tests, are ignored. ring validation can be enabled during normal operation and in low-power sleep mode. the ring validation circuit operates by calculating the time between alternating crossings of positive and negative ring thresholds to validate that the ring frequency is within tolerance. high- and low-frequency tolerances are programmable in the ras[5:0] and rmx[5:0] fields. the rcc[2:0] bits define the length of time the ring signal must be within tolerance. once the duration of the ring frequency is validated by the rcc bits, the circuitry stops checking for frequency tolerance and begins checking for the end of the ring signal, which is defined by a lack of additional threshold crossings for a period of time configured by the rto[3:0] bits. when the ring frequency is first validated, a timer defined by the rdly[2:0] bits is started. if the rdly[2:0] timer expires before the ring timeout, the ring is validated, and a valid ring is indicated. if the ring timeout expires before the rd ly[2:0] timer, a valid ring is not indicated. ring validation requires five parameters: ! timeout parameter to place a lower limit on the frequency of the ring signal on the ras[5:0] bits (offset 0x48, bits 5:0). the frequency is measured by calculating the time betw een crossings of positive and negative ring thresholds. ! minimum count to place an upper limit on the frequency on the rmx[5:0] bits (offset 0x46, bits 5:0). ! time interval over which the ring signal must be the correct frequency on the rcc[ 2:0] bits (offset 0x47, bits 2:0). ! timeout period that defi nes when the ring pulse has ended with the most recent ring threshold crossing on the rto [3:0] bits (offset 0x47, bits 6:3). ! delay period between when the ring signal is validated and when a valid ring signal is indicated to help accommodate distinctive ring on the rdly [2:0] bits (offset 0x47, bit 7; offset 0x46, bits 7:6) the ring validation enable bit, rngv (offset 0x48,bit 7), enables or disables the ring validation feature in normal operating mode and low-power sleep mode. ringer impedance and threshold the ring detector in many daas is ac coupled to the line with a large 1 f, 250 v decoupling capacitor. the ring detector on the si3052 is resistively coupled to the line. the network produces a high ringer impedance to the line of approximately 20 m ? to meet the majority of country ptt specifications including fcc and tbr21. several countries including poland, south africa, and slovenia require a maximum ringer impedance that can be met with an internally-synthesized impedance by setting the rz bit (offset 0x40, bit 1). countries also specify ringer thresholds differently. the rt bit (offset 0x40, bit 0) selects between two different ringer thresholds: 15 v 10% and 21.5 v 10%. these two settings satisfy ringer threshold requirements worldwide. the thresholds are set so that a ring signal is guaranteed to not be detected below the minimum, and a ring signal is guaranteed to be detected above the maximum. dtmf dialing the si3018 meets all the country requirements for dtmf dialing listed in table 14 on page 28. if desired, higher dtmf levels can be achieved by setting the dial bit (offset 0x42, bi t 6) at low loop currents (<15 ma). higher dtmf levels can also be achieved if the amplitude is increased and the peaks of the dtmf signal are clipped at digital full scale, avoiding wrapping the waveform.
si3052/17/11/18 rev. 1.0 35 clipping the signal prod uces distortion and intermodulation of the signal. generally, increased distortion between 10?20% is acceptable during dtmf signaling. several db higher dtmf levels can be achieved with this technique, compared with a digital full-scale peak signal. pulse dialing and spark quenching going off- and on-hook to generate make and break pulses accomplishes pulse dialing. the nominal rate is 10 pulses per second. some countries have tight specifications for pulse fi delity including make and break times, make resistance , and rise and fall times. in a traditional solid-state dc holding circuit, there are considerations for meeting these requirements. the si3052 dc holding circuit has active control of the on-hook and off-hook transients to maintain pulse dialing fidelity. spark quenching requirements in countries, such as italy, the netherlands, south africa, and australia, address the on-hook transition during pulse dialing. these tests provide an inductive dc feed resulting in a large voltage spike. a spike is caused by the line inductance and the sudden decrease in current through the loop when going on-hook. the traditional way of addressing this problem is to put a parallel rc shunt across the hookswitch relay. the capacitor is large (~1 f, 250 v) and relatively expensive. in the si3052, the ohs bit (offset 0x40, bit 6), ohs2 bit (offset 0x4f, bit 3), and sq[1:0] bits (offset 0x6b, bits 6,4) can ramp down the loop current to pass these tests without requiring additional components. a slow ramp-down of the loop current introduces a delay between the time the oh bit is cleared and the time the daa actually goes on-hook. to ensure proper operation of the daa during pulse dialing, disable the automatic resistor calibration that is performed each time the daa enters the off-hook state by setting the rcald bit. billing tone det ection and receive overload ?billing tones? or ?metering pulses? generated by the central office can produce modem connection difficulties. the billing tone is a 12 or 16 khz signal and is occasionally used in germany, switzerland, and south africa. depending on line conditions, the billing tone might be large enough to cause major errors related to the modem data. the si3052 chipset can provide feedback indicating the beginning and end of a billing tone. billing tone detection is en abled by setting the bte bit (offset 0x41, bit 2). b illing tones less than 1.1 v pk on the line are filtered out by the low-pass digital filter on the si3052. the rov bit (offse t 0x41, bit 1) is set when a line signal is greater than 1.1 v pk , indicating a receive overload condition. the btd bit (offset 0x41, bit 0) is set when a line signal (billin g tone) is la rge enough to excessively reduce the line-de rived power supply of the si3018 line-side device. when the btd bit is set, the dc termination is changed to an 800 ? dc impedance to ensure minimum line voltag e levels even in the presence of billing tones. the ovl bit (offset 0x43, bit 2) can be pulled following a billing tone detection. when the ovl bit returns to 0, indicating that the billing t one has passed, the rov bit remains sticky and must be written to 0 to be reset. after the billing tone passes, th e daa initiates an auto- calibration sequence that must complete before data can be transmitted. certain line events, such as an off-hook event on a parallel phone or a polarity reversal, can trigger the rov or the btd bits, after which the rov bit must be reset. look for multiple events before qualifying if billing tones are actually present. although the daa remains of f-hook during a billing tone event, the received data from the line is corrupted when a large billing tone occurs. to receive data through a billing tone, an exte rnal lc filter must be added. a modem manufacturer can provide this filter in the form of a dongle that connects on the phone line before the daa. the manufacturer does not have to include a costly lc filter internal to the modem when it is only necessary to suppor t a few countries. alternatively, when a billing tone is detected, the system software can notify the user that a billing tone has occurred. the user can contact the telephone company to disable the billing tones or to purchase an external lc filter. billing tone filter (optional) to operate without degrada tion during billing tones in germany, switzerland, and south africa, an external lc notch filter is required. the si3052 can remain off-hook during a billing tone event, bu t modem data is lost in the presence of large billing tone signals. the notch filter design requires two notches, one at 12 khz and one at 16 khz. because these components are fairly expensive and few co untries supply billing tone support, this filter is placed in an external dongle or added as a population option for these countries. figure 27 shows an example billin g tone filter. l1 must carry the entire loop current. the series resistance of the inductors is important to achieve a narrow and deep notch. this design has more than 25 db of attenuation at 12 and 16 khz.
si3052/17/11/18 36 rev. 1.0 figure 27. billing tone filter the billing tone filter affect s the daa?s ac termination and return loss. the curren t complex ac termination passes worldwide return loss specifications with and without the billing tone filter by at least 3 db. the ac termination is optimized for frequency response and hybrid cancellation while having greater than 4 db of margin with or without the dongles for south africa, australia, tbr21, germany, and switzerland country- specific specifications. on-hook line monitor the si3052 receives line activity when in an on-hook state through the rng1/2 pins. this mode detects caller id data and no line current is drawn. see ?caller id? on page 36. this mode is enabled by setting the onhm bit (offset 0x35, bit 3). arx [2:0] (offset 0x3f, bits 2:0) provides gain to the normal receive path of the daa and functions as a gain bit for the on-hook line monitor. caller id the si3052 can pass caller id data from the phone line to a software caller id decoder. type i caller id type i caller id sends the cid data while the phone is on-hook. in systems where the caller id data is passed on the phone line between the first and second rings, utilize the following method to capture the caller id data: 1. after identifying a ring signal using one of the methods described in "ring detection" on page 33, determine when the first ring has completed. 2. assert the onhm bit (offset 0x35, bit 3) to enable current caller id. 3. the low-current adc, which is powered from the system- side device, digitizes the caller id data passed across the rng 1/2 pins. 4. clear the onhm bit after the caller id data is received. in systems where the caller id data is preceded by a line polarity (battery) reversal, use the following method to capture the caller id data: 1. enable full-wave rectified ring detection (offset 0x42, bit 1). 2. monitor the rdtp and rdtn register bits to identify whether a polarity reversal or ring signal has occurred. a polarity reversal trips either the rdtp or rdtn ring detection bits, and, thus, the full-wave ring detector must be used to distinguish a polarity reversal from a ring. the lowest specified ring frequen cy is 15 hz; therefore, if a battery reversal occurs, the dsp software should wait a minimum of 40 ms to verify that the event observed is a battery reversal and not a ring signal. this time is greater than half the period of the l ongest ring signal. if another edge is detected during this 40 ms pause, this event is characterized as a ring signal and not a battery reversal. 3. assert the onhm bit (offset 0x35, bit 3) to enable the low- current caller id adc. the low-current adc, which is powered from the system-side device, digitizes the caller id data passed across the rng 1/2 pins. 4. clear the onhm bit after the caller id data is received. type ii caller id type ii caller id sends the cid data while the phone is off-hook and is often referred to as caller id/call waiting (cid/cw). to receive the cid data while off-hook, use the following procedure: 1. the caller alert signal (cas) tone is sent from the central office (co) and is digitized along with the line data. the software must detect the presence of this tone. 2. since the si3052 is the only device on the line and is type ii cid-compliant, the software must mute its upstream data output to avoid propagation of its reply tone and the subsequent cid data. after muting its upstream data output, the software must then return an acknowledgement (ack) tone to the co to request the table 17. component values?optional billing tone filters symbol value c1,c2 0.027 f, 50 v, 10% c3 0.01 f, 250 v, 10% l1 3.3 mh, >120 ma, <10 ? , 10% l2 10 mh, >40 ma, <10 ? , 10% l2 c3 ring tip from line to daa c1 c2 l1
si3052/17/11/18 rev. 1.0 37 transmission of the cid data. 3. the co then responds with th e cid data, and the software unmutes the upstream data output and continues with normal operation. 4. the muting of the upstream data path by the software mutes the handset in a telephone application so the user cannot hear the acknowledgement tone and cid data being sent. the cid data presented to the software could have up to a 10% dc offset. the software caller id decoder must either use a high-pass or a band-pass filter to accurately retrieve the caller id data. overload detection the si3052 can be programmed to detect an overload condition that exceeds the normal operating power range of the daa circuit. to use the overload detection feature, the following steps should be performed: 1. set the oh bit (offset 0x35, bit 0) to go off-hook, and wait 25 ms to allow line transients to settle. 2. enable overload detection by setting the ope bit (offset0x41, bit3). if the daa senses an overload situation, it automatically presents an 800 ? impedance to the line to reduce the hookswitch current. at this time, the daa also sets the opd bit (offset 0x43, bit 0) to indicate that an overload condition exists. the line cu rrent detector within the daa has a threshold that is dependant upon the ilim bit (offset 0x4a, bit 1). when ilim = 0, the overload detection threshold equals 160 ma. when ilim = 1, the overload detection threshold equals 60 ma. the ope bit should always be cleared before going off-hook. gain control the si3052 supports multiple receive gain and transmit attenuation settings (offset 0x3f). the receive path supports gains of 0, 3, 6, 9, and 12 db, as selected with the arx[2:0] bits. the receive path can be muted with the rxm bit. the transmit path supports attenuations of 0, 3, 6, 9, and 12 db, as selected with the atx[2:0] bits. the transmit path can be muted with the txm bit. sample rate converter the scr [3:0] bits (offset 0x37, bits 3:0) are used to select the sample rate. th e following sample rates are supported: 7200, 8000, 8229, 8400, 9000, 9600, 10286, 12000, 13714, and 16000 hz. filter selection the si3052 supports two filter selections for the receive and transmit signals as defined in table 10 and table 11 on page 13. the iire (offset 0x40, bit 4) selects between the iir and fir filters. the iir filter provides a lower, but non-linear, group delay than the default fir filter. power management the si3052 supports four basic power management operation modes: normal operation, reset operation, sleep mode, and full powerdown mode. the power management modes are controlled by the pdl and pdn bits (offset 0x36, bits 4,3). on powerup or following a rese t, the si3052 is in reset operation. the pdl bit is set, and the pdn bit is cleared. the si3052 is fully-operational except for the isocap? link. no communication between the si3052 and si3017/11/18 can occur during reset operation. bits associated with the si3017/11/18 are not valid in this mode. the most common mode of operation is normal operation. the pdl and pdn bits are cleared. the si3052 is fully-operational, and the isocap link is passing information between the si3052 and the si3017/11/18. a valid sample rate must be programmed before entering this mode. the si3052 supports a low-power sleep mode for the wake-up-on-ring feature of many modems. the sample rate must be programmed with a valid non-zero value before enabling sleep mode. the pdn bit must then be set and the pdl bit cleared. the si3052 is non- functional except for the isocap link signal. to take the si3052 out of sleep mode, pulse (reset ) low. in summary, the powerdown/up sequence for sleep mode is as follows: 1. src[3:0] must have a valid non-zero value. 2. set the pdn bit (offset 0x36, bit 3) and clear the pdl bit (offset 0x36, bit 4). 3. reset the si3052 by pulsing the reset pin. 4. program registers to required settings. the si3052 also supports an additional powerdown mode. when the pdn and pdl bits are set, the chipset enters a complete powerdown mode and draws negligible current (deep sleep mode). normal operation is restored using the same process for taking the si3052 out of sleep mode. calibration the si3017/11/18 initiates an auto-calibration by default when the device goes off-hook or experiences a loss in line power. calibration removes offsets that are present in the on-chip adc and which could affect the adc dynamic range. auto-calibrati on is initiated after the daa dc termination stabilizes and takes 256 ms to complete. because of the large variation in line conditions and line card behavior that is presented to
si3052/17/11/18 38 rev. 1.0 the daa, it might be beneficial to use manual calibration instead of auto-calibration. execute manual calibration as close to 256 ms as possible before valid transmit/receive data is expected. the following steps implement manual calibration: 1. the cald (offset 0x41, bit 5) bit must be set to 1. 2. the mcal bit (offset 0x41, bit 6) must be toggled to one and then 0 to begin and complete the calibration. 3. the calibration is completed in 256 ms . in-circuit testing four loopback modes exist allowing increased coverage of system components. for three of the test modes, an off-hook sequence must be performed. for the start-up test mode, no line-side power is necessary, and no off-hook sequence is required. the start-up test mode is enabled by default. when the pdl bit (offset 0x36, bit 4) is set (the default case), the line- side is in a powerdown mode, and the pci side is in a digital loop-back mode. data received is passed through the internal filters and transmitted. this path introduces approximately 0.9 db of attenuation. there is a group delay of transmit and receive filters. clearing the pdl bit disables this mode, and the data is switched to the receive data from the line-side. when the pdl bit is cleared, the fdt bit (offse t 0x3c, bit 6) becomes active indicating the successful communication between the si3017/11/18 and the si3052. this verifies that the isocap? link is operational. the remaining test modes require an off-hook sequence to operate. the following sequence defines the off-hook requirements: 1. powerup or reset. 2. program the required sample rate. 3. enable line-side device by clearing pdl bit. 4. issue off-hook 5. allow calibration to occur. 6. set required test mode. the isocap? digital loopback mode allows the data pump to provide a digital input test pattern and receive that digital test pattern back . to enable this mode, set the dl bit (offset 0x31, bit 1). the isolation barrier is actually being tested. the digital stream is delivered across the isolation capacitors (c1 and c2) to the line- side device and returned across the same barrier. while an off-hook sequence is necessary, a valid line feed is not needed for this test. the analog loopback mode allows an external device to drive a signal on the telephone line into the si3017/11/18 line-side devic e and have it driven back out onto the line. this mode is for testing external components connecting the rj-11 jack (tip and ring) to the si3017/11/18. to enable this mode, set the al bit (offset 0x32, bit 3). the final testing mode, internal analog loopback, allows the system to test the basic operation of the transmit and receive paths on the line-side device and the external components. in this test mode, the data pump provides a digital test waveform. data is passed across the isolation barrier, transmitted to and received from the line, passed back across the isolation barrier, and presented to the data pump. to enable this mode, clear the hbe bit (offset 0x32, bit 1). the test circuit in figure 2 on page 11 is an adequate line feed for this test. note: all test modes are mutually-e xclusive. if more than one test mode is enabled concurrently, the results are unpredictable. revision identification the revision of the system side (si3052) and line side (si3017/11/18) can be determined using the srev[3:0] bits (offset 0x3b, bits 3:0) and lrev[3:0] bits (offset 0x3d, bits 5:2), respectively. table 18 lists the revision values. register map the si3052 is designed to provide backwards compatibility to previous de signs based on the si3035 and si3034 daas. when the map bit (offset 0x31, bit 6) is cleared (default value), the si3052 operates in this backwards-compatible mode. when the map bit is set, several bits in the regi ster map become available and several other bits are no longer accessible. the si3052 is designed to operate in either map = 1 or map = 0. following powerup or reset, the desired map mode should be selected prior to setting other bits, and the map mode should remain in the same state until the next power up or reset. table 19 shows the bits affected by the state of the map bit. table 18. revision values revision si3052 si3017/11/18 c 0011 0011 d 0100 0100
si3052/17/11/18 rev. 1.0 39 when map = 1, the atm[7:0] bits repl ace the atm[1:0] and txm bits. the arm[7:0] replaces the arm[1:0] and rxm bits. the dcv[1:0], mi ni[1:0], and ilim bits replace the dct[1:0] bi ts. table 20 lists the equivalent settings for dc termination. table 20 should be used to translate the dct[1:0] bits in table 14, ?country specific register settings,? on page 28. the dial, fjm, and vol[1:0] bits do not have a map = 1 equivalent and are unused. the dcr bit switches the dc termination into 800 ? mode. this is the same mode used by the billing tone detector and overload detector. the hybx registers are describe d in the section, "transhybrid balance" on page 33. table 19. bits selected by map bit map = 0 map = 1 atm[1:0], txm atm[7:0] arm[1:0], rxm arm[7:0] dct[1:0] dcv[1:0] dial mini[1:0] fjm ilim vol [1:0] dcr hybx[7:0] table 20. dc termination equivalents dcv[1:0] mini[1:0] ilim dct[1:0] = 00 (low voltage) 00 11 0 dct[1:0] = 01 (jate) 01 11 0 dct[1:0] = 10 (fcc) 10 00 0 dct[1:0] = 11 (tbr21) 10 00 1
si3052/17/11/18 40 rev. 1.0 pci configuration registers note: registers not listed here are re served and must not be written. table 21. pci register summary register name bits 00h pci device id and vendor id d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 did[15:0] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 vid[15:0] 04h pci status and command d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 dpe sse rmas rtas stas dst[1:0] dpd fbbc c66 cpm ints d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 intd fbbm see step pen mwi bme mae ioae 08h device revision identification d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 cc[23:8] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cc[7:0] rev[7:0] 0ch cache line size, master latency timer d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 ht[7:0] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mltc[5:0] cls[7:0] 10h memory base address d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 mba[31:16] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mba[15:0] 14h i/o base address d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 ioba[31:16] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ioba[15:0] 2ch subsystem id, subsystem vendor id d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 ssid[15:0] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 svid[15:0]
si3052/17/11/18 rev. 1.0 41 34h capabilities pointer d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cptr[7:0] 3ch max_lat, min_gnt, interrupt pin, interrupt line d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 mlat[7:0] mgnt[7:0] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 intp[7:0] intl[7:0] 40h retry time- out, trdy timeout d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 rt[7:0] tyt[7:0] 80h power management capabilities d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 p3c p3h pd2 pd1 pd0 d2s d1s auxc[2:0] dvs pcl ver[2:0] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 nxt[7:0] cid[7:0] 84h power management control and status (vaux powered) d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pms dsc[1:0] dse[3:0] pme pst[1:0] table 21. pci register summary (continued) register name bits
si3052/17/11/18 42 rev. 1.0 reset setting = 0x30521543 pci register 00h. pci device id and vendor id bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name did[15:0] type r bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name vid[15:0] type r bit name function 31:16 did[15:0] device identification. pci device id is 3052 for the si3052 device. 15:0 vid[15:0] vendor identification. pci vendor id is 1543 for silicon la boratories.
si3052/17/11/18 rev. 1.0 43 reset setting = 0x02900080 pci register 04h. pci status and command bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name dpe sse rmas rtas stas dst[1:0] dpd fbbc c66 cpm ints type rrrrr r rr rrr bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name intd fbbm see step pen mwi bme mae ioae type r/w r/w r/w r r/w r/w r/w r/w r/w bit name function 31 dpe detect parity error. 30 sse signaled system error. 29 rmas received master abort status. set when pci master terminates a host-to-pci transaction with a master abort. 28 rtas received target abort status. set when the si3052 initiates a pci transaction and it is terminated by the target. 27 stas signaled target abort status. 26:25 dst[1:0] device select timing. indicates timing of devsel when the si3052 responds to a pci transaction as a target. 24 dpd data parity detected. 23 fbbc fast back-to-back capable status flag. 22 reserved read returns zero. 21 c66 66 mhz capable status flag. 20 cpm capabilities list. pme supported. 19 ints interrupt status. 18:11 reserved read returns zero. 10 intd interrupt disable. 9 fbbm fast back-to-back master enable. 8 see system error enable 7step data stepping enable. 6 pen parity error enable. 5 reserved read returns zero. 4mwi memory write and invalidate enable. 3 reserved read returns zero. 2bme bus master enable. 1mae memory access enable. 0ioae i/o access enable.
si3052/17/11/18 44 rev. 1.0 reset setting = 0x07030003 reset setting = 0x00000000 pci register 08h. device revision identification bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name cc[23:8] type r bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name cc[7:0] rev[7:0] type r r bit name function 31:8 cc[23:0] class code. 7:0 rev[7:0] revision identification number. pci register 0ch. cache line size, master latency timer bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name ht[7:0] type r bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name mltc[5:0] cls[7:0] type r/w r/w bit name function 31:24 reserved read returns zero. 23:16 ht[7:0] header type. a single function, non-bridge type header format. 15:10 mltc[5:0] master latency timer count. sets the minimum number of pci clock cycle s that the si3052 is guaranteed access to the pci bus. after the count has expired, t he si3052 surrenders the pci bus when other pci master devices are granted the bus by th e arbiter. programmable in increments of 1ms. 9:8 reserved read returns zero. 7:0 cls[7:0] cache line size. all cache type transactions are aliases to normal reads and writes.
si3052/17/11/18 rev. 1.0 45 reset setting = 0x00000000 reset setting = 0x00000001 pci register 10h. memory base address bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name mba[31:16] type r/w bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name mba[15:0] type r/w bit name function 31:0 mba[31:0] memory base address. memory space is in 4096 byte increments. pci register 14h. i/o base address bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name ioba[31:16] type r/w bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name ioba[15:0] type r/w bit name function 31:0 ioba[31:0] i/o base address. i/o space is 256 bytes.
si3052/17/11/18 46 rev. 1.0 reset setting = n/a reset setting = 0x00000080 pci register 2ch. subsystem id, subsystem vendor id bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name ssid[15:0] type r bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name svid[15:0] type r bit name function 31:16 ssid[15:0] pci subsystem id. eprom or resistor id configurable. 15:0 svid[15:0] pci subsystem vendor id. eprom or resistor id configurable. pci register 34h. ca pabilities pointer bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name type bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name cptr[7:0] type r bit name function 31:8 reserved read returns zero. 7:0 cptr[7:0] capabilities pointer. location of pme information.
si3052/17/11/18 rev. 1.0 47 reset setting = 0x3e010100 reset setting = 0x00000000 pci register 3ch. max_lat, min_gnt, interrupt pin, interrupt line bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name mlat[7:0] mgnt[7:0] type rr bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name intp[7:0] intl[7:0] type rr/w bit name function 31:24 mlat[7:0] max_lat. sets the value of max_lat. see pci 2.2 spec ification, section 6.2.4 (250 ns units). the maximum latency between bus grants is limited to 62?250 ns. 23:16 mgnt[7:0] min_gnt. identifies the length of the burst period, assuming a 33 mhz clock (250 ns units). a mini- mum grant of 250 ns is required for burst transactions. 15:8 intp[7:0] interrupt pin. identifies which interrupt pin the si3 052 uses. default interrupt pin is inta . 7:0 intl[7:0] interrupt line. identifies the interrupt line register to which the si3052 is connected. pci register 40h. retry timeout, trdy timeout bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name type bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name rt[7:0] tyt[7:0] type rr bit name function 31:16 reserved read returns zero. 15:8 rt[7:0] retry timeout. sets number of retries that the si3052 as master performs. 7:0 tyt[7:0] trdy timeout. sets number of pci clocks that the si3052 as master waits for trdy.
si3052/17/11/18 48 rev. 1.0 reset setting = 0xc8420001 pci register 80h. power management capabilities bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name p3c p3h pd2 pd1 pd0 d2s d1s auxc[2:0] dvs pcl ver[2:0] type rrrrrrr r r r r bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name nxt[7:0] cid[7:0] type rr bit name function 31 p3c pme support d3 cold. anded with 3.3 vaux pin. 30 p3h pme support d3 hot. 29 pd2 pme support d2. not supported. 28 pd1 pme support d1. not supported. 27 pd0 pme support d0. 26 d2s d2 support. not supported. 25 d1s d1 support. not supported. 24:22 auxc[2:0] aux_current. less than 55 ma in d3 cold. 21 dvs device specific. 20 reserved read returns zero. 19 pcl pme clock. 18:16 ver[2:0] version. complies with ppm 1.1. 15:8 nxt[7:0] next item. 7:0 cid[7:0] capability id.
si3052/17/11/18 rev. 1.0 49 reset setting = 0x00000000 pci register 84h. power management control and status (vaux powered register) bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name type bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name pms dsc[1:0] dse[3:0] pme pst[1:0] type r/w r r r/w r/w bit name function 31:16 reserved read returns zero. 15 pms pme status (sticky). write 1 to clear. 14:13 dsc[1:0] data scale. no data register implemented. 12:9 dse[3:0] data select. no data register implemented. 8pme pme enable (sticky). 7:2 reserved read returns zero. 1:0 pst[1:0] power state. 00 = d0 01 = d1 (not supported) 10 = d2 (not supported) 11 = d3 hot
si3052/17/11/18 50 rev. 1.0 pci and daa control registers note: registers not listed here are re served and must not be written. table 22. pci register summary (32-bit) offset name bits 0x00 dma and interrupt control d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 mtie die wie taie maie rbie raie waie wbie d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dm[1:0] dmar dmae dmam dmai drst prst 0x04 dma and interrupt status d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 daa eer wfu wff wfe rfo rff rfe d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mto dis wis pta pma drb dra dwa dwb 0x08 dma read address start d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 dras[31:16] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dras[15:0] 0x0c dma read address stop d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 drap[31:16] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 drap[15:0] 0x10 dma read address interrupt d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 drai[31:16] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 drai[15:0] 0x14 current dma read address d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 cdra[31:16] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cdra[15:0] 0x18 dma write address start d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 dwas[31:16] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dwas[15:0]
si3052/17/11/18 rev. 1.0 51 0x1c dma write address stop d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 dwap[31:16] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dwap[15:0] 0x20 dma write address interrupt d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 dwai[31:16] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dwai[15:0] 0x24 current dma write address d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 cdwa[31:16] d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cdwa[15:0] 0x28 watchdog timer d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 stpm stpe xtal wts wtc d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 wdt[15:0] table 22. pci register summary (32-bit) (continued) offset name bits
si3052/17/11/18 52 rev. 1.0 table 23. daa register summary (8-bit) offset name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x31 control 1 sr map pwmm[1:0] pwme dl 0x32 control 2 wdte al rdm hbe rxe 0x33 interrupt mask rdtm rovm fdtm btdm dodm lcsm 0x34 interrupt source rd ti rovi fdti btdi dodi lcsi 0x35 daa control 1 rdtn rdtp onhm rdt oh 0x36 daa control 2 atm[1] 1 arm[1] 1 pdl pdn atm[0] 1 arm[0] 1 0x37 sample rate control src[3:0] 0x38 reserved 0x39 reserved 0x3a daa control 3 ddl 0x3b system-side revision lsid[3:0] srev[3:0] 0x3c line-side status fdt lcs[4:0] 0x3d line-side revision lrev[3:0] 0x3e reserved 0x3f tx/rx gain control txm 1 atx[2:0] rxm 1 arx[2:0] 0x40 international control 1 act2 ohs act iire dct[1:0] 1 rz rt 0x41 international control 2 calz mcal cald ope bte rov btd 0x42 international control 3 dial 1 fjm 1 vol[1:0] 1 rfwe 0x43 international control 4 ovl opd 0x44 aout rx attenuation arm[7:0] 2 0x45 aout tx attenuation atm[7:0] 2 0x46 ring validation control 1 rdly[1:0] rmx[5:0] 0x47 ring validation control 2 rdly[2] rto[3:0] rcc[2:0] 0x48 ring validation control 3 rngv ras[5:0] 0x49 resistor calibration rcald 0x4a dc termination control dcv[1:0] 2 mini[1:0] 2 ilim 2 dcr 2 0x4b reserved 0x4c reserved 0x4d reserved note: all register bits are available when map = 0 and map = 1 except 1. only available when map = 0 2. only available when map = 1
si3052/17/11/18 rev. 1.0 53 0x4e reserved 0x4f daa control 4 foh[1:0] ohs2 0x5d hybrid 1 hyb1[7:0] 2 0x5e hybrid 2 hyb2[7:0] 2 0x5f hybrid 3 hyb3[7:0] 2 0x60 hybrid 4 hyb4[7:0] 2 0x61 hybrid 5 hyb5[7:0] 2 0x62 hybrid 6 hyb6[7:0] 2 0x63 hybrid 7 hyb7[7:0] 2 0x64 hybrid 8 hyb8[7:0] 2 0x65 reserved 0x66 reserved 0x67 reserved 0x68 reserved 0x69 reserved 0x6a reserved 0x6b spark quenching control sq1 sq0 table 23. daa register summary (8-bit) (continued) offset name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 note: all register bits are available when map = 0 and map = 1 except 1. only available when map = 0 2. only available when map = 1
si3052/17/11/18 54 rev. 1.0 reset setting = 0x00000000 pci register offset 0x00 dma and interrupt control bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name mtie die wie taie maie rbie raie waie wbie type r/w r/w r/w r/w r/w r/w r/w r/w r/w bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name dm[1:0] dmar dmae dmam dmai drst prst type r/w r/w r/w r/w r/w r/w r/w bit name function 31:25 reserved read returns zero. 24 mtie dma master timeout interrupt enable. 0 = interrupt disable. 1 = interrupt enable. 23 die daa interrupt enable. 0 = interrupt disable. 1 = interrupt enable. 22 wie watchdog timer interrupt enable. 0 = interrupt disable. 1 = interrupt enable. 21 taie pci target abort interrupt enable. 0 = interrupt disable. 1 = interrupt enable. 20 maie pci master abort interrupt enable. 0 = interrupt disable. 1 = interrupt enable. 19 rbie dma read end of buffer interrupt enable. 0 = interrupt disable. 1 = interrupt enable. 18 raie dma read address interrupt enable. 0 = interrupt disable. 1 = interrupt enable. 17 waie dma write address interrupt enable. 0 = interrupt disable. 1 = interrupt enable. 16 wbie dma write end of buffer interrupt enable. 0 = interrupt disable. 1 = interrupt enable.
si3052/17/11/18 rev. 1.0 55 15:13 reserved read returns zero. 12:11 dm[1:0] data mode. 00 = direct. 01 = indirect, parallel. 10 = indirect, serial, lsb first. 11 = indirect, serial, msb first. 10 reserved read returns zero. 9dmar dma restart. 0 = dma continue. 1=dma restart. 8dmae dma enable. 0 = dma disable. 1 = dma enable. 7dmam dma master mode. 0 = multiple mode. 1 = single mode. 6dmai dma interrupt mode. 0 = interrupt status bit is sticky. 1 = interrupt status bit is non-sticky. applies to address and end-of-buffer interrupts. 5:2 reserved read returns zero. 1drst dma reset. 0 = dma continue. 1=dma reset. 0prst pci daa soft reset. 0 = normal operation. 1 = daa reset. the pci registers are not affected. all daa registers are reset to default values. write zero to clear. bit name function
si3052/17/11/18 56 rev. 1.0 reset setting = 0x00000000 pci register offset 0x04 dma and interrupt status bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name daa eer wfu wff wfe rfo rff rfe type rr r/wr/wr/wr/wr/w r/w bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name mto dis wis pta pma drb dra dwa dwb type r/w r/w r/w r/w r/w r/w r/w r/w r/w bit name function 31:24 reserved read returns zero. 23 daa daa status. 0 = daa ready. 1 = daa not ready. 22 eer eprom read status. 0 = no status. 1 = eprom read failure. 21 wfu dma write fifo underrun. 20 wff dma write fifo full. 19 wfe dma write fifo empty. 18 rfo dma read fifo overrun. 17 rff dma read fifo full. 16 rfe dma read fifo empty. 15:9 reserved read returns zero. 8mto dma master timeout status. 0 = normal operation. 1 = master timeout from trdy timer or retry timer. write 1 to clear. 7dis daa interrupt status. 0 = normal operation. 1 = daa interrupt has occurred. write 1 to clear. 6wis watchdog timer interrupt status. 0 = normal operation. 1 = watchdog timer has expired. write 1 to clear. 5pta pci target abort interrupt status. 0 = normal operation. 1 = pci target abort has occurred. write 1 to clear.
si3052/17/11/18 rev. 1.0 57 4pma pci master abort interrupt status. 0 = normal operation. 1 = pci master abort has occurred. write 1 to clear. 3drb dma read end of buffer interrupt status. 0 = normal operation. 1 = dma read has reached end of buffer. write 1 to clear. 2dra dma read address interrupt status. 0 = normal operation. 1 = dma read has reached interrupt address. write 1 to clear. 1dwa dma write address interrupt status. 0 = normal operation. 1 = dma write has reached interrupt address. write 1 to clear. 0dwb dma write end of buffer interrupt status. 0 = normal operation. 1 = dma write has reached end of buffer. write 1 to clear. bit name function
si3052/17/11/18 58 rev. 1.0 reset setting = 0x00000000 reset setting = 0x00000000 pci register offset 0x08 dma read address start bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name dras[31:16] type r/w bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name dras[15:0] type r/w bit name function 31:0 dras[31:0] dma read address start. pci register offset 0x0c dma read address stop bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name drap[31:16] type r/w bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name drap[15:0] type r/w bit name function 31:0 drap[31:0] dma read address stop.
si3052/17/11/18 rev. 1.0 59 reset setting = 0x00000000 reset setting = 0x00000000 pci register offset 0x10 dma read address interrupt bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name drai[31:16] type r/w bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name drai[15:0] type r/w bit name function 31:0 drai[31:0] dma read address interrupt. pci register offset 0x14 current dma read address bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name cdra[31:16] type r bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name cdra[15:0] type r bit name function 31:0 cdra[31:0] current dma read address.
si3052/17/11/18 60 rev. 1.0 reset setting = 0x00000000 reset setting = 0x00000000 pci register offset 0x18 dma write address start bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name dwas[31:16] type r/w bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name dwas[15:0] type r/w bit name function 31:0 dwas[31:0] dma write address start. pci register offset 0x1c dma write address stop bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name dwap[31:16] type r/w bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name dwap[15:0] type r/w bit name function 31:0 dwap[31:0] dma write address stop.
si3052/17/11/18 rev. 1.0 61 reset setting = 0x00000000 reset setting = 0x00000000 pci register offset 0x20 dma write address interrupt bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name dwai[31:16] type r/w bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name dwai[15:0] type r/w bit name function 31:0 dwai[31:0] dma write address interrupt. pci register offset 0x24 current dma write address bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name cdwa[31:16] type r bitd15d14d13d12d11d10d9d8d7d6d5d4d3d2d1 d0 name cdwa[15:0] type r bit name function 31:0 cdwa[31:0] current dma write address.
si3052/17/11/18 62 rev. 1.0 reset settings = 0x02000000 pci register offset 0x28 watchdog timer bit d31 d30 d29 d28 d27 d26 d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 name stpm stpe xtal wts wtc type r/w r/w r/w r/w r/w bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name wdt[15:0] type r/w bit name function 31:27 reserved read returns zero. 26 stpm address/data stepping mode. 0 = 4 steps. 1 = 2 steps. 25 stpe address/data stepping enable. 0 = disabled. 1 = enabled. 24 xtal external crystal frequency select. 0 = 16.384 mhz 1 = 32.768 khz 25:18 reserved read returns zero. 17 wts pci watchdog timer status. 0 = watchdog timer idle/counting. 1 = watchdog timer expired. 16 wtc pci watchdog timer control. 0 = watchdog timer disabled. 1 = watchdog timer enabled. when set this bit is cleared by a hardware reset. 15:0 wdt[15:0] pci watchdog timer. timer is free running and clocked by the pci system clock. for 33 mhz pci, the timer increments every (256/33 mhz) = 7.76 s. the timer overflows in 508 ms without register accesses, generating an interrupt and stopping dma operations.
si3052/17/11/18 rev. 1.0 63 reset settings = 0000_0000 daa register offset 0x31 control 1 bitd7d6d5d4d3d2d1d0 name sr map pwmm[1:0] pwme dl type r/w r/w r/w r/w r/w bit name function 7sr software reset. 0 = enables si3052 for normal operation. 1 = sets all registers to their reset value. note: bit clears automatica lly after being set. 6map register map. 0 = basic register set (si3014 compatible) selected. 1 = enhanced register set selected. note: this bit should be set during initialization only. 5:4 pwmm[1:0] pulse-width modulation mode. selects the type of signal on the call progress aout pin. 00 = pwm output clocked at 16.384 mhz. a lo cal density of 1s and 0s tracks the com- bined transmit and receive signal. 01 = balanced conventional pwm output signal has high and low portions of the modu- lated pulse centered on the 32 khz sample clock. 10 = conventionally pwm output signal returns to 0 at 32 khz intervals and rises at a time in the 32 khz period proportional to the instantaneous amplitude. 11 = reserved 3pwme pulse-width modulation enable. 0 = call progress pwm aout disabled. 1 = call progress pwm aout enabled. 2 reserved read returns zero. 1dl isolation digital loopback. 0 = digital loopback across isolation barrier disabled. 1 = enables digital loopback mode across isolation barrier. the line-side device must be enabled and off-hook before setting this mode. this data path includes rx and tx filters. a valid phone line is not necessary for this mode. 0 reserved read returns zero.
si3052/17/11/18 64 rev. 1.0 reset settings = 0000_0011 daa register offset 0x32 control 2 bitd7d6d5d4d3d2d1d0 name wdte al rdm hbe rxe type r/w r/w r/w r/w r/w bit name function 7:5 reserved read returns zero. 4wdte daa watchdog timer enable. 0 = watchdog timer disabled. 1 = watchdog timer enabled. when set, this bit is cleared only by a hardware reset. the watchdog timer monitors daa register writes. if a register write does not occur within a 4.096 second window, the daa is put into an on-hook state. only a write of a daa regis- ter restarts the timer. 3al analog loopback. 0 = analog loopback mode disabled. 1 = enables external analog loopback mode. 2rdm ring detect mode. 0 = ring detect on positive threshold. 1 = ring detect on positive and negative threshold. 1hbe hybrid enable. 0 = disconnects hybrid in transmit path. 1 = connects hybrid in transmit path. 0rxe receive enable. 0 = receive path disabled. 1 = enables receive path.
si3052/17/11/18 rev. 1.0 65 reset settings = 0000_0000 daa register offset 0x33 interrupt mask bitd7d6d5d4d3d2d1d0 name rdtm rovm fdtm btdm dodm lcsm type r/w r/w r/w r/w r/w r/w bit name function 7rdtm ring detect interrupt mask. 0 = a ring signal does not cause an interrupt. 1 = a ring signal causes an interrupt. 6rovm receive overload interrupt mask. 0 = a receive overload does not cause an interrupt. 1 = a receive overload causes an interrupt. 5fdtm frame detect interrupt mask. 0 = isocap frame lock does not cause an interrupt. 1 = isocap frame lock causes an interrupt. 4btdm billing tone detect interrupt mask. 0 = a billing tone does not cause an interrupt. 1 = a billing tone causes an interrupt. 3dodm drop out detect interrupt mask. 0 = a line supply dropout does not cause an interrupt. 1 = a line supply dropout causes an interrupt. 2lcsm loop current sense overload interrupt mask. 0 = loop current sense overload does not cause an interrupt. 1 = loop current sense overload causes an interrupt. 1:0 reserved read returns zero.
si3052/17/11/18 66 rev. 1.0 reset settings = 0000_0000 daa register offset 0x34 interrupt status bitd7d6d5d4d3d2d1d0 name rdti rovi fdti btdi dodi lcsi type r/w r/w r/w r/w r/w r/w bit name function 7 rdti ring detect interrupt status. 0=no ring. 1 = ring detected. write 0 to clear. 6rovi receive overload interrupt status. 0 = no receive overload. 1 = receive overload dete cted. write 0 to clear. 5fdti frame detect interrupt status. 0 = frame detect established. 1 = frame detect lost. write 0 to clear. 4btdi billing tone detect interrupt status. 0 = no billing tone. 1 = billing tone detected. write 0 to clear. 3dodi drop out detect interrupt status. 0 = line-side power available. 1 = line-side power unavailable. reads 1 when off hook. 2lcsi loop current sense overload interrupt. 0 = the lcs bits have not reached max (all ones). 1 = the lcs bits have reached max value. if the lcsm bit is set, a hardware interrupt occurs. this bit must be written to 0 to clear it. lcsi does not necessarily imply that an overlo ad situation has occurred. an overload sit- uation in the daa is determined by the status of the opd bit. after the lcsi interrupt fires, the opd bit should be checked to determine if an overload situation exists. 1:0 reserved read returns zero.
si3052/17/11/18 rev. 1.0 67 reset settings = 0000_0000 daa register offset 0x35 daa control 1 bitd7d6d5d4d3d2d1d0 name rdtn rdtp onhm rdt oh type rr r/wr r/w bit name function 7 reserved read returns zero. 6 rdtn ring detect signal negative. 0 = no ring signal is occurring. 1 = a negative ring signal is occurring. 5rdtp ring detect signal positive. 0 = no ring signal is occurring. 1 = a positive ring signal is occurring. 4 reserved read returns zero. 3onhm on-hook line monitor. 0 = normal on-hook mode. 1 = enables low-power monitoring mode allowing the dsp to re ceive line activity without going off-hook. this mode is used for caller-id detection. 2 rdt ring detect. 0 = reset either 4.5?9 seconds after last posit ive ring is detected or when the system executes an off-hook. 1 = indicates a ring is occurring. 1 reserved read returns zero. 0oh off-hook. 0 = line-side device on-hook. 1 = causes the line-side device to go off-hook.
si3052/17/11/18 68 rev. 1.0 reset settings = 0111_0000 daa register offset 0x36 daa control 2 bitd7d6d5d4d3d2d1d0 name atm[1] arm[1] pdl pdn atm[0] arm[0] type r/w r/w r/w r/w r/w r/w bit name function 7 reserved read returns zero. 6,1 atm[1:0] aout transmit path level control (map = 0 only). 00 = ?20 db transmit path attenuation for call progress aout pin only. 01 = ?32 db transmit path attenuation for call progress aout pin only. 10 = mutes transmit path for call progress aout pin only. 11 = ?26 db transmit path attenuation for call progress aout pin only. 5,0 arm[1:0] aout receive path leve l control (map = 0 only). 00 = 0 db receive path attenuation for call progress aout pin only. 01 = ?12 db receive path attenuation for call progress aout pin only. 10 = mutes receive path for call progress aout pin only. 11 = ?6 db receive path attenuation for call progress aout pin only. 4pdl powerdown line-side chip. 0 = normal operation. program the clock generator before clearing this bit. 1 = powers down the si3017/11/18. 3pdn powerdown pci daa. 0 = normal operation. 1 = powers down the daa logic. a daa soft re set is required to restore normal operation. the pci interface is not affected. 2 reserved read returns zero.
si3052/17/11/18 rev. 1.0 69 reset settings = 0000_0001 reset settings = 0000_0000 reset settings = 0000_0000 daa register offset 0x37 sample rate control bitd7d6d5d4d3d2d1d0 name src[3:0] type r/w bit name function 7:4 reserved read returns zero. 3:0 src[3:0] sample rate control. sets the sampling rate. 0000 = 7200 hz 0001 = 8000 hz 0010 = 8229 hz 0011 = 8400 hz 0100 = 9000 hz 0101 = 9600 hz 0110 = 10286 hz 0111 = 12000 hz 1000 = 13714 hz 1001 = 16000 hz 1010?1111 = reserved daa register offset 0x38 reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. daa register offset 0x39 reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero.
si3052/17/11/18 70 rev. 1.0 reset settings = 0000_0000 reset settings = xxxx_xxxx daa register offset 0x3a daa control 3 bitd7d6d5d4d3d2d1d0 name ddl type r/w bit name function 7:1 reserved read returns zero. 0ddl digital data loopback. 0 = normal operation. 1 = loopback transmit to receive before the filt ers. output data is identical to input data. daa register offset 0x3b system-side revision bitd7d6d5d4d3d2d1d0 name lsid[3:0] srev[3:0] type rr bit name function 7:4 lsid[3:0] line-side id. 0000 = si3017 fcc 0001 = si3018 global 0100 = si3011 tbr21 other = reserved 3:0 srev[3:0] system-side revision. four bit value indicating the revision of the si3052 device. 0011 = rev c 0100 = rev d
si3052/17/11/18 rev. 1.0 71 reset settings = n/a reset settings = 00xx_xx00 daa register offset 0x3c line-side status bitd7d6d5d4d3d2d1d0 name fdt lcs[4:0] type rr bit name function 7 reserved read returns zero. 6fdt frame detect. 0 = indicates isocap link has not established frame lock. 1 = indicates isocap link frame lock is established. 5 reserved read returns zero. 4:0 lcs[4:0] loop current sense. five-bit value returning the loop current in 3.3 ma/bit resolution when the daa is in an off- hook state. 00000 = indicates the loop current is less than required for normal operation. 00100 = indicates minimum loop current for normal operation. 11111 = indicates a loop current is > 127 ma. daa register offset 0x3d line-side revision bitd7d6d5d4d3d2d1d0 name lrev[3:0] type r bit name function 7:6 reserved read returns zero. 5:2 lrev[3:0] line-side revision. four-bit value indicating the revision of the si3017/11/18 device. 0011 = rev c 0100 = rev d 1:0 reserved read returns zero.
si3052/17/11/18 72 rev. 1.0 reset settings = 0000_0000 reset settings = 0000_0000 daa register offset 0x3e reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. daa register offset 0x3f tx/rx gain control bitd7d6d5d4d3d2d1d0 name txm atx[2:0] rxm arx[2:0] type r/wr/wr/wr/w bit name function 7txm transmit mute (map = 0 only). 0 = transmit signal is not muted. 1 = mutes the transmit signal. 6:4 atx[2:0] analog transmit attenuation. 000 = 0 db attenuation 001 = 3 db attenuation 010 = 6 db attenuation 011 = 9 db attenuation 1xx = 12 db attenuation 3rxm receive mute (map = 0 only). 0 = receive signal is not muted. 1 = mutes the receive signal. 2:0 arx[2:0] analog receive gain. 000=0db gain 001=3db gain 010=6db gain 011=9db gain 1xx = 12 db gain
si3052/17/11/18 rev. 1.0 73 reset settings = 0000_1000 daa register offset 0x40 international control 1 bitd7d6d5d4d3d2d1d0 name act2 ohs act iire dct[1:0] rz rt type r/w r/w r/w r/w r/w r/w r/w bit name function 7act2 ac termination select 2. works with the act bit to select one of four ac terminations. si3018 settings: act2 act ac termination 00real, 600 ? 0 1 global complex impedance 1 0 tbr21 complex impedance 1 1 new zealand co mplex impedance the global complex impedance satisfies minimum re turn loss requirements in a country requiring a complex ac termination. the other complex impedances can be used for improved return loss performance. si3011 settings: act2 act ac termination 00real, 600 ? 0 1 tbr21 complex impedance 1 0 tbr21 complex impedance 11real, 600 ? si3017 settings: act2 act ac termination xxreal, 600 ? 6ohs on-hook speed. this bit, in combination with the ohs2 bit and the sq[1:0] bits, se ts the amount of time for the line-side device to go on-hook. the on-hook speed s specified are measured from the time the oh bit is cleared until loop current equals zero. si3018 settings: ohs ohs2 sq[1:0] mean on-hook speed 0 0 00 less than 0.5 ms 0 1 00 3 ms 10% (meets etsi standard) 1 x 11 26 ms 10% (meets australia spark quenching spec) si3011 and si3017 settings: ohs ohs2 sq[1:0] mean on-hook speed x x xx less than 0.5 ms 5act ac termination select. when the act2 bit is cleared, the act bit selects the following: 0 = selects the real impedance (600 w). 1 = selects the complex impedance. 4iire iir filter select. 0 = fir filter selected. 1 = iir filter selected.
si3052/17/11/18 74 rev. 1.0 3:2 dct[1:0] dc termination select (map = 0 only). si3018 settings: 00 = low voltage mode. 01 = japan, lower voltage mode. 10 = fcc, standard voltage mode. 11 = tbr21, current limiting mode. si3011 settings: 00,10 = fcc, standard voltage mode. 01,11 = tbr21, current limiting mode. si3017 settings: xx = fcc, standard voltage mode. 1rz ringer impedance. si3018 settings: 0 = maximum (high) ringer impedance. 1 = synthesize ringer impedance. see ?ringer impedance and threshold? on page 34.. si3011 and si3017 settings: x = maximum (high) ringer impedance. 0rt ringer threshold select. satisfies country requirements on ring detection. signals below the lower le vel do not generate a ring detection; signals above the upper level are guaranteed to generate a ring detection. si3018 settings: 0 = 11 to 22 vrms 1 = 17 to 33 v rms si3011 and si3017 settings: x = 11 to 22 v rms bit name function
si3052/17/11/18 rev. 1.0 75 reset settings = 0000_0000 daa register offset 0x41 international control 2 bitd7d6d5d4d3d2d1d0 name calz mcal cald ope bte rov btd type r/w r/w r/w r/w r/w r/w r/w bit name function 7calz clear calibration. 0 = normal operation. 1 = clear calibration data. this bit must be written back to 0 after being set. 6mcal manual calibration. 0 = no calibration. 1 = initiate calibration. 5cald auto-calibration disable. 0 = enable auto-calibration. 1 = disable auto-calibration. 4 reserved read returns zero. 3ope overload protect enable. 0 = disabled. 1 = enabled. when the ope bit is set, the opd indicates wh en an overload condition is occurring. the opd bit should always be cleared before going off-hook, and set 25 ms following off-hook in order to prevent false overload detections. 2bte billing tone protect enable. when set, the daa can detect a billing tone signal on the lin e and maintain an off-hook state through the billing tone. if a billing tone is detected, the bt d bit is set to indicate the event. 0 = billing tone detection disabled . the btd bit is not functional. 1 = billing tone detecti on enabled. the bt d is functional. 1rov receive overload. set when the receive input has an excessive input level (i.e., receive pin goes below ground). cleared by writing a zero to this location (sticky). 0 = normal receive input level. 1 = excessive receive input level. 0btd billing tone detected. set if a billing tone is detected. automatically clea red (non-sticky). 0 = no billing tone detected. 1 = billing tone detected.
si3052/17/11/18 76 rev. 1.0 reset settings = 0000_0000 daa register offset 0x42 international control 3 bitd7d6d5d4d3d2d1d0 name dial fjm vol[1:0] rfwe type r/w r/w r/w r/w bit name function 7 reserved read returns zero. 6dial dtmf dialing mode (map = 0 only). si3018 settings: 0 = normal operation. 1 = increase headroom for dtmf dialing. si3011 and si3017 settings: x = normal operation. 5fjm force japan dc termination mode (map = 0 only). si3018 settings: 0 = normal operation. 1 = when dct[1:0], is set to 10 b (fcc mode), setting this bit forces the japan dc termination mode. si3011 and si3017 settings: x = normal operation. 4:3 vol[1:0] line voltage adjust (map = 0 only). when set, this bit adjusts the tip-ring line voltage. lowering this voltage improves margin in low voltage countries. si3018 settings: 00 = normal operation. 01 = ?0.125 v below japan mode. 10 = equivalent to dct[1:0] = 01 (japan mode). 11 = equivalent to dct[1:0] = 01 (japan mode). si3011 and si3017 settings: xx = normal operation. 2 reserved read returns zero. 1rfwe ring detector full-wave rectifier enable. when rngv is disabled, this bit controls the ring detector mode. when rngv is enabled, this bit configures the rdt bit to either follow the ringing signal detected by the ring valida- tion circuit, or to follow an unqualified ring detect one-shot signal initiated by a ring-threshold crossing and terminated by a fixed counte r timeout of approximately five seconds. rngv rfwe rdt bit 0 0 half-wave 0 1 full-wave 1 0 validated ring envelope 1 1 ring threshold crossing one-shot 0 reserved read returns zero.
si3052/17/11/18 rev. 1.0 77 reset settings = 0000_0000 daa register offset 0x43 international control 4 bitd7d6d5d4d3d2d1d0 name ovl opd type rr bit name function 7:3 reserved read returns zero. 2ovl overload detected. has the same function as rov but clears itself after the overlo ad is removed. see ?billing tone detection and receive overload? on page 35. mask ed by the off-hook counter only and is not affected by the bte bit. 0 = normal receive input level. 1 = excessive receive input level. 1 reserved read returns zero. 0opd overload protect detect. this bit is used to indicate that the daa has detected a line feed overload. the detector firing threshold depends on the setting of the ilim bit. opd ilim overload threshold overload status 0 0 160 ma no overload condition exists 0 1 60 ma no overload condition exists 1 0 160 ma an overload condition has been detected 1 1 60 ma an overload condition has been detected this bit must be enabled by setting the ope bit. opd is a sticky bit and is cleared by writing ope to zero.
si3052/17/11/18 78 rev. 1.0 daa register offset 0x44 call progress receive attenuation (map = 1) reset settings = 0000_0000 bit d7 d6 d5 d4 d3 d2 d1 d0 name arm[7:0] type r/w bit name function 7:0 arm[7:0] aout receive path attenuation. when decremented from the default setting, th ese bits linearly attenuate the aout receive path signal used for call progress monitoring. se tting the bits to 0s mutes the aout receive path. 0111_1111 = +6 db (gain) 0100_0000 = 0 db 0010_0000 = ?6 db (attenuation) 0001_0000 = ?12 db ... 0000_0000 = mute note: function available when daa register offset 0x31 bit 6 is set to 1 (map = 1).
si3052/17/11/18 rev. 1.0 79 daa register offset 0x45 call progress transmit attenuation (map = 1) reset settings = 0000_0000 bit d7 d6 d5 d4 d3 d2 d1 d0 name atm[7:0] type r/w bit name function 7:0 atm[7:0] aout receive path attenuation. when decremented from the default setting, these bits linearly attenuate the aout transmit path signal used for call progress monitoring. setting the bits to 0s mutes the aout transmit path. 0111_1111 = +6 db (gain) 0100_0000 = 0 db 0010_0000 = ?6 db (attenuation) 0001_0000 = ?12 db ... 0000_0000 = mute note: function available when daa register offset 0x31 bit 6 is set to 1 (map = 1).
si3052/17/11/18 80 rev. 1.0 daa register offset 0x46 ring validation control 1 reset settings = 1001_0110 bit d7 d6 d5 d4 d3 d2 d1 d0 name rdly[1:0] rmx[5:0] type r/w r/w bit name function 7:6 rdly[1:0] ring delay. these bits, in combination with the rdly[2] bit, set the amount of time between when a ring signal is validated and when a valid ring signal is indicated. rdly[2] rdly[1:0] delay 000 0ms 001 256ms 010 512ms ... 111 1792ms 5:0 rmx[5:0] ring assertion maximum count. these bits set the maximum ring frequency for a valid ring signal within a 10% margin of error. during ring qualification, a timer is lo aded with the ras[5:0] field upon a tip/ring event and decrements at a regular rate. when a subsequent tip/ ring event occurs, the timer value is compared to the rmx[5:0] field, and, if it exceeds the value in rmx[5:0], the frequency of the ring is too high and the ring is invalidated. the difference between ras[5:0] and rmx[5:0] identifies the minimum duration between tip/ring events to qualify as a ring, in binary-coded increments of 2.0 ms (nominal). a tip/ring event typically occurs twice per ring tone pe riod. at 20 hz, tip/ring events would occur every 1/(2 x 20 hz) = 25 ms. to calculate the correct rmx[5:0] value for a frequency range [f_min, f_max], the following equation should be used: to compensate for error margin and ensure a sufficient ring detection window, it is rec- ommended that the calculated value of rmx[5:0] be incremented by 1. rmx 5:0 [] ras 5:0 [] 1 2 f_max 2 ms -------------------------------------------- - rmx ras , ?
si3052/17/11/18 rev. 1.0 81 daa register offset 0x47 ring validation control 2 reset settings = 0010_1101 bit d7 d6 d5 d4 d3 d2 d1 d0 name rdly[2] rto[3:0] rcc[2:0] type r/w r/w r/w bit name function 7 rdly[2] ring delay bit 2. this bit, in combination with the rdly[1:0] bits, sets the amount of time between when a ring signal is validated and when a valid ring signal is indicated. rdly[2] rdly[1:0] delay 0 00 0 m s 0 01 256 m s 010 512 m s ... 1 11 1792 m s 6:3 rto[3:0] ring timeout. determine when ringing is finished after the most recent ring threshold crossing. 0000 = invalid 0001 = 128 x 1 = 128 ms 0010 = 128 x 2 = 256 ms ... 1111=128x15=1920ms 2:0 rcc[2:0] ring confirmation count. determine the time interval over which the ring signal must meet tolerances defined by ras[5:0] and rmx[5:0] to be classified as a valid ring signal. 000 = 100 ms 001 = 150 ms 010 = 200 ms 011 = 256 ms 100 = 384 ms 101 = 512 ms 110 = 640 ms 111 = 1024 ms
si3052/17/11/18 82 rev. 1.0 daa register offset 0x48 ring validation control 3 reset settings = 0001_1001 reset settings = 000x_xxxx bitd7d6d5d4d3d2d1d0 name rngv ras[5:0] type r/w r/w bit name function 7 rngv ring validation enable. 0 = ring validation feature is disabled. 1 = ring validation feature is enabled in normal operating mode and low-power mode. 6 reserved read returns zero. 5:0 ras[5:0] ring assertion time. these bits set the minimum ring frequency fo r a valid ring signal. during ring qualifica- tion, a timer is loaded with t he ras[5:0] field upon a tip/ri ng event and decrements at a regular rate. if a second or subsequent tip/ring event occurs after the timer has timed out then the frequency of the ring is t oo low and the ring is invalidated. the differ- ence between ras[5:0] and rmx[5:0] id entifies the minimum duration between tip/ring events to qualify as a ring, in bina ry-coded increments of 2.0 ms (nominal). a tip/ring event typically occurs twice per ring tone period. at 20 hz, tip/ring events would occur every 1/(2 x 20 hz) = 25 ms. to calculate the corr ect ras[5:0] value for a frequency range [f_min, f_max], the following equation should be used: daa register offset 0x49 resistor calibration bitd7d6d5d4d3d2d1d0 name rcald type r/w bit name function 7:6 reserved read returns zero. 5 rcald resistor calibration disable. 0 = internal resistor calibration enabled. 1 = internal resistor calibration disabled. 4:0 reserved read returns zero or one. ras 5:0 [] 1 2f_min 2 ms -------------------------------------------
si3052/17/11/18 rev. 1.0 83 daa register offset 0x4a dc termination control (map = 1) reset settings = 0000_0000 bitd7d6d5d4d3d2d1d0 name dcv[1:0] mini[1:0] ilim dcr type r/w r/w r/w r/w bit name function 7:6 dcv[1:0] tip/ring voltage adjust. adjust the voltage on the dct pin of the lin e-side device, which affects the tip/ring voltage on the line. low voltage countries sh ould use a lower tip/ri ng voltage. raising the tip/ring voltage improves signal headroom. si3018 settings: dcv[1:0] dct pin voltage 00 3.1 v 01 3.2 v 10 3.35 v 11 3.5 v si3011 and si3017 settings: dcv[1:0] dct pin voltage xx 3.35 v 5:4 mini[1:0] minimum operational loop current. adjusts the minimum loop current so the daa can operate. increasing the minimum operational loop current improves signal headroom at a lower tip/ring voltage. si3018 settings: mini[1:0] min loop current 00 10 ma 01 12 ma 10 14 ma 11 16 ma si3011 and si3017 settings: mini[1:0] min loop current xx 10 ma 3:2 reserved read returns zero. 1 ilim current limiting enable. si3018 and si3011 settings: 0 = current limiting mode disabled. 1 = current limiting mode enabled. limits loop current to a maximum of 60 ma per the tbr21 standard. si3017 settings: x = current limiting mode disabled. 0 dcr dc impedance selection. 0 = 50 w dc termination is selected. use this mode for all standard applications. 1 = 800 ? dc termination is selected. note: function available when daa registers offset 0x31 bit 6 is set to 1 (map = 1).
si3052/17/11/18 84 rev. 1.0 reset settings = 0000_xxxx daa register offset 0x4c reserved reset settings = 0000_0000 daa register offset 0x4d reserved reset settings = 0000_0000 daa register offset 0x4b reserved bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero or one. bitd7d6d5d4d3d2d1d0 name type bit name function 7:0 reserved read returns zero. bit d7 d6 d5 d4 d3 d2 d1 d0 name type bit name function 7:0 reserved read returns zero.
si3052/17/11/18 rev. 1.0 85 daa register offset 0x4e reserved reset settings = 0000_0000 daa register offset 0x4f daa control 4 reset settings = 0010_0000 bit d7 d6 d5 d4 d3 d2 d1 d0 name type bit name function 7:0 reserved read returns zero. bit d7 d6 d5 d4 d3 d2 d1 d0 name foh[1:0] ohs2 type r/w r/w bit name function 7 reserved read returns zero. 6:5 foh[1:0] fast off-hook selection. determines the length of the off-hook counter. 00 = 512 ms 01 = 128 ms (default) 10 = 64 ms 11 = 8 ms 4 reserved read returns zero. 3 ohs2 on-hook speed 2. si3018 settings: this bit, in combination with the ohs bit and t he sq[1:0] bits on-hook speeds specified are measured from the time the oh bit is cleared until loop current equals zero. ohs ohs2 sq[1:0] mean on-hook speed 0 0 00 less than 0.5 ms 0 1 00 3 ms 10% (meets etsi standard) 1 x 11 26 ms 10% (meets australia spark quenching spec) si3011 and si3017 settings: ohs ohs2 sq[1:0] mean on-hook speed x x xx less than 0.5 ms 2:0 reserved read returns zero.
si3052/17/11/18 86 rev. 1.0 daa register offset 0x5d programmable hybrid register 1 (map = 1) reset settings = 0000_0000 daa register offset 0x5e programmable hybrid register 2 (map = 1) reset settings = 0000_0000 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb1[7:0] type r/w bit name function 7:0 hyb1[7:0] hybrid 1. programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the first tap in t he four-tap filter. when this register is set to 0s, this filter stage does not effect on the hybrid response. refer to ?an84: digital hybrid with the si305x daas? for more information on selecting coefficients for the pro- grammable hybrid. note: function available when daa registers offset 0x31 bit 6 is set to 1 (map = 1). bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb2[7:0] type r/w bit name function 7:0 hyb2[7:0] hybrid 2. programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the first tap in t he four-tap filter. when this register is set to 0s, this filter stage does not effect on the hybrid response. refer to ?an84: digital hybrid with the si305x daas? for more information on selecting coefficients for the pro- grammable hybrid. note: function available when daa registers offset 0x31 bit 6 is set to 1 (map = 1).
si3052/17/11/18 rev. 1.0 87 daa register offset 0x5f programmable hybrid register 3 (map = 1) reset settings = 0000_0000 daa register offset 0x60 programmable hybrid register 4 (map = 1) reset settings = 0000_0000 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb3[7:0] type r/w bit name function 7:0 hyb3[7:0] hybrid 3. programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the first tap in t he four-tap filter. when this register is set to 0s, this filter stage does not effect on the hybrid response. refer to ?an84: digital hybrid with the si305x daas? for more information on selecting coefficients for the pro- grammable hybrid. note: function available when daa registers offset 0x31 bit 6 is set to 1 (map = 1). bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb4[7:0] type r/w bit name function 7:0 hyb4[7:0] hybrid 4. programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the first tap in t he four-tap filter. when this register is set to 0s, this filter stage has no effect on th e hybrid response. refer to ?an84: digital hybrid with the si305x daas? for more information on selecting coefficients for the pro- grammable hybrid. note: function available when daa registers offset 0x31 bit 6 is set to 1 (map = 1).
si3052/17/11/18 88 rev. 1.0 daa register offset 0x61 programmable hybrid register 5 (map = 1) reset settings = 0000_0000 daa register offset 0x62 programmable hybrid register 6 (map = 1) reset settings = 0000_0000 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb5[7:0] type r/w bit name function 7:0 hyb5[7:0] hybrid 5. programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the first tap in t he four-tap filter. when this register is set to 0s, this filter stage does not effect on the hybrid response. refer to ?an84: digital hybrid with the si305x daas? for more information on selecting coefficients for the pro- grammable hybrid. note: function available when daa registers offset 0x31 bit 6 is set to 1 (map = 1). bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb6[7:0] type r/w bit name function 7:0 hyb6[7:0] hybrid 6. programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the first tap in t he four-tap filter. when this register is set to all 0s, this filter stage does not effect on the hybrid response. re fer to ?an84: digital hybrid with the si305x daas? for more information on selecting coefficients for the pro- grammable hybrid. note: function available when daa registers offset 0x31 bit 6 is set to 1 (map = 1).
si3052/17/11/18 rev. 1.0 89 daa register offset 0x63 programmable hybrid register 7 (map = 1) reset settings = 0000_0000 daa register offset 0x64 programmable hybrid register 8 (map = 1) reset settings = 0000_0000 bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb7[7:0] type r/w bit name function 7:0 hyb7[7:0] hybrid 7. programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the first tap in t he four-tap filter. when this register is set to all 0s, this filter stage does not effect on the hybrid response. re fer to ?an84: digital hybrid with the si305x daas? for more information on selecting coefficients for the pro- grammable hybrid. note: function available when daa registers offset 0x31 bit 6 is set to 1 (map = 1). bit d7 d6 d5 d4 d3 d2 d1 d0 name hyb8[7:0] type r/w bit name function 7:0 hyb8[7:0] hybrid 8. programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. this register represents the first tap in t he four-tap filter. when this register is set to all 0s, this filter stage does not effect on the hybrid response. re fer to ?an84: digital hybrid with the si305x daas? for more information on selecting coefficients for the pro- grammable hybrid. note: function available when daa registers offset 0x31 bit 6 is set to 1 (map = 1).
si3052/17/11/18 90 rev. 1.0 reset settings = 0000_0000 daa register offset 0x6b spark quenching control bitd7d6d5d4d3d2d1d0 name0sq10sq00 000 type r/w r/w bit name function 7 reserved always write this bit to zero. 6, 4 sq[1:0] spark quenching. these bits, in combination with the ohs bit an d the ohs2 bit, set the amount of time for the line-side device to go on-hook. the on-hook speeds specified are measured from the time the oh bit is cleared until loop current equals zero. si3018 settings: ohs ohs2 sq[1:0] mean on-hook speed 0 0 00 less than 0.5 ms 0 1 00 3 ms 10% (meets etsi standard) 1 x 11 26 ms 10% (meets australia spark quenching spec) si3011 and si3017 settings: ohs ohs2 sq[1:0] mean on-hook speed x x xx less than 0.5 ms 5 reserved always write this bit to zero. 3:0 reserved always write these bits to zero.
si3052/17/11/18 rev. 1.0 91 pin descriptions: si3052 table 24. pin descriptions pin # pin name description 1v io 3.3/5 v io digital supply input. 2ad[17] address/data bit input/output. multiplexed address/data bit for the pci interface. 3ad[16] address/data bit input/output. multiplexed address/data bit for the pci interface. 4c/be [2] command/byte enable bit input/output. multiplexed command/byte enables for the pc i interface. the pin is an output during master operation and an input during slave o peration. the pin indicates cycle type dur- ing the address phase and byte enable during the data phase of a transaction. 5frame cycle frame indicator input/output. pci bus master output indicating the be ginning and duration of a bus transfer. 6irdy initiator ready input/output. pci bus master output indicating that the initia tor device is ready to transmit or receive data. 7trdy target ready input/output. pci bus target output indicating that the ta rget device is ready to transmit or receive data. 8 devsel device select input/output. pci bus target output indicating the device has decoded the address of the current transaction that matches the target device?s select range. 9stop stop transaction input/output. pci bus target output indicating a request to the bus master to stop the current transac- tion. 10 perr parity error input/output. reports pci bus data parity errors. si3052 64-lead tqfp (epad) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 20 19 18 24 23 22 21 31 30 29 28 27 26 25 32 64 61 62 63 57 58 59 60 50 51 52 53 54 55 56 49
si3052/17/11/18 92 rev. 1.0 11 serr system error input/output. reports pci bus system errors. 12 par address/data parity bit input/output. even parity across ad[31:0] and c/be[3:0 ] for address and data bus phases. the par- ity is delayed one pci clock cycle from th e corresponding address or data bus phase. 13 c/be [1] command/byte enable bit input/output. multiplexed command/byte enables for the pc i interface. the pin is an output during master operation and an input during slave o peration. the pin indicates cycle type dur- ing the address phase and byte enable during the data phase of a transaction. 14 ad[15] address/data bit input/output. multiplexed address/data bit for the pci interface. 15 ad[14] address/data bit input/output. multiplexed address/data bit for the pci interface. 16 v io 3.3/5 v io digital supply input. 17 ad[13] address/data bit input/output. multiplexed address/data bit for the pci interface. 18 ad[12] address/data bit input/output. multiplexed address/data bit for the pci interface. 19 ad[11] address/data bit input/output. multiplexed address/data bit for the pci interface. 20 ad[10] address/data bit input/output. multiplexed address/data bit for the pci interface. 21 ad[09] address/data bit input/output. multiplexed address/data bit for the pci interface. 22 ad[08] address/data bit input/output. multiplexed address/data bit for the pci interface. 23 c/be [0] command/byte enable bit input/output. multiplexed command/byte enables for the pc i interface. the pin is an output during master operation and an input during slave o peration. the pin indicates cycle type dur- ing the address phase and byte enable during the data phase of a transaction. 24 ad[07] address/data bit input/output. multiplexed address/data bit for the pci interface. 25 v io 3.3/5 v io digital supply input. 26 ad[06] address/data bit input/output. multiplexed address/data bit for the pci interface. table 24. pin descriptions (continued) pin # pin name description
si3052/17/11/18 rev. 1.0 93 27 ad[05] address/data bit input/output. multiplexed address/data bit for the pci interface. 28 ad[04] address/data bit input/output. multiplexed address/data bit for the pci interface. 29 ad[03] address/data bit input/output. multiplexed address/data bit for the pci interface. 30 ad[02] address/data bit input/output. multiplexed address/data bit for the pci interface. 31 ad[01] address/data bit input/output. multiplexed address/data bit for the pci interface. 32 ad[00] address/data bit input/output. multiplexed address/data bit for the pci interface. 33 inta pci interrupt output (open drain). level triggered interrupt pin for internal device interrupt sources. 34 3.3vaux 3.3 vaux sense input. 35 xout crystal output. connection to 16.384 mhz crystal. 36 xin crystal input. connection to 16.384 mhz crystal. 37 rst pci device reset input. pci bus master reset signal. 38 clkrun / pnpid/ ee_sd system clock control input/output (open drain). an optional pci signal defined for mobile applications. as an input, high indicates that pciclk is active. the signal is driven lo w when the bus controller wants to stop pci- clk. as an output, low indicates a request to activate pciclk. if unused, this pin requires a weak pulldown. pci pnp id select input. resistor selection for pci plug -n-play (pnp) identification. eprom serial data input/output. serial data input/output to external pnp eprom. 39 aout/ pnpid/ ee_sc call progress monitor output. pulse-width modulation (pwm) signal for driving a call progress speaker. pci pnp id select input. resistor selection for pci plug -n-play (pnp) identification. eprom serial clock output. serial clock output to external pnp eprom. table 24. pin descriptions (continued) pin # pin name description
si3052/17/11/18 94 rev. 1.0 40 pme power management event output (open drain). indicates a pci power management event. this pin powers up in the high impedance state. 41 c2a isolation capacitor 2 a input/output. differential isolation for communica tion with the daa line-side device. 42 c1a isolation capacitor 1 a input/output. differential isolation for communica tion with the daa line-side device. 43 va voltage regulator bypass output. 44 vd 3.3 v digital supply input. 45 pciclk pci bus clock input. pci bus clock for all bus transaction timing. all synchronous signals are driven and sampled on the rising edge of this clock. 46 gnt master grant input. indicates that the system arbi ter has granted pci bus access. 47 req master request output (tri-state). indicates a request to the system arbite r for access to the pci bus. when rst is low, this pin is high-impedance. 48 ad[31] address/data bit input/output. multiplexed address/data bit for the pci interface. 49 ad[30] address/data bit input/output. multiplexed address/data bit for the pci interface. 50 ad[29] address/data bit input/output. multiplexed address/data bit for the pci interface. 51 ad[28] address/data bit input/output. multiplexed address/data bit for the pci interface. 52 ad[27] address/data bit input/output. multiplexed address/data bit for the pci interface. 53 ad[26] address/data bit input/output. multiplexed address/data bit for the pci interface. 54 ad[25] address/data bit input/output. multiplexed address/data bit for the pci interface. 55 v io 3.3/5 v id digital supply input. 56 ad[24] address/data bit input/output. multiplexed address/data bit for the pci interface. table 24. pin descriptions (continued) pin # pin name description
si3052/17/11/18 rev. 1.0 95 57 c/be [3] command/byte enable bit input/output. multiplexed command/byte enables for the pc i interface. the pin is an output during master operation and an input during slave o peration. the pin indicates cycle type dur- ing the address phase and byte enable during the data phase of a transaction. 58 idsel initialize device select input. chip select during pci configur ation register read/write cycles. 59 ad[23] address/data bit input/output. multiplexed address/data bit for the pci interface. 60 ad[22] address/data bit input/output. multiplexed address/data bit for the pci interface. 61 ad[21] address/data bit input/output. multiplexed address/data bit for the pci interface. 62 ad[20] address/data bit input/output. multiplexed address/data bit for the pci interface. 63 ad[19] address/data bit input/output. multiplexed address/data bit for the pci interface. 64 ad[18] address/data bit input/output. multiplexed address/data bit for the pci interface. epad gnd exposed die paddle ground. table 24. pin descriptions (continued) pin # pin name description
si3052/17/11/18 96 rev. 1.0 pin descriptions: si3017/11/18 table 25. si3017/11/18 pin descriptions pin # pin name description 1qe transistor emitter. connects to the emitter of q3. 2 dct dc termination. provides dc termination to the telephone network. 3 rx receive input. serves as the receive side input from the telephone network. 4ib internal bias 1. provides internal bias. 5c1b isolation capacitor 1b. connects to one side of isolation capa citor c1 and communicates with the si3052. 6c2b isolation capacitor 2b. connects to one side of isolation capacitor c2 and communicate with the si3052. 7vreg voltage regulator. connects to an external capacitor to provide bypassing for an internal power supply. 8rng1 ring 1. connects through a capacitor to the ring le ad of the telephone line. provides the ring and caller id signals to the si3052. 9rng2 ring 2. connects through a capacitor to the tip lead of the telephone line. provides the ring and caller id signals to the si3052. 10 vreg2 voltage regulator 2. connects to an external capacitor to provide bypassing for an internal power supply. 11 sc circuit enable. enables transistor network. 12 qe2 transistor emitter 2. connects to the emitter of q4. 13 qb transistor base. connects to the base of transistor q3. used to go on- and off-hook. 14 dct3 dc termination 3. provides the dc terminatio n to the telephone network. 15 ignd isolated ground. connects to ground on the line-side interface. 16 dct2 dc termination 2. provides dc termination to the telephone network. qe dct rx ib c1b c2b vreg dct2 ignd dct3 qb qe2 sc vreg2 rng2 rng1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
si3052/17/11/18 rev. 1.0 97 ordering guide region interface system-side line-side temperature part # package part # package fcc pci si3052-kq tqfp si3017-ks soic 0 to 70 c tbr21 pci si3052-kq tqfp si3011-ks soic 0 to 70 c global pci si3052-kq tqfp si3018-ks soic 0 to 70 c global pci si3052-kq tqfp si3018-kt tssop 0 to 70 c global ac-link SI3054-KS soic si3018-ks soic 0 to 70 c global ac-link si3054-kt tssop si3018-kt tssop 0 to 70 c
si3052/17/11/18 98 rev. 1.0 package outline: 64-pin tqfp figure 28 illustrates the package details for the si3052. table 26 lists the valu es for the dimensions shown in the illustration. figure 28. 64-pin thin quad flat package (tqfp) table 26. 64-pin package diagram dimensions symbol millimeters min nom max a? ?1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 12.00 bsc d1 10.00 bsc e 12.00 bsc e1 10.00 bsc l 0.45 0.60 0.75 e 0.50 bsc b 0.17 0.22 0.27 b1 0.17 0.20 0.23 d d1 e e1 1 16 a 17 32 33 48 49 64 exposed pad 4.5 x 4.5 mm e see detail a see detail b 0 min. 0.08/0.20 r l detail a gauge plane a2 a1 0-7 1.00 ref 0.08 r. min. 0.20 min. detail b 0.09/0.20 0.09/0.16 b b1 with lead finish base metal
si3052/17/11/18 rev. 1.0 99 package outline: 16-pin soic figure 29 illustrates the packag e details for the si3017/11/18. table 27 lists the values for the dimensions shown in the illustration. figure 29. 16-pin small outline integrated circuit (soic) package table 27. package diagram dimensions symbol millimeters typical* min max a 1.35 1.75 ! a1 .10 .25 ! a2 1.30 1.50 b.33.51 c.19.25 ! d 9.80 10.01 e 3.80 4.00 e 1.27 bsc ? h 5.80 6.20 h.25.50 l .40 1.27 ?0.10 0o 8o ! *note: typical parameters are for information purposes only. e h a1 b c h l e see detail f detail f a 16 9 8 1 gauge plane 0.010 d a2 seating plane
si3052/17/11/18 100 rev. 1.0 document change list revision 0.86 to revision 1.0 ! si3017 descriptions added. ! si3011 descriptions added. ! table 2 on page 5 tbd values defined. ! table 3 on page 6 tbd values defined. ! figure 13 on page 16 updated. ! figure 14 on page 17 updated. ! "bill of materials" on page 18 updated. ! figure 14 on page 17 updated. ! table 14 on page 28 updated. ! "initialization" on page 30 updated. ! "parallel handset detection" on page 30 updated. ! table 15 on page 31 updated. ! "dc termination" on page 32 updated. ! "ring detection" on page 33 updated. ! "dtmf dialing" on page 34 updated. ! "billing tone detection and receive overload" on page 35 updated. ! "on-hook line monitor" on page 36 updated. ! "overload detection" on page 37 updated. ! "in-circuit testing" on page 38 updated. ! "revision identification" on page 38 updated. ! "register map" on page 38 updated. ! table 19 and table 20 added. ! register descriptions updated.
si3052/17/11/18 rev. 1.0 101 notes:
si3052/17/11/18 102 rev. 1.0 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, isomodem, and isocap are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. si licon laboratories products are not designed, intended, or autho rized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon labor atories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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