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preliminary rev. 0.8 3/06 copyright ? 2006 by silicon labo ratories SI8250/1/2 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. SI8250/1/2 d igital p ower c ontroller features description SI8250/1/2 provides all control and prot ection functions necessary to implement highly intelligent, fast response power delivery and management control systems for isolated and non-isolated power supplies. on-board processing capability enables intelligent contro l optimization for improved system performance and new capabilities such as serial connectivity via the pmbus or on-board uart. the SI8250/1/2 family is in-system flas h programmable enabling control and protection parameters such as system regu lation and protection settings, start-up and shutdown modes, loop response, and modulation timing to be readily modified. the built-in high-speed control path provides loop updates every 100ns and provides pulse-by-pulse current li miting and over-current protection even while the internal cpu is disabled. the si825x family is supported by the SI8250dk development kit, which contains everything required to develop and program power supply applications with the si825x family of digital controllers. single-chip, flash-based digital power controller supports isolated and non-isolated applications enables new system capabilities such as: - adaptive dead-time control for higher efficiency - nonlinear control for faster transient response - self diagnostics for higher reliability - full pmbus command set implementation for system connectivity highly integrated control solution: high-speed digital hardware control loop in-system programmable supervisory processor programmable system protection functions hardware cycle-by-cycle current limiting and ocp external clock and frame synchronization inputs performs system management functions such as external power supply sequencing and fan control/monitoring in-system flash programmable flash can also be used as nv memory for data storage low cost, comprehensive development tool kit includes: graphical, easy-to-use system design tools integrated development environment in-system, on-line debugger turnkey isolated 35 w digital half-bridge target board typical applications isolated and non-isolated dc/dc converters ac/dc converters fully pb-free and rohs compliant packages 32-pin lqfp 28-pin 5 x 5 mm qfn temp range: ?40 to +125 oc patents pending pin assignments: see page 23 4 5 6 7 2 1 3 11 12 13 14 9 8 10 18 17 16 15 20 21 19 25 26 27 28 23 22 24 SI8250/1/2 top view rst / c2ck ipk vsense gnd vdd vref p1.0/vin/ain0 p1.1/ain1 p1.2/ain2 p1.3/ain3 p1.4/ain4 p1.5/ain5 p1.6/ain6 p1.7/ain7/c2d p0.7 p0.6 p0.5 p0.4 p0.3/xclk p0.2 p0.1 p0.0 ph6 ph5 ph4 ph3 ph2 ph1 gnd gnd 1 vsense p0.0 p0.5 p0.2 p0.1 p0.3 / xclk p1.0/vin/ain0 ipk p0.6 p0.7 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 p0.4 SI8250/1/2 top view p1.1/ain1 gnda vdda rst/c2ck gnd vdd p1.5/ain5 p1.6/ain6 p1.7/ain7/c2d ph6 ph5 p1.4/ain4 vdd gnd ph3 p1.3/ain3 p1.2/ain2 vref ph4 ph2 ph1 28-pin qfn 32-pin lqfp free datasheet http:///
SI8250/1/2 2 preliminary rev. 0.8 free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. benefits of digital power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1. system operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2. control processor functional block descriptions (figur e 1) . . . . . . . . . . . . . . . . . . . 16 3.3. system management processo r functional block descriptions . . . . . . . . . . . . . . . . 17 4. design tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. example applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 6. layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7. pin descriptions?SI8250/1/2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. package outline?32lqfp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10. package outline?28qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 free datasheet http:///
SI8250/1/2 4 preliminary rev. 0.8 1. electrical specifications table 1. absolute maximum ratings* parameter conditions min. typ. max. units ambient temperature under bias ?55 ? +135 c storage temperature ?65 ? +150 c voltage on any port0 pin with respect to gnd ?0.3 ? 5.5 v voltage on all other pins with respect to gnd ?0.3 ? 4.0 v voltage on vdd with respect to gnd ?0.3 ? 4.0 v maximum total current through vdd or gnd ? ? 400 ma maximum output current sunk by rst or any port pin ??80ma *note: stresses above those listed under "2.1 absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only, and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specificat ion is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 2. dc electrical specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units supply voltage 2.25 ? 2.75 v supply current, all peripherals enabled analog + digital supply current. ? 26 ? ma lockout mode supply current analog + digital supply current. (see table 1 on page 4) ?300? a digital supply current (shutdown) oscillator not ru nning, vdd mon- itor disabled ??tbda digital supply ram data retention voltage ?1.5? v free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 5 table 3. reference dac electrical specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units resolution ? ? 9 bits lsb size ? 2.44 ? mv integral nonlinearity (inl) ?2 ? +2 lsb differential nonlinearity (dnl) ?1.0 ? +1.0 lsb settling time 1/2 lsb change from 0 to full scale ?2?s turn-on time ? 20 ? s noise 2 mhz bw ? 1 ? mv pp power supply rejection ? 70 ? db supply current ? 220 ? a shutdown supply current ? 0.1 ? a free datasheet http:///
SI8250/1/2 6 preliminary rev. 0.8 table 4. adc0 (12-bit adc) specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units dc accuracy resolution ? 12 ? bits integral nonlinearity ? ? 2 lsb differential nonlinearity gua ranteed monotonic ? ? 1 lsb offset error ? 3 ? lsb full scale error differential mode ? 3 ? lsb offset temperature coefficient ? tbd ? ppm/c dynamic performance (10 khz sine-wave single-ended input, 0 to 1 db below full scale, 200 ksps) signal-to-noise plus distortion ? 64 ? db total harmonic distortion up to the 5 th harmonic ? 83 ? db spurious-free dynamic range ? ?73 ? db conversion rate conversion time in sar clocks note 1 ? 13 ? clocks track/hold acquisition time note 2 1 ? ? s throughput rate ? ? 200 ksps analog inputs input voltage range 0 ? v ref v input capacitance ? 15 ? pf temperature sensor linearity notes 3, 4 ? tbd ? c gain notes 3, 4 ? 1353 ? v/c offset notes 3, 4 (temp = 0 c) ? 488 ? mv power specifications power supply current (v dd sup- plied to adc0) operating mode, 200 ksps ? 780 ? a power-on time after v ref settle, before tracking begins ?5? s power supply rejection ? tbd ? mv/v notes: 1. an additional 2 f clk cycles are required to star t and complete a conversion. 2. additional tracking time may be required depending on the output impedance connected to the adc input. 3. represents one standard deviation from the mean. 4. includes adc offset, gain, and linearity variations. free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 7 table 5. adc1 specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units sampling frequency adcsp = 0 ? 10 ? msps adcsp = 1 ? 5 ? resolution ? ? 6 bits lsb size 4 ? 20 mv differential input voltage range note 1 ?32 ? +31 lsb common-mode input voltage range 0.8 ? 1.3 v integral nonlinearity ?2 ? +2 lsb differential nonlinearity ?1 ? +1 lsb gain error ? 5 ? % offset error ? 3 ? mv input bias current ? 5 ? a standby mode supply current disabled ? 0.1 ? a operating mode supply current ? ? 3 ma notes: 1. lsb size (mv) is programmable using the res[3:0] bits in the adc1cn register. table 6. dsp filter engine electrical specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units resolution 1 ??9bits dithering 2 ??6bits standby mode supply current disabled ? 0.1 ? a notes: 1. internal word length = 22 bits. 2. up to a total 15 bits of resolution when dithering is enabled. free datasheet http:///
SI8250/1/2 8 preliminary rev. 0.8 table 7. peak current limit detector electrical specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units ipk input to dpwm output latency 10 mv overdrive ? 45 ? ns threshold detector voltage vt[3:0] = 0000 35 50 65 mv vt[3:0] = 0001 85 100 115 vt[3:0] = 0010 135 150 165 vt[3:0] = 0011 185 200 215 vt[3:0] = 0100 235 250 265 vt[3:0] = 0101 285 300 315 vt[3:0] = 0110 335 350 365 vt[3:0] = 0111 485 400 415 vt[3:0] = 1000 435 450 465 vt[3:0] = 1001 485 500 515 vt[3:0] = 1010 535 550 565 vt[3:0] = 1011 585 600 615 vt[3:0] = 1100 635 650 665 vt[3:0] = 1101 685 700 715 vt[3:0] = 1110 735 750 765 vt[3:0] = 1111 785 800 815 hysteresis hyst[1:0] = 00 ? 0 ? mv hyst[1:0] = 01 ? 5 ? hyst[1:0] = 10 ? 10 ? hyst[1:0] = 11 ? 20 ? blanking time leb[1:0] = 00, f pll = 200 mhz ? 0 ? ns leb[1:0] = 01, f pll =200mhz ? 20 ? leb[1:0] = 10, f pll =200mhz ? 40 ? leb[1:0] = 11, f pll = 200 mhz ? 80 ? input capacitance ? 4.5 ? pf input bias current ? 0.1 ? a shutdown supply current enable bit = 0 ? 0.1 ? a active supply current iin = (vt + 100 mvpp), 1.5 mhz sq. wave ?100?a free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 9 table 8. dpwm specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units clock frequency dpwmsp[4:3] = 00 ? ? 200 mhz dpwmsp[4:3] = 01 ? ? 50 dpwmsp[4:3] = 1x ? ? 25 resolution no dithering ? ? 9 bits dithering enabled ? ? 15 time resolution dpwmsp[4:3] = 00 5 ? ? ns dpwmsp[4:3] = 01 20 ? ? dpwmsp[4:3] = 1x 40 ? ? sync pulse set-up time sync signal minimum low time before positive transition 3??dpwm clock cycles ph rise, fall time 50pf on pin ? ? 5 ns output resistance high i out =?5ma ? 75 ? ? output resistance low i out =8ma ? 40 ? ? shutdown supply current ? ? 0.1 a table 9. bandgap voltage reference specs ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units output voltage ? 1.20 ? v temperature stability ?1 ? +1 % turn-on response (0.01%, 4.7 f) ? 6.5 ? ms no load ? 2 ? s noise 4.7 f ? 2 ? v (rms) bandgap current ? 60 ? a reference buffer current ? 30 ? a power supply rejection ? 50 ? db free datasheet http:///
SI8250/1/2 10 preliminary rev. 0.8 table 10. comparator0 specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units vin 0 ? v dd v low-speed supply current ? 8 ? a full-speed supply current ? 225 ? a hysteresis cp0hyp[1:0] = 00 ? 0 ? mv cp0hyp[1:0] = 01 ? 7 ? cp0hyp[1:0] = 10 ? 14 ? cp0hyp[1:0] = 11 ? 28 ? cp0hyn[1:0] = 00 ? 0 ? cp0hyn[1:0] = 01 ? ?7 ? cp0hyn[1:0] = 10 ? ?14 ? cp0hyn[1:0] = 11 ? ?28 ? response time low power mode, 25 mv overdrive ? 180 ? ns high-speed mode, 25 mv overdrive ? 25 ? input capacitance ? 5 ? pf cmrr ? 50 ? db input offset ? 5 ? mv free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 11 table 11. reset electrical characteristics ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 8.5ma, vdd = 2.5v ? ? 0.7 v rst input high voltage 0.7 x v dd ?? v rst input low voltage ? ? 0.3 x v dd v rst input pull-up current rst =0.0 ? 25 tbd a vdd por threshold 2.0 2.1 2.2 v missing clock detector timeout time from last system clock ris- ing edge to start of reset ? 250 650 s reset time delay delay between release of any reset source and code execu- tion at location 0x0000 5.0 ? ? s minimum rst low time to gen- erate a system reset 6.5 ? ? s vdd monitor turn-on time 100 ? ? s vdd monitor supply current ? 40 ? a table 12. flash electrical characteristics ta = ?40 to +125 c, vdd = 2.25 v ? 2.75 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units flash size SI8250 32768 (1) ?? bytes si8251, si8252 16383 (1) ?? endurance 10 k 100 k ? erase/write read cycle time tbd ? ? ns erase cycle time 50 mhz system clock 32 ? 48 ms write cycle time 50 mhz system clock 76 ? 114 s notes: 1. the last 512 bytes of memory are reserved. free datasheet http:///
SI8250/1/2 12 preliminary rev. 0.8 table 13. port i/o dc electrical characteristics ta = ?40 to +125 c, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameters conditi ons min typ max units port0 input voltage tolerance push-pull ? ? v dd + 0.7 v open-drain ? ? 5.5 port1 input voltage tolerance ? ? v dd + 0.7 output high voltage i oh =?3ma, port i/o push-pull v dd ? 0.4 ? ? v i oh =?10a, port i/o push-pull v dd ? 0.1 ? ? i oh = ?10 ma, port i/o push-pull ?v dd ? 0.8 ? output low voltage i ol =8.5ma ? ? 0.6 v i ol =10a ? ? 0.1 i ol = 25 ma ? 1.25 ? input high voltage (0.7) v dd ??v input low voltage ? ? (0.3) v dd v input leakage current weak pullup off ? ? 10 a weak pullup on, v in =0v ? 20 50 table 14. pll specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units stabilization time ? 30 ? s input frequency range 15 ? 25 mhz pll frequency ? 200 ? mhz cycle-to-cycle jitter ? 250 ? ps supply current ? 15 ? ma shutdown current ? 0.1 ? a free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 13 table 15. 25mhz oscillator specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units frequency ? 24.5 ? mhz start-up time ? 100 ? s power supply sensitivity ? 0.3 ? %/v temperature coefficient ? 50 ? ppm/ c supply current ? 450 ? a shutdown current ? 0.1 ? a table 16. low frequency oscillator (lfo) specifications ta = ?40 to +125 c, vdd = 2.5 v, sysclk = 25 mhz, pllclk = 200 mhz unless otherwise specified. parameter conditions min typ max units frequency ? 80 ? khz start-up time ? 100 ? s power supply sensitivity ? 1.7 ? %/v temperature coefficient ? 1000 ? ppm/ c supply current ? 4 ? a shutdown current ? 0.1 ? a free datasheet http:///
SI8250/1/2 14 preliminary rev. 0.8 2. benefits of digital power control digitally controlled power systems have the following key advantages over analog implementations: in-system programmability : virtually all aspects of digital controller behavior can be changed in software locally or remo tely, and without hardware modification. this benefits the system in several ways: hardware designs can be segregated into base platforms (for example, by form factor or output power), and optimized to the end application in software. this lowers development costs by reducing the total number of hardware designs required to address a given application segment. the controller's ability to readily accept change makes possible low-cost, custom po wer supply versions with relatively short lead-time. the cost and risk of field configuration and/or updating is greatly reduced, loweri ng the overhead associated with customer support. more advanced control algorithms : power supply design with fixed-function analog components leads to many performance trade-offs. for example, analog compensator design routinely trades stability for higher loop bandwidth, and places the required poles and zeros using passive components. the "if- then-else" decision-making capability of digital control can change loop bandwidth as needed for optimum control response. for example the controller can operate the compensator at a relatively low bandwidth during steady-state operation, but significantly extend bandwidth during a transient. this adaptive response concept can be applied to improve other operating parameters such as efficiency. power efficiency optimization : in a switched mode power supply, it is desirabl e to maintain high power efficiency over a wide range of loads. software algorithms can optimize efficiency at every point of line and load. for example, the software can adjust dead time with changes load, disable synchronous rectification at low loads, or take other measures to maximize efficiency. higher operating precision : switch timing, control response and protection sett ing thresholds in analog systems are typically determined by the values of external passive components. these components typically have a wide tolerance and vary with temperature and time. designers must allow for these tolerances when considering worst case operating conditions. digital control offers tighter parameter tolerances with greatly reduced temperature/time variations resulting in improved worst-case operating specifications. power management and power delivery functions in a single package : power management functions, such as external supply sequencing, pmbus communication support and fan control can be performed by the digital controller, eliminating dedicated external components. system connectivity : pmbus and other emerging communication protocols enable system processors to communicate with the power supply to obtain data and command action. for example, the system processor may request the power supply operating history, perform self-diagnostics or change system settings without taking the supply off-line. communications with the system controller enables notification of a pending power supply failure, enhancing system reliability. this attribute also reduces the cost and complexity of field configurations and upgrades. higher integration/smaller size/lower cost : many discrete circuits can be transformed to lines of software code, eliminating components and saving cost. the digital controller can be used to execute self-diagnostic routines during production test thereby reducing test time and saving cost. the small physical size of th e SI8250 in particular (5 x 5 mm) saves board space. free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 15 3. product description figure 1. functional block diagram figure 2. SI8250 top-level block diagram SI8250/1/2 system management processor i/o (8) i/o (8) 50mips 8051 cpu 1280 byte ram 16/32 kb flash port 0 8 mux temp sensor port 1 hardware debug reset control 2% 25 mhz osc, and lfo interrupt control 4x 16-bit timers smbus 3 ch pca i/o port latches adc registers & limit detectors 12-bit 200 ksps adc uart auto scan logic vsense debug port vdd sysclkin control processor ipk vsense vref gate control (6) multiphase dpwm pulse-by-pulse current limiter and ocp icyc u(n) 10 mhz adc refdac vref dsp filter engine vsense ocp power stages SI8250 system management processor port 0 i/o crossbar temp sensor port 1 50mips 8051 cpu and memory digital peripherals: - uart - smbus port - 4 x 16-bit timers - 3 ch pca (pwm) - i/o port latches vsense debug port vdd sysclkin control processor ipk vsense vref multiphase dpwm pulse-by-pulse current limiter and ocp icyc u(n) adc1 10msps refdac vref dsp filter engine vsense ocp adc 0 12-bit, 200ksps 10-channel up to 6 gate control outputs gate drivers 16 general-purpose analog/digital i/o lines supply input voltage output filter switches and magnetics analog input (e.g. average current) digital ouput (e.g. fan speed control) vout peak current signal (e.g. ct) free datasheet http:///
SI8250/1/2 16 preliminary rev. 0.8 3.1. system operation figure 2 shows the SI8250/1/2 controlling a non- isolated dc/dc converter operating in digital voltage mode control. the output volt age signal connects to the vsense input through a resistive divider, limiting the common mode voltage range applied to adc1 to a maximum of vref. the equivalent resistance of the divider and the capacitor form an anti-aliasing filter with a cutoff frequency equal to adc1 sampling frequency of divided by 2 (the amplitudes of frequencies above fs/2 must be minimized to prevent aliasing). differential adc1 and the dsp filter engine together perform the same function as an analog error amplifier and associated rc compensation network. adc1 digitizes the difference between the scaled output voltage and a programmable reference voltage provided by the refdac. the adc1 output signal is frequency compensated (in digital domain) by the dsp filter engine. the resulting output from the dsp filter engine is a digital code that represents the compensated duty cycle ratio, u(n). the digital pwm generator (dpwm) directly varies output timing to the external gate drivers based on the value of u(n) until the difference between vsense and adc1 reference level is driven to zero. sensing circuitry within the power stages (current transformer, sense amp, etc.) provides a signal representative of inductor or transformer current. this signal connects to the pulse-by-pulse current limiting hardware in the SI8250/1/2 via the ipk input pin. this current limiting circuitry is similar to that found in a voltage mode analog pwm. it contains a fast analog comparator and a programmable leading-edge blanking circuit to prevent unwanted tripping of the current sensing circuitry on the leading edge of the current pulse. current limiting occurs when the sensed current exceeds the programmed threshold. when this occurs, the on-going active portions of the pwm outputs are terminated. a programmable ocp counter keeps track of the number of consecut ive current limit cycles, and automatically shuts the supply down when the accumulated number of li mit cycles exceeds the programmed maximum. the system management processor is based on a 50 million instruction per second (mips) 8051 cpu and dedicated a/d converter (adc0). adc0 digitizes key analog parameters that are used by the mcu to provide protection, as well as manage and control other aspects of the power system. on-board digital peripherals include: timers, an smbus interface port (for pmbus or other protocols); and a universal asynchronous receiver/transmitter (uart) for serial communications, useful for communicating across an isolation boundary. the system management processor serves several purposes, among these are: 1. continuously optimizes co ntrol processor operation (e.g. efficiently optimization) 2. executes user-specific al gorithms (e.g. support for proprietary system interfaces) 3. provides regulation for low-bandwidth system variables (e.g. vin feed-forward) 4. performs system fault detection and recovery 5. provides system housekeeping functions such as pmbus communication support 6. manages external device functions (e.g. external supply sequencing, fa n control/monitoring) the SI8250/1/2 system development requires using the SI8250dk, a comprehensive development kit providing all required hardware and software for control system design. it comes complete with pre-written and verified application software, and a set of tools that enable the user to adapt this software to the end application. it also includes a turnkey isolated half-bridge dc/dc converter based on the SI8250/1/2 for evaluation and experimentation. 3.2. control pro cessor functional block descriptions (figure 1) adc 1 : differential input, 10 msps control loop analog- to-digital converter. adc1 digitizes the difference between the vsense input and the programmable voltage reference level from the refdac. adc1 can be operated at either 5 msps or 10 msps and has a programmable lsb size to pr event limit cycle oscillation (limit cycle oscillation can also be avoided using dithering to increase dpwm resolution). adc1 has programmable conversion rates of 10 msps and 5 msps to accommodate a wide loop gain range. adc1 also contains a hardware transient detector that interrupts the cpu at the onset of an output load or unload transient. the cpu respon ds by executing specific algorithms to accelerate output recovery. these algorithms may include increasing loop bandwidth or other measures. refdac : 9-bit digital-to-analog converter provides the output voltage reference setting. the refdac uses the on-board band gap as its voltage reference, or can be referenced to an external voltage reference source. refdac is used for output voltage calibration, margining and positioning. the cpu continuously manages the refdac during soft-start and soft-stop. dsp filter engine : this two-stage loop compensation filter is the functional equivalent of an active rc compensation in an analog control scheme. the first filter stage is a pid filter providing one pole and two free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 17 zeros. the second stage is selectable: a two-pole low- pass filter (lpf) for the fastest possible response, or sinc (multiple zero) decimat ion filter for relatively quieter operation. the pid plus the lpf result in a three pole, two zero composite filt er, while the pid plus the sinc results in a single po le, multiple zero composite filter. the sinc filter provides zeros at intervals equal to f s /(2*dec) where dec is the decimation ratio (i.e. ratio of input to output sampling rate). dec is a software- programmable parameter, and can be programmed such that zero placement occurs that the pwm frequency and its harmonics. this creates more than 100 db attenuation at these frequencies providing lower system noise levels. the end-to-end response of the filter is defined using only six software parameters, and can be re- programmed during converter operation to implement nonlinear control response for improved transient resolution. as described in the adc1 section above, limit cycle oscillation can be avoided by increasing adc1 lsb size to allow the dpwm lsb to fit within a single adc1 output code (i.e. zero-error bin). however in some applications, it may not be desirable to lower adc1 sensitivity. for such applications, limit cycle oscillation can be avoided by dithering the dpwm output. the dsp filter engine contains a pseudo-random, broadband noise generator - mixing this noise into the filter output randomly moves the gate control output(s) over a range of 1 lsb, such that the time-averaged resolution of the dpwm is increased. the filter response is programmed using s-domain design tools included in the SI8250dk development kit, greatly minimizing software writing tasks. pulse-by-pulse current limiter/ocp : high-speed comparator with 4-bit dac threshold generator and 2-bit programmable leading-edge blanking delay generator. the comparator output causes the dpwm to terminate the on-going portions of the active outputs when the peak current signal applied to the ipk input exceeds the threshold setting. hardware performs an ocp supply shutdown when the number of consecutive current limit events equals a programmed maximum. dpwm : output generator may be programmed for pulse width (pwm) or phase-shift modulation using design tools contained in the SI8250dk design kit. the dpwm may be modulated by the front-end of the control processor (adc1 and dsp filter engine); or by the cpu. the dpwm has individually programmable stop states for supply off (disable) and ocp. software bypass mode allows the cpu to force selected outputs high or low while the remaining outputs continue normal operation. the dpwm includes an external sync input and enable input, both of which can be connected to the i/o pins. the enable is a logic input used to turn the power supply on and off. it can be configured to be active high or active low. the sync input allows the start of each switching cycle to be synchronized to an external clock source, including another SI8250/1/2. 3.3. system management processor func- tional block descriptions adc0 : self-sequencing, 10-input, 200 ksps analog-to- digital converter. this general-purpose adc acquires other analog system parameters for supplemental control by the cpu (e.g. dead time control using average input current as the control variable). adc0 also converts the output of the on-board temperature sensor. eight of the ten analog inputs may be connected to the i/o pins for external interface. the remaining two analog inputs (vsense and temp sensor) are internally connected. when placed in auto sequencing mode, adc0 autom atically converts, stores and limit-checks each analog input, and interrupts the cpu when a converted result is outside of its programmed range. this feature greatly facilitates protection functions be cause all measurement and comparison operations are automated. temperature sensor : this sensor measures the die temperature of the SI8250/1/2. it can achieve 3 c accuracy with a single-point calibration and 1 c with a two-point calibration. the temperature output signal is digitized by adc0. 8051 cpu : 50mips cpu core with 1k of sram and up to 32 kb of flash memory. this processor has its own on-board oscillator and pll, reset sources and real- time in-system hardware debug interface e liminating the need for external processo r supervisors, timebases, and "emulators". the cpu has an external interrupt (int0/) that can be connected to an external device via the i/o pins. when interrupted, the cpu suspends execution of the current task, and immediately vectors to an interrupt service rout ine specifically designed to handle the interrupting device. digital peripherals : peripherals include: four 16-bit timers, a three-channel programmable counter array (pca), each channel useful as a pwm, an smbus port useful as a pmbus interface, a uart (useful as a serial data port for isolated applications, and two 8-bit i/o port latches for logic control outputs. free datasheet http:///
SI8250/1/2 18 preliminary rev. 0.8 4. design tools the SI8250dk development kit (figure 3) contains everything required to develop applications with the si825x family of digital power controllers. this kit supports all phases of power supply development from controller design through real-time system debugging. it also includes a turnkey, 35 w isolated dc/dc target board for evaluation and experimentation. figure 3. SI8250dk development kit figure 4. software download to SI8250 mounted in power supply figure 5. timing design tool (top) and buck regulator compensation tool (bottom) the tool set enables the user to configure pre-written application software included in the kit to his application using a set of pc-based graphic al user interface (guis). these guis (figure 5) allow the user to quickly and easily specify and verify system timing, loop compensation and protection settings, and compile and download the resulting code into the SI8250/1/2 (figure 4). free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 19 5. example applications isolated dc/dc converter : a 35 w, 400 khz SI8250-based half bridge conv erter is shown in figure 6. this circuit is the same as that of the target (evaluation) board shipped in the SI8250dk development kit. figure 6. isolated half-bridge dc/dc converter the SI8250/1/2 is located on the secondary-side of the power supply for optimum transient response. dpwm outputs ph3 and ph4 control gates of the synchronous re ctifiers via a dual driver i.c. dpwm outputs ph1 and ph2 control the gates of the primary-si de switching transistors with isolatio n provided by a silicon laboratories isolator. a current transformer circuit provides peak current sensing. primary side analog parameters (input voltage and current and the filter node voltage ) are digitized by a silicon laborat ories c8051f300 mi crocontroller and passed to the SI8250/1/2 using the on-board uart thro ugh additional channels of the isolator i.c. to the SI8250/1/2. the SI8250/1/2 is uses the application software includ ed with the SI8250dk development kit after being configured for the half-bridge application using the tools supplied in the kit. when power is applied, the cpu executes an internal reset followed by initializat ion of all parameters. the SI8250/1/2 remains in a low-power state, monitoring di gitized vin data from the primary-side mcu until vin is within specified limits. at this time, th e controller is fully enabled and executes soft-start by monitoring vout while sequentially incrementing the loop voltage reference (refda c) until the supply output voltage is within specified range, at which time stead y-state operation begins. during steady-state operation, the mcu operates in in terrupt mode where hardware events divert program execution to specific routines in priority order. 2.2uf 180nh 6 x 100 uf cerami c dri v er p2 irlr8113 irlr8113 180nh . 0.001 6:1 si 8250 di gital controll er vout p3 p4 ph4 ph3 p2 p1 10k 3.9k 0.01uf ipk vsense iout c8051f300 microcontrol ler 33k 1k ai n rx isol ator ph2 ph1 0.010 ai n 1uh 33k 1k vin+ 1.2nf 120uf vi n- gnd vdd 3v3p iin dc bal ai n vin 2.2uf tx 4.7 drive r p1 4.7 0.01uf 4.7 4.7 7. 5 ~ + ~ - fds3572 fds3572 dri v er p3 dri v er p4 200 200 3v3p vdda gnda 3v3p vddb gndb gnd vdd free datasheet http:///
SI8250/1/2 20 preliminary rev. 0.8 single phase pol (point of load) converter : a 65 w, 400 khz si8252 based single phase pol converter block diagram is shown in figure 7. dpwm outputs ph1 and ph2 control the gates of the buck and synchronous switching transistors. a lossless current se nsing method that relies on the resist or and inductance of the inductor is used to measure the current for over current protecti on. the input voltage is measured using resistor divider network and analog input port ain0 of 12bit, 200 khz adc0. figure 7. single-phase pol block diagram when power is applied, the cpu executes an internal re set followed by initialization of all parameters. the si8252 remains in a low-power state, monitoring digitized vin data until vin is within specified limits. at this time, the controller is fully enabled and executes soft-start by moni toring output voltage while sequentially incrementing the loop voltage reference (refdac) until t he supply output voltage is within spec ified range, at which time steady- state operation begins. as in the previous half-bridge example, transient respons e is improved by adjusting l oop gain at the onset of a transient (i.e. nonlinear control). the efficiency of th e pol converter can be optimized over the complete load range by dynamically adjusting the dead-times. typical efficiency simulation results for the pol are shown in figure 8. in this case, the single-pha se pol operates at a pwm frequency of 400 khz with an output voltage of 3.3 v and an input voltage range of 10 to 15 v. the curve shows the efficiency with an input voltage of 12.0 v. figure 8. pol efficiency ph1 ph2 vsense ipk driver driver vin +2.5 v cin gnd si8252 ain0 vin vout load ipk differential amplifier l c vdd ipk 0 5 10 15 20 25 80 85 90 95 eff io () io free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 21 6. layout considerations the mixed-signal nature of the SI8250/1/2 mandates clean bias supplies and ground returns. it is best to provide separate ground planes for analog, digital and power switch returns. these planes shoul d tie together at only one point to eliminate the possibility of circulating ground currents. for best performance, the vdd supply should be decoup led from the main supply. the lqfp-32 package provides the best noise performance because it has separate a nalog and digital vdd and ground inputs (avdd, agnd). as shown in figure 9, the avdd is decoupled by a filter consisting of a 1 ? resistor in series with a 500 ma, 40 ? ferrite bead and a parallel combination of a 10 uf with a 0.1 uf high-frequency bypass capacitor. all connections should be kept as short as possible. the vdda and gnda should be connected into their respective ground planes. the qfn-28 package shares analog and digital power with ground on the same pins. power supply decoupling is shown in figure 10. again, all conn ections should be kept as short as possible. figure 9. power supply connections for lqfp-32 package figure 10. power supply connections for qfn-28 package avdd dvdd ferrite bead 500 ma, 40 ? 0.1 uf 10 uf SI8250/1/2 agnd dgnd agnd 10 uf 0.1 uf 2.5 v 1 ? keep trace lengths as short as possible vdd ferrite bead 500 ma, 40 ? 0.1 uf 10 uf SI8250/1/2 gnd 2.5 v 1 ? keep trace lengths as short as possible free datasheet http:///
SI8250/1/2 22 preliminary rev. 0.8 in both cases, the bias supplies must be filtered us ing low esr/esl capacitors placed close to the ic pins. thick copper traces should be connected to the bias pins (vdd, vdda) and the ground pins (gnd, gnda) to reduce resistance and inductance. the copper routings from the drivers to the fets should be kept short and wide, especially in very high frequency app lications, to reduce inductance of the tr aces so that the drive signals can be kept clean. connections betw een vsense and the output voltage must be kept absolutely as short as possible to minimize inductance and parasitic ringing effects. it is best to locate the SI8250/1/2 as close to th e output voltage terminal as possible and use a kelvin connection to ensure to difference in ground potential between the SI8250/1/2 and the output voltage ground return. most applications will require access to the debug pins. these pins are susceptible to damage from electrostatic discharge (esd). it is therefore recommended the debug circ uit interface use the input pr otection circuitry shown in figure 11. figure 11. debug interface pin protection circuit debug connector 10 10 SI8250/1/2 debug pins (c2d, c2ck) 2.5 v free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 23 7. pin descriptions?SI8250/1/2 figure 12. example pin configurations table 17. pin descriptions name qfn-28 pin # lqfp-32 pin# type description rst /c2ck 1 1 d i/o reset input or bidirect debug clock ipk 22 ain inductor current input vsense 33 ain output voltage feedback input gnd 4? ain ground gnda ?4 ain ground vdd 5? ain power supply input vdda ?5 ain power supply input vref 66 ain external voltage reference input p1.0/vin or ain0 7 7 d i/o or ain port 1 i/o or scaled power supply input voltage or adc input 0 p1.1/ain1 8 8 d i/o or ain port 1 i/o or adc input 1 p1.2/ain2 9 9 d i/o or ain port 1 i/o or adc input 2 p1.3/ain3 10 10 d i/o or ain port 1 i/o or adc input 3 p1.4/ain4 11 11 d i/o or ain port 1 i/o or adc input 4 gnd ?12 ain ground vdd ?13 ain power supply input p1.5/ain5 12 14 d i/o or ain port 1 i/o or adc input 5 p1.6/ain6 13 15 d i/o or ain port 1 i/o or adc input 6 p1.7/ ain7/c2d 14 16 d i/o, din or ain port 1 i/o or adc input 7 or c2 data 32-pin lqfp 28-pin qfn 1 vsense p0.0 p0.5 p0.2 p0.1 p0.3 / xclk p1.0/vin/ain0 ipk p0.6 p0.7 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 p0.4 SI8250/1/2 top view p1.1/ain1 gnda vdda rst/c2ck gnd vdd p1.5/ain5 p1.6/ain6 p1.7/ain7/c2d ph6 ph5 p1.4/ain4 vdd gnd ph3 p1.3/ain3 p1.2/ain2 vref ph4 ph2 ph1 4 5 6 7 2 1 3 11 12 13 14 9 8 10 18 17 16 15 20 21 19 25 26 27 28 23 22 24 SI8250/1/2 top view rst / c2ck ipk vsense gnd vdd vref p1.0/vin/ain0 p1.1/ain1 p1.2/ain2 p1.3/ain3 p1.4/ain4 p1.5/ain5 p1.6/ain6 p1.7/ain7/c2d p0.7 p0.6 p0.5 p0.4 p0.3/xclk p0.2 p0.1 p0.0 ph6 ph5 ph4 ph3 ph2 ph1 gnd gnd free datasheet http:///
SI8250/1/2 24 preliminary rev. 0.8 pin functions: rst/c2ck : cpu reset or debug tool clock. driving this pin low re sets the cpu. this pin is also clocked by the usb debug adaptor during debug. ipk : input to the peak current detector for pulse-by-pulse current limiting and over-current protection shutdown control. vsense : adc1 inverting input. this is the voltage feedback input for the SI8250. the maximum allowable signal is vref. gnd : digital ground for the 32lqfp package, and the main ground for the 28mlp package. gnda : analog ground for 32lqfp only. vdd : digital supply voltage for the 32lqfp package, and main supply voltage for the 28mlp package. vdda : analog supply for 32lqfp only. p1.0/vin or ain0 : programmable multifunction i/o pin. this pin can be software configured to be either a port 1 digital input or output, or an adc0 input at amux addre ss 0. if used in a non-isolated application, positive input supply voltage must be tied to this input through a resistor divider and anti-aliasing capacitor to minimize the frequencies above fs/2 (100khz) to prevent aliasing. isol ated applications may use this input as general-purpose digital i/o or analog input. p1.1 or ain1?p1.7 or ain7 : programmable multifunction i/o pins. these pins can be software configured to be a port 1 digital input or output, or an adc0 input. p1.7 also serves as the debug data input (c2d) and is used during debug by the usb debug adaptor. p1.7 may be used as ge neral-purpose digital i/o when not in debug mode. any of the digital peripherals may be programmed to connect to these pins. p0.0?p0.7 : programmable multifunction i/o pins. these pins c an be software configured to be either a port 1 digital input or output, or an adc0 input. any of th e digital peripherals (including the enable input) may be programmed to connect to these pins. p0.3 may be progra mmed to serve as an exter nal (25mhz nominal) clock input. ph1?ph6 : dpwm gate control (complementary drive) outp uts. these signals connect to the mosfet gates through an external gate driver. the output levels swing between ground and vdd. p0.7 15 17 d i/o port 0 i/o p0.6 16 18 d i/o port 0 i/o p0.5 17 19 d i/o port 0 i/o p0.4 18 20 d i/o port 0 i/o p0.3/xclk 19 21 d i/o port 0 i/o p0.2 20 22 d i/o port 0 i/o p0.1 21 23 d i/o port 0 i/o p0.0 22 24 d i/o port 0 i/o or bidirectional debug data ph6 23 25 dout phase 6 switch control output ph5 24 26 dout phase 5 switch control output ph4 25 27 dout phase 4 switch control output vdd ?28 ain power supply input gnd ?29 ain ground ph3 26 30 dout phase 3 switch control output ph2 27 31 dout phase 2 switch control output ph1 28 32 dout phase 1 switch control output table 17. pin descriptions (continued) name qfn-28 pin # lqfp-32 pin# type description free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 25 8. ordering guide ordering number flash memory number of pwm outputs uart package SI8250-iq 32 kb 6 yes lqfp-32 SI8250-im 32 kb 6 yes qfn-28 si8251-iq 16 kb 6 yes lqfp-32 si8251-im 16 kb 6 yes qfn-28 si8252-iq 16 kb 3 no lqfp-32 si8252-im 16 kb 3 no qfn-28 free datasheet http:///
SI8250/1/2 26 preliminary rev. 0.8 9. package outline?32lqfp figure 13 illustrates the package details for the 32-pin lqfp version of the si 8250/1/2. table 18 lists the values for the dimensions shown in the illustration. figure 13. 32-pin lqfp package diagram table 18. lqfp-32 package dimensions mm min typ max a??1.60 a1 0.05 ? 0.15 a2 1.35 1.40 1.45 b 0.300.370.45 d ? 9.00 ? d1 ? 7.00 ? e ? 0.80 ? e ? 9.00 ? e1 ? 7.00 ? pin 1 identifier a1 e b 1 32 e1 d1 d e a2 a l free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 27 10. package outline?28qfn figure 14 illustrates the package details for the 28-lead qfn version of the si82 50/1/2. table 19 lists the values for the dimensions shown in the illustration. figure 14. 28-lead quad flat no-lead (qfn) package diagram table 19. qfn-28 package dimensions mm mm min typ max min typ max a 0.80 0.90 1.00 l 0.45 0.55 0.65 a1 0 0.02 0.05 n ? 28 ? a2 0 0.65 1.00 nd ? 7 ? a3 ? 0.25 ? ne ? 7 ? b 0.180.230.30 r 0.09 ? ? d ? 5.00 ? aa ? 0.435 ? d2 2.90 3.15 3.35 bb ? 0.435 ? e ? 5.00 ? cc ? 0.18 ? e2 2.90 3.15 3.35 dd ? 0.18 ? e?0.5? 1 e d a2 a a1 e a3 e2 r e l bottom view side view 2 3 4 5 6 7 8 9 10 12 13 14 21 20 19 17 16 15 28 27 26 24 23 22 e2 25 2 d2 11 18 d2 2 6 x e 6 x e detail 1 detail 1 aa bb cc dd b free datasheet http:///
SI8250/1/2 28 preliminary rev. 0.8 d ocument c hange l ist revision 0.7 to revision 0.8 updated dpwm phase output drive-high and drive- low resistance in table 8, ?dpwm specifications,? on page 9. free datasheet http:///
SI8250/1/2 preliminary rev. 0.8 29 n otes : free datasheet http:///
SI8250/1/2 30 preliminary rev. 0.8 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: product info@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages. free datasheet http:///

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