View HB56SW832DZJ-6L_7318493.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hb56sw832dzj series 32 mb edo dram s.o.dimm 8-mword 32-bit, 2 k refresh, 2-bank module (16 pcs of 4 m 4 components) ade-203-790b (z) rev.2.0 nov. 1997 description the hb56sw832dzj is a 8m 32 dynamic ram small outline dual in-line memory module (s.o.dimm), mounted 16 pieces of 16-mbit dram (hm51w17405) sealed in tcp package. an outline of the hb56sw832dzj is 72-pin zig zag dual tabs socket type compact and thin package. therefore, the hb56sw832dzj makes high density mounting possible without surface mount technology. the hb56sw832dzj provides common data inputs and outputs. decoupling capacitors are mounted on the module board. features 72-pin zig zag dual tabs socket type ? outline: 59.69 mm (length) 25.40 mm (height) 3.80 mm (thickness) ? lead pitch: 1.27 mm single 3.3 v (+0.3 v, C0.15 v) supply high speed ? access time: t rac = 60/70 ns (max) t cac = 15/18 ns (max) low power dissipation ? active mode: 2.74/2.45 w (max) ? standby mode (ttl): 115.2 mw (max) (cmos): 8.64 mw (max) (l/ls-version) edo mode capability refresh period ? 2048 refresh cycles: 32 ms 128 ms (l/ls-version) 3 variations of refresh ? ras -only refresh ? cas -before- ras refresh ? self refresh (ls-version)
hb56sw832dzj series 2 ordering information type no. access time package contact pad hb56sw832dzj-6 hb56sw832dzj-7 60 ns 70 ns 72-pin small outline dimm gold HB56SW832DZJ-6L hb56sw832dzj-7l 60 ns 70 ns HB56SW832DZJ-6Ls hb56sw832dzj-7ls 60 ns 70 ns
hb56sw832dzj series 3 pin arrangement 1 pin 71 pin 72 pin 2 pin front side back side pin arrangement front side back side pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1v ss 37 dq18 2 dq0 38 dq19 3 dq1 39 v ss 4 dq2 40 ce0 5 dq3 41 ce2 6 dq4 42 ce3 7 dq5 43 ce1 8 dq6 44 re0 9 dq7 45 re1 10 v cc 46 nc 11 pd1 47 we 12 a0 48 nc 13 a1 49 dq20 14 a2 50 dq21 15 a3 51 dq22 16 a4 52 dq23 17 a5 53 dq24 18 a6 54 dq25 19 a10 55 nc 20 nc 56 dq27 21 dq9 57 dq28 22 dq10 58 dq29 23 dq11 59 dq31 24 dq12 60 dq30 25 dq13 61 v cc 26 dq14 62 dq32 27 dq15 63 dq33 28 a7 64 dq34 29 nc 65 nc 30 v cc 66 pd2 31 a8 67 pd3 32 a9 68 pd4 33 re3 69 pd5 34 re2 70 pd6 35 dq16 71 pd7 36 nc 72 v ss
hb56sw832dzj series 4 pin description pin name function a0 to a10 address inputs: row address: a0 to a10 column address: a0 to a10 refresh address: a0 to a10 dq0 to dq7, dq9 to dq16, dq18 to dq25, dq27 to dq34 data-in/data-out re0 to re3 row address strobe ( ras ) ce0 to ce3 column address strobe ( cas ) we read/write enable v cc power supply v ss ground pd1 to pd7 presence detect nc no connection presence detect pin arrangement function pin no. pin name 60 ns 70 ns 11 pd1 nc nc 66 pd2 nc nc 67 pd3 v ss v ss 68 pd4 v ss v ss 69 pd5 nc v ss 70 pd6 nc nc 71 pd7 nc nc pd7 (ls-version) v ss v ss
hb56sw832dzj series 5 block diagram we re1 ce0 dq0 dq1 dq2 dq3 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o cas ras we d0 dq4 dq5 dq6 dq7 cas ras we d1 dq9 dq10 dq11 dq12 cas ras we d2 dq13 dq14 dq15 dq16 cas ras we d3 ce1 re0 i/o i/o i/o i/o cas ras we d8 i/o i/o i/o i/o cas ras we d9 i/o i/o i/o i/o cas ras we d10 i/o i/o i/o i/o cas ras we d11 i/o i/o i/o i/o i/o i/o i/o i/o dq18 dq19 dq20 dq21 cas ras we d4 dq22 dq23 dq24 dq25 cas ras we d5 ce2 re3 re2 i/o i/o i/o i/o cas ras we d12 i/o i/o i/o i/o cas ras we d13 i/o i/o i/o i/o i/o i/o i/o i/o dq27 dq28 dq29 dq30 cas ras we d6 dq31 dq32 dq33 dq34 cas ras we d7 ce3 i/o i/o i/o i/o cas ras we d14 i/o i/o i/o i/o cas ras we d15 a0 to a10 v cc v ss d0 to d15 d0 to d15 d0 to d15 0.1 m f 8 pcs * d0 to d15 : hm51w17405 oe oe oe oe oe oe oe oe oe oe oe oe oe oe oe oe
hb56sw832dzj series 6 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v t C0.5 to +4.6 v supply voltage relative to v ss v cc C0.5 to +4.6 v short circuit output current iout 50 ma power dissipation pt 8 w operating temperature topr 0 to +70 c storage temperature tstg C55 to +125 c recommended dc operating conditions (ta = 0 to 70 c) parameter symbol min typ max unit note supply voltage v ss 000 v v cc 3.15 3.3 3.6 v 1 input high voltage v ih 2.0 v cc +0.3 v 1 input low voltage v il C0.3 0.8 v 1 note: 1. all voltage referred to v ss .
hb56sw832dzj series 7 dc characteristics (ta = 0 to 70 c, v cc = 3.3 v +0.3 v, C0.15 v, v ss = 0 v) 60 ns 70 ns parameter symbol min max min max unit test conditions notes operating current i cc1 760 680 ma t rc = min 1, 2 standby current i cc2 32 32 ma ttl interface ras , cas = v ih dout = high-z 16 16 ma cmos interface ras , cas 3 v cc C 0.2 v dout = high-z standby current (l/ls-version) i cc2 2.4 2.4 ma cmos interface ras , cas 3 v cc C 0.2 v dout = high-z ras -only refresh current i cc3 760 640 ma t rc = min 2 standby current i cc5 80 80 ma ras = v ih , cas = v il dout = enable 1 cas -before- ras refresh current i cc6 760 680 ma t rc = min edo page mode current i cc7 680 640 ma t hpc = min 1, 3 battery backup current (standby with cbr refresh) (l/ls-version) i cc10 6.4 6.4 ma cmos interface dout = high-z cbr refresh: t rc = 62.5 m s t ras 0.3 m s self refresh mode current (ls-version) i cc11 4.0 4.0 ma cmos interface ras , cas 0.2 v dout = high-z input leakage current i li C10 10 C10 10 m a 0 v vin 4.6 v output leakage current i lo C10 10 C10 10 m a 0 v vout 4.6 v dout = disable output high voltage v oh 2.4 v cc 2.4 v cc v high iout = C2 ma output low voltage v ol 0 0.4 0 0.4 v low iout = 2 ma notes: 1. i cc depends on output load condition when the device is selected, i cc max is specified at the output open condition. 2. address can be changed once or less while ras = v il . 3. address can be changed once or less while cas = v ih .
hb56sw832dzj series 8 capacitance (ta = 25 c, v cc = 3.3 v +0.3 v, C0.15 v) parameter symbol typ max unit notes input capacitance (address) c i! 100 pf 1 input capacitance ( we )c i2 132 pf 1 input capacitance ( cas )c i3 48pf1 input capacitance ( ras )c i4 48pf1 i/o capacitance (dq) c i/o 25 pf 1, 2 notes: 1. capacitance measured with boonton meter or effective capacitance measuring method. 2. cas = v ih to disable dout. ac characteristics (ta = 0 to 70 c, v cc = 3.3 v +0.3 v, C0.15 v, v ss = 0 v) * 1 , * 2 , * 18 test conditions input rise and fall times: 2 ns input levels: 0 v, 3.0 v input timing reference levels: 0.8 v, 2.0 v output timing reference levels: 0.8 v, 2.0 v output load: 1 ttl gate + c l (100 pf) (including scope and jig)
hb56sw832dzj series 9 read, write, and refresh cycles (common parameters) 60 ns 70 ns parameter symbol min max min max unit notes random read or write cycle time t rc 104 124 ns ras precharge time t rp 40 50 ns cas precharge time t cp 10 13 ns ras pulse width t ras 60 10000 70 10000 ns cas pulse width t cas 10 10000 13 10000 ns row address setup time t asr 00ns row address hold time t rah 10 10 ns column address setup time t asc 00ns column address hold time t cah 10 13 ns ras to cas delay time t rcd 14 45 14 52 ns 3 ras to column address delay time t rad 12 30 12 35 ns 4 ras hold time t rsh 13 13 ns cas hold time t csh 40 45 ns cas to ras precharge time t crp 55ns cas delay time from din t dzc 00ns transition time (rise and fall) t t 2 50 2 50 ns 5 refresh period (2,048 cycles) t ref 32 32 ms refresh period (2,048 cycles) (l/ls-version) t ref 128 128 ms
hb56sw832dzj series 10 read cycle 60 ns 70 ns parameter symbol min max min max unit notes access time from ras t rac 60 70 ns 6, 7 access time from cas t cac 15 18 ns 7, 8, 15 access time from address t aa 30 35 ns 7, 9, 15 read command setup time t rcs 00ns read command hold time to cas t rch 00ns10 read command hold time from ras t rchr 60 70 ns read command hold time to ras t rrh 55ns10 column address to ras lead time t ral 30 35 ns column address to cas lead time t cal 18 23 ns cas to output in low-z t clz 00ns output data hold time t oh 33ns19 output buffer turn-off time t off 15 15 ns 11, 19 cas to din delay time t cdd 15 18 ns output data hold time from ras t ohr 33ns19 output buffer turn-off time to ras t ofr 15 15 ns 19 output buffer turn-off to we t wez 15 15 ns we to din delay time t wed 15 18 ns ras to din delay time t rdd 15 18 ns ras to next cas delay time t rncd 60 70 ns write cycle 60 ns 70 ns parameter symbol min max min max unit notes write command setup time t wcs 00ns12 write command hold time t wch 10 13 ns write command pulse width t wp 10 10 ns data-in setup time t ds 00ns13 data-in hold time t dh 10 13 ns 13
hb56sw832dzj series 11 refresh cycle 60 ns 70 ns parameter symbol min max min max unit notes cas setup time (cbr refresh cycle) t csr 55ns cas hold time (cbr refresh cycle) t chr 10 10 ns we setup time (cbr refresh cycle) t wrp 00ns we hold time (cbr refresh cycle) t wrh 10 10 ns ras precharge to cas hold time t rpc 55ns edo page mode cycle 60 ns 70 ns parameter symbol min max min max unit notes edo page mode cycle time t hpc 25 30 ns 16 edo page mode ras pulse width t rasp 100000 100000 ns 14 access time from cas precharge t cpa 35 40 ns 7, 15 ras hold time from cas precharge t cprh 35 40 ns output data hold time from cas low t doh 3 3 ns 7, 15 read command hold time from cas precharge t rchc 35 40 ns self refresh mode (l/ls-version) 60 ns 70 ns parameter symbol min max min max unit notes ras pulse width (self refresh) t rass 100 100 m s ras precharge time (self refresh) t rps 110 130 ns cas hold time (self refresh) t chs C50 C50 ns
hb56sw832dzj series 12 notes: 1. ac measurements assume t t = 2 ns. 2. an initial pause of 200 m s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing ras -only refresh cycle or cas -before- ras refresh). if the internal refresh counter is used, a minimum of eight cas -before- ras refresh cycles are required. 3. operation with the t rcd (max) limit insures that t rac (max) can be met, t rcd (max) is specified as a reference point only; if t rcd 3 t rcd (max) + t aa (max) - t cac (max), then access time is controlled exclusively by t cac . 4. operation with the t rad (max) limit insures that t rac (max) can be met, t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, then access time is controlled exclusively by t aa . 5. v ih (min) and v il (max) are reference levels for measuring timing of input signals. also, transition times are measured between v ih (min) and v il (max). 6. assumes that t rcd t rcd (max) and t rad t rad (max). if t rcd or t rad is greater than the maximum recommended value shown in this table, t rac exceeds the value shown. 7. measured with a load circuit equivalent to 1 ttl loads and 100 pf. 8. assumes that t rcd 3 t rcd (max) and t rcd + t cac (max) 3 t rad + t aa (max). 9. assumes that t rad 3 t rad (max) and t rcd + t cac (max) t rad + t aa (max). 10. either t rch or t rrh must be satisfied for a read cycles. 11. t off (max) defines the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 12. early write cycle only (t wcs 3 t wcs (min)). 13. these parameters are referred to cas leading edge in early write cycles. 14. t rasp defines ras pulse width in edo page mode cycles. 15. access time is determined by the longest among t aa , t cac and t cpa . 16. t hpc (min) can be achieved during a series of edo page mode write cycles or edo page mode read cycles. 17. when output buffers are enabled once, sustain the low impedance state until valid data is obtained. when output buffer is turned on and off within a very short time, generally it causes large v cc / v ss line noise, which causes to degrade v ih min./ v il max level. 18. all the v cc and v ss pins shall be supplied with the same voltages. 19. data output turns off and becomes high impedance from later rising edge of ras and cas . hold time and turn off time are specified by the timing specifications of later rising edge of ras and cas between t ohr and t oh , and between t ofr and t off . 20. please do not use t rass timing, 10 m s t rass 100 m s. during this period, the device is in transition state from normal operation mode to self refresh mode. if t rass 3 100 m s, then ras precharge time should use t rps instead of t rp . 21. if you use distributed cbr refresh mode with 15.6 m s interval in normal read/write cycle, cbr refresh should be executed within 15.6 m s immediately after exiting from and before entering into self refresh mode. 22. if you use ras only refresh or cbr burst refresh mode in normal read/write cycle, 2048 cycles of distributed cbr refresh with 15.6 m s interval should be executed within 32 ms immediately after exiting from and before entering into the self refresh mode. 23. xxx: h or l (h: v ih (min) v in v ih (max), l: v il (min) v in v il (max)) ///////: invalid dout when the address, clock and input pins are not described on timing waveforms, their pins must be applied v ih or v il .
hb56sw832dzj series 13 timing waveforms * 23 read cycle ras address we dout din t rc t ras t rp t csh t crp t rcd t rsh t cas t t t rad t ral t cal t asc t cah t asr row column t rah t rcs t rch t rrh t cdd t dzc high-z dout t rac t aa t cac t clz t oh t off cas t rdd t wed t ofr t ohr t wez t rchr
hb56sw832dzj series 14 early write cycle ras address we din dout t rc * t ras t rp t crp t csh t rcd t rsh t cas t t t asr t rah t asc t cah column row t wcs t wch t wp t ds t dh din t wcs wcs (min) high-z* t cas
hb56sw832dzj series 15 ras -only refresh cycle ras address dout high-z row t rc t rp t ras t t t crp t rpc t crp t asr t rah t off t ofr cas
hb56sw832dzj series 16 cas -before- ras refresh cycle ras cas we dout address t rc t rp t ras t rpc t csr t chr t rpc t crp t cp t wrh t wrp t cp t t t off t ofr high-z t rp
hb56sw832dzj series 17 edo page mode read cycle din dout we address ras t cp t cp t cp t t t rch t rrh t dzc t cdd t rdd high-z t ofr t off t oh t ohr t cpa t aa t cac t cac t aa t rac t aa t cac t cpa t aa t cac t t rasp t rp t cas t cas t cas t cal t csh t rncd t hpc t hpc crp t t asr t rah column 1 column 2 column 3 column 4 t t cah t asc t cah t cah t asc t cah t asc t wed t ral row dout 2 dout 4 dout 1 t cas t rcs t t rcs dout 3 t t cprh t hpc t wez doh t doh rch t rchr t cal t cal t cal t rsh t rchc cpa asc cas
hb56sw832dzj series 18 edo page mode early write cycle * t wcs wcs (min) ras address we din dout t rasp t rp t t t csh t hpc t rsh t crp t cas t cp t cas t cp t cas t rcd t asr t rah t asc t cah t asc t cah t asc t cah t t wcs t t wcs t t wcs t dh t ds t dh t ds t dh t ds din 1 din 2 din n high-z* t row column 1 column 2 column n cas wch wch wch t wp t wp t wp
hb56sw832dzj series 19 self refresh cycle (ls-version) * 20, 21, 22 ras dout t rp t rass t rps t rpc t t t cp t csr t chs t crp t off t ofr high-z cas wrp t wrh t we
hb56sw832dzj series 20 physical outline unit : mm inch 1.00 0.10 0.039 0.004 3.18 0.125 3.80 max 0.150 max 2 ?r2.00 0.10 2 ?r0.079 0.004 r2.00 r0.079 a 2.00 0.079 3.18 min 0.125 min 1 59.69 2.350 71 7.62 0.300 44.45 1.750 2 72 8.25 0.325 5.00 0.197 51.66 2.034 2 ?r3.00 min 2 ?r0.118 min 44.45 1.750 2 ?1.80 2 ?0.071 1.80 0.071 17.78 0.700 25.40 1.000 3.00 min 0.118 min 3.00 min 0.118 min detail a 0.25 max 2.54 min 1.00 0.05 0.039 0.002 0.010 max 0.100 min 1.27 typ 0.050 typ 3.18 min 0.125 min component area (front) component area (back) front side back side
hb56sw832dzj series 21 when using this document, keep the following in mind: 1. this document may, wholly or partially, be subject to change without notice. 2. all rights are reserved: no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without hitachis permission. 3. hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the users unit according to this document. 4. circuitry and other examples described herein are meant merely to indicate the characteristics and performance of hitachis semiconductor products. hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. no license is granted by implication or otherwise under any patents or other rights of any third party or hitachi, ltd. 6. medical applications: hitachis products are not authorized for use in medical applications without the written consent of the appropriate officer of hitachis sales company. such use includes, but is not limited to, use in life support systems. buyers of hitachis products are requested to notify the relevant hitachi sales offices when planning to use the products in medical applications. hitachi, ltd. semiconductor & ic div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 for further information write to: hitachi semiconductor (america) inc. 2000 sierra point parkway brisbane, ca. 94005-1897 u s a tel: 800-285-1601 fax:303-297-0447 hitachi europe gmbh continental europe dornacher stra? 3 d-85622 feldkirchen m?nchen tel: 089-9 91 80-0 fax: 089-9 29 30-00 hitachi europe ltd. electronic components div. northern europe headquarters whitebrook park lower cookham road maidenhead berkshire sl6 8ya united kingdom tel: 01628-585000 fax: 01628-585160 hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 hitachi asia (hong kong) ltd. unit 706, north tower, world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel: 27359218 fax: 27306071 copyright ?hitachi, ltd., 1997. all rights reserved. printed in japan.
hb56sw832dzj series 22 revision record rev. date contents of modification drawn by approved by 1.0 jun. 12, 1997 initial issue (referred to hm51w16405/hm51w17405 rev. 3.0) s. tsukui k. yoshizaki 2.0 nov. 1997 change of subtitle

▲Up To Search▲

Price & Availability of HB56SW832DZJ-6L

	To Download HB56SW832DZJ-6L Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .