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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information. ? 1997 data sheet mos integrated circuit mc-458cd64s, 458cd64ls 8m-word by 64-bit synchronous dynamic ram module (so dimm) document no. m13041ej6v0ds00 (6th edition) date published february 1999 ns cp(k) printed in japan the mark ? ? ? ? shows major revised points. description the mc-458cd64s and mc-458cd64ls are a 8,388,608 words by 64 bits synchronous dynamic ram module (small outline dimm) on which 8 pieces of 64m sdram: m pd4564163 are assembled. this module provides high density and large quantities of memory in a small space without utilizing the surface- mounting technology on the printed circuit board. decoupling capacitors are mounted on power supply line for noise reduction. features 8,388,608 words by 64 bits organization clock frequency and access time from clk part number /cas latency clock frequency access time from clk power consumption (max.) (max.) (max.) active standby mc-458cd64s-a80 cl = 3 125 mhz 6 ns 3,168 mw 14.4 mw cl = 2 100 mhz 6 ns 2,736 mw (cmos level i nput ) mc-458cd64s-a10 cl = 3 100 mhz 6 ns 2,736 mw cl = 2 77 mhz 7 ns 2,232 mw mc-458cd64s-a10b cl = 3 100 mhz 7 ns 2,736 mw cl = 2 67 mhz 8 ns 1,944 mw mc-458cd64s-a10bl cl = 3 100 mhz 7 ns 2,736 mw cl = 2 67 mhz 8 ns 1,944 mw MC-458CD64LS-A10B cl = 3 100 mhz 7 ns 2,736 mw cl = 2 67 mhz 8 ns 1,944 mw MC-458CD64LS-A10Bl cl = 3 100 mhz 7 ns 2,736 mw cl = 2 67 mhz 8 ns 1,944 mw fully synchronous dynamic ram, with all signals referenced to a positive clock edge pulsed interface possible to assert random column address in every cycle quad internal banks controlled by ba0, ba1 (bank select) programmable burst-length (1, 2, 4, 8 and full page) programmable wrap sequence (sequential / interleave) programmable /cas latency (2, 3) automatic precharge and controlled precharge cbr (auto) refresh and self refresh single 3.3 v 0.3 v power supply lvttl compatible 4,096 refresh cycles/64 ms burst termination by burst stop command and precharge command 144-pin small outline dual in-line memory module (pin pitch = 0.8 mm) unbuffered type serial pd
2 mc-458cd64s, 458cd64ls data sheet m13041ej6v0ds00 ordering information part number clock frequency mhz (max.) package mounted devices mc-458cd64s-a80 125 mhz 144-pin small outline dimm 8 pieces of m pd4564163g5 (rev. e) mc-458cd64s-a10 100 mhz (socket type) (400 mil tsop (ii)) mc-458cd64s-a10b 100 mhz edge connector : gold plated mc-458cd64s-a10bl 100 mhz 26.67 mm (1.05 inch) height MC-458CD64LS-A10B 100 mhz 8 pieces of m pd4564163g5 (rev. l) MC-458CD64LS-A10Bl 100 mhz (400 mil tsop (ii))
3 mc-458cd64, 458cd64ls data sheet m13041ej6v0ds00 pin configuration 144-pin dual in-line memory module socket type (edge connector : gold plated) /xxx indicates active low si gnal. a0 - a11 : address inputs [row: a0 - a11, column: a0 - a7 ] ba0 (a13), ba1 (a12) : sdram bank select dq0 - dq63 : data inputs/outputs clk0, clk1 : clock input cke0, cke1 : clock enable input /cs0, /cs1 : chip select input /ras : row address strobe /cas : column address strobe /we : write enable dqmb0 - dqmb7 : dq mask enable sda : serial data i/o for pd scl : clock input for pd v cc : power supply v ss : ground nc : no connection 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 vss dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 vss dqmb0 dqmb1 a0 a1 a2 vss dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 vss nc nc 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 clk0 vcc /ras /we /cs0 /cs1 nc vss nc nc dq 16 dq 17 dq 18 dq 19 vss dq 20 dq 21 dq 22 dq 23 vcc a6 a8 vss a9 a10 vcc dqmb2 dqmb3 vss dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 vss sda 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 vss dq 32 dq 33 dq 34 dq 35 vcc dq 36 dq 37 dq 38 dq 39 vss dqmb4 dqmb5 vcc a3 a4 a5 vss dq 40 dq 41 dq 42 dq 43 vcc dq 44 dq 45 dq 46 dq 47 vss nc nc 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 cke0 vcc /cas cke1 nc nc clk1 vss nc nc vcc dq 48 dq 49 dq 50 dq 51 vss dq 52 dq 53 dq 54 dq 55 vcc a7 ba0 (a13) vss ba1 (a12) a11 vcc dqmb6 dqmb7 vss dq 56 dq 57 dq 58 dq 59 vcc dq 60 dq 61 dq 62 dq 63 vss scl vcc cc v cc v cc v cc v cc v cc v
4 mc-458cd64s, 458cd64ls data sheet m13041ej6v0ds00 block diagram cke0 /cs0 a0 - a11 a0 - a11 : d0 - d7 v cc d0 - d7 d0 - d7 serial pd scl sda a0 a1 a2 dqmb0 dqmb1 /cs cke d0 udqm ldqm dq 0 dq 1 dq 4 dq 3 dq 2 dq 5 dq 6 dq 7 dqmb2 dqmb3 /cs cke d1 udqm ldqm dqmb6 dqmb7 /cs cke d3 udqm ldqm dqmb4 dqmb5 /cs cke d2 udqm ldqm dq 0 dq 1 dq 2 dq 5 dq 4 dq 3 dq 6 dq 7 dq 8 dq 9 dq 10 dq 13 dq 12 dq 11 dq 14 dq 15 dq 15 dq 14 dq 11 dq 12 dq 13 dq 10 dq 9 dq 8 dq 16 dq 17 dq 18 dq 21 dq 20 dq 19 dq 22 dq 23 dq 24 dq 25 dq 26 dq 29 dq 28 dq 27 dq 30 dq 31 dq 48 dq 49 dq 50 dq 53 dq 52 dq 51 dq 54 dq 55 dq 56 dq 57 dq 58 dq 61 dq 60 dq 59 dq 62 dq 63 dq 32 dq 33 dq 34 dq 37 dq 36 dq 35 dq 38 dq 39 dq 40 dq 41 dq 42 dq 45 dq 44 dq 43 dq 46 dq 47 /ras /ras : d0 - d7 /cas /cas : d0 - d7 /we /we : d0 - d7 v ss ba0 a13 : d0 - d7 clk0 clk : d0, d2 clk : d1, d3 10 w c ba1 a12 : d0 - d7 /cs cke d4 ldqm udqm dq 0 dq 1 dq 4 dq 3 dq 2 dq 5 dq 6 dq 7 /cs cke d5 ldqm udqm /cs cke d7 ldqm udqm /cs cke d6 ldqm udqm dq 15 dq 14 dq 11 dq 12 dq 13 dq 10 dq 9 dq 8 dq 7 dq 6 dq 3 dq 4 dq 5 dq 2 dq 1 dq 0 dq 8 dq 9 dq 12 dq 11 dq 10 dq 13 dq 14 dq 15 cke1 /cs1 clk1 clk : d4, d6 clk : d5, d7 10 w dq 0 dq 1 dq 4 dq 3 dq 2 dq 5 dq 6 dq 7 dq 15 dq 14 dq 11 dq 12 dq 13 dq 10 dq 9 dq 8 dq 0 dq 1 dq 4 dq 3 dq 2 dq 5 dq 6 dq 7 dq 15 dq 14 dq 11 dq 12 dq 13 dq 10 dq 9 dq 8 dq 8 dq 9 dq 12 dq 11 dq 10 dq 13 dq 14 dq 15 dq 7 dq 6 dq 3 dq 4 dq 5 dq 2 dq 1 dq 0 dq 8 dq 9 dq 12 dq 11 dq 10 dq 13 dq 14 dq 15 dq 7 dq 6 dq 3 dq 4 dq 5 dq 2 dq 1 dq 0 dq 7 dq 6 dq 3 dq 4 dq 5 dq 2 dq 1 dq 0 dq 8 dq 9 dq 12 dq 11 dq 10 dq 13 dq 14 dq 15 remark d0 - d7 : m pd4564163 (1m words x 16 bits x 4 banks)
5 mc-458cd64, 458cd64ls data sheet m13041ej6v0ds00 electrical specifications all voltages are referenced to v ss (gnd). after power up, wait more than 100 m s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol condition rating unit voltage on power supply pin relative to gnd v cc C0.5 to +4.6 v voltage on input pin relative to gnd v t C0.5 to +4.6 v short circuit output current i o 50 ma power dissipation p d 8w operating ambient temperature t a 0 to +70 c storage temperature t stg C55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions parameter symbol condition min. typ. max. unit supply voltage v cc 3.0 3.3 3.6 v high level input voltage v ih 2.0 v cc + 0.3 v low level input voltage v il C0.3 + 0.8 v operating ambient temperature t a 070 c capacitance (t a = 25 c, f = 1 mhz) parameter symbol test condition min. typ. max. unit input capacitance c i1 a0 - a11, ba0(a13), ba1(a12), /ras, /cas, /we 60 pf c i2 clk0, clk1 30 c i3 cke0, cke1 30 c i4 /cs0, /cs1 30 c i5 dqmb0 C dqmb7 20 data input/output capacitance c i/o dq0 - dq63 20 pf
6 mc-458cd64s, 458cd64ls data sheet m13041ej6v0ds00 dc characteristics (recommended operating conditions unless otherwise noted) [mc-458cd64s] parameter symbol test condition min. max. unit notes operating current i cc1 burst length = 1, t rc 3 t rc(min.) /cas latency = 2 -a80 460 ma 1 -a10 420 -a10b 380 /cas latency = 3 -a80 560 -a10 460 -a10b 460 precharge standby current in i cc2 p cke v il(max.) , t ck = 15 ns 8 ma power down mode i cc2 ps cke v il(max.) , t ck = 4 precharge standby current in non power down mode i cc2 ncke 3 v ih(min.) , t ck = 15 ns, /cs 3 v ih(min.) , input signals are changed one time during 30 ns. 160 ma i cc2 ns cke 3 v ih(min.) , t ck = , input signals are stable. 48 active standby current in i cc3 p cke v il(max.) , t ck = 15 ns 40 ma power down mode i cc3 ps cke v il(max.) , t ck = 32 active standby current in non power down mode i cc3 ncke 3 v ih(min.) , t ck = 15 ns, /cs 3 v ih(min.) , input signals are changed one time during 30 ns. 200 ma i cc3 ns cke 3 v ih(min.) , t ck = , input signals are stable. 80 operating current i cc4 t ck 3 t ck(min.) , i o = 0 ma /cas latency = 2 -a80 760 ma 2 (burst mode) -a10 620 -a10b 540 /cas latency = 3 -a80 880 -a10 760 -a10b 760 cbr (auto) refresh current i cc5 t rc 3 t rc(min.) /cas latency = 2 -a80 620 ma 3 -a10 620 -a10b 520 /cas latency = 3 -a80 640 -a10 640 -a10b 560 self refresh current i cc6 cke 0.2 v-axx8ma -axxl 3.2 input leakage current i i(l) v i = 0 to 3.6 v, all other pins not under test = 0 v C 8+8 m a output leakage current i o(l) d out is disabled, v o = 0 to 3.6 vC3+3 m a high level output voltage v oh i o = C 4.0 ma 2.4 v low level output voltage v ol i o = + 4.0 ma 0.4 v notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck(min.) . 2 .i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck(min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck(min.) .
7 mc-458cd64, 458cd64ls data sheet m13041ej6v0ds00 [mc-458cd64ls] parameter symbol test condition min. max. unit notes operating current i cc1 burst length = 1, t rc 3 t rc(min.) /cas latency = 2 -a10b 380 ma 1 /cas latency = 3 -a10b 460 precharge standby current in i cc2 p cke v il(max.) , t ck = 15 ns 8 ma power down mode i cc2 ps cke v il(max.) , t ck = 4 precharge standby current in non power down mode i cc2 ncke 3 v ih(min.) , t ck = 15 ns, /cs 3 v ih(min.) , input signals are changed one time during 30 ns. 160 ma i cc2 ns cke 3 v ih(min.) , t ck = , input signals are stable. 48 active standby current in i cc3 p cke v il(max.) , t ck = 15 ns 40 ma power down mode i cc3 ps cke v il(max.) , t ck = 32 active standby current in non power down mode i cc3 ncke 3 v ih(min.) , t ck = 15 ns, /cs 3 v ih(min.) , input signals are changed one time during 30 ns. 200 ma i cc3 ns cke 3 v ih(min.) , t ck = , input signals are stable. 120 operating current i cc4 t ck 3 t ck(min.) , i o = 0 ma /cas latency = 2 -a10b 540 ma 2 /cas latency = 3 -a10b 760 cbr (auto) refresh current i cc5 t rc 3 t rc(min.) /cas latency = 2 -a10b 520 ma 3 /cas latency = 3 -a10b 560 self refresh current i cc6 cke 0.2 v-axx8ma -axxl 3.2 input leakage current i i(l) v i = 0 to 3.6 v, all other pins not under test = 0 v C 8+8 m a output leakage current i o(l) d out is disabled, v o = 0 to 3.6 vC3+3 m a high level output voltage v oh i o = C 4.0 ma 2.4 v low level output voltage v ol i o = + 4.0 ma 0.4 v notes 1. i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc1 is measured on condition that addresses are changed only one time during t ck(min.) . 2 .i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, i cc4 is measured on condition that addresses are changed only one time during t ck(min.) . 3. i cc5 is measured on condition that addresses are changed only one time during t ck(min.) . ?
8 mc-458cd64s, 458cd64ls data sheet m13041ej6v0ds00 ac characteristics (recommended operating conditions unless otherwise noted) ac characteristics test conditions ac measurements assume t t = 1 ns. reference level for measuring timing of input signals is 1.4 v. transition times are measured between v ih and v il . if t t is longer than 1 ns, reference level for measuring timing of input signals is v ih (min.) and v il (max.) . an access time is measured at 1.4 v. t ck t ch t cl 2.0 v 1.4 v 0.8 v clk 2.0 v 1.4 v 0.8 v input t setup t hold output t ac t oh
9 mc-458cd64, 458cd64ls data sheet m13041ej6v0ds00 synchronous characteristics -a80 -a10 -a10b unit note parameter symbol min. max. min. max. min. max. clock cycle time /cas latency = 3 t ck3 8 (125 mhz) 10 (100 mhz) 10 (100 mhz) ns /cas latency = 2 t ck2 10 (100 mhz) 13 (77 mhz) 15 (67 mhz) ns access time from clk /cas latency = 3 t ac3 667ns1 /cas latency = 2 t ac2 678ns1 clk high level width t ch 333.5ns clk low level width t cl 333.5ns data-out hold time t oh 333ns1 data-out low-impedance time t lz 000ns data-out high-impedance time /cas latency = 3 t hz3 363637ns /cas latency = 2 t hz2 363738ns data-in setup time t ds 222.5ns data-in hold time t dh 111ns address setup time t as 222.5ns address hold time t ah 111ns cke setup time t cks 222.5ns cke hold time t ckh 111ns cke setup time (power down exit) t cksp 222.5ns command (/cs0, /cs1, /ras, /cas, /we, dqmb0 - dqmb7) setup time t cms 222.5ns command (/cs0, /cs1, /ras, /cas, /we, dqmb0 - dqmb7) hold time t cmh 111ns note 1. output load output z = 50 w 1.4 v 50 pf 50 w
10 mc-458cd64s, 458cd64ls data sheet m13041ej6v0ds00 asynchronous characteristics parameter symbol -a80 -a10 -a10b unit note min. max. min. max. min. max. act to ref/act command period (operation) t rc 70 70 90 ns ref to ref/act command period (refresh) t rc1 70 70 90 ns act to pre command period t ras 48 120,000 50 120,000 60 120,000 ns pre to act command period t rp 20 20 30 ns delay time act to read/write command t rcd 20 20 30 ns act(one) to act(another) command period t rrd 16 20 20 ns data-in to pre command period t dpl 81010ns data-in to act(ref) command /cas latency = 3 t dal3 1clk+20 1clk+20 1clk+30 ns period (auto precharge) /cas latency = 2 t dal2 1clk+20 1clk+20 1clk+30 ns mode register set cycle time t rsc 222clk transition time t t 0.5 30 1 30 1 30 ns refresh time (4,096 refresh cycles) t ref 64 64 64 ms
11 mc-458cd64, 458cd64ls data sheet m13041ej6v0ds00 serial pd (1/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 0 defines the number of bytes written into serial pd memory 80h 1 0 0 0 0 0 0 0 128 bytes 1 total number of bytes of serial pd memory 08h 0 0 0 0 1 0 0 0 256 bytes 2 fundamental memory type 04h 0 0 0 0 0 1 0 0 sdram 3 number of rows 0ch 0 0 0 0 1 1 0 0 12 rows 4 number of columns 08h 0 0 0 0 1 0 0 0 8 columns 5 number of banks 02h 0 0 0 0 0 0 1 0 2 banks 6 data width 40h 0 1 0 0 0 0 0 0 64 bits 7 data width (continued) 00h 0 0 0 0 0 0 0 0 0 8 voltage interface 01h 0 0 0 0 0 0 0 1 lvttl 9 cl = 3 cycle time -a80 80h 1 0 0 0 0 0 0 0 8 ns -a10 a0h 1 0 1 0 0 0 0 0 10 ns -a10b/-a10bl a0h 1 0 1 0 0 0 0 0 10 ns 10 cl =3 access time -a80 60h 0 1 1 0 0 0 0 0 6 ns -a10 60h 0 1 1 0 0 0 0 0 6 ns -a10b/-a10bl 70h 0 1 1 1 0 0 0 0 7 ns 11 dimm configuration type 00h 0 0 0 0 0 0 0 0 none 12 refresh rate/type 80h 1 0 0 0 0 0 0 0 normal 13sdram width 10h00010000 16 14 error checking sdram width 00h 0 0 0 0 0 0 0 0 none 15 minimum clock delay 01h 0 0 0 0 0 0 0 1 1 clock 16 burst length supported 8fh 1 0 0 0 1 1 1 1 1, 2, 4, 8, f 17 number of banks on each sdram 04h 0 0 0 0 0 1 0 0 4 banks 18 /cas latency supported 06h 0 0 0 0 0 1 1 0 2, 3 19 /cs latency supported 01h 0 0 0 0 0 0 0 1 0 20 /we latency supported 01h 0 0 0 0 0 0 0 1 0 21 sdram module attributes 00h 0 0 0 0 0 0 0 0 22 sdram device attributes : general 0eh 0 0 0 0 1 1 1 0 23 cl = 2 cycle time -a80 a0h 1 0 1 0 0 0 0 0 10 ns -a10 d0h 1 1 0 1 0 0 0 0 13 ns -a10b/-a10bl f0h 1 1 1 1 0 0 0 0 15 ns 24 cl = 2 access time -a80 60h 0 1 1 0 0 0 0 0 6 ns -a10 70h 0 1 1 1 0 0 0 0 7 ns -a10b/-a10bl 80h 1 0 0 0 0 0 0 0 8 ns 25-26 00h 0 0 0 0 0 0 0 0 27 t rp(min.) -a80 14h 0 0 0 1 0 1 0 0 20 ns -a10 14h 0 0 0 1 0 1 0 0 20 ns -a10b/-a10bl 1eh 0 0 0 1 1 1 1 0 30 ns 28 t rrd(min.) -a80 10h 0 0 0 1 0 0 0 0 16 ns -a10 14h 0 0 0 1 0 1 0 0 20 ns -a10b/-a10bl 14h 0 0 0 1 0 1 0 0 20 ns 29 t rcd(min.) -a80 14h 0 0 0 1 0 1 0 0 20 ns -a10 14h 0 0 0 1 0 1 0 0 20 ns -a10b/-a10bl 1eh 0 0 0 1 1 1 1 0 30 ns 30 t ras(min.) -a80 30h 0 0 1 1 0 0 0 0 48 ns -a10 32h 0 0 1 1 0 0 1 0 50 ns -a10b/-a10bl 3ch 0 0 1 1 1 1 0 0 60 ns 31 module bank density 08h 0 0 0 0 1 0 0 0 32m bytes
12 mc-458cd64s, 458cd64ls data sheet m13041ej6v0ds00 (2/2) byte no. function described hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 notes 32 command and add -a80 20h 0 0 1 0 0 0 0 0 2 ns setup time -a10 20h 0 0 1 0 0 0 0 0 2 ns -a10b/-a10bl 00h 0 0 0 0 0 0 0 0 33 command and add -a80 10h 0 0 0 1 0 0 0 0 1 ns hold time -a10 10h 0 0 0 1 0 0 0 0 1 ns -a10b/-a10bl 00h 0 0 0 0 0 0 0 0 34 data signal input setup -a80 20h 0 0 1 0 0 0 0 0 2 ns time -a10 20h 0 0 1 0 0 0 0 0 2 ns -a10b/-a10bl 00h 0 0 0 0 0 0 0 0 35 data signal input hold -a80 10h 0 0 0 1 0 0 0 0 1 ns time -a10 10h 0 0 0 1 0 0 0 0 1 ns -a10b/-a10bl 00h 0 0 0 0 0 0 0 0 36-61 00h 0 0 0 0 0 0 0 0 62 spd revision -a80 12h 0 0 0 1 0 0 1 0 1.2 -a10 12h000100101.2 -a10b/-a10bl 01h 0 0 0 0 0 0 0 1 1 63 checksum -a80 dfh 1 1 0 1 1 1 1 1 for bytes 0 - 62 -a10 45h 0 1 0 0 0 1 0 1 -a10b/-a10bl 32h 0 0 1 1 0 0 1 0 64-71 manufactures jedec id code 72 manufacturing location 73-90 manufactures p/n 91-92 revision code 93-94 manufacturing date 95-98 assembly serial number 99-125 mfg specific 126 intel specification -a80 64h 0 1 1 0 0 1 0 0 100 mhz frequency -a10 64h 0 1 1 0 0 1 0 0 100 mhz -a10b/-a10bl 66h 0 1 1 0 0 1 1 0 66 mhz 127 intel specification /cas -a80 c7h 1 1 0 0 0 1 1 1 latency support -a10 c5h 1 1 0 0 0 1 0 1 -a10b/-a10bl 06h 0 0 0 0 0 1 1 0 timing chart refer to the synchronous dram module timing chart information (m13348x) .
13 mc-458cd64, 458cd64ls data sheet m13041ej6v0ds00 package drawing h a a1 (area a) c b e n a (area b) detail of a part y r m1 (area b) l m2 (area a) i f q u2 t u1 m x d2 w d1 v d item millimeters a b c d e f h i 67.6 29.0 3.7 0.8(t.p) 23.2 l 20.0 3.3 3.8 max. 4.6 32.8 n d1 1.5 0.10 d2 4.0 q r2.0 r 4.0 0.10 s 1.8 t 1.0 0.1 u1 3.2 min. u2 4.0 min. v 0.25 max. w 0.6 0.05 y 2.0 min. m1 4.67 m2 22.0 f a1 67.6 0.15 x 2.55 min. 26.67 0.15 s (optional holes) m 144 pin dual in-line module (socket type)
14 mc-458cd64s, 458cd64ls data sheet m13041ej6v0ds00 [memo]
15 mc-458cd64, 458cd64ls data sheet m13041ej6v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
mc-458cd64s, 458cd64ls caution for handling memory modules when handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ic, chip capacitors and chip resistors. it is necessary to avoid undue mechanical stress on these components to prevent damaging them. when re-packing memory modules, be sure the modules are not touching each other. modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m7 98. 8

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