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oki semiconductor pedl7655/56-000 issue date: sep. 14, 2004 ml86v7655/56 preliminary ntsc/pal-compatible, 6ch dac-equipped digital vi deo encoder with format conversion function 1/22 general description the ml86v7655 is an ntsc/pal compatible digital video en code. it encodes digital image data such as itu-r bt.656 and itu-r bt.601 to analog video signals. as digital input, rgb (4:4:4), ycbcr (4:4:4), and progressive scan signals are supported besides generic itu-r bt.601 and itu-r bt.656. as anal og video output, rgb and component si gnals can be output in interlace or progressive format in addition to ntsc/pal s-video and composite outputs. dac simultaneous 6-channel output or independent output for each ch annel can be selected. with the i/p and p/i conversion function, interlaced digital signals can be output as progressive signals or progressive digital signals can be output as interlaced signals. the ml86v7656 suppo rts macrovision copy protection (compliant with version 7.1. l1 for interlace and version 1.2 for progressive). features ? supported video type: ntsc/pal ? scanning method: interlace/pr ogressive/single-field signals ? input data format itu-r bt.656-4 type (y/cbcr 4:2:2 10-bit multiple xing, synchronization signal information added) itu-r bt.601 (y/cbcr 4:2:2 20-bit non-multiple xing (y/cbcr 4:1:1 20-bit non-multiplexing) y/cbcr 4:2:2 10-bit multiplexing, without synchronization signal ycbcr 4:2:2 20-bit non-multiplexing (progressive) ycbcr 4:4:4 30-bit/24-bit non-mu ltiplexing (interlaced/progressive) rgb 4:4:4 30-bit/24-bit non-mul tiplexing (interlaced/progressive) ? input pixel frequency (input double-speed clock frequency) 12.272727 mhz (24.545454 mhz): ntsc square pixel 13.5 mhz (27 mhz): ntsc/pal itu-r bt.601 14.318182 mhz (28.636364 mhz): ntsc 4fsc 14.75 mhz (29.5 mhz): pal square pixel 18 mhz (36 mhz): ntsc/pal itu-r bt.601 wide ? output format composite (cvbs) s-video (y/c separate signals) rgb (interlace/progressive) ycbcr component (int erlace/progressive) ? scan type conversion function / color space conv ersion function interlace to progressive / progressive to interlace ycbcr to rgb / rgb to ycbcr ? built-in 6ch 11-bit dac: capable of simultaneous output of composite, s-video, ycbcr or rgb ? output load resistance: 300 ? (a video amp is required when a tv monitor is connected.) ? master/slave operation (slave only for itu-r bt.656 mode) ? color bar output ? 3-bit title graphic input interface ? luminance adjustment ? rgb gain adjustment ? expanded luminance range mode ? synchronization signal level adjustment ? cgms/wss information adding function ? closed caption information adding function
pedl7655/56-000 oki semiconductor ml86v7655/56 2/22 ? supports macrovision copyguard function (only available in the ml86v7656) conforms to version 7.1.l1 for interlace conforms to version 1.2 for progressive ? i2c-bus type serial interface ? supply voltage: 3.3 v (i/o supply)/2.5 v (core supply) (scl and sda pins only, 5 v tolerant) ? package: 100-pin plastic tqfp (tqfp100-p-1414-0.5-k) (ml86v7655tb/ML86V7656TB)
pedl7655/56-000 oki semiconductor ml86v7655/56 3/22 block diagram yd 9:0 cd 9:0 11bit dac 11bit dac 11bit dac ys cvbs cs lpf lpf subcarrier generator color burst generator bd 9:0 sync generator timing controller clkx2 imod 2:0 irgb ipal iprg i444 ycbcr to yuv y u v rgb to ycbcr ycbcr to rgb progressive to interlace interlace to progressive y c ycbcr interlace ycbcr/rgb progressive ycbcr/rgb sync controller cb / b y / g cr / r selector 11bit dac 11bit dac 11bit dac interlace ycbcr/rgb progressive ycbcr/rgb oclkx1 ovsync ocsync/ohsync fout test 5:0 i2c interface sda scl sla input data decoder overlay & color bar controller olc olr olg olb reset_l orgb oprg vsync_l hsync_l csync_l blank_l cgms/wss/cc contoller y / rgb level adjustment
pedl7655/56-000 oki semiconductor ml86v7655/56 4/22 pin configuration (top view) standby 46 47 48 49 45 80 79 78 77 76 21 22 23 24 25 bd0 62 ovsync 63 64 ocsync / ohsync dgnd1 65 41 42 43 44 hsync_l bd1 61 bd2 60 bd3 59 bd4 58 bd5 57 bd6 56 bd7 55 bd8 54 bd9 53 52 cd0 51 dvdd1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 sda scl ipal imod0 imod1 i444 irgb iprg 98 27 blnak_l 28 ms 29 yd9 30 yd8 31 yd7 32 yd6 33 34 yd4 35 yd3 36 yd2 37 38 yd1 yd0 39 cd9 40 97 96 95 94 93 92 91 90 89 87 86 85 15 16 clkx2 vsync_l 26 dvdd2 100 99 dvdd2 88 17 18 19 20 cd8 cd7 cd6 84 83 82 81 olc olr olg olb ys avdd cs agnd cvbs avdd y/g cb/b avdd cr/r agnd comp fs xvref dgnd1 agnd agnd dvdd1 orgb oprg test0 test1 test2 imod2 dgnd2 oclkx1 cd5 cd4 test3 cd1 66 67 68 69 70 71 72 73 74 75 agnd avdd 50 sla dvdd2 dvdd2 dgnd1 cd2 dgnd2 dgnd2 yd5 dvdd1 dgnd2 cd3 reset_l test5 nc nc nc nc nc fout test4 100-pin plastic tqfp
pedl7655/56-000 oki semiconductor ml86v7655/56 5/22 pin function pin symbol type description 1 nc no connection 2 dvdd1 i/o power supply (3.3 v) 3 sda i/o data pin for i 2 c bus (5 v tolerant pin) 4 scl i data pin for i 2 c bus (5 v tolerant pin) 5 sla i i 2 c bus slave address least significant bit specification pin 6 ms i master/slave select pin ?1?: master mode ?0?: slave mode 7 dgnd2 core digital power supply (2.5 v) 8 dvdd2 core digital power supply (2.5 v) 9 imod0 i input mode-0 control pin 10 imod1 i input mode-1 control pin 11 imod2 i input mode-2 control pin 12 ipal i pal/ntsc mode select pin ?1?: pal, ?0?: ntsc 13 irgb i rgb/ycbcr input select pin ?1?: rgb input, ?0?: ycbcr input 14 iprg i progressive/interlaced input select pin ?1?: progressive inpu t, ?0?: interlaced input 15 i444 i 4:2:2/4:4:4 select pin ?1?: 4:4:4 input, ?0?: 4:2:2 input 16 orgb i rgb/ycbcr output select pin ?1?: rgb output, ?0?: ycbcr output 17 oprg i progressive output/inter laced output select pin ?1?: progressive outpu t, ?0?: /interlaced output 18 reset_l i system reset pin. reset at a ?l? level. 19 test0 i test mode control 0. tie this pin to gnd. 20 test1 i test mode control 1. tie this pin to gnd. 21 test2 i test mode control 2. tie this pin to gnd. 22 test3 i test mode control 3. tie this pin to gnd. 23 test4 i test mode control 4. tie this pin to gnd. 24 clkx2 i system clock input pin 25 dgnd2 core digital gnd 26 dvdd2 core digital power supply (2.5 v) 27 oclkx1 o clkx1 output pin outputs 1/2-divided frequency of clkx2 28 vsync_l i/o vertical sync signal input-output pin when in master mode: output; when in slave mode: input 29 hsync_l i/o horizontal sync signal input-output pin when in master mode: output; when in slave mode: input 30 blank_l i/o blank signal input-output pin when in master mode: output; when in slave mode: input 31 yd9 i video signal input pin; brightness y, g signal, bit[9] 32 yd8 i video signal input pin; brightness y, g signal, bit[8] 33 yd7 i video signal input pin; brightness y, g signal, bit[7]
pedl7655/56-000 oki semiconductor ml86v7655/56 6/22 pin function (continued) pin symbol type description 34 dvdd1 i/o power supply (3.3 v) 35 yd6 i video signal input pin; brightness y, g signal, bit[6] 36 yd5 i video signal input pin; brightness y, g signal, bit[5] 37 yd4 i video signal input pin; brightness y, g signal, bit[4] 38 yd3 i video signal input pin; brightness y, g signal, bit[3] 39 yd2 i video signal input pin; brightness y, g signal, bit[2] 40 yd1 i video signal input pin; brightness y, g signal, bit[1] 41 yd0 i video signal input pin; brightness y, g signal, bit[0] 42 dgnd1 i/o gnd 43 cd9 i video signal input pin; color difference c/cr, r signal, bit[9] 44 cd8 i video signal input pin; color difference c/cr, r signal, bit[8] 45 cd7 i video signal input pin; color difference c/cr, r signal, bit[7] 46 cd6 i video signal input pin; color difference c/cr, r signal, bit[6] 47 cd5 i video signal input pin; color difference c/cr, r signal, bit[5] 48 cd4 i video signal input pin; color difference c/cr, r signal, bit[4] 49 cd3 i video signal input pin; color difference c/cr, r signal, bit[3] 50 dgnd2 core digital gnd 51 dvdd2 core digital power supply (2.5 v) 52 cd2 i video signal input pin; color difference c/cr, r signal, bit[2] 53 cd1 i video signal input pin; color difference c/cr, r signal, bit[1] 54 cd0 i video signal input pin; color difference c/cr, r signal, bit[0] 55 test5 i/o test pin. tie this pin to gnd. 56 bd9 i/o video signal input pin; color difference cb, b signal, bit[9] 57 bd8 i/o video signal input pin; color difference cb, b signal, bit[8] 58 bd7 i/o video signal input pin; color difference cb, b signal, bit[7] 59 bd6 i/o video signal input pin; color difference cb, b signal, bit[6] 60 bd5 i/o video signal input pin; color difference cb, b signal, bit[5] 61 bd4 i/o video signal input pin; color difference cb, b signal, bit[4] 62 bd3 i/o video signal input pin; color difference cb, b signal, bit[3] 63 bd2 i/o video signal input pin; color difference cb, b signal, bit[2] 64 bd1 i/o video signal input pin; color difference cb, b signal, bit[1] 65 bd0 i/o video signal input pin; color difference cb, b signal, bit[0] 66 dvdd2 core digital power supply (2.5 v) 67 dgnd2 core digital gnd 68 ovsync o component vertical sync signal output 69 ocsync/ ohsync o composite synchronization signal output/component horizontal synchronization signal output select either output with t he internal register ochsel. 70 olb i overlay text color (blue) input pin 71 olg i overlay text color (green) input pin 72 olr i overlay text color (red) input pin 73 olc i transparency control. when set to ?1?, an overlay signal is displayed. connect this pin to gnd if it is not used. 74 standby i standby enable input pin ?1?: standby, ?0?: normal operation
pedl7655/56-000 oki semiconductor ml86v7655/56 7/22 pin function (continued) pin symbol type description 75 dgnd1 i/o gnd 76 dvdd1 i/o power supply (3.3 v) 77 fout o field information signal output pin 78 nc no connection 79 agnd analog gnd 80 y/g o y/g output pin 81 avdd analog power supply 82 cb/b o cb/b output pin 83 agnd analog gnd 84 cr/r o cr/b output pin 85 avdd analog power supply 86 agnd analog gnd 87 xvref i/o reference voltage input pin 88 fs i video output full-scale adjustment pin 89 comp o internal reference voltage output pin 90 avdd analog power supply 91 cvbs o composite signal output pin 92 agnd analog gnd 93 cs o separate c signal output pin 94 avdd analog power supply 95 nc no connection 96 ys o separate y signal output pin 97 agnd analog gnd 98 nc no connection 99 nc no connection 100 dgnd1 i/o gnd
pedl7655/56-000 oki semiconductor ml86v7655/56 8/22 absolute maximum ratings parameter symbol condition rating unit power supply voltage (i/o) vdd1 ta = 25 c ?0.3 v to +4.6 v v power supply voltage (core) vdd2 ta = 25 c ?0.3 v to +3.6 v v power supply voltage (analog) avdd ta = 25 c ?0.3 v to +4.6 v v input voltage v i ta = 25 c ?0.3 v to +6.0 v v output short-circuit current i os ? 50 ma power dissipation p d ta = 25 c 1 w storage temperature t stg ? ?55 to +150 c caution: product quality may suffer if any of the abso lute maximum ratings above is exceeded, even for an instant. that is, the absolute maximum ratings are ra ted values at which the product is on the verge of suffering physical damage. therefore the product must be used under conditions that ensure that no absolute maximum rating will ever be exceeded. recommended operating conditions parameter symbol min. typ. max. unit power supply voltage (i/o) vdd1 3.0 3.3 3.6 v power supply voltage (core) vdd2 2.25 2.5 2.75 v power supply voltage (analog) avdd 3.0 3.3 3.6 v operating temperature t a ?40 ? +85 c external reference voltage v refex ? 1.23 ? v d/a output setting resistance r iadj 500 1000 1330 ? d/a output load resistance r l ? 300 ? ?
pedl7655/56-000 oki semiconductor ml86v7655/56 9/22 electrical characteristics dc characteristics 1 ta = ?40 to +85 c, dvdd1 = 3.3 v 0.3 v, vdd2 = 2.5 0.25 v, avdd = 3.3 v 0.3 v, dgnd1, dgnd2, agnd = 0 v parameter symbol conditio n min. typ. max. unit ?h? level input voltage 1 v ih1 ? 2.2 ? vdd1 +0.3v v ?h? level input voltage 2 v ih2 *1 ? 2.2 ? 5.5 v ?l? level input voltage v il ?0.3 ? +0.8 v voltage at schmitt trigger threshold value v t+ ? ? ? 2.1 v voltage at schmitt trigger threshold value v t- ? 0.7 ? ? v voltage at schmitt trigger hysteresis value v h ? ? 0.4 ? v ?h? level output voltage v oh i oh = ?4 ma 2.4 ? ? v ?l? level output voltage v ol i ol = 4 ma ? ? 0.4 v input leakage current i li v in = vdd1 or gnd1 ?10 ? +10 a ?h? level input current (pull-down resistance) i ih v in = vdd1 20 ? 250 a output leakage current i lo v out = vdd1 or gnd1 ?10 ? +10 a power supply current (during operation) i dd1 clkx2 = 36 mhz, r l = 300 ? ? ? 160 ma power supply current (when stopped 1) i dds1 clkx2 = 0 mhz, v in = v il ? ? 45 ma power supply current (when stopped 2) i dds2 clkx2 = 0 mhz, v in = v il standby = v ih ? ? 5 ma *1: vih2 is applied to the sda and scl pins only. note: the power supply current does not include the current consumption of the output buffer (no load). dc characteristics 2 ta = ?40 to +85 c, dvdd1 = 3.3 v 0.3 v, vdd2 = 2.5 0.25 v, avdd = 3.3 v 0.3 v, dgnd1, dgnd2, agnd = 0 v parameter symbol conditio n min. typ. max. unit dac internal reference voltage v refin ? 1.187 1.23 1.313 v dac integral linearity sinl ? ? 4 ? lsb dac differential linearity sdnl ? ? 2 ? lsb
pedl7655/56-000 oki semiconductor ml86v7655/56 10/22 ac characteristics ta = ?40 to +85 c, dvdd1 = 3.3 v 0.3 v, vdd2 = 2.5 0.25 v, avdd = 3.3 v 0.3 v, dgnd1, dgnd2, agnd = 0 v parameter symbol conditio n min. typ. max. unit ntsc square pixel ? 24.545454 ? mhz pal square pixel ? 29.5 ? mhz ntsc 4fsc ? 28.636364 ? mhz ntsc/pal itu-r bt601 ? 27 ? mhz clock frequency (clkx2 frequency) f clk ntsc/pal itu-r bt601 wide ? 36 ? mhz clock duty ratio dt clk ? 45 ? 55 % input data setup time t si ? 6 ? ? ns input data hold time t hi ? 5 ? ? ns output delay time t od c l = 20 pf ? ? 18 ns reset pulse time t rstp ? 100 ? ? ns i 2 c clock cycle time t cci2c rpull_up = 4.7 k ? 10 ? ? s i 2 c clock ?h? level time t hi2c rpull_up = 4.7 k ? 4 ? ? s i 2 c clock ?l? level time t li2c rpull_up = 4.7 k ? 4.7 ? ? s i 2 c data setup time t dsi2c rpull_up = 4.7 k ? 250 ? ? ns i 2 c data hold time t dhi2c rpull_up = 4.7 k ? 0 ? 3.45 s
pedl7655/56-000 oki semiconductor ml86v7655/56 11/22 power-on sequence turn on the power supplies in the following order: dvdd1 avdd dvdd2. turn them off in the reverse order. after every power supply reach es its specified voltage and the cloc k clkx2 is stabilized, input the reset signal. reset input timing input the reset signal for the reset pulse time t rstp . reset_l trstp figure 1 reset signal input timing
pedl7655/56-000 oki semiconductor ml86v7655/56 12/22 i 2 c interface timing use the i 2 c interface to set the internal register values. the i 2 c interface is compliant with the 100 khz (scl frequency) standard mode. figure 2 shows the basic timing. make sure that the sda value does not change while scl is at a ?h? level. for information on timing parameter values refer to the ac characteristics. s tdsi2c tdhi2c msb 1789129 p tcci2c thi2c tli2c start condition stop condition sda scl ack 2 figure 2 i 2 c interface basic timing figures 3 and 4 show the i 2 c interface input format. write format s slave address w a subaddress a data 0 a ???.. data n a p figure 3 write format write data to the specified subaddress register. if multiple data items are written in succession, the subaddress is incremented automatically for each data item. read format s slave address w a subaddress a sr slave address ra data 0 am ???.. data n am p figure 4 read format read data of the register at the specified subaddre ss. if multiple data items are written in succession, the subaddress is incremented automatically for each data item. table 1 symbols used in the input formats symbol meaning s start condition sr restart condition slave address slave address ?100_010x? specify x from the sla pin (?1? or ?0?) w write r read a acknowledge (slave) am acknowledge (master) sub address subaddress data n write and read data at subaddress p stop condition
pedl7655/56-000 oki semiconductor ml86v7655/56 13/22 input-output timing (1) input timing input signal: vsync_l, hsync_l, blank_l, imod0 to 3, ipal, irgb, iprg, i444, orgb, oprg, ms, yd, cd, bd olc, olr, olg, olb (2) output timing output signal: vsync_l, hsync_l, blank_l, ovsync, ocsync/ohsync, fout, oclkx1 (vsync_l, hsync_l, and blank_l are configured as output pins in master mode.) vih vil clkx2 vih vil input signal t si t hi t od vih vil clkx2 vih vil output signal
pedl7655/56-000 oki semiconductor ml86v7655/56 14/22 description of functional blocks this section describes the functions of the blocks shown in the block diagram. for a detailed explanation of all the functions, refer to the user?s manual. (1) input data decoder converts the video data format based on the format of the digitally input video data. itu bt.656, 20-bit 4:2:2 ycbcr, and 10-bit 4:2:2 ycbcr input data are converted to 4:4:4 ycbcr data. when itu bt.656 is input, the synchronization information is separate d from the sav and eav information to generate a synchronization signal. rgb input data is output to the next block. the input video signal limiter function clips the input video signal at the quantization level (64?940) specified by itu-r bt601. in the extended luminance range mode, the limiter function clips the input video signal at the quantization level (4?1016). (2) overlay & color bar controller a 3-bit title graphic and color bar are generated. the 3-bit title graphic becomes effective when the olc pin is set to ?h?. the rgb graphic data input from th e olr, olg and olb pins can be replaced with input video data in pixel units. the input video data s upports ycbcr input, rgb input, interlaced input and progressive input. with this function, letters can be displayed on the screen, as with the osd function. the built-in color bar becomes effective by setting the internal register value. the color bar is a color bar with a luminance order (25%, 50%, 75% and 100%). it supports ntsc, pal and ycbcr, rgb, cvbs, s-video, interlaced and progressive. (3) progressive to interlace converts progressive video data (ycb cr, rgb) to interlaced video data. progressive video data to be input supports ycbcr (4:2:2 and 4:4:4) and rgb. (4) interlace to progressive converts interlaced video data (ycbcr , rgb) to progressive video data. (5) rgb to ycbcr/ycbcr to rgb converts rgb/ycbcr data to ycbcr/rgb data. (6) y/rgb level adjustment this block adjusts the levels of the luminance signal y, rgb data. the luminance signal level can be adjusted in 16 steps (78.125% to 125%, in increments of 3.125%) by setting the internal register value. rgb data gain can be set from 0.0 to 2.0 times by setting the internal register value. a different setting can be made for each channel of r, g, and b. (7) ycbcr to yuv converts ycbcr data to yuv data. (8) sync controller this block adds a synchronization signal to the video signal, adds vbi data, and adjusts the synchronization signal level and offset of the signal. (9) cgms/wss/cc controller this block generates data of cgms-a(copy generation management system - analog), wss (wide screen signaling), and cc (closed caption). (10) lpf removes high frequency components from video data.
pedl7655/56-000 oki semiconductor ml86v7655/56 15/22 (11) color burst & subcarrier generator these blocks generate the amplitude of the u and v components of a burst signal, and generate an color subcarrier. (12) 11-bit dac converts digital video signals, with 11-bit resolution, to analog video signals and outputs them. the dac output is of the current drive type. connect an external load resistor (300 ? ) to the analog output pin. connect a video amplifier to the output stage of the encoder to drive a 75 ? load. (13) sync generator & timing controller this block generates video synchronization signals and controls the timing of internal operations. a slave mode and a master mode are available. in the slave mode, operation is based on synchronization signals input from outside. in the master mode, operation is based on synchronization signals generated within the lsi. (14) i2c interface i 2 c-bus serial interface. used to set oper ation modes and internal register values.
pedl7655/56-000 oki semiconductor ml86v7655/56 16/22 video data input control (1) types of input video pixel frequencies the ml86v7655/56 support the pixel frequencies for input video shown in table 2. every pixel frequency can be selected. (note) the input clock frequency should be double the pixel frequency. table 2 types of input pixel frequencies pixel frequency (mhz) input clkx2 frequency (mhz) ntsc itu-r bt601 13.5 27 pal itu-r bt601 13.5 27 ntsc square pixel 12.272727 24.545454 ntsc 4fsc 14.318182 28.63634 pal square pixel 14.75 29.5 ntsc itu-r bt601 wide 18.0 36 pal itu-r bt601 wide 18.0 36 (2) input data formats for interlaced and progressive scanning table 3 shows the scanning method (interlaced/progressive) and data type. table 3 types of input data formats input data format scanning method data type sampling rate for color difference data input pin interlaced ycbcr 4:2:2 or 4:1:1 *1 yd/cd or yd *2 interlaced ycbcr 4:4:4 yd/cd/bd interlaced rgb 4:4:4 yd/cd/bd progressive ycbcr 4:2:2 yd/cd progressive ycbcr 4:4:4 yd/cd/bd progressive rgb 4:4:4 yd/cd/bd *1 : change internal register value to select 4:2:2 or 4:1:1. *2 : use only the yd pin for video data/synchronized information multiplexing input (e.g., itu-r bt-656). table 4 shows the available scanning methods for ntsc and pal. table 4 scanning methods scanning method no. of lines frequency ntsc interlaced 262.5 60 hz ntsc progressive 525 60 hz pal interlaced 312.5 50 hz pal progressive 625 50 hz
pedl7655/56-000 oki semiconductor ml86v7655/56 17/22 (3) video data/synchronization information multiplexing input format types the ml86v7655/56 support the video data/synchroniza tion information multiple xing input interfaces and data multiplexing (no multiplexing for sync si gnals) input interfaces shown in table 5. table 5 types of multiplexed input interfaces input interface input clkx2 frequency (mhz) data input pin ntsc itu-r bt656 style(*1) 27 yd pal itu-r bt656 style(*1) 27 yd ntsc 4:2:2 10-bit multiplexing (no multiplexing for sync signals)(*2) 27 yd ntsc square pixel 4:2:2 10-bit multiplexing (no multiplexing for sync signals)(*2) 24.545454 yd ntsc 4fsc 4:2:2 10-bit multiplexing (no multiplexing for sync signals)(*2) 28.63634 yd pal 4:2:2 10-bit multiplexing (no multiplexing for sync signals)(*2) 27 yd pal square pixel 4:2:2 10-bit mu ltiplexing (no multiplexing for sync signals)(*2) 29.5 yd ntsc square pixel itu-r bt656 style(*3) 24.545454 yd pal square pixel itu-r bt656 style(*3) 28.63634 yd ntsc 4fsc itu-r bt656 style(*3) 29.5 yd *1: itu-r bt656 style input interface. for details, refe r to ?video interface timing? in the user?s manual. *2: 4:2:2 10-bit multiplexing (no multiplexing for sync signals) in terface. this interface multiplexes ycbcr and inputs the data from the yd pin. input the synchronization signal from the vsync_l, hsync_l and blank_l pins. for details, refer to the ?input data format ? and ?video interface timing? sections in the user?s manual. *3: itu-r bt656 style input interface for squarepixe l and 4fsc. this interface multiplexes video data and synchronization information and inputs the data from the yd pin. synchronization information is multiplexed as sav and eav. for details, refer to the ?video interface timing? section in the user?s manual.
pedl7655/56-000 oki semiconductor ml86v7655/56 18/22 video data output control video signals (composite signals, separate video signals and component ycbcr/rgb signals) can be simultaneously output from the 6-channel d/a converter. composite signals are output from the cvbs pin, and separate video signals are output from the ya and cs pins. ycbcr or rgb signals are exclusively output from the y/g, cb/b and cr/r pins. for each input data scanning method, conversion from interl aced to progressive and from progressive to interlaced is possible. color space conversion, such as ycbcr rgb and rgb ycbcr, is also possible. table 6 shows the available output formats for each input format. for example, 4:2:2 ycbcr progressive video data can be simultaneously output in three different video formats, composite, s-video and ycbcr interlaced. table 6 correspondence of input formats and output formats output format input format composite s-video ycbcr interlaced ycbcr progressive rgb interlaced rgb progressive 4:2:2/4:1:1 ycbcr { { { { { { 4:4:4 ycbcr interlaced { { { { { { 4:2:2 ycbcr progressive { { { { { { 4:4:4 ycbcr progressive { { { { { { rgb interlaced { { { { { { rgb progressive { { { { { { { : output enabled table 7 shows the output pins from which video data is output. change the internal register values to enable/disable d/a converter output for each channel. table 7 vidieo output pins output format pin name composite cvbs s-video ys, cs ycbcr/rgb interlaced/progressive y/g, cb/b, cr/r
pedl7655/56-000 oki semiconductor ml86v7655/56 19/22 internal registers use the i2c interface to change the internal register values . for details on register functions, refer to the user?s manual. table 8 register map sub address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 extsel mssel reserved mltdat imodsel[2:0] 01 reserved in2s i411 spl411 npsel i444sel irgbsel iprgsel 02 sonsel ldsel pisel ofinv ohcsel cssel orgbsel oprgsel 03 cbon bbon mcon sbon rgblev setup outlev[1:0] 04 reserved dmask1 reserved dmask2 05 reserved 06 cntctl tfon reserved frun blkadj[3:0] 07 reserved synclev1(cvbs)[2:0 ] reserved synclev2(comp)[2:0] 08 nosig reserved lumlev[3:0] 09 ggain[7:0] 0a bgain[7:0] 0b rgain[7:0] 0c dacoffset[1:0] dacoff[5:0] 0d reserved ffm reserved 0e reserved 0f reserved - - - - - - - 10 ccen [1:0] reserved ccln [4:0] 11 ccod0 [7:0] 12 ccod1 [7:0] 13 cced0 [7:0] 14 cced1 [7:0] 15 reserved ccstat [1:0] 16 cgmsen reserved wd01 [5:0] 17 wd02 [7:0] 18 crcon reserved crcdata[5:0] 19 gp12 [7:0] 1a wssen reserved gp34 [5:0] 1b to 3f reserved reserved: reserved for the system. do not use these registers.
pedl7655/56-000 oki semiconductor ml86v7655/56 20/22 package dimensions tqfp100-p-1414-0.50-k mirror finish package material epoxy resin lead frame material 42 alloy pin treatment solder plating ( 5m) package weight (g) 0.55 typ. 5 rev. no./last revised 4/oct. 28, 1996 notes for mounting the su rface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humi dity absorbed in storage. therefore, before you perform reflow mounting, contact oki?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ( unit: mm )
pedl7655/56-000 oki semiconductor ml86v7655/56 21/22 revision history page document no. date previous edition current edition description pedl7655-000 sep. 14, 2004 ? ? preliminary edition 1
pedl7655/56-000 oki semiconductor ml86v7655/56 22/22 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. wh en planning to use the product, please ensure that the external conditions are reflected in the act ual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accide nt, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s industrial and intellectual prop erty right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this docu ment are intended for use in genera l electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifi cally authorized by oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traf fic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of de termining the legality of export of these products and will take appropriate and necessary st eps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2004 oki electric industry co., ltd.

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