rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a programmable oscillator functional block diagram frequency select sine wave generator phase detect logic sin cos from transducer fbias sel1 sel2 ad2s99 exc synref synchronous reference los to transducer push/ pull o/p stage exc product highlights dynamic phase compensation the ad2s99 dynamically compensates for any phase variation in a transducer by phase locking its synchronous reference out- put to the transducers secondary windings. programmable excitation frequency the excitation frequency is easily programmed to 2 khz, 5 khz, 10 khz, or 20 khz by using the frequency select pins. interme- diate frequencies are available by adding an external resistor. signal loss detection the ad2s99 has the ability to detect if both the transducer sec- ondary winding connections become disconnected from its sin and cos inputs. the los output pin pulls high when a sig- nal loss is detected. integration the ad2s99 integrates the transducer excitation, synchronous reference, and loss of signal detection functions into a small, cost effective package. general description the ad2s99 programmable sinusoidal oscillator provides sine wave excitation for resolvers and a wide variety of ac transduc- ers. the ad2s99 also provides a synchronous reference output signal (3 v p-p square wave) that is phase locked to its sin and cos inputs. in an application, the sin and cos inputs are connected to the transducers secondary windings. the synchronous reference output compensates for temperature and cabling dependent phase shifts and eliminates the need for external preset phase compensation circuits. the synchronous reference output can be used as a zero crossing reference for resolver-to- digital converters such as analog devices ad2s80a, ad2s82a, ad2s83 and ad2s90. the ad2s99 is packaged in a 20-pin plcc and operates over C40 c to +85 c. features programmable sinusoidal oscillator synthesized synchronous reference output programmable output frequency range: 2 khzC20 khz loss-of-signal indicator 20-pin plcc package low cost applications excitation source for: resolvers synchros lvdts rvdts pressure transducers load cells ac bridges ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 ad2s99
ad2s99Cspecifications parameter min typ max units test conditions frequency output range sel1 sel2 2 khz 2000 hz v ss v ss 5 khz 5000 hz v ss gnd 10 khz 10000 hz gnd v ss 20 khz 20000 hz gnd gnd accuracy frequency 10 % ap grade @ +25 c 20 % ap grade C40 c to +85 c 5 % bp grade @ +25 c 10 % bp grade C40 c to +85 c amplitude 3 10 % ap grade @ +25 c 20 % ap grade C40 c to +85 c 3 5 % bp grade @ +25 c 10 % bp grade C40 c to +85 c power supply rejection ratio 0.002 v p-p/v output variation as function of change in power supply voltage analog outputs amplitude exc, exc 2 v rms exc to gnd, exc to gnd synref 3 v p-p square wave synref offset 200 mv current drive capability exc, exc v s = 5 v 8 ma rms r load = 500 w exc to exc c load = 1000 pf capacitive drive 1000 pf total harmonic distortion exc, exc C25 db analog inputs sin, cos amplitude 1.8 2.0 2.2 v rms phase lock range C45 +45 degrees additional phase delay 10 degrees ap grade 10 degrees bp grade frequency select inputs sel1, sel2 1 v ss agnd v dc los output output low voltage 0.7 v dc i ol = 400 m a output high voltage v dd v dc 50 k w pull up to v dd (open drain output) sin, cos los threshold 0.5 0.6 0.8 v rms power supplies v dd +4.75 +5.25 v dc v ss C4.75 C5.25 v dc quiescent current i dd , i ss 8 15 ma no load temperature range operating C40 +85 c storage C65 +150 c notes 1 frequency select pins sel1 and sel2 must be connected to appropriate voltage levels before power is applied. specifications subject to change without notice. rev. b C2C (v s = 6 4.75 v to 6 5.25 v @ C40 8 c to +85 8 c unless otherwise noted)
rev. b C3C ad2s99 absolute maximum ratings* v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 v v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C7 v operating temperature . . . . . . . . . . . . . . . . . . C40 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . . C65 c to +150 c analog input voltages (sin and cos) . . . . . . . . . v ss C 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to v dd + 0.3 v frequency select (sel1, sel2) . . . . . . . . . . . . . . v ss C 0.4 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to agnd + 0.4 v *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions power supply voltage (v dd to v ss ) . . . . . . 4.75 v to 5.25 v analog input voltage (sin and cos) . . . . . . . . 2 v rms 10% frequency select (sel1 and sel2) . . . . . . . . . v ss to agnd operating temperature range . . . . . . . . . . . . . C40 c to +85 c pin designations pin no. mnemonic description 1 sel2 frequency select 2 2 sel1 frequency select 1 3 fbias external frequency adjust pin 5 sin resolver output sin 6 1 dgnd digital ground 7 cos resolver output cos 10 synref synthesized reference output 11 los indicates when both the sin and cos are below the threshold. 12 v dd positive power supply 16 1 agnd analog ground 17 exc resolver reference one 18 exc resolver reference two 3 19 2 v ss negative power supply 20 2 v ss negative power supply notes 1 pins 6 and 16 must be connected together. 2 pins 19 and 20 must be connected together. 3 resolver reference two ( exc ) is 180 phase advanced with respect to resolver reference one (exc). pin configuration nc = no connect nc sin nc dgnd cos fbias sel1 v ss sel2 v ss nc synref nc los v dd exc nc agnd nc 19 3 1 2 20 4 5 8 6 7 12 13 911 10 18 17 14 16 15 top view (not to scale) ad2s99 exc ordering guide model temperature range package option* ad2s99ap C40 c to +85 c p-20a ad2s99bp C40 c to +85 c p-20a *p = plcc. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad2s99 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad2s99 rev. b C4C 20 0 6 2 4 4 0 12 8 10 14 16 18 28 24 20 16 12 8 additional resistance ?k w resistor pullup to v dd from fbias frequency ?khz figure 2. typical added resistance value ad2s99 oscillator output stage the output of the ad2s99 oscillator consists of two sinusoidal signals, exc, and exc . exc is 180 phase advanced with re- spect to exc. the excitation winding of a transducer should be connected across exc (pin 17) and exc (pin 18). with low impedance transducers, it may be necessary to in- crease the output current drive of the ad2s99. in such an in- stance, an external buffer amplifier can be used to provide gain (as needed), and additional current drive for the excitation out- put (either exc or exc ) of the ad2s99, providing a single ended drive to the transducer. refer to figures 6, 7 and 8 for sample buffer configurations. the amplitude modulated sin and cos output signals from a re- solver should be connected as feedback signals to the ad2s99. the synref output compensates for any primary to secondary phase errors in the resolver. these errors can degrade the accuracy of a resolver-to-digital converter (r/d converter). sin, from the resolver, should be connected to the ad2s99 sin input and cos should be connected to the ad2s99 cos input. the sin lo, cos lo (resolver signal returns) should be con- nected to agnd and the r/d converter as applicable. the synthesized reference (synref) from the ad2s99 should be connected to the reference input pin of the r/d converter. the synref signal is a square wave at the oscillator frequency of amplitude 3 v p-p and is phase coherent with the sin and cos inputs. if this signal is used to drive the reference input of the ad2s90 r/d converter, a coupling capacitor and resistor to gnd must be connected between the synref output of the ad2s99 and the ref input of the r/d converter (see figure 3). please read the appropriate r/d converter data sheets for further clarification. loss of signal during normal operation when both the sin and cos signals on the resolver secondary windings are connected to the ad2s99, the los output pin of the ad2s99 (pin 11) is at a logic lo ( < 0.7 v). if both the sin and cos signals on the re- solver secondary windings fall below the los threshold level of the ad2s99, the los pin of the ad2s99 will pull up to a logic hi (v dd ) level. connecting the ad2s99 oscillator refer to figure 1. positive supply voltage v dd should be con- nected to pin 12 and negative supply voltage v ss should be con- nected to both pins 19 and 20. reversal of these power supplies will destroy the device. the appropriate voltage level for the power supplies is 5 v dc 5%. both v ss pins (19 and 20) must be connected together, and digital ground (pin 6) must be con- nected to analog ground (pin 16) locally at the ad2s99. v dd nc = no connect nc sin nc dgnd cos fbias sel1 v ss sel2 v ss nc synref nc los v dd exc nc agnd nc 19 3 1 2 20 4 5 8 6 7 12 13 911 10 18 17 14 16 15 ad2s99 exc 0.1 m f v ss 4.7 m f ref resolver sin 0.1 m f 4.7 m f r x * to ad2s80/ ad2s90 ref input 50k w * r x is only required for intermediate frequencies. fixed frequencies only require a link. sel2 = gnd ] sel1 = v ss ] ?khz mode increase r x to lower output frequency (see graph) cos . . . 100nf 100k w figure 1. typical configuration it is recommended that decoupling capacitors are connected in parallel between v dd and analog ground and v ss and analog ground in close proximity to the ad2s99. the recommended values for the decoupling capacitors are 100 nf (ceramic) and 4.7 m f (tantalum). when multiple ad2s99s are used, separate decoupling capacitors should be used for each ad2s99. frequency adjustment the output frequency of the ad2s99 is programmable to four standard frequencies (2, 5, 10, or 20 khz) using the sel1 and sel2 pins. the output can also be adjusted to provide interme- diate frequencies by connecting a resistor from the fbias pin to the positive supply v dd . the fbias pin is connected directly to v dd during normal operation. a graph showing the typical added resistance values for various intermediate frequencies is provided in figure 2. the procedure for obtaining an intermedi- ate frequency is: 1. set the output frequency via the sel1, sel2 pins to the fre- quency immediately above the required intermediate fr equency. 2. connect the frequency adjust pin fbias to v dd via an exter- nal resistor. for example: to obtain an output frequency of 8 khz, set the nominal output frequency to 10 khz by connecting sel1 to gnd and sel2 to v ss . connect fbias to v dd via a 6 k w resistor (refer to figure 2).
rev. b C5C ad2s99 ad2s99/ad2s90 typical configuration figure 3 shows a typical circuit configuration for the ad2s99 oscillator and the ad2s90 resolver-to-digital converter. the maximum level of the sin and cos input signals to the ad2s90 should be 2 v rms 10%. all the analog ground sig- nals should be star connected to the ad2s90 agnd pin. if shielded twisted pair cables are used for the resolver signals, the shields should also be terminated at the ad2s90 agnd pin. the synref output of the ad2s99 should be connected to the ref input pin of the ad2s90 via a 0.1 m f capacitor with a 100 k w resistor to gnd. this is to block out any dc offset in the synref signal. for more detailed information please refer to the ad2s90 data sheet. nc = no connect nc sin nc dgnd cos exc exc nc agnd nc 19 31 2 20 4 5 8 6 7 12 13 911 10 18 17 14 16 15 top view (not to scale) ad2s99 sel1 v ss sel2 v ss nc synref nc los v dd 19 3 1 2 20 4 5 8 6 7 12 13 9 11 10 18 17 14 16 15 4.7? 4.7? 0.1? 0.1? cos sin ref s2 s4 s3 s1 r4 r2 resolver ref cos agnd sin sin lo v dd v ss dgnd ad2s90 top view (not to scale) 0.1? 100k w v dd v ss v dd 0.1? 50k w 4.7? 0.1? 4.7? v ss sel2 = gnd sel1 = v ss f out = 5khz cos lo s4 s3 s1 s2 v dd power return fbias v dd figure 3. ad2s99 and ad2s90 example configuration
ad2s99 rev. b C6C ad2s99/ad2s82a typical configuration figure 4 shows a typical circuit configuration for the ad2s99 oscillator and the ad2s82a resolver-to-digital converter. the maximum level of the sin and cos input signals to the ad2s82a should be 2 v rms 10%. all the analog ground sig- nals should be star connected to the ad2s82a agnd pin. if shielded twisted pair cables are used for the resolver signals, the shields should also be terminated at the ad2s82a agnd pin. coupling capacitor c3, and resistor to gnd r3, between the synref output of the ad2s99 and the ref input pin of the ad2s82a are optional. for additional information on selecting component values for the ad2s82a, please refer to the ad2s82a data sheet or the application note passive compo- nent selection and dynamic modeling for the ad2s80 series resolver-to-digital converters (an-266). 44 1 2 64 5 21 24 23 22 18 20 19 39 38 35 34 33 37 36 3 7 8 11 12 13 9 10 40 41 42 25 28 27 26 43 31 30 29 32 15 16 17 14 top view (not to scale) ad2s82a db2 db6 sin i/p +v s msb db1 nc db3 db4 db5 db7 db8 ? s rc data load comp sc2 dir busy inhibit nc sc1 digital gnd sig gnd a gnd demod i/p integrator o/p demod o/p cos i/p ac error o/p reference i/p vco o/p vco i/p integrator i/p db9 db10 db13 db14 db15 db11 db12 enable byte select lsb db16 +v l cos sin ref resolver agnd 0v ?2v r6 r4 r1 c5 r5 c4 c2 c1 r2 c3 r3 r3, c3 optional velocity output +12v agnd +5v dgnd digital output data +5v 10? 0.1? 0.1? 10? 0.1? 10? nc = no connect nc sin nc dgnd cos exc exc nc agnd nc 19 3 1 2 20 4 5 8 6 7 12 13 911 10 18 fbias 17 14 16 15 top view (not to scale) ad2s99 nc synref nc v dd los sel1 v ss sel2 v ss ?v synref cos sin 50k los sel1 = gnd sel2 = v ss f out = 10khz 0.1? 4.7? 0.1? 4.7? fbias figure 4. ad2s99 and ad2s82a example configuration
rev. b C7C ad2s99 ad2s99/ad2s93 typical configuration figure 5 shows a typical circuit configuration for the ad2s99 oscillator and the ad2s93 lvdt-to-digital converter. the maximum level of the a and b transducer input signals to the ad2s93 should be 1 v rms 20%. all the analog ground sig- nals should be star connected to the ad2s93 agnd pin. if shielded twisted pair cables are used for the lvdt signals, the shields should also be terminated at the ad2s93 agnd pin. the synref output of the ad2s99 cannot be used as the ref input signal for the ad2s93. the zero crossing reference for the ad2s93 should be taken from the primary winding of the lvdt through a phase lead or lag network. the phase com- pensation network ensures that the ref input is phase coherent with the a and b input signals to the ad2s93. nc = no connect nc sin nc dgnd cos exc exc nc agnd nc 19 3 1 2 20 4 5 8 6 7 12 13 911 10 18 17 14 16 15 top view (not to scale) ad2s99 fbias sel1 v ss sel2 v ss nc synref nc los v dd 4.7? 4.7? 0.1? 0.1? sec pri lvdt v dd v ss v dd 0.1? 50k w 4.7? 0.1? 4.7? v ss sel2 = gnd sel1 = v ss f out = 5khz v dd nc = no connect data sclk unr clkout nc nc 26 27 28 4 2 3 15 18 17 16 12 14 13 25 24 21 20 19 23 22 1 56 91011 78 cs r2 c2 c1 c3 r5 r6 r7 c4 dmodout b a phase comp los top view (not to scale) ad2s93 b nc los gain diff agnd a v ss dgnd dir null ovr ref nc vel dmodin acerror vgain intin v dd figure 5. ad2s99 and ad2s93 example configuration
ad2s99 rev. b C8C +v s ssm2142 4 6 7 8 5 2 1 3 ? s nc = no connect nc sin nc dgnd cos exc exc nc agnd nc 19 31 2 20 4 5 8 6 7 12 13 911 10 18 17 14 16 15 top view (not to scale) ad2s99 fbias sel1 v ss sel2 v ss nc synref nc los v dd * * * optional; consult appropriate analog devices data sheet. resolver figure 8. the ssm2142 as a single ended to differential driver outline dimensions dimensions shown in inches and (mm). plcc (p-20a) 0.395 (10.02) 0.385 (9.78) sq 0.110 (2.79) 0.085 (2.16) 0.330 (8.38) 0.290 (7.37) 0.048 (1.21) 0.042 (1.07) 0.356 (9.04) 0.350 (8.89) sq 0.048 (1.21) 0.042 (1.07) 0.050 (1.27) bsc 0.020 (0.50) r 19 3 top view 18 14 9 8 pin 1 identifier 4 13 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.040 (1.01) 0.025 (0.64) 0.180 (4.57) 0.165 (4.19) cos sin ref v out v out = 2v rms nc = no connect nc sin nc dgnd cos exc exc nc agnd nc 19 3 1 2 20 4 5 8 6 7 12 13 9 11 10 18 17 14 16 15 top view (not to scale) ad2s99 fbias sel1 v ss sel2 v ss nc synref nc los v dd figure 6. sample buffer configuration v out v out = 2v rms x ( ) resolver v in exc pin 16 pin 17 agnd r1 r2 r1 r2 v out v out = 2v rms x 2 x ( ) resolver v in exc pin 16 pin 17 agnd r1 r2 r1 r2 r1 r2 exc pin 18 op279 op279 a suitable amplifier for above is the op279 figure 7. sample buffer configurations c1978bC10C6/95 printed in u.s.a.
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