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? make sure the next card you purchase has... data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7382 features ? accuracy up to 1.3 arc minutes internal synthesized reference +5 volt only option programmable: - resolution: 10-, 12-, 14-, or 16-bit - bandwidth - tracking rate differential resolver input mode velocity output eliminates tachometer built-in-test (bit ) output, no 180 hangup -55 to +125c operating temperature class k and mil-prf-38534 options description the rdc-19220/2s is a low-cost, versatile, state-of-the-art 16-bit monolithic resolver-to-digital (r/d) converter. this single chip con- verter offers programmable features such as resolution, bandwidth and velocity output scaling. resolution programming allows selection of 10, 12, 14, or 16 bits, with accuracies to 1.3 minutes. this feature combines the high track- ing rate of a 10-bit converter with the precision and low-speed veloc- ity resolution of a 16-bit converter in one package. the internal synthesized reference section eliminates errors due to quadrature voltage. previously, a 6 degree phase shift caused prob- lems for a 16-bit converter. the synthesized reference capability ensures operation with a phase shift up to 45 degrees. the velocity output (vel) from the rdc-19220/2s, which can be used to replace a tachometer, is a 4 v signal referenced to ground. the full-scale value of vel is set by the user with a single resistor. the rdc-19220/2s converter is available with operating temperature ranges of 0 to +70c, -40 to +85c, and -55 to +125c. applications the low cost, small size, high accuracy, and versatile performance of the rdc-19220/2s converter makes it ideal for use in modern high performance industrial control systems. typical applications include motor control, radar antenna positioning, machine tool control, robot- ics, and process control. class k and mil-prf-38534 processing is available for space and military applications. ? 1999, 2000 data device corporation rdc-19220/2s 16-bit monolithic tracking resolver-to-digital (r/d) converter
2 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 sin -s +s cos -c +c +5c +cap -cap -5c a gnd +5 v gnd -5 v control transformer -5 v inverter (rdc-19222 only) data latch gain demodulator 16-bit up/down counter hysteresis +ref -ref bit r 1 vco & timing - + - + ab inh em bit 1 thru bit 16 el ab cb e r s r c r v r b c bw c bw 10 vsum vel vco integrator synthesized reference (rdc1922xs only) rdc-19220 series signal inputs reference input external components (rc may be left unconnected) resolution control digital output power supply inputs/ground figure 1. rdc-19220/2s block diagram
3 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 these specifications apply over the rated power supply, temperature, and reference frequency ranges; 10% signal amplitude variation & 10% harmonic distortion. parameter value unit resolution 10, 12, 14, or 16 (notes 1 & 2) bits reference type voltage: differential single ended overload frequency input impedance sig/ref phase shift (+ref, -ref) differential 10 max (note 9) 5 max (note 9) 25 continuous 100 transient dc to 10,000 (note 8) 10m min //20 pf 45 max from 400 hz to 10 khz (note 5) v v v hz ohm deg signal input type voltage: operating overload input impedance (+s, -s, sin, +c, -c, cos) resolver, differential, groundbased 2 15% 25 continuous 10m min //10 pf. vrms v ohm digital input/output logic type inputs inhibit (inh ) enable bits 1 to 8 (em ) enable bits 9 to 16 (el ) resolution and mode control (a & b) (see notes 1 and 2) outputs parallel data (1-16) converter busy (cb) built-in-test (bit ) drive capability ttl/cmos compatible logic 0 = 0.8 v max. / logic 1 = 2.0 v min. loading=10 a max p.u. current source to +5 v //5 pf max., cmos transient protected logic 0 inhibits; data stable within 0.1 s logic 0 enables; data stable within 150 ns logic 1 = high impedance, data high z within 100 ns mode b a resolution resolver 0 0 10 bits ? 0 1 12 bits ? 1 0 14 bits ? 1 1 16 bits lvdt -5 v 0 8 bits ? 0 -5 v 10 bits ? 1 -5 v 12 bits ? -5 v -5 v 14 bits 10, 12, 14 or 16 parallel lines; natural binary angle positive logic (see note 2) 0.25 to 0.75 s positive pulse leading edge initiates counter update. logic 0 for bit condition. 100 lsbs of error with a filter of 500 s total, loss-of-signal (los) less than 500 mv, or loss-of-ref erence (lor) less than 500 mv. 50 pf+ logic 0; 1 ttl load, 1.6 ma at 0.4 v max. logic 1; 10 ttl loads, -0.4 ma at 2.8 v min logic 0; 100 mv max driving cmos logic 1; +5 v supply minus 100 mv min driving cmos high z; 10 ua //5 pf max frequency range accuracy -xx2 -xx3 (note 3) repeatability differential linearity frequency range accuracy -xx5 (note 3) repeatability differential linearity hz min min lsb lsb hz min lsb lsb 4 +1 lsb 2 +1 lsb 1 1 table 1. rdc-19220/2s specifications notes: 1. unused data bits are set to logic ?0.? 2. in lvdt mode, bit 16 is lsb for 14-bit resolution or bit 12 is lsb for 10-bit resolution 3. accuracy in lvdt mode is 0.15% + 1 lsb of full scale. 4. if the frequency is between 47hz and 1khz, then there may be 1 lsb of jitter at quadrant boundaries. 5. the maximum phase shift tolerance will degrade linearly from 45 degrees at 400 hz to 30 degrees at 60 hz. 6. see text, general setup considerations. 7. when using internally generated -5v the internal -5v charge pump when measured at the converter pin, may be as low as -20% (o r -4v). 8.-xx5 accuracy is 1minute + 1 lsb up to 5 khz max. 9. a signal less than 500 mv will assert bit. 4 +1 lsb 2 +1 lsb 1 1 5 +1 lsb 3 +1 lsb 2 2 47-1k (note 4) 1k - 4k 4k - 10k 1 +1 lsb 1 1 1 +1 lsb 1 1 47-1k (note 4) 1k - 5k (note 8)
4 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 theory of operation the rdc-19220/2s series of converter is a single cmos custom monolithic chip. it is implemented using mixed signal cmos technology which merges precision analog circuitry with digital logic to form a complete high-performance tracking resolver-to- digital converter. for user flexibility and convenience, the con- verter bandwidth, dynamics, and velocity scaling are externally set with passive components. figure 1 is the rdc-19220/2s functional block diagram. the converter operates with 5 v dc power supplies. analog signals are referenced to analog ground, which is at ground potential. the converter is made up of two main sections; a converter and a digital interface. the converter front-end consists of sine and cosine differential input amplifiers. these inputs are protected to 25 v with 2 k ? resistors and diode clamps to the 5 v dc sup- plies. these amplifiers feed the high accuracy control transformer (ct). its other input is the 16-bit digital angle . its output is an analog error angle, or difference angle, between the two inputs. the ct performs the ratiometric trigonometric com- putation of sin cos - cos sin = sin( - ) using amplifiers, switches, logic and capacitors in precision ratios. note: the transfer function of the ct is normally trigonometric, but in lvdt mode the transfer function is triangular (linear) and could thereby convert any lin- ear transducer output. the converter accuracy is limited by the precision of the com- puting elements in the ct. for enhanced accuracy, the ct in these converters use capacitors in precision ratios, instead of the more conventional precision resistor ratios. capacitors used as computing elements with op-amps need to be sampled to elimi- nate voltage drifting. therefore, the circuits are sampled at a high rate (70 khz) to eliminate this drifting and at the same time to cancel out the op-amp offsets. the error processing is performed using the industry standard technique for type ii tracking r/d converters. the dc error is integrated yielding a velocity voltage which in turn drives a volt- age-controlled oscillator (vco). this vco is an incremental inte- grator (constant voltage input to position rate output) which, together with the velocity integrator, forms a type ii servo feed- back loop. a lead in the frequency response is introduced to sta- bilize the loop and a lag at higher frequency is introduced to reduce the gain and ripple at the carrier frequency and above. the settings of the various error processor gains and break fre- quencies are done with external resistors and capacitors so that the converter loop dynamics can be easily controlled by the user. parameter value unit table 1. rdc-19220/2s specifications (cont.) power supplies nominal voltage voltage range max volt. w/o damage current v % v ma (notes 6 and 7) +5 -5 5 5 +7 -7 14 typ, 22 max (each) temperature range operating -30x -20x -10x storage c c c c 0 to +70 -40 to +85 -55 to +125 -65 to +150 physical characteristics size: 40-pin ddip 44-pin j-lead weight: 40-pin ddip 44-pin j-lead in(mm) in(mm) oz (g) oz (g) 2.0 x 0.6 x 0.2 (50.8 x 15.24 x 5.08) 0.690 square (17.526) plastic ceramic n/a 0.24 (6.80) 0.08 (2.27) 0.064 (1.84) thermal resistance junction to case, jc 40-pin ddip (ceramic) 44-pin j-lead (plastic) 44-pin j-lead (ceramic) c/w c/w c/w 4.6 72.6 2.4 dynamic characteristics resolution tracking rate-min (note 6) bandwidth(closed loop) max ka a1 a2 a b acceleration (1 lsb lag) settling time(179 step) bits rps hz 1/sec 2 1/sec 1/sec 1/sec 1/sec deg/s 2 msec (at maximum bandwidth) 10 12 14 16 1152 288 72 18 1200 1200 600 300 5.7m 5.7m 1.4m 360k 19.5 19.5 4.9 1.2 295k 295k 295k 295k 2400 2400 1200 600 1200 1200 600 300 2m 500k 30k 2k 2 8 20 50 velocity characteristics polarity voltage range(full scale) scale factor error scale factor tc reversal error linearity zero offset zero offset tc load noise v % ppm/c % % mv v/c k ? vp/v positive for increasing angle 4 (at nominal ps) 10 typ 20 max 100 typ 200 max 0.75 typ 1.3 max 0.25 typ 0.50 max 5 typ 10 max 15 typ 30 max 8 max 1 typ 0.125 min, 2 max
5 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 transfer function and bode plot the dynamic performance of the converter can be determined from its transfer function block diagrams and its bode plots (open and closed loop). these are shown in figures 2, 3, and 4. the open loop transfer function is as follows: where: a is the gain coefficient a 2 = a 1 a 2 b is the frequency of lead compensation the components of gain coefficient are error gradient, integrator gain, and vco gain. these can be broken down as follows: where: c s = 10 pf f s = 70 khz when rs = 30 k ? f s = 100 khz when rs = 20 k ? f s = 125 khz when rs = 15 k ? c vco = 50 pf r v , r b , and c bw are selected by the user to set velocity scaling and bandwidth. - error gradient = 0.011 volts per lsb (ct+error amp+demod with 2 vrms input) - integrator gain = volts per second per volt - vco gain = lsbs per second per volt 1 1.25 r v c vco c s f s 1.1c bw open loop transfer function = a ( s b + 1 ) 2 s ( s 10b + 1 ) 2 error processor resolver input ( ) velocity out digital position out ( ) vco ct s a + 1 1 b s s + 1 10b h = 1 + - e a 2 s -12 db/oct ba 2a -6 db/oct 10b (rad/sec) 2a 2 2 a (rad/sec) f = bw (hz) = bw 2 a closed loop (b = a/2) gain = 0.4 gain = 4 (critically damped) open loop figure 3. transfer function block diagram #2 figure 4. bode plots general setup conditions ddc has external component selection software which consid- ers all the criteria below and, in a simple fashion, asks the key parameters (carrier frequency, resolution, bandwidth, and track- ing rate) to derive the external component values. the following recommendations should be considered when installing the rdc-19220/2s resolver-to-digital (r/d) converter: 1) when setting the bandwidth (bw) and tracking rate (tr) (selecting five external components), the system require- ments need to be considered. for the greatest noise immuni- ty, select the minimum bw and tr the system will allow. 2) power supplies are 5v dc. for lowest noise performance it is recommended that a 0.1f or larger cap be connected from each supply to ground near the converter package. 3) resolver inputs and velocity output are referenced to agnd. this pin should be connected to gnd near the converter package. digital currents flowing through ground will not dis- turb the analog signals. 4) the bit output, which is active low, is activated by an error of approximately 100 lsbs. during normal operation, for step inputs or on power up, a large error can exist. gain 11 mv/lsb 16 bit up/down counter r 1 vco r v r b c bw c /10 bw vel -vco h = 1 -vsum vel c f s s ct + - resolver input ( ) r s 50 pf c vco digital output ( ) demod 1.25 v threshold 1 figure 2. transfer function block diagram #1
6 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 r c table 3. max tracking rate (min) in rps r s resolution 10 12 14 16 30k or open* 30 k 1152 288 72 18 depending on the reso- lution, select one of the values from this row, for use in converter max tracking rate formula. (see formula in step 5.) *the use of a high quality thin-film resistor will provide better temperature stability than leaving open. 5 5 10 10 30 k 30k or open* 16 14 12 10 resolution r s r c table 4. carrier frequency (max) in khz carrier frequency is shown in table 4. 5) setup of bandwidth and velocity scaling for the optimized crit- ically damped case should proceed as follows: 6) selecting a f bw that is too low relative to the maximum appli- cation tracking rate can create a spin-around condition in which the converter never settles. the relationship to insure against spin-around is as follows (table 2.): - select the desired f bw (closed loop), based on overall system dynamics. - select fcarrier 3.5 f bw - compute r v = 55 k ? x { } application max rate - compute c bw (pf) = 3.2 x f s (hz) x 10 8 r v x (f bw ) 2 - where fs = 70 khz for r s = 30 k ? 100 khz for r s = 20 k ? 125 khz for r s = 15 k ? - compute r b = 0.9 c bw x f bw - compute c bw 10 for the converter max tracking rate value, see the row indicated in table 3. higher tracking rates and carrier frequencies tracking rate (nominally 4 v) is limited by two factors: velocity voltage saturation and maximum internal clock rate (nominally 1,333,333 hz). an understanding of their interaction is essential to extending performance. the general setup considerations section makes note of the selection of rv for the desired velocity scaling. rv is the input resistor to an inverting integrator with a 50 pf nominal feedback capacitor. when it integrates to -1.25 v, the converter counts up 1 lsb and when it integrates to +1.25 v, the converter counts down 1 lsb. when a count is taken, a charge is dumped on the capacitor such that the voltage on it changes 1.25 v in a direc- tion to bring it to 0 v. the output counts per second per volt input is therefore: as an example: calculate rv for the maximum counting rate, at a vel voltage of 4 v. for a 12-bit converter there are 2 12 or 4096 counts per rotation. 1,333,333/4096 = 325 rotations per second or 333,333 counts per second per volt. the maximum rate capability of the rdc-19220/2s is set by r s . when r s = 30 khz it is nominally 1,333,333 counts/second, which equates to 325 rps (rotations per second). this is the absolute maximum; it is recommended to only run at < 90% of this rate (as given in table 3), therefore the minimum r v will be limited to 55 kohms. 1 r v = = 48k ohms (333,333 x 50 pf x 1.25) 1 (r v x 50 pf x 1.25) table 2. tracking/bw relationship rps (max)/bw resolution 1 10 0.50 12 0.25 14 0.125 16 7) rdc-19222 package only: when using the built-in -5 v inverter connect as shown: the current drain from the +5 v supply doubles. no external -5 v supply is needed. the power supply 47f caps shown may be substituted with 10f caps if the p/s lines are clean (min noise). when using the built-in -5 v inverter, the maximum tracking rate should be scaled for a velocity output of 3.5 v max. use the fol- lowing equation to determine tracking rate used in the formula in step 5: note: when using the highest bw and tracking rates, use of the -5 v inverter is not recommended. tr (required) x (4.0) = tracking rate used in calculation (3.5) rdc-19222 10f 23 25 +cap -cap .01uf (-5c) -5v 22 17 .01uf (+5c) +5v 26 2 47uf 47uf + + figure 5. -5v built-in inverter
7 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 bottom view 0.81 max (20.57) 0.30 max (7.62) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.115 max (2.92) 1 345 109876 11 12 14 15 20 19 18 17 16 pin numbers for ref. only terminals 0.025 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder plated brass t1a t1b bottom view side view dimensions are shown in inches (mm). 1 5 3 6 10 11 15 16 20 t1a t1b synchro input resolver output -sin +sin -cos +cos s1 s3 s2 figure 6a. transformer layout and schematic (synchro input - 52034/52035) figure 6b. transformer layout and schematic (resolver input - 52036/52037/52038) 1 3 6 10 11 15 16 20 t1a t1b resolver input resolver output -sin +sin -cos +cos s1 s3 s2 s4 bottom view 0.81 max (20.57) 0.30 max (7.62) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.600 (15.24) 0.115 max (2.92) 1 345 109876 11 12 14 15 20 19 18 17 16 pin numbers for ref. only terminals 0.025 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder plated brass t1a t1b bottom view side view dimensions are shown in inches (mm). * 10% frequency (hz) and line-to-line input voltage (vrms) tolerances ** 2 vrms output magnitudes are -2 vrms 0.5% full scale *** angle accuracy (max minutes) **** 3 vrms to ground or 6 vrms differential (3% full scale) dimensions are for each individual main and teaser 60 hz synchro transformers are active (requires 15 vdc power supplies) 400 hz transformer temperature range: -55c to +125c 60 hz transformer (52039-x, 24133-x) temperature ranges: add to part number -1 or -3, -1 = -55c to +85c -3 = 0 to +70c 3/6 **** 115 60 reference 24133-x 2 90 60 synchro 52039-x 3.4 115 400 reference b-426 2 90 400 r - r 52038 2 26 400 r - r 52037 2 11.8 400 r - r 52036 2 90 400 s - r 52035 2 11.8 400 s - r 52034 out (vrms)** in (vrms)* frequency (hz)* type p/n table 5. transformers 1.125 n/a 1.1 1 0.81 n/a 0.81 1 0.81 1 0.81 1 0.81 1 0.81 1 length (in) angle accuracy*** 1.125 1.14 0.61 0.61 0.61 0.61 0.61 0.61 width (in) .42 .42 0.32 0.3 0.3 0.3 0.3 0.3 height (in) 6d 6d 6c 6b 6b 6b 6a 6a figure number
8 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 1 5 6 10 input output bottom view 0.32 max (8.13) 0.61 max (15.49) 0.15 max (3.81) 0.09 max (2.29) 0.100 (2.54) typ tol non cum 13 25 109876 terminals 0.025 0.001 (6.35 0.03) diam 0.125 (3.18) min length solder-plated brass t1a side view dimensions are shown in inches (mm). 0.105 (2.66) 0.600 (15.24) 0.81 max (20.57) 0.125 min (3.17) figure 6c. transformer layout and schematic (reference input - b-426) b-426 1 5 6 10 rl rh rl rh s1 s3 s4 s2 1 3 6 10 11 15 20 16 external reference lo hi -s sin -r +r -vsum vel -vco digital output 16 cb bit inh em el a b +5v -5v +s +c -c cos agnd gnd rdc-19220 tib tia tia tib s1 s3 s2 resolution control } 52036(11.8v) 52037(26v) or 52038(90v) or 52034(11.8v) 52037(90v) or 1 3 10 6 16 11 15 20 5 or synchro input +s +c agnd gnd rs rc rb cbw cbw/10 rv 30k ? 30k ? figure 7. typical transformer connections 1.14 max (28.96) case is black and non-conductive 1.14 max (28.96) * s1 * s3 (+15 v) +15 v (-r) +s + * * (rh) s2 (rl) + * (v) v (+r) +c (-vs) -vs 52039 or 24133 0.21 0.3 (5.33 0.76) 0.85 0.010 (21.59 0.25) 0.175 0.010 (4.45 0.25) noncumulative tolerance 0.040 0.002 dia. pin. solder plated brass 0.42 (10.67) max. 0.25 (6.35) min. (bottom view) 0.13 0.03 (3.30 0.76) rh rl +15 v v (analog gnd) -vs (-15 v) output +r (rh) -r (rl) 24133 input s1 +15 v v (analog gnd) -vs (-15 v) output +s +c 52039 input s2 s3 the mechanical outline is the same for the synchro input trans- former (52039) and the reference input transformer (24133), except for the pins. pins for the reference transformer are shown in parenthesis ( ). an asterisk * indicates that the pin is omitted. figure 6d. 60 hz synchro and reference transformer diagrams (synchro input - 52039 / reference input - 24133)
9 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 r 1 r 3 r 2 r 4 external ref lo hi resolver s4 s3 s1 s2 gnd +s -s sin cos -c +c a gnd -r +r notes: 1) resistors selected to limit vref peak to between 1.5 v and 4 v. 2) if external reference lo is grounded, then r3 and r4 are not needed, and -r is connected to gnd. 3) 10k ohms, 1 % series current limit resistors are recommended. see note 3. see note 3. note: five external bw components as shown in figures 1 and 2 are necessary for the r/d to function. r 1 r 2 s3 s1 s2 +s -s sin cos -c +c a gnd s4 r 1 r 2 r2 2 = r1 + r2 x volt r1 + r2 should not load the resolver too much; it is recommended that r2 = 10k. r1 + r2 ratio errors will result in angular errors, 2 cycle, 0.1% ratio error = 0.029? peak error. note: five external bw components as shown in figures 1 and 2 are necessary for the r/d to function. figure 8. typical connections, 2 volt resolver, direct input figure 9. typical connections, x-volt resolver, direct input typical inputs figures 8 through 10 illustrate typical input configurations
10 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 r i s1 s3 +s -s sin r f r i r f r i s4 s2 +c -c r f r i r f cos a gnd resolver input converter - + - + note: five external bw components as shown in figures 1 and 2 are necessary for the r/d to function. ri x 2 vrms = resolver l-l rms voltage rf rf 6 k ? s1 and s3, s2 and s4, and rh and rl should be ideally twisted shielded, with the shield tied to agnd at the converter. r i s1 s3 +s -s sin r f r i r f r i s4 s2 +c -c r f r i r f cos a gnd converter 810 12 15 13 2 3 1 6 16 7 4 5 - + - + resolver input note: five external bw components as shown in figures 1 and 2 are necessary for the r/d to function. s1 and s3, s2 and s4, and rh and rl should be ideally twisted shielded, with the shield tied to agnd at the converter. for ddc-49530: ri = 70.8 k ? , 11.8 v input, synchro or resolver. for ddc-49590: ri = 270 k ? , 90 v input, synchro or resolver. maximum addition error is 1 lsb. figure 10a. differential resolver input figure 10b. differential resolver input, using ddc-49530 (11.8 v) or ddc-49590 (90 v)
11 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 r i s1 s3 +s -s sin r f r i r f r i s2 +c -c r /2 i cos a gnd converter r i r / 3 f r / 3 f - + - + ri x 2 vrms = resolver l-l rms voltage rf rf 6 k ? s1, s2, and s3 should be triple twisted shielded; rh and rl should be twisted shielded, in both cases the shield should be tied to agnd at the converter. note: five external bw components as shown in figures 1 and 2 are necessary for the r/d to function. r i s1 s3 +s -s sin r f r i r f r i s2 +c -c r /2 i cos a gnd converter 8 15 11 15 14 2 3 1 6 16 7 4 5 r i 9 r / 3 f r / 3 f 10 - + - + note: five external bw components as shown in figures 1 and 2 are necessary for the r/d to function. s1, s2, and s3 should be triple twisted shielded; rh and rl should be twisted shielded, in both cases the shield should be tied to agnd at the converter. 90 v input = ddc-49590: ri = 270 k ? , 90 v input, synchro or resolver. 11.8 v input = ddc-49530: ri = 70.8 k ? , 11.8 v input, synchro or resolver. maximum addition error is 1 lsb. figure 10c. synchro input figure 10d. synchro input, using ddc-49530 (11.8 v) or ddc-49590 (90 v)
12 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 dc inputs as noted in table 1 the rdc-19220/2s will accept dc inputs. it is necessary to set the ref input to dc by tying +ref to +5 v and -ref to gnd or -5 v. (with dc inputs, the bit output is not valid.) velocity trimming rdc-19220/2s specifications for velocity scaling, reversal error, and offset are contained in table 1. velocity scaling and offset are externally trimmable for applications requiring tighter specifi- cations than those available from the standard unit. figure 11 shows the setup for trimming these parameters with external potentiometers. it should also be noted that when the resolution is changed, velocity scaling is also changed. since the vel out- put is from an integrator with capacitor feedback, the vel voltage cannot change instantaneously. therefore, when changing reso- lution while moving, there will be a transient with a magnitude proportional to the velocity and a duration determined by the converter bandwidth. 8 10 -vco vel +5 v -5 v 100 k ? (offset) 100 r v 0.8 r v 0.4 r (scaling) v rdc-19220/2s figure 11. velocity trimming table 6. 12-bit lvdt output code for figure 12b lvdt output msb lsb + over full travel + full travel -1 lsb +0.5 travel +1 lsb null - 1 lsb -0.5 travel - full travel - over full travel 01 xxxx xxxx xxxx 00 1111 1111 1111 00 1100 0000 0000 00 1000 0000 0001 00 1000 0000 0000 00 0111 1111 1111 00 0100 0000 0000 00 0000 0000 0000 11 xxxx xxxx xxxx cos t reference input. the phase angle of the synthesized ref- erence is determined by the signal input. the reference input is used to choose between the +180 and -180 phases. the syn- thesized reference will always be exactly in phase with the signal input, and quadrature errors will therefore be reduced. the syn- thesized reference circuit also eliminates the 180 false error null hang up. due to the inductive nature of resolvers, the output signals typical- ly lead the reference by 6, and a 6 phase shift will cause prob- lems for a 1.3 / 2.3 arc minute accuracy converter. a synthesized reference will always be exactly in phase with the signal input. lvdt (linear variable differential transformer) mode as shown in table 1 the rdc-19220/2s unit can be made to operate as a lvdt-to-digital converter by connecting resolution control inputs a and b to ?0,? ?1,? or the -5 volt supply. in this mode the rdc-19220/2s functions as a ratiometric tracking lin- ear converter. when linear ac inputs are applied from an lvdt the converter operates over one quarter of its range. this results in two less bits of resolution for lvdt mode than are provided in resolver mode. the lvdt output signals will need to be scaled to be compatible with the converter input. figure 12b is a schematic of an input scaling circuit applicable to 3-wire lvdts. the value of the scal- ing constant ?a? is selected to provide an input of 2 vrms at full stroke of the lvdt. the value of scaling constant ?b? is selected to provide an input of 1 vrms at null of the lvdt. suggested com- ponents for implementing the input scaling circuit are a quad op- amp, such as a 4741 type, and precision thin-film resistors of 0.1% tolerance. figure 12a illustrates a 2-wire lvdt configu- ration. data output of the rdc-19220/2s is binary coded in lvdt mode. the most negative stroke of the lvdt is represented by all zeros and the most positive stroke of the lvdt is repre- sented by all ones. the most significant 2 bits (2 msbs) may be used as overrange indicators. positive overrange is indicated by code ?01? and negative overrange is indicated by code ?11? (see table 6). synthesized reference the synthesized reference section of the rdc-19220/2s elimi- nates errors caused by quadrature voltage which is due to a phase shift between the reference and the signal lines. quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. due to the inductive nature of synchros and resolvers, their signals lead the reference signal (rh and rl) by about 6. when an uncompensated reference signal is used to demodu- late the control transformer?s output, quadrature voltages are not completely eliminated. as shown in figure 1, the converter synthesizes its own cos( t + ) reference signal from the sin cos( t + ), cos ? cos( t + ) signal inputs and from the
13 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 +s -s sin ar r +c -c cos r' - + - + r/2 r r ar br 2r' 2r' r' br +ref -ref r' r' r v b v a notes: 1. r' 10 k ? 2. consideration for the value of r is lvdt loading. 3. rms values given. v b v a lvdt output +fs -fs null cos sin rdc-19220 input -fs +fs null 1v 2v 1 1 b = = v a null v b null 2 a = (v a - v b ) max a sin = 1+ (v a - v b ) 2 a cos = 1- (v a - v b ) 2 figure 12b. 3-wire lvdt scaling circuit +s -s sin ar r +c -c cos r - + - + r r r ar c 1 br 2r 2r r br +ref -ref r c 2 2 wire lvdt ref in r 2 v fs = 2 v figure 12a. 2-wire lvdt direct input c1 = c2, set for phase lag = phase lead through the lvdt.
14 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 inhibit, enable, and cb timing the inhibit (inh ) signal is used to freeze the digital output angle in the transparent output data latch while data is being trans- ferred. application of an inhibit signal does not interfere with the continuous tracking of the converter. as shown in figure 13, angular output data is valid 150 ns maximum after the applica- tion of the negative inhibit pulse. output angle data is enabled onto the tri-state data bus in two bytes. enable msbs (em ) is used for the most significant 8 bits and enable lsbs (el ) is used for the least significant 8 bits. as shown in figure 14, output data is valid 150 ns maximum after the application of a negative enable pulse. the tri-state data bus returns to the high impedance state 100 ns maximum after the rising edge of the enable signal. the converter busy (cb) signal indicates that the tracking con- verter output angle is changing 1 lsb. as shown in figure 15, output data is valid 50 ns maximum after the middle of the cb pulse. the cb pulse width is 1/40 fs, which is nominally 375 ns. built-in-test (bit ) the built-ln-test output (bit ) monitors the level of error from the demodulator. this signal is the difference in the input and output angles and ideally should be zero; if it exceeds approximately 100 lsbs (of the selected resolution) the logic level at bit will change from a logic 1 to a logic 0. this condition will occur during a large step and reset after the converter settles out. bit will also change to logic 0 for an over- velocity condition, because the converter loop cannot maintain input-output or if the converter malfunctions where it cannot maintain the loop at a null. bit will also be set low for a detected loss-of-signal (los) and/or a loss-of-reference (lor). the bit signal may pulse during certain error conditions, i.e., when the converter is in a spin around condition or the signal amplitude is on the threshold of los. los will be detected if both sin and cos input voltages are less than 500 mv peak. lor will be detected if the differential refer- ence voltage is less than 500 mv peak. data data valid 150 ns max inhibit 100 ns max enable 150 ns max data data valid high z high z 1/40 f s (375 nsec nominal) cb 50 ns data data valid data valid * * next cb pulse cannot occur for a minimum of 150 nsec. figure 13. inhibit timing figure 14. enable timing figure 15. converter busy timing
15 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 built-in-test bit 21 ground gnd 20 converter busy cb 22 analog ground a gnd 19 msb bit 1 23 enable msbs em 18 bit 9 24 current set r c 17 bit 2 25 sampling set r s 16 bit 10 26 power supply -5 v 15 bit 3 27 signal input -s 14 bit 11 28 signal input +sin 13 bit 4 29 signal input +s 12 bit 12 30 signal input -c 11 bit 5 31 signal input cos 10 bit 13 32 signal input +c 9 bit 6 33 velocity output vel 8 bit 14 34 vel sum point -vsum 7 bit 7 35 neg. vco input -vco 6 bit 15 36 -reference input -ref 5 bit 8 37 +reference input +ref 4 lsb bit 16 38 inhibit inh 3 enable lsbs el 39 resolution control b 2 power supply +5 v 40 resolution control a 1 description name # description name # pin out function tables by model number the following tables detail pin out functions by the ddc model number. the rdc-19220s has differential inputs but requires both 5 v power supplies. the rdc-19222s has differential inputs and can be used with 5 v or +5 v only. neg. terminal ground pos. terminal neg. supply cap analog ground enable msbs pos. supply cap current set built-in-test sampling set converter busy power supply msb signal input signal input signal input signal input signal input signal input velocity output vel sum point neg. vco input -reference input +reference input inhibit resolution control resolution control power supply (see note) lsb enable lsbs description -cap gnd +cap 23 24 25 -5c (-5v) a gnd em 22 21 20 +5c (+5v) 26 r c 19 bit 27 r s 18 cb 28 -5v 17 bit 1 29 -s 16 bit 9 30 sin 15 bit 2 31 +s 14 bit 10 32 -c 13 bit 3 33 cos 12 bit 11 34 +c 11 bit 4 35 vel 10 bit 12 36 -vsum 9 bit 5 37 -vco 8 bit 13 38 -ref 7 bit 6 39 +ref 6 bit 14 40 inh 5 bit 7 41 b 4 bit 15 42 a 3 bit 8 43 +5v 2 bit 16 44 el 1 name # name # description table 8. rdc-19222s (44-pin) pin outs table 7. rdc-19220s (40-pin) pin outs note: when using the built-in -5 v inverter: connect pin 2 to 26, pin 17 to 22, and a 10 f/10 vdc capacitor from pin 23 (negative terminal) to pin 25 (posi- tive terminal). connect a 47 f/10 vdc capacitor from -5 v to gnd. the current drain from the +5 v supply doubles. no external -5 v supply is needed.
16 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 2.000 0.020 (50.8 0.51) 0.590 0.010 (14.99 0.25) 0.100 0.010 typ (2.54 0.25) 0.018 0.006 typ (0.46 0.15) 0.050 0.020 typ (1.27 0.51) 0.012 0.004 typ (0.31 0.10) +0.050 0.600 - 0.020 +1.27 (15.25 ) - 0.51 dimensions shown are in inches (mm). 1 20 0.125 0.200 (3.18 25.4) 0.050 0.010 (1.27 0.25) 0.085 0.010 (2.16 0.25) 40 21 pin numbers for ref only 0.095 0.010 (2.41 0.25) figure 16. rdc-19220s (40-pin ddip) ceramic package mechanical outline alternate pin 1 identifier 0.650 sq. nom (16.51) 0.690 sq. .005 (17.53) dimensions shown are in inches (mm) tolerance in inches pin 1 identifier .050 .002 (1.27) 0.010 x 45 chfr (3) (0.25) 640 .020 min .620 sq .010 (15.75) .016 .005 (.41) .155 max (3.94) pin #'s shown for reference only figure 17. rdc-19222s (44-pin plastic j-lead) mechanical outline 0.630 0.020 typ (16.00 0.51) 0.500 0.010 (12.70 0.25) dimensions shown are in inches (mm) 0.020 x 45 (0.51) chamfer (orientation mark) 0.040 x 45 chamfer (1.02) (3 places) 0.113 (ref) (2.87) 0.065 0.007 (1.65 0.18) 640 0.075 0.010 (1.91 0.25) 17 18 28 29 39 1 0.075 0.010 (1.91 0.25) 0.500 0.010 (12.70 0.25) 0.050 typ (1.27) 7 0.650 sq 0.010 (16.51 0.25) 0.690 0.010 typ (17.53 0.25) pin numbers for ref only 0.017 typ (0.43) figure 18. rdc-19222s (44-pin ceramic j-lead) mechanical outline
17 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 ddc-49530, ddc-57470 resistor values (11.8 v inputs) table 9. front-end thin-film resistor networks (see figure 20) symbol abs value ( ? ) tol (%) rel to rel value ( ? ) tol (%) tcr(ppm) r1 70.8 k 0.1 25 r2 r3 r1 r4 12 k 12 k 0.02 0.02 2 2 r4 r1 70.8 k 0.02 2 r5 r1 70.8 k 0.02 2 r6 r1 35.4 k 0.02 2 r7 r6 6.9282 k 0.02 2 r8 r6 5.0718 k 0.02 2 r9 r11 5.0718 k 0.02 2 r10 r11 6.9282 k 0.02 2 r11 r1 70.8 k 0.02 2 ddc-49590 resistor values (90 v inputs) r1 270 k 0.1 25 r2 r1 6 k 0.02 2 r3 r4 6 k 0.02 2 r4 r1 270 k 0.02 2 r5 r1 270 k 0.02 2 r6 r1 135 k 0.02 2 r7 r6 3.4641 k 0.02 2 r8 r6 2.5359 k 0.02 2 r9 r11 2.5359 k 0.02 2 r10 r11 3.4641 k 0.02 2 r11 r1 270 k 0.02 2 r11 r10 r9 16 15 14 13 r8 r7 r6 12 11 10 9 r1 r2 12 3 r5 78 r3 r4 45 6 figure 20. (ddc-49530, ddc-49590, ddc-57470) layout and resistor values (see table 9) 16 15 14 13 12 11 10 9 12 3 r2 78 r1 45 6 figure 19. (ddc-55688-1) layout and resistor values (r1 and r2 = 10 k ? 1.0% tol, absolute tc = 100 ppm max) 0.870 max (22.10) 0.250 0.005 (6.35 0.13) dimensions shown are in inches (mm). +0.025 0.325 -0.015 +0.64 (8.26 ) -0.38 0.13 0.005 (3.30 0.13) 0.020 min (0.51) 0.125 min (3.18) 0.075 0.015 (1.91 0.38) 0.018 0.003 (0.46 0.08) 0.100 typ (2.54) 0.320 - 0.300 (8.13 - 7.62) 0.015 0.009 (0.38 0.23) figure 21. 16-pin thin-film resistor network dip mechanical outline (ddc-49530, ddc-55688-1) figure 22. 16-pin thin-film resistor network flat-pack mechanical outline (ddc-57470) .405 0.299 (7.6) dimensions shown are in inches (mm). 0.406 (10.3) 0.014 (.36) 0.342 (8.7) 7? 45? 0.101 (2.6) 0.092 (2.3) 0.009 (0.23) 0.810 max 0.305 max 0.200 max 0.125 min 0.100 typ 0.300 0.10 pin #1 datecode xxx-xxx dimensions shown are in inches figure 23. 16-pin thin-film resistor network dip mechanical outline - ceramic package (ddc-49590)
18 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 ordering information rdc-19222s - xxxx (plastic package: 44-pin j-lead) supplemental process requirements: t = tape and reel blank = none of the above accuracy: 2 = 4 minutes + 1 lsb 3 = 2 minutes + 1 lsb 5 = 1 minute + 1 lsb (maximum reference frequency = 5khz) process requirements: 0 = no burn-in 9 = solder dip, without burn-in temperature grade: 2 = -40 to +85c 3 = 0 to +70c rdc-1922xs - xxxx (ceramic package) supplemental process requirements: t = tape and reel (not available in 40-pin ddip package) s = pre-cap source inspection l = 100% pull test q = pre-cap source and 100% pull test k = one lot date code w = one lot date code and pre-cap source inspection y = one lot date code and 100% pull test z = one lot date code, pre-cap source inspection and 100% pull test blank = none of the above accuracy: 3 = 2 minutes + 1 lsb process requirements: 0 = standard ddc processing, without burn-in 1 = mil-prf-38534 compliant 2 = standard ddc processing, with burn-in 3 = mil-prf-38534 compliant, with pind testing 4 = mil-prf-38534 compliant, with solder dip 5 = mil-prf-38534 compliant, with pind testing, and solder dip 6 = standard ddc processing, with pind testing, and burn-in 7 = standard ddc processing, with solder dip, and burn-in 9 = standard ddc processing, with solder dip, without burn-in temperature grade / data requirements: 1 = -55 to +125c 4 = -55 to +125c, with variables test data package: 0 = 40-pin ddip, (?+5 volt only? power supply feature - not available) 2 = 44-pin j-lead standard ddc processing test mil-std-883 method(s) condition(s) inspection 2009, 2017 ? seal 1014 a and c temperature cycle 1010 c constant acceleration 2001 3000g burn-in 1015, table 1 ?
19 data device corporation www.ddc-web.com rdc-19220/2s f-05/03-0 ordering information (continued) rdc-19229s - 4xxx (class k processed part ordering information) mandatory process requirements selection: (one of the following must be selected) l = 100% pull test q = pre-cap source and 100% pull test (contact factory for availability) y = one lot date code and 100% pull test z = one lot date code, pre-cap source inspection and 100% pull test (contact factory for availability) accuracy: 3 = 2 minutes + 1 lsb process requirements: (burn-in is in accordance with mil-std-883 class k) 6 = 320 hour burn-in at +125c, with pind testing 8 = 320 hour burn-in at +125c, with pind testing and solder dip temperature grade / data requirements: 4 = -55 to +125c, with variables test data package: 9 = screened to class k, 44-pin j-lead ceramic package thin-film resistor networks: (operating temperature range: -55 to +125c) ddc-49530 = 11.8 v input, dip ddc-57470 = 11.8 v input, surface mount ddc-49590 = 90 v input, dip ddc-55688-1 = 2 v direct, dip external component selection software (refer to general setup conditions section) can be downloaded from ddc?s web site: www.ddc-web.com.
data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u 20 f-05/03-0 printed in the u.s.a. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7382 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7382 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)8141-349-087, fax: +49-(0)8141-349-089 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com

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