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rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a variable resolution, resolver-to-digital converter ad2s83 general description the ad2s83 is a monolithic 10-, 12-, 14-, or 16-bit tracking resolver-to-digital converter. the converter allows users to select their own resolution and dynamic performance with external components. the converter allows users to select the resolution to be 10, 12, 14, or 16 bits and to track resolver signals rotating at up to 1040 revs per second (62,400 rpm) when set to 10-bit resolution. the ad2s83 converts resolver format input signals into a paral- lel natural binary digital word using a ratiometric tracking con- version method. this ensures high noise immunity and tolerance of long leads allowing the converter to be located remote from the resolver. the position output from the converter is presented via 3-state output pins which can be configured for operations with 8- or 16-bit bus. byte select, enable and inhibit pins ensure easy data transfer to 8- and 16-bit data bus, and outputs are provided to allow for cycle or pitch counting in external counters. a precise analog signal proportional to velocity is also available and will replace a tachogenerator. the ad2s83 operates over reference frequencies in the range 0 hz to 20,000 hz. product highlights high accuracy velocity output. a precision analog velocity signal with a typical linearity of 0.1% and reversion error less than 0.3% is generated by the ad2s83. the provision of this signal removes the need for mechanical tachogenerators used in servo systems to provide loop stabilization and speed control. resolution set by user. two control pins are used to select the resolution of the ad2s83 to be 10, 12, 14 or 16 bits allow- ing optimum resolution for each application. ratiometric tracking conversion . this technique provides continuous output position data without conversion delay. it also provides noise immunity and tolerance of harmonic distor- tion on the reference and input signals. dynamic performance set by the user. by selecting external resistor and capacitor values the user can determine band- width, maximum tracking rate and velocity scaling of the converter to m atch the system requirements. the component values are easy to select using the free component selection software design aid. models available information on the models available is given in the ordering guide. functional block diagram features tracking r/d converter high accuracy velocity output high max tracking rate 1040 rps (10 bits) 44-lead plcc package 10-, 12-, 14-, or 16-bit resolution set by user ratiometric conversion stabilized velocity reference dynamic performance set by user industrial temperature range applications dc and ac servo motor control process control numerical control of machine tools robotics axis control one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2000 a3 ripple clock r4 vco i/p tracking rate selection r6 velocity signal integrator i/p bandwidth selection r3 c3 reference i/p hf filter r2 c2 c1 r1 demod o/p integrator o/p direction busy dig gnd 16 data bits sc1 sc2 data load byte select 5v +12v ?2v gnd cos sig gnd sin ac error o/p vco o/p c7 ad2s83 r7 3k3 c6 390pf r8 ?2v +12v offset adjust r9 r5 c4 c5 r ?2r dac phase sensitive detector vco + data transfer logic 16-bit up/down counter segment switching output data latch a2 a1 enable inhibit
ad2s83?pecifications parameter conditions min typ max unit signal inputs (sin, cos) frequency 1 0 20,000 hz voltage level 1.8 2.0 2.2 v rms input bias current 60 150 na input impedance 1.0 m ? reference input (ref) frequency 0 20,000 hz voltage level 1.0 8.0 v pk input bias current 60 150 na input impedance 1.0 m ? performance repeatability 1 lsb allowable phase shift (signals to reference) ?0 +10 degree max tracking rate 10 bits 1040 rps 12 bits 260 rps 14 bits 65 rps 16 bits 16.25 rps bandwidth user selectable accuracy angular accuracy a, i 8 +1 lsb arc min monotonicity guaranteed monotonic missing codes (16-bit resolution) a, i 4 codes velocity signal linearity 2, 3, 4 ad2s83ap 0 khz?00 khz 40 c to +85 c 0.15 0.25 % fsr 0.5 mhz? mhz ?0 c to +85 c 0.25 1.0 % fsr ad2s83ip 0 khz?00 khz 40 c to +85 c 0.25 0.5 % fsr 0.5 mhz? mhz ?0 c to +85 c 0.25 1.0 % fsr reversion error ad2s83ap ?0 c to +85 c 0.5 1.0 % o/p ad2s83ip ?0 c to +85 c 1.0 1.5 % o/p dc zero offset 5 3mv gain scaling accuracy 1.5 3 % fsr output voltage 1 ma load 8v dynamic ripple mean value 1.0 % rms o/p input/output protection analog inputs overvoltage protection 8v analog outputs short circuit o/p protection 5.6 8 10.4 ma digital position resolution 10, 12, 14, and 16 bits output format bidirectional natural binary load 3 lsttl inhibit 6 sense logic lo to inhibit time to stable data 240 390 490 ns enable 6 logic lo enables position output logic hi outputs in high enable 6 /disable time impedance state 35 110 ns byte select 6 sense logic hi ms byte db1?b8 logic lo ls byte db1?b8 time to data available 60 140 ns short cycle inputs internally pulled high via 100 k ? to +v s sc1 sc2 0 0 10-bit resolution 0 1 12-bit resolution 1 0 14-bit resolution 1 1 16-bit resolution ( v s = 12 v dc 5%; v l = 5 v dc 10%; t a = ?0 c to +85 c) C2C rev. e
parameter conditions min typ max unit complement internally pulled high via 100 k ? to +v s . logic lo to activate; no connect for normal operation data load sense internally pulled high via 100 k ? 150 300 ns to +v s . logic lo allows data to be loaded into the counters from the data lines busy 6, 7 sense logic hi when position o/p changing width 150 350 ns load use additional pull-up (see figure 2) 1 lsttl direction 6 sense logic hi counting up logic lo counting down max load 3 lsttl ripple clock 6 sense logic hi all 1s to all 0s all 0s to all 1s width dependent on input velocity 300 ns reset before next busy load 3 lsttl digital inputs input high voltage, v ih inhibit , enable 2.0 v db1?b16, byte select v s = 11.4 v, v l = 5.0 v input low voltage, v il inhibit , enable 0.8 v db1?b16, byte select v s = 12.6 v, v l = 5.0 v digital inputs input high current, i ih inhibit , enable 100 a db1?b16 v s = 12.6 v, v l = 5.5 v input low current, i il inhibit , enable 100 a db1?b16, byte select v s = 12.6 v, v l = 5.5 v digital inputs low voltage, v il enable = hi 1.0 v sc1, sc2, data load v s = 12.0 v, v l = 5.0 v low current, i il enable = hi ?00 a sc1, sc2, data load v s = 12.0 v, v l = 5.0 v digital outputs high voltage, v oh db1?b16 2.4 v ripple clk, dir v s = 12.0 v, v l = 4.5 v i oh = 100 a low voltage, v ol db1?b16 0.4 v ripple clk, dir v s = 12.0 v, v l = 5.5 v i ol = 1.2 ma notes 1 angular accuracy is not guaranteed <50 hz reference frequency. 2 linearity derates from 500 khz?000 khz @ 0.0017%/khz. 3 refer to definition of linearity, ?he ad2s83 as a silicon tachogenerator. 4 worst case reversion error at temperature extremes. 5 velocity output offset dependent on value for r6. 6 refer to timing diagram. 7 busy pulse guaranteed up to a vco rate of 900 khz. all min and max specifications are guaranteed. specifications in boldface are tested on all production units at final electrical test. specifications subject to change without notice. ad2s83 C3C rev. e
ad2s83?pecifications parameter conditions min typ max unit three-state leakage db1?b16 only current i l v s = 12.0 v, v l = 5.5 v 20 a v ol = 0 v v s = 12.0 v, v l = 5.5 v 20 a v oh = 5.0 v ratio multiplier ac error output scaling 10 bit 177.6 mv/bit 12 bit 44.4 mv/bit 14 bit 11.1 mv/bit 16 bit 2.775 mv/bit phase sensitive detector output offset voltage 12 mv gain in phase w.r.t. ref ?.882 ?.9 ?.918 v rms/v dc in quadrature w.r.t. ref 0.02 v rms/v dc input bias current 60 150 na input impedance 1.0 m ? input voltage 8v integrator open-loop gain at 10 khz 57 60 63 db dead zone current (hysteresis) 90 100 110 na/lsb input offset voltage 15 mv input bias current 60 150 na output voltage range 8 v vco maximum rate 1.1 mhz vco rate +ve dir 8.25 8.50 8.75 khz/ a ?e dir 8.25 8.50 8.75 khz/ a vco power supply sensitivity rate +v s +0.5 %/v ? s ?.5 %/v input offset voltage 3mv input bias current 12 50 na input bias current tempco +0.22 na/ c linearity of absolute rate ad2s83ap 0 khz?00 khz 0.15 0.25 % fsr 0.5 mhz? mhz 0.25 1.0 % fsr ad2s83ip 0 khz?00 khz 0.25 0.5 % fsr 0.5 mhz? mhz 0.25 1.0 % fsr reversion error ad2s83ap 0.5 1.0 % output ad2s83ip 1.0 1.5 % output power supplies voltage levels +v s +11.4 +12.6 v ? s ?1.4 ?2.6 v +v l +4.5 +5 +v s v current i s v s @ 12 v 12 23 ma i s v s @ 12.6 v 19 30 ma i l +v l @ 5.0 v 0.5 1.5 ma all min and max specifications are guaranteed. specifications in boldface are tested on all production units at final electrical test. specifications subject to change without notice. ( v s = 12 v dc 5%; v l = 5 v dc 10%; t a = ?0 c to +85 c) ordering guide temperature package package model range accuracy description option ad2s83ap ?0 c to +85 c 8 arc min plastic leaded chip carrier p-44a ad2s83ip ?0 c to +85 c 8 arc min plastic leaded chip carrier p-44a rev. e C4C
ad2s83 C5C rev. e pin function descriptions p in nos. mnemonic description 1 demod o/p demodulator output 2 reference i/p reference signal input 3 ac error o/p ratio multiplier output 4 cos cosine input 5 analog gnd power ground 6 signal gnd resolver signal ground 7 sin sine input 8+v s positive power supply 10?5 db1?b16 parallel output data 26 +v l logic power supply 27 enable logic hi?utput data pins in high impedance state logic lo?resents active data to the output pins 28 byte select logic hi?ost significant byte to db1?b8 logic lo?east significant byte to db1?b8 30 inhibit logic lo inhibits data transfer to output latches 31 digital gnd digital ground 32, 33 sc2?c1 select converter resolution 34 data load logic lo db1?b16 inputs logic hi db1?b16 outputs 35 complement active logic lo 36 busy converter busy, data not valid while busy hi 37 direction logic state defines direction of input signal rotation 38 ripple clock positive pulse when conver ter output changes from 1s to all 0s or vice v ersa 39 ? s negative power supply 40 vco i/p vco input 41 vco o/p vco output 42 integrator o/p integrator output 43 integrator i/p integrator input 44 demod i/p demodulator input absolute maximum ratings 1 (with respect to gnd) + v s 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 v dc ? s 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?3 v dc +v l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +v s reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 v to ? s sin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 v to v s cos . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 v to v s any logical input . . . . . . . . . . . . . . . . . . ?.4 v dc to +v l dc demodulator input . . . . . . . . . . . . . . . . . . . . . . . +13 v to ? s integrator input . . . . . . . . . . . . . . . . . . . . . . . . . . +13 v to ? s vco input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +13 v to ? s power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mw operating temperature industrial (ap, ip) . . . . . . . . . . . . . . . . . . . ?0 c to +85 c storage temperature . . . . . . . . . . . . . . . . . . ?5 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . 300 c caution 1 absolute maximum ratings are those values beyond which damage to the device may occur. 2 correct polarity voltages must be maintained on the +v s and ? s pins. recommended operating conditions power supply voltage (+v s , ? s ) . . . . . . . . . . 12 v dc 5% power supply voltage v l . . . . . . . . . . . . . . . . . +5 v dc 10% analog input voltage (sin and cos) . . . . . . . 2 v rms 10% analog input voltage (ref) . . . . . . . . . . . . . . 1 v to 8 v peak signal and reference harmonic distortion . . . . . . 10% (max) phase shift between signal and reference . . . 10 degrees (max) ambient operating temperature range industrial (ap, ip) . . . . . . . . . . . . . . . . . . . ?0 c to +85 c pin configuration 9 10 11 12 13 7 8 16 17 14 15 2144 3 4 5 6424140 43 35 36 37 38 39 33 34 31 32 29 30 v s ripple clock direction busy comp data load sc1 db14 db11 db12 db13 db15 sin i/p +v s nc (msb) db1 db2 db3 db4 nc = no connect db5 db6 db7 db8 sc2 digital gnd inhibit nc signal gnd analog gnd cos i/p ac error o/p ref i/p demod o/p demod i/p integrator i/p integrator o/p vco o/p vco i/p 18 19 20 21 22 23 24 25 26 27 28 pin 1 identifier top view (not to scale) ad2s83 (lsb) db16 +v l enable byte select db10 db9 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad2s83 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad2s83 rev. e C6C bit weight table binary resolution degrees minutes seconds bits (n) (n n ) /bit /bit /bit 0 1 360.0 21600.0 1296000.0 1 2 180.0 10800.0 648000.0 2 4 90.0 5400.0 324000.0 3 8 45.0 2700.0 162000.0 4 16 22.5 1350.0 81000.0 5 32 11.25 675.0 40500.0 6 64 5.625 337.5 20250.0 7 128 2.8125 168.75 10125.0 8 256 1.40625 84.375 5062.5 9 512 0.703125 42.1875 2531.25 10 1024 0.3515625 21.09375 1265.625 11 2048 0.1757813 10.546875 632.8125 12 4096 0.0878906 5.273438 316.40625 13 8192 0.0439453 2.636719 158.20313 14 16384 0.0219727 1.318359 79.10156 15 32768 0.0109836 0.659180 39.55078 16 65536 0.0054932 0.329590 19.77539 17 131072 0.0027466 0.164795 9.8 8770 18 262144 0.0013733 0.082397 4.9 4385 connecting the converter the power supply voltages connected to +v s and ? s pins should be +12 v dc and ?2 v dc and must not be reversed. the voltage applied to v l can be +5 v dc to +v s . it is recommended that the decoupling capacitors are connected in parallel between the power lines +v s , ? s and analog ground adjacent to the converter. recommended values are 100 nf (ceramic) and 10 f (tantalum). also capacitors of 100 nf and 10 f should be connected between +v l and digital ground adjacent to the converter. when more than one converter is used on a card, separate de- coupling capacitors should be used for each converter. the resolver connections should be made to the sin and cos inputs, reference input and signal ground as shown in figure 11 and described in the connecting the resolver section. the two signal ground wires from the resolver should be joined at the signal ground pin of the converter to minimize the coupling between the sine and cosine signals. for this reason it is also recommended that the resolver is connected using indi- vidually screened twisted pair cables with the sine, cosine and reference signals twisted separately. signal ground and analog ground are connected internally. analog ground and digital ground must be connected externally and as close to the converter as possible. the external components required should be connected as shown in figure 1. converter resolution two major areas of the ad2s83 specification can be selected by the user to optimize the total system performance. the resolu- tion of the digital output is set by the logic state of the inputs sc1 and sc2 to be 10, 12, 14 or 16 bits; and the dynamic char- acteristics of bandwidth and tracking rate are selected by the choice of external components. the choice of the resolution will affect the values of r4 and r6 which scale the inputs to the integrator and the vco respec- tively (see component selection section). if the resolution is changed, then new values of r4 and r6 must be switched into the circuit. note: when changing resolution under dynamic conditions, do it when the busy is low, i.e., when data is not changing. a1 a2 segment switching ripple clock tracking rate selection velocity signal r5 c4 c5 integrator i/p bandwidth selection r8 12v +12v offset adjust r9 r3 c3 reference i/p hf filter r2 c2 c1 r1 demod o/p phase sensitive detector integrator o/p direction busy dig gnd 16 data bits sc1 sc2 data load byte select 5v +12v 12v gnd cos sig gnd sin ac error o/p ad2s83 vco o/p vco i/p c7 150pf vco + data transfer logic a3 r4 r7 3k3 c6 390pf output data latch r - 2r dac 16-bit up/down counter r6 inhibit enable figure 1. connection diagram
ad2s83 C7C rev. e converter operation when connected in a circuit such as shown in figure 10, the ad2s83 operates as a tracking resolver-to-digital converter. the output will automatically follow the input for speeds up to the selected maximum tracking rate. no convert command is necessary as the conversion is automatically initiated by each lsb increment, or decrement, of the input. each lsb change of the converter initiates a busy pulse. the ad2s83 is remarkably tolerant of input amplitude and frequency variation because the conversion depends only on the ratio of the input signals. consequently there is no need for accurate, stable oscillator to produce the reference signal. the inclusion of the phase sensitive detector in the conversion loop ensures high immunity to signals that are not phase or frequency coherent or are in quadrature with the reference signal. signal conditioning the amplitude of the sine and cosine signal inputs should be maintained within 10% of the nominal values if full perfor- mance is required from the velocity signal. the digital position output is relatively insensitive to amplitude variation. increasing the input signal levels by more than 10% will result in a loss in accuracy due to internal overload. reduc- ing levels will result in a steady decline in accuracy. with the signal levels at 50% of the correct value, the angular error will increase to an amount equivalent to 1.3 lsb. at this level the repeatability will also degrade to 2 lsb and the dynamic response will also change, since the dynamic characteristics are propor- tional to the signal level. the ad2s83 will not be damaged if the signal inputs are applied to the converter without the power supplies and/or the reference. reference input the amplitude of the reference signal applied to the converter? input is not critical, but care should be taken to ensure it is kept within the recommended operating limits. the ad2s83 will not be damaged if the reference is supplied to the converter without the power supplies and/or the signal inputs. harmonic distortion the amount of harmonic distortion allowable on the signal and reference lines is 10%. square waveforms can be used but the input levels should be adjusted so that the average value is 1.9 v rms. (for example, a square wave should be 1.9 v peak.) triangular and sawtooth waveforms should have a amplitude of 2 v rms. note: the figure specified of 10% harmonic distortion is for calibration convenience only. position output the resolver shaft position is represented at the converter out- put by a natural binary parallel digital word. as the digital posi- tion output of the converter passes through the major carries, i.e., all ?s?to all ?s?or the inverse, a ripple clock (rc) logic output is initiated indicating that a revolution or a pitch of the input has been completed. the direction of input rotation is indicated by the direction (dir) logic output. this direction data is always valid in advance of a ripple clock pulse and, as it is internally latched, only changing state (1 lsb min change in input) with a correspond- ing change in direction. both the ripple clock pulse and the direction data are unaffected by the application of the inhibit . the static positional accuracy quoted is the worst case error that can occur over the full operating temperature excluding the effects of offset signals at the integrator input (which can be trimmed out?ee figure 1), and with the following conditions: input signal amplitudes are within 10% of the nominal; phase shift between signal and reference is less than 10 degrees. these operating conditions are selected primarily to establish a repeatable acceptance test procedure which can be traced to national standards. in practice, the ad2s83 can be used well outside these operating conditions providing the above points are observed. velocity signal the tracking converter technique generates an internal signal at the output of the integrator (integrator output) that is proportional to the rate of change of the input angle. this is a dc analog output referred to as the velocity signal. it is recommended that the velocity output be buffered. the sense is positive for an increasing angular input and nega- tive for decreasing angular input. the full-scale velocity output is 8 v dc. the output velocity scaling and tracking rate are a function of the resolution of the converter; this is summarized below. max tracking nominal scaling res rate (rps) (rps/v dc) 10 1040 130 12 260 32.5 14 65 8.125 16 16.25 2.03 (velocity o/p = 8 v dc nominal) the output velocity can be suitably scaled and used to replace a conventional dc tachogenerator. for more detailed information see the ad2s83 as a silicon tachogenerator section. dc error signal the signal at the output of the phase sensitive detector (demodulator output) is the signal to be nulled by the tracking loop and is, therefore, proportional to the error between the input angle and the output digital angle. as the converter is a type 2 servo loop, the demodulator output signal will increase if the output fails to track the input for any reason. this is an indication that the input has exceeded the maximum tracking rate of the converter or, due to some internal or exter- nal malfunction, the converter is unable to reach a null. by con- necting two external comparators, this voltage can be used as a ?uilt-in-test.
ad2s83 rev. e C8C component selection the following instructions describe how to select the external components for the converter in order to achieve the required bandwidth and tracking rate. in all cases the nearest ?referred value?component should be used, and a 5% tolerance will not degrade the overall performance of the converter. care should be taken that the resistors and capacitors will function over the required operating temperature range. the components should be connected as shown in figure 1. free pc compatible software is available to help users select the optimum component values for the ad2s83, and display the transfer gain, phase and small step response. for more detailed information and explanation, see the circuit functions and dynamic performance section. 1. hf filter (r1, r2, c1, c2) the function of the hf filter is to remove any dc offset and to reduce the amount of noise present on the signal inputs to the ad2s83, reaching the phase sensitive detector and affecting the outputs. r1 and c2 may be omitted?n which case r2 = r3 and c1 = c3, calculated below?ut their use is particularly recommended if noise from switch mode power supplies and brushless motor drive is present. values should be chosen so that 15 k ? r 1 = r 2 56 k ? c 1 = c 2 = 1 2 r 1 f ref and f ref = reference frequency (hz) this filter gives an attenuation of three times at the input to the phase sensitive detector. 2. gain scaling resistor (r4) (see phase sensitive demodula- tor section.) if r1, c2 are used: r 4 = e dc 100 10 ? 9 1 3 ? where 100 10 9 = current/lsb if r1, c2 are not used: r 4 = e dc 100 10 9 ? where e dc = 160 10 3 for 10 bits resolution = 40 10 3 for 12 bits = 10 10 3 for 14 bits = 2.5 10 3 for 16 bits = scaling of the dc error in volts/lsb 3. ac coupling of reference input (r3, c3) select r3 and c3 so that there is no significant phase shift at the reference frequency. that is, r 3 = 100 k ? c 3 > 1 r 3 f ref f with r3 in ? . 4. maximum tracking rate (r6) the vco input resistor r6 sets the maximum tracking rate of the converter and hence the velocity scaling as at the max tracking rate, the velocity output will be 8 v. decide on your maximum tracking rate, t, in revolutions per second. when setting the value for r6, it should be remembered that the linearity of the velocity output is specified across 0 khz 500 khz and 500 khz 1000 khz. the following conversion can be used to determine the corresponding rps: rps = vco rate ( hz ) 2 n note that t must not exceed the maximum tracking rate or 1/16 of the reference frequency. r 6 = 6. 81 10 10 t n ? where n = bits per revolution = 1,024 for 10 bits resolution = 4,096 for 12 bits = 16,384 for 14 bits = 65,536 for 16 bits 5. closed-loop bandwidth selection (c4, c5, r5) a. choose the closed-loop bandwidth (f bw ) required ensuring that the ratio of reference frequency to band- width does not exceed the following guidelines: resolution ratio of reference frequency/bandwidth 10 2.5 : 1 12 4 : 1 14 6 : 1 16 7.5 : 1 typical values may be 100 hz for a 400 hz reference fre- quency and 500 hz to 1000 hz for a 5 khz reference frequency. b. select c4 so that c 4 = 21 r 6 f bw 2 f with r6 in ? and f bw , in hz selected above. c. c5 is given by c 5 = 5 c 4 d. r5 is given by r 5 = 4 2 f bw c 5 ? 6. vco phase compensation the following values of c6 and r7 should be connected as close as possible to the vco output, pin 41. c 6 = 390 pf , r 7 = 3. 3 k ? 7. vco optimization to optimize the performance of the vco a capacitor, c7, should be placed across the vco input and output, pins 40 and 41. c 7 = 150 pf
ad2s83 C9C rev. e 8. offset adjust offsets and bias currents at the integrator input can cause an additional positional offset at the output of the converter of 1 arc minute typical, 5.3 arc minutes maximum. if this can be tolerated, then r8 and r9 can be omitted from the circuit. if fitted, the following values of r8 and r9 should be used: r 8 = 4. 7 m ? , r 9 = 1 m ? potentiometer to adjust the zero offset, ensure the resolver is disconnected and all the external components are fitted. connect the cos pin to the reference input and the sin pin to the signal ground and with the power and reference applied, adjust the potentiometer to give all 0s on the digital output bits. the potentiometer may be replaced with select on test resistors if preferred. data transfer to transfer data the inhibit input should be used. the data will be valid 490 ns after the application of a logic lo to the inhibit . this is regardless of the time when the inhibit is applied and allows time for an active busy to clear. by using the enable input the two bytes of data can be transferred after which the inhibit should be returned to a logic hi state to enable the output latches to be updated. busy output the validity of the output data is indicated by the state of the busy output. when the input to the converter is changing, the signal appearing on the busy output is a series of pulses at ttl level. a busy pulse is initiated each time the input moves by the analog equivalent of one lsb and the internal counter is incremented or decremented. inhibit input the inhibit logic input only inhibits the data transfer from the up-down counter to the output latches and, therefore, does not interrupt the operation of the tracking loop. releasing the inhibit automatically generates a busy pulse to refresh the output data. enable input the enable input determines the state of the output data. a logic hi maintains the output data pins in the high imped- ance condition, and the application of a logic lo presents the data in the latches to the output pins. the operation of the enable has no effect on the conversion process. byte select input the byte select input selects the byte of the position data to be presented at the data output db1 to db8. the least sig- nificant byte will be presented on data output db9 to db16 (with the enable input taken to a logic lo ) regardless of the state of the byte select pin. note that when the ad2s83 is used with a resolution less than 16 bits the unused data lines are pulled to a logic lo. a logic hi on the byte select input will present the eight most significant data bits on data output db1 and db8. a logic lo will present the least sig- nificant byte on data outputs 1 to 8, i.e., data outputs 1 to 8 will duplicate data outputs 9 to 16. the operation of the byte select has no effect on the con- version process of the converter. ripple clock as the output of the converter passes through the major carry, i.e., all 1s to all 0s or the converse, a positive going edge on the ripple clock (rc) output is initiated indicating that a revolution, or a pitch, of the input has been completed. the minimum pulsewidth of the ripple clock is 300 ns. ripple clock is normally set high before a busy pulse and resets before the next positive going edge of the next busy pulse. the only exception to this is when dir chan ges while the ripple clock is high. resetting of the ripple clock will only occur if the dir remains stable for two consecutive posi- tive busy pulse edges. if the ad2s83 is being used in a pitch and revolution counting application, the ripple and busy will need to be gated to prevent false decrement or increment (see figure 2). ripple clock is unaffected by inhibit . 5v 5k1 in4148 busy in4148 ripple clock 2n3904 0v 10k 1k 5v to counter (clock) note: do not use above cct when inhibit is low. figure 2. diode transistor logic n and gate
ad2s83 rev. e C10C parameter t min * t max * condition t 1 150 350 busy width v h v h t 2 10 25 ripple clock v h to busy v h t 3 470 580 ripple clock v l to next busy v h t 4 16 45 busy v h to data v h t 5 3 25 busy v h to data v l t 6 70 140 inhibit v h to busy v h t 7 485 625 min dir v h to busy v h t 8 515 670 min dir v h to busy v h t 9 490 inhibit v l to data stable t 10 40 110 enable v l to data v h t 11 35 110 enable v l to data v l t 12 60 140 byte select v l to data stable t 13 60 125 byte select v h to data stable * ns v h busy ripple clock data inhibit dir inhibit enable data byte select data v h v h v h v h v h v h v h v l v l v l v l v l v l v l v l v z t 11 t 10 t 9 t 8 t 7 t 6 t 5 t 4 t 3 t 2 t 1 t 12 t 13 figure 3. digital timing
ad2s83 C11C rev. e direction output the direction (dir) output indicates the direction of the input rotation. any change in the state of dir precedes the corresponding busy, data and ripple clock updates. dir can be considered as an asynchronous output and can make multiple changes in state between two consecutive lsb update cycles. this occurs when the direction of rotation of the input changes but the magnitude of the rotation is less than 1 lsb. complement the complement input is an active low input and is inter- nally pulled to +v s via 100 k ? . strobing data load and complement pins to logic lo will set the logic hi bits of the ad2s83 counter to a lo state. those bits of the applied data which are logic lo will not change the corresponding bits in the ad2s83 counter. for example: initial counter state 1 0 1 0 1 applied data word 1 1 0 0 0 counter state after data load 1 1 0 0 0 initial counter state 1 0 1 0 1 applied data word 1 1 0 0 0 counter state after data load and complement 0 0 1 0 1 in order to read the counter following a data load , the procedure below should be followed: 1. place outputs in high impedance state ( enable = hi). 2. present data to pins. 3. pull data load and complement pins to ground. 4. wait 100 ns. 5. remove data from pins. 6. remove outputs from high impedance state ( enable = lo). 7. read outputs. circuit functions and dynamic performance the ad2s83 allows the user great flexibility in choosing the dynamic characteristics of the resolver-to-digital conversion to ensure the optimum system performance. the characteristics are set by the external components shown in figure 1. the component selection section explains how to select desired maximum tracking rate and bandwidth values. the following paragraphs explain in greater detail the circuit of the ad2s83 and the variations in the dynamic performance available to the user. loop compensation the ad2s83 (connected as shown in figure 1) operates as a type 2 tracking servo loop where the vco/counter combination and integrator perform the two integration functions inherent in a type 2 loop. additional compensation in the form of a pole/zero pair is required to stabilize the loop. this compensation is implemented by the integrator compo- nents (r4, c4, r5, c5). the overall response the converter is that of a unity gain second order low-pass filter, with the angle of the resolver as the input and the digital position data as the output. the ad2s83 does not have to be connected as tracking con- verter, parts of the circuit can be used independently. this is particularly true of the ratio multiplier which can be used as a control transformer. (for more information contact motion control applications.) a block diagram of the ad2s83 is given in figure 4. ratio multiplier vco phase sensitive demodulator ac error a, sin ( ) sin t sin sin t cos sin t digital clock direction r4 r5 r6 c5 c4 velocity integrator figure 4. functional diagram
ad2s83 rev. e C12C ratio multiplier the ratio multiplier is the input section of the ad2s83. this compares the signal from the resolver (angle ) to the digital (angle ) held in the counter. any difference between these two angles results in an analog voltage at the ac error output. this circuit function has historically been called a control transformer as it was originally performed by an electromechanical device known by that name. the ac error signal is given by a 1 sin ( ) sin t where = 2 f ref f ref = reference frequency a1 = the gain of the ratio multiplier stage = 14.5. so for 2 v rms inputs signals ac error output in volts/(bit of error) = 2 sin 360 n ? ? ? ? ? ? a 1 where n = bits per rev = 1,024 for 10-bit resolution = 4,096 for 12-bit resolution = 16,384 for 14-bit resolution = 65,536 for 16-bit resolution giving an ac error output = 178 mv/bit @ 10-bit resolution = 44.5 mv/bit @ 12-bit resolution = 11.125 mv/bit @ 14-bit resolution = 2.78 mv/bit @ 16-bit resolution the ratio multiplier will work in exactly the same way whether the ad2s83 is connected as a tracking converter or as a control transformer, where data is preset into the counters using the data load pin. hf filter the ac error output may be fed to the psd via a simple ac coupling network (r2, c1) to remove any dc offset at this point. note, however, that the psd of the ad2s83 is a wide- band demodulator and is capable of aliasing hf noise down to within the loop bandwidth. this is most likely to happen where the resolver is situated in particularly noisy environments, and the user is advised to fit a simple hf filter r1, c2 prior to the phase sensitive demodulator. the attenuation and frequency response of a filter will affect the loop gain and must be taken into account in deriving the loop transfer function. the suggested filter (r1, c1, r2, c2) is shown in figure 1 and gives an attenuation at the reference frequency (f ref ) of three times at the input to the phase sensitive demodulator. values of components used in the filter must be chosen to ensure that the phase shift at f ref is within the allowable signal to reference phase shift of the converter. phase sensitive demodulator the phase sensitive demodulator is effectively ideal and devel- ops a mean dc output at the demodulator output pin of 22 ( demodulator input rms voltage ) for sinusoidal signals in phase or antiphase with the reference (for a square wave the demodulator output voltage will equal the demodulator input). this provides a signal at the demodulator output which is a dc level proportional to the positional error of the converter. dc error scaling = 160 mv/bit (10-bit resolution) = 40 mv/bit (12-bit resolution) = 10 mv/bit (14-bit resolution) = 2.5 mv/bit (16-bit resolution) when the tracking loop is closed, this error is nulled to zero unless the converter input angle is accelerating. integrator the integrator components (r4, c4, r5, c5) are external to the ad2s83 to allow the user to determine the optimum dynamic characteristics for any given application. the component selection section explains how to select com ponents for a chosen bandwidth. since the output from the integrator is fed to the vco input, it is proportional to velocity (rate of change of output angle) and can be scaled by selection of r6, the vco input resistor. this is explained in the voltage controlled oscillator (vco) section below. to prevent the converter from flickering (i.e., continually toggling by 1 bit when the quantized digital angle, , is not an exact representation of the input angle, ) feedback is internally applied from the vco to the integrator input to ensure that the vco will only update the counter when the error is greater than or equal to 1 lsb. in order to ensure that this feedback hys- teresis is set to 1 lsb the input current to the integrator must be scaled to be 100 na/bit. therefore, r 4 = dc error scaling ( mv / bit ) 100 ( na / bit ) any offset at the input of the integrator will affect the accuracy of the conversion as it will be treated as an error signal and offset the digital output. one lsb of extra error will be added for each 100 na of input bias current. the method of adjusting out t his offset is given in the component selection section. voltage controlled oscillator (vco) the vco is essentially a simple integrator feeding a pair of dc level comparators. whenever the integrator output reaches one of the comparator threshold voltages, a fixed charge is injected into the integrator input to balance the input current. at the same time the counter is clocking either up or down, dependent on the polarity of the input current. in this way the counter is clocked at a rate proportional to the magnitude of the input current of the vco.
ad2s83 C13C rev. e during the vco reset period the input continues to be inte- grated. the reset period is constant at 40 ns. the vco rate is fixed for a given input current by the vco scaling factor: = 8.5 khz / a the tracking rate in rps per a of vco input current can be found by dividing the vco scaling factor by the number of lsb changes per rev (i.e., 4096 for 12-bit resolution). the input resistor r6 determines the scaling between the con- verter velocity signal voltage at the integrator output pin and the vco input current. thus to achieve a 5 v output at 100 rps (6000 rpm ) and 12-bit resolution the vco input cur- rent must be: (100 4096)/(8500) = 48.2 a thus, r6 would be set to: 5/(48.2 10 6 ) = 103.7 k ? the velocity offset voltage depends on the vco input resistor, r6, and the vco bias current and is given by velocity offset voltage = r 6 ( vco bias current) the temperature coefficient of this offset is given by velocity offset tempco = r6 ( vco bias current tempco) where the vco bias current tempco is typically +0.22 na/ c. the maximum recommended rate for the vco is 1.1 mhz which sets the maximum possible tracking rate. since the minimum voltage swing available at the integrator output is 8 v, this implies that the minimum value for r6 is 62 k ? . as max current a min value r k = = = =? 11 10 85 10 129 6 8 129 10 62 6 3 6 . . transfer function by selecting components using the method outlined in the sec- tion component selection, the converter will have a critically damped time response and maximum phase margin. the closed-loop transfer function is given by: out in = 14 (1 + s n ) ( s n + 2.4) ( s n 2 + 3.4 s n + 5.8 ) where, s n , the normalized frequency variable is given by: s n = 2 s f bw and f bw is the closed-loop 3 db bandwidth (selected by the choice of external components). the acceleration constant k a , is given approximately by k a = 6 ( f bw ) 2 sec 2 the normalized gain and phase diagrams are given in figures 5 and 6. frequency f bw 12 12 gain plot 9 0 3 6 9 6 3 0.0 2 0.04 0.1 0.2 0.4 1 figure 5. gain plot frequency f bw 180 180 phase plot 135 0 45 90 135 90 45 0.0 2 0.04 0.1 0.2 0.4 1 figure 6. phase plot
ad2s83 rev. e C14C the small signal step response is shown in figure 7. the time from the step to the first peak is t 1 , and the t 2 is the time from the step until the converter is settled to 1 lsb. the times t 1 and t 2 are given approximately by t 1 = 1 f bw t 2 = 5 f bw r 12 where r = resolution, i.e., 10, 12, 14 or 16. t 2 t 1 time figure 7. small step response the large signal step response (for steps greater than 5 degrees) applies when the error voltage exceeds the linear range of the converter. typically the converter will take three times longer to reach the first peak for a 179 degrees step. in response to a velocity step, the velocity output will exhibit the same time response characteristics as outlined above for the position output. the ad2s83 as a silicon tachogenerator position control using the ad2s83 the ad2s83 has been optimized for use as a feedback device for velocity as well as position. a traditional position control loop shown below compares a demand position with an actual to derive a position error and hence a velocity demand. + position demand actual position motor feedback source control terms position electronics figure 8. position control quality of control may be reduced if the load on a motor varies dynamically. system reaction and compensation for a sudden change in the loading depends on how rapidly the system can update the velocity demand to the motor. this can cause rapid acceleration of the motor until the loop updates with a new velocity demand. the only effective way to compensate for dynamic loading effects is to introduce a 2nd order term which will provide the motor with an acceleration or deceleration demand signal (see figure 9). control terms position electronics + position demand actual position motor feedback source velocity electronics figure 9. position control and velocity control traditionally this would need to be implemented by using sepa- rate position and speed feedback transducers, e.g., an encoder or resolver and a dc tachogenerator. the ad2s83 can decode the resolver to provide both velocity and position information. dc tachogenerator the dc tachogenerator is a small permanent magnet dc generator. the output is a dc voltage which is proportional to the speed of the rotor and whose polarity is determined by the direction of rotation. physically they are similar to a resolver. velocity error derivation the velocity error is the difference between the synthesized dc velocity demand derived from the actual and demand positions and the feedback from the tachogenerator or the ad2s83. the velocity demand is usually derived via a dac so apart from any quantization noise it is clean. the velocity feedback, therefore, needs to be as close to a pure dc level as possible. the errors which determine the quality of the resultant acceleration demand to the motor are explained below. linearity linearity is the maximum deviation from the ideal straight line velocity characteristic. the line used is given by: v = mx + c where v = velocity m = gain scaling x = dc voltage c = zero velocity dc offset linearity is generally a function of the input velocity to the tachogenerator or resolver. reversion error reversion or reversal error is an offset which is dependent on the direction of rotation of the transducer; e.g., if 10 rps = 1.000 v dc, then 10 rps = 1.003 v dc with +0.3% reversion error and fso = 8 v dc. zero velocity dc offset this is a residual dc offset present at zero input velocity. this can be externally nulled.
ad2s83 C15C rev. e ripple content ripple content is due to several factors. tachogenerators suffer from ripple due to the speed of rotation, commutator segments and the number of poles. the resolver/rdc combination has a predominant ripple at twice the resolver reference as a result of the synchronous demodulator and at a frequency twice per revolution due to the resolver windings mismatch. motor torque pulsations which are a consequence of excessive velocity ripple have a detrimental effect upon the quality of speed control in servo systems. the resultant cogging effect will be particularly noticeable at low speed and when the motor is in the low torque region. other undesirable side effects such as the increase in acoustic noise from a motor and a temperature rise in the motor stator windings are possible results of the presence of torque ripple. for more detailed information of the causes and sources of errors see the velocity errors section. ad2s83 comparison with dc tachogenerator comparative tests of the ad2s83 and a dc tachogenerator were carried out. the tachogenerator was connected at the nondrive end of the motor shaft with the resolver located behind the drive shaft of the motor. the ad2s83 was located remotely. the ad2s83 was set up with a 200 hz bandwidth, reference fre- quency of 2.6 khz and resolution of 14 bits. the comparative analysis can be summarized: ad2s83 dc tacho conditions linearity % 0.1 0.1 0 3600 rpm reversion error % fso 0.3 0.25 note the typical operating range of dc tachogenerator is 0 rpm-3600 rpm. the resolver/ad2s83 combination will oper- ate up to speeds in excess of 10000 rpm. ripple effects the comparative analysis of the output ripple from the tacho- generator and the ad2s83 is illustrated below. minimization of the ad2s83 output ripple is discussed in detail in the velocity errors section. other factors other factors concerning choice of feedback source have to be addressed. on average the mtbf of a tachogenerator is 347 days as opposed to typically 8 years for a resolver. resolvers are relatively insensitive to temperature whereas a tachogenerator will be specified up to a maximum of 100 c with a 0.1%/ c (above 25 c) degradation in output voltage. the brushless resolver requires no preventative maintenance; the brushes on a tachogenerator, however, will require periodic checking. acceleration error a tracking converter employing a type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. this additional error can be defined using the acceleration constant k a of the converter. k a = input acceleration error in output angle the numerator and denominator must have consistent angular units. for example if k a is in sec 2 , then the input acceleration may be specified in degrees/sec 2 and the error output in degrees. k a does not define maximum input acceleration, only the error due to acceleration. the maximum acceleration allowable before the converter loses track is dependent on the angular accuracy requirements of the system. angular accuracy k a = degrees / sec 2 k a can be used to predict the output position error for a given input acceleration. for example for an acceleration of 100 revs/sec 2 , k a = 2.7 10 6 sec 2 and 12-bit resolution. error in lsbs = input acceleration [ lsb / sec 2 ] k a [sec 2 ] = 100 [ rev / sec 2 ] 2 12 2. 7 10 6 = 0.15 lsbs or 47.5 seconds of arc to determine the value of k a based on the passive components used to define the dynamics of the converter the following should be used. k a = 4. 04 10 11 2 n r 6 r 4 ( c 4 + c 5) where n = resolution of the converter. r4, r6 in ohms c5, c4 in farads.
ad2s83 rev. e C16C sources of errors integrator offset additional inaccuracies in the conversion of the resolver signals will result from an offset at the input to the integrator. this offset will be treated as an error signal. the resulting angular error will typically be 1 arc minute over the operating tempera- ture range. a description of how to adjust the zero offset is given in the component selection section; the circuit required is shown in figure 1. differential phase shift phase shift between the sine and cosine signals from the resolver is known as differential phase shift and can cause static error. some differential phase shift will be present on all resolvers as a result of coupling. a small resolver residual voltage (quadrature voltage) indicates a small differential phase shift. additional phase shift can be introduced if the sine channel wires and the cosine channel wires are treated differently. for instance, differ- ent cable lengths or different loads could cause differential phase shift. the additional error caused by differential phase shift on the input signals approximates to error = 0.53 a b arc minutes where a = differential phase shift (degrees). b = signal to reference phase shift (degrees). this error can be minimized by choosing a resolver with a small residual voltage, ensuring that the sine and cosine signals are handled identically and removing the reference phase shift (see the connecting the resolver section). by taking these precau- tions the extra error can be made insignificant. most resolvers exhibit a phase shift between the signal and the refe rence. this phase shift will, however, give rise under dynamic conditions to an additional error defined by: shaft speed ( rps ) phase shift ( degrees ) reference frequency = error degrees under static operating conditions phase shift between the refer- ence and the signal lines alone will not theoretically affect the converter s static accuracy. for example, for a phase shift of 20 degrees, a shaft rotation of 22 rps and a reference frequency of 5 khz, the converter will exhibit an additional error of: 22 20 5000 = 0.088 degrees this effect can be eliminated by placing a phase shift in the reference to the converter equivalent to the phase shift in the resolver (see the connecting the resolver section). note: capacitive and inductive crosstalk in the signal and reference leads and wiring can cause similar problems . velocity errors some ripple or noise will always be present in the velocity signal. velocity signal ripple is caused by, or related to, the following parameters. the resulting effects are generally addi- tive. this means diagnosis needs to be an iterative process in order to define the source of the error. 1.0 reference frequency a ripple content at the reference frequency is superimposed on the velocity signal output. the amplitude depends on the loop bandwidth. this error is a function of a dc offset at the input to phase sensitive demodulator (psd). 2.0 resolver inaccuracies impedance mismatch occur in the sine and cosine windings of the resolver. these give rise to differential phase shift between the sine and cosine inputs to the rdc and varia- tions in the resolver output amplitudes. 2.1 sine and cosine amplitude mismatch this is normally identified by the presence of asymmetrical ripple voltages. 2.2 differential phase s hift between the sine and cosine inputs the frequency of this ripple is usually twice the input veloc- ity, and the amplitude is proportional to the magnitude of the velocity signal. the phase shift is normally induced through the connections from the resolver to the converter. maintaining equal lengths of screened twisted pair cable from the resolver to the ad2s83 will reduce the effects of resistive imbalance, and therefore, reduce differential phase shift. 3.0 lsb update ripple lsb update noise occurs as the resolver rotates and the digital outputs of the rdc are updated. for a correctly scaled loop, this ripple component has a magnitude of approximately 2 mv peak at 16-bit resolution. 3.1 ripple due to the lsb rate given by: lsb rate = n reference frequency the psd generates sums and differences of all its compo- nent input frequencies, so when the lsb update rate is an multiple of the reference frequency, a beat frequency is generated. the magnitude of this ripple is a function of the lsb weighting, i.e., ripple is less at 16 bits. 4.0 torque ripple torque ripple is a phenomenon associated with motors. an ac motor naturally exhibits a sinusoidal back emf. in an ideal system the current fed to the motor should, in order to cancel, also be sinusoidal. in practice the current is often trapezoidal. consequently, the output torque from the motor will not be smooth and torque ripple is created. if the load- ing on a motor is constant, the velocity of the motor shaft will vary as a result of the cyclic variation of motor torque. the variation in velocity then appears on the velocity output as ripple. this is not an error but a true velocity variation in the system.
ad2s83 C17C rev. e offset errors the limiting factor in the measuring of low or creep speeds is the level of dc offset present at zero velocity. the zero velocity dc offset at the output of the ad2s83 is a function of the input bias current to the vco and the value for the input resistor r6. see circuit functions and dynamic performance vco. the offset can be minimized by reducing the maximum tracking rate so reducing the value for r6. offset is a function of tracking rate and therefore resolution; the dc offset is lowest at 16 bits. to increase the dynamic range of the velocity dynamic resolu- tion switching can be employed. (contact mcg applications for more information.) connecting the resolver the recommended connection circuit is shown in figure 11. in cases where the reference phase relative to the input signals from the resolver requires adjustment, this can be easily achieved by varying the value of the resistor r2 of the hf filter (see figure 1). assume that r1 = r2 = r and c1 = c2 = c and reference frequency = 1 2 rc . by altering the value of r2, the phase of the reference relative to the input signals will change in an approximately linear manner for phase shifts of up to 10 degrees. increasing r2 by 10% introduces a phase lag of two degrees. decreasing r2 by 10% introduces a phase lead of two degrees. r9 1m r8 4.7m r2 15k r4 130k r6 62k r5 200k r7 3.3k r3 100k c3 100nf 100nf c2 2.2nf c7 150pf c4 1.2nf c6 390pf c5 6.2nf 100nf velocity o/p 12v 0v cos low ref low cos high sin low sin high +12v reference input resolver signal msb +5v enable lsb byte select inhibit sc2 data load busy ripple clock complement direction note: r7, c6 and c7 should be connected as close as possible to the converter pins. signal screens should be connected to pin 5. 6543214443424140 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 ad2s83 top view (not to scale) data output data output r1 15k c1 2.2nf figure 11. typical circuit configuration c r phase lead = arc tan 1 2 frc r c phase lag = arc tan 2 frc phase shift circuits ' (023 ) typical circuit configuration figure 11 shows a typical circuit configuration for the ad2s83 with 12-bit resolution. values of the external components have been chosen for a reference frequency of 5 khz and a maximum tracking rate of 260 rps with a bandwidth of 520 hz. placing the values for r4, r6, c4, and c5 in the equation for k a gives a value of 1.65 10 6 . the resistors are 0.125 w, 5% tolerance preferred values. the capacitors are 100 v ceramic, 10% toler- ance components. for signal and reference voltages greater than 2 v rms a simple voltage divider circuit of resistors can be used to generate the correct signal level at the converter. care should be taken to ensure that the ratios of the resistors between the sine signal line and ground and the cosine signal line and ground are the same. any difference will result in an additional position error. for more information on resistive scaling of sin, cos, and reference converter inputs refer to the application note, circuit applications of the 2s81 and 2s80 resolver-to-digital converters.
ad2s83 rev. e C18C applications control transformer the ratio multiplier of the ad2s83 can be used independently of the loop integrators as a control transformer. in this mode, the resolver inputs are m ultiplied by a digital angle , any difference between and will be represented by the ac error output as sin t sin ( ) or the demod output as sin ( ). to use the ad2s83 in this mode refer to the control transformer application note. other product ad2s90 . low-cost resolver-to-digital converter with outputs which emulate optical encoders and a serial output for absolute position information. unlike the ad2s83, the ad2s90 requires no external components to operate. the ad2s90 is built on lc 2 mos and packaged in a 20-lead plcc. ad2s80a/ad2s81a/ad2s82a . monolithic resolver-to-digital converter. the ad2s80/ad2s82a offer selectable 10, 12, 14, 16 bits of resolution. the ad2s81a has 12-bit resolution. all devices have user s electable dynamics. the ad2s80a is available in 40-lead ddip, 44-lead lcc and is qualified to mil-std- 883b rev. e. the is available in a 44-lead plcc, and the ad2s81a in a 28-lead ddip.
ad2s83 C19C rev. e outline dimensions dimensions shown in inches and (mm). plastic leaded chip carrier (plcc) (p-44a) 6 pin 1 identifier 7 40 39 17 18 29 28 top view (pins down) 0.695 (17.65) 0.685 (17.40) sq 0.656 (16.66) 0.650 (16.51) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 0.020 (0.50) r 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) bsc 0.63 (16.00) 0.59 (14.99) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.040 (1.01) 0.025 (0.64) 0.025 (0.63) 0.015 (0.38) 0.110 (2.79) 0.085 (2.16) 0.056 (1.42) 0.042 (1.07) printed in u.s.a. c00006cC1.5C10/00 (rev. e)

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