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high-performance, low-power system on chip with sdram and improved digital audio interface 1 copyright ? cirrus logic, inc. 2000 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com overview features block diagram the maverick ? ep7312 is designed for ultra-low-power applications such as pdas, two-way pagers, smart cellular phones or any hand-held device that features the added capability of digital audio decompression. the core-logic functionality of the device is built around an arm720t processor with 8 kbytes of four-way set-associative uni- fied cache and a write buffer. incorporated into the arm720t is an enhanced memory management unit (mmu) which allows for support of sophisticated operat- ing systems like microsoft ? windows ce. the ep7312 also includes a 32-bit real-time clock and comparator. (continued on page 3) n arm720t processor arm7tdmi cpu 8 kbytes of four-way set-associative cache mmu with 64-entry tlb (translation look-aside buffer) write buffer thumb code support enabled n dynamically programmable clock speeds of 18, 36, 49, and 74 mhz at 2.5 v n maverickkey ? ids 32-bit unique sdmi id 128-bit random id n ultra low power designed for applications that require long battery life while using standard aa/aaa batteries or rechargeable cells typical power numbers l 90 mw at 74 mhz in the operating state l 30 mw at 18 mhz in the operating state l 10 mw in the idle state (clock to the cpu stopped, everything else running) l <1 mw in the standby state (real-time clock on, everything else stopped) ds508pp1 sep 00 32.768-khz oscillator pll interrupt controller power management sdram cntrl lcd controller arm7tdmi cpu core 8-kbyte cache mmu timer counters(2) arm720t internal data bus 3.6864 mhz 32.768 khz eint[1-3], fiq, medchg batok, extpwr pwrfl, batchg uart2 irda d[0-31] npor, run, reset, wakeup expclk, word, ncs[0-3], exprdy, write moe, mwe, sdclk, sdqm[0-1], sdras, sdcas a[0-27], dra[0-14] lcd drive led and photodiode async interface 2 internal address bus 13 - mhz input on-chip boot rom async interface 1 on-chip sram 48 kbytes cl-ps6700 intf pb[0-1], ncs[4-5] expansion cntrl uart1 epb bridge epb bus ice-jtag test and development write buffer state control memory controller lcd dma ssi1 (adc) pwm adcclk, adcin, adcout, smpclk, adccs ssiclk, ssitxfr, ssitxda, ssirxda, ssirsfr dc to dc ports a, b, d (8-bit) port e (3-bit) keybd drivers (0-7) gpio rtc flashing led drive codec ssi2 dai ep7312
2 ds 5 08pp1 ep7312 hi g h-performanc e system - on - chi p with s dra m an d digital au d io i n terface features (cont.) n advance d audio decoder / decompression c a p abi l ity a l low s fo r s upport of multi p le audio de c ompres s ion algorithms s u ppor t s mpeg 1, 2, and 2. 5 l ayer 3 audio d e coding, inclu d ing iso compliant mpeg 1 a nd 2 layer 3 s u pport for a ll s t andard s a mple rate s a nd bit rates s u ppor t s bit streams w i th adaptive b i t rates improved dai (dig i t al a u dio interface) provid i ng glue- less i nterf a ce to low-power dacs, adcs, and codecs n sdram controller s u ppor t s fo u r interna l mem o r y ban k s t o t a ling 2 56 m bi t s in si z e sdram me m o ry interface i s programma b le fr o m 4 to 3 2 bi t s wide. n lcd controller inter f a ces dire c tly to a sin g le-scan p a nel mon o chrome o r color stn lcd p a nel wi d t h siz e i s program m able fro m 3 2 to 10 2 4 pi x els in 16-pixe l increme n ts v ideo frame b u f fer size p ro g ra m mabl e up to 12 8 kb y tes b i t s per pixel of 1, 2, or 4 bi t s n memory controller de c odes up to 6 s e p a rate me m o ry seg m en t s of up to 256 mb y tes each e a ch seg m ent can be c onfigured a s 8 , 1 6 , o r 3 2 b i t s wi d e and supp o r t s p age-mod e a cce s s progra m mabl e a cce s s time for co n ventiona l rom / s ram / flash memory s u ppor t s remov a ble flash card i n t e rface e n ables connection to removabl e f l ash card for addi- tion of ex p a n sion flash memory modules n 48 kbytes (0x9600) of on-chip sram for fast pro- gram execution and / or as a fram e buffer n synchronous serial interface a dc ( ssi) inter f a ce: master mode only ; spi a and microwire1 a -co m p a tible (12 8 k bi t s/s op e rat i on) n on-chip rom; for manufacturing su p port n 27-bi t s of general-purpose i/o thr e e 8-bit and one 3-bit gpio port su p por t s sca n ning ke y board matrix n t wo u a r t s (16550 type) su p por t s bit rates up to 1 15.2 kbi t s/s con t a ins two 16-byte fifos for tx and rx ua r t1 su p por t s modem control s i gnals n sir (u p to 1 15 . 2 kb i t s/s infrared encoder / decoder i rd a (infrared da t a ass o ciation) sir protocol enco d er / decoder n dc - t o-dc converter interface (pwm) pro v ides two 9 6 khz c l ock outp u t s w i t h p ro g r a mmab l e duty ratio (fr o m 1-in-16 to 15-in-16) that can b e u sed to dr i ve a dc to dc converter n t wo ti m er c o unters n a vailable in 208- p in lqfp or 256-ball pbga p a c k ag e s n e v a l u a tion k i t a v a i l ab l e w i th bo m , s ch e m a t i c s , sample code, a n d desig n da t abase n support for up t o two ultra-low-power cl-ps6700 pc c ard c o ntrol l ers n dedicated le d flasher pin from th e r tc n full j t a g boundary scan and embedded ice a su p port n co m merc i a l and in d ustrial operatin g temperature range versions n the ep7312 i s optimized for low power d issi p ation and is fabricated on a fu l l y s t atic 0.2 5 m i cron cmos process. c o ntacting cirrus logic su p port for a co m p l et e list i ng of direct sales , distribu t or , and sale s represen t a t iv e contac t s, visit t h e c i rru s logic we b s i t e at: http:/ / www.c i rrus . com / corporate/contacts/sa l es . cfm p r e li m i na r y pro d uct i nf o rma t i o n desc r i bes p r oducts wh i ch are i n p ro d uct i on, b ut for w h i ch fu l l cha r acte r iz a t i on d a ta i s not yet availa b l e . a d vance p rod u ct info r - mat i o n d e scr i be s pr o ducts w h i ch a r e in d e ve l opm e nt a n d sub j ect to deve l o p ment cha n ges. c i r r us l og i c, i nc. h as m ad e best effo r t s to e n sure that the inf o r m a t i o n cont a i n ed i n th i s docu m ent i s accu r ate and r e l i ab l e. howeve r , the i nfo r mat i on i s su b j e ct to chan g e w i t h out n o t i ce and i s prov i d e d a s is witho u t w a rra n ty of a n y ki n d ( e x p r e ss o r i m p li ed ). n o re s p o n si b ility is a ss u m ed by c irr u s l o g ic, i n c. f o r th e u s e of t h is i n for m a t i o n , n or f o r i n f r i ng e me n ts of p a tents o r ot h er r i g hts of th i rd p a rt i es. th i s docu m ent i s the pr o perty of c i rr u s l og i c, inc. and i m p l i e s no l i ce n s e u nder p atents, co p yr i ghts, t r ade m a rks, or t r ade secr e ts. no pa r t of this publicati o n may be copie d , r epr o duce d , s t ored in a ret r ieval system, or t r ansmit t ed, in any form o r b y a ny mea n s ( e lectr o n i c, m echa n i c a l , p hoto g rap h i c, o r oth e rwise) witho u t the p r ior written conse n t of cirrus l o gic, inc. it e ms from any cirrus l ogic website or disk may be p rinted fo r use b y th e use r . however, n o pa r t o f t h e p r int o ut o r electr o nic f ile s m a y b e c o pied , re p r o d uced , sto r e d in a r etriev a l system , o r tra n smitted, in an y fo r m o r by any me a n s ( electr o nic, mech a nical, pho t ogr a ph i c, o r ot h erw i se ) wi t hout the p r i o r w r i tte n consent of c i r r us l o g i c, inc . fu r ther m or e , n o part of t h i s pub li cat i o n m a y be u sed a s a b a s i s fo r man u factu r e or sa l e of any i t ems w i t h out the pr i o r w r i t ten conse n t of c i rr u s l o g i c, i nc. t h e n ames of pr o ducts of c i r rus log i c, inc. or o t h e r vendo r s a nd supp l i e r s a p pea r i n g in t his d o cume n t may b e t rad e mark s or se r vice mark s of thei r res p ectiv e owne r s whic h ma y b e r e gister e d in some j u risdictions. a list of cirr u s l o gic, i nc. t r ad e - ma r ks an d service marks c a n be f ound at h t tp://www.cirr u s.com.
3 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface overview (cont.) power management the ep7312 is designed for ultra-low-power operation. its core operates at only 2.5 v, while its i/o has an operation range of 2.5 vC3.3 v. the device has three basic power states: operating this state is the full performance state. all the clocks and peripheral logic are enabled. idle this state is the same as the operating state, except the cpu clock is halted while waiting for an event such as a key press. standby this state is equivalent to the computer being switched off (no display), and the main oscilla- tor shut down. an event such as a key press can wake- up the processor. maverickkey ? unique id maverickkey unique hardware programmed ids are a solution to the growing concern over secure web content and commerce. with internet security playing an impor- tant role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. the maverickkey unique ids provide oems with a method of utilizing specific hardware ids such as those assigned for sdmi (secure digital music initiative) or any other authentication mechanism. both a specific 32-bit id as well as a 128-bit random id is programmed into the ep7312 through the use of laser probing technology. these ids can then be used to match secure copyrighted content with the id of the target device the ep7312 is powering, and then deliver the copyrighted information over a secure connection. in addition, secure transactions can benefit by also matching device ids to server ids. maverickkey ids provide a level of hardware security required for todays internet appliances. memory interfaces there are two main external memory interfaces. the first one is the rom / sram / flash-style interface that has programmable wait-state timings and includes burst-mode capability, with eight chip selects decoding six 256 mbyte sections of addressable space. for maximum flexibility, each bank can be specified to be 8-, 16-, or 32-bits wide. this allows the use of 8-bit-wide boot rom options to minimize overall system cost. the on-chip boot rom can be used in product manufacturing to serially download sys- tem code into system flash memory. to further mini- mize system memory requirements and cost, the arm thumb ? instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industry-leading code density. the second is the programmable 4- or 32-bit-wide sdram interface that allows direct connection of up to four internal banks of sdram, totaling 256 mbits. to assure the lowest possible power consumption, the ep7312 supports self-refresh drams, which are placed in a low- power state by the device when it enters the low-power standby state. a dma address generator is also provided that fetches video display data for the lcd controller from main sdram memory. the display frame buffer start address is programmable. in addition, the built-in lcd controller can utilize external or internal sram for memory, thus elimi- nating the need for sdrams. digital audio capability the ep7312 uses its powerful 32-bit risc processing engine to implement audio decompression algorithms in software. the nature of the on-board risc processor and the availability of efficient c-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the ep7312. serial interfaces the ep7312 includes two 16550-type uarts for rs-232 serial communications, both of which have two 16-byte fifos for receiving and transmitting data. the uarts support bit rates up to 115.2 kbits/s. an irda sir protocol encoder / decoder can be optionally switched into the rx / tx signals to / from one of the uarts to enable these sig- nals to drive an infrared communication interface directly. improved digital audio interface (dai) the ep7312 integrates an interface to enable a direct con- nection to many low cost, low power, high quality audio converters. in particular, the dai can directly interface with the crystal ? cs43l41 / 42 / 43 low-power audio dacs and the crystal ? cs53l32 low-power adc. some of these devices feature digital bass and treble boost, digi- tal volume control and compressor-limiter functions. packaging the ep7312 is available in a 208-pin lqfp package and a 256-ball pbga package. system design as shown in system block diagram, simply adding desired memory and peripherals to the highly integrated ep7312 completes a low-power system solution. all necessary interface logic is integrated on-chip .
4 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface overview (cont.) lcd keyboard battery dc-to-dc converters adc digitizer ir led and photodiode 2 rs-232 transceivers additional i/o cl-ps6700 pc card controller pc card socket ncs[4] pb0 expclk dd[0-3] cl1 cl2 frm m d[0-31] a[0-27] col[0-7] pa[0-7] dc input nmoe write pb[0-7] pd[0-7] pe[0-2] npor npwrfl batok nextpwr nbatchg run wakeup ncs[0] ncs[1] drive[0-1] fb[0-1] ep7312 adcclk nadccs adcout adcin smpclk leddrv phdin rxd1/2 txd1/2 dsr cts dcd cs[n] word ncs[2] ncs[3] 16 flash 16 flash 1 6 flash external memory- mapped expansion buffers buffers and latches 16 flash power supply unit and comparators crystal codec/ssi2/ dai ssiclk ssitxfr ssitxda ssirxda ssirxfr rtcin ledflsh figure 1. a maximum ep7312 based system note: a system can only use one of the following peripheral interfaces at any given time: ssi2, codec, or dai. crystal moscin 16 sdram 16 sdram 1 6 sdram 16 sdram sdcs[1] s dqm[0-3] sdcs[0] sdqm[0-3] sdras/ sdcas
5 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface table of contents power management ............................................................................................................. .... 3 maverickkey? unique id ....................................................................................................... .3 memory interfaces ............................................................................................................ ........ 3 digital audio capability ..................................................................................................... ....... 3 serial interfaces ............................................................................................................ ........... 3 improved digital audio interface (dai) ..................................................................................... 3 packaging .................................................................................................................... ............. 3 system design ................................................................................................................ ......... 3 1. conventions ............................................................................................................... ......... 6 1.1. acronyms and abbreviations .............................................................................................. 6 1.2. units of measurement .................................................................................................... ... 8 1.3. general conventions ...................................................................................................... .... 8 1.4. pin description conventions .............................................................................................. 8 2. electrical specifications ............................................................................................. 9 2.1. absolute maximum ratings ................................................................................................ 9 2.2. recommended operating conditions ................................................................................ 9 2.3. dc characteristics ....................................................................................................... ...... 9 2.4. ac characteristics ....................................................................................................... ..... 13 3. 208-pin lqfp package characteristics .................................................................. 22 3.1. 208-pin lqfp pin diagram .............................................................................................. 22 3.2. 208-pin lqfp package specifications ............................................................................ 23 3.3. 208-pin lqfp numeric pin listing ................................................................................... 24 3.4. jtag boundary scan signal ordering for 208-pin lqfp ................................................ 27 4. 256-pin pbga package characteristics .................................................................. 29 4.1. 256-pin pbga pin diagram ............................................................................................. 29 4.2. ep7312 256-ball pbga (17 17 1.61-mm body) dimensions .................................... 30 4.3. 256-ball pbga ball listing ............................................................................................... 31 5. ordering information ................................................................................................... 34 6. index ..................................................................................................................... ................. 35 list of figures figure 1. a maximum ep7312 based system ............................................................................... 4 figure 2. consecutive memory read cycles with minimum wait states ..................................... 15 figure 3. sequential page mode read cycles with minimum wait states .................................. 16 figure 4. consecutive memory write cycles with minimum wait states ..................................... 17 figure 5. sdram read cycles sdcas latency = 2 ................................................................... 18 figure 6. sdram read cycles sdcas latency = 3 ................................................................... 19 figure 7. sdram write cycles .................................................................................................. .. 19 figure 8. sdram refresh cycles ................................................................................................ 20 figure 9. lcd controller timings .............................................................................................. ... 20 figure 10. ssi1 interface for ad7811/2 ....................................................................................... 2 1 figure 11. ssi2 interface timings ............................................................................................. ... 21 figure 12. 208-pin lqfp (low profile quad flat pack) pin diagram .......................................... 22 figure 13. 208-pin lqfp package outline drawing .................................................................... 23 figure 14. 256-ball plastic ball grid array diagram ..................................................................... 29 figure 15. 256-ball pin diagram ............................................................................................... ... 29 figure 16. 256-ball pbga package drawing ............................................................................... 30
6 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface list of tables table 1. acronyms and abbreviations ........................................................................................... 7 table 2. unit of measurement .................................................................................................. ...... 8 table 3. pin description conventions .......................................................................................... .. 8 table 4. absolute maximum ratings ............................................................................................. 9 table 5. recommended operating conditions .............................................................................. 9 table 6. dc characteristics ................................................................................................... ........ 9 table 7. ac timing characteristics ............................................................................................ .. 13 table 8. 208-pin lqfp numeric pin listing ................................................................................ 24 table 9. jtag boundary scan signal ordering for 208-pin lqfp package .............................. 27 table 10. 256-ball pbga ball listing .......................................................................................... .31
7 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 1. conventions this section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet. 1.1. acronyms and abbreviations table 1 lists abbreviations and acronyms used in this data sheet. acronym/ abbreviation definition a/d analog-to-digital adc analog-to-digital converter cmos complementary metal oxide semi- conductor codec coder / decoder d/a digital-to-analog dma direct-memory access epb embedded peripheral bus fcs frame check sequence fifo first in / first out fiq fast interrupt request gpio general purpose i/o ict in circuit test ir infrared irq standard interrupt request table 1. acronyms and abbreviations irda infrared data association jtag joint test action group lcd liquid crystal display led light-emitting diode lqfp low profile quad flat pack lsb least significant bit mips millions of instructions per second mmu memory management unit msb most significant bit pbga plastic ball grid array pcb printed circuit board pda personal digital assistant pia peripheral interface adapter pll phase locked loop psu power supply unit p/u pull-up resistor risc reduced instruction set computer rtc real-time clock sir slow (9600C115.2 kbps) infrared sram static random access memory ssi synchronous serial interface tap test access port tlb translation lookaside buffer uart universal asynchronous receiver acronym/ abbreviation definition table 1. acronyms and abbreviations (cont.)
8 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 1.2. units of measurement 1.3. general conventions hexadecimal numbers are presented with all letters in uppercase and a lowercase h appended or with a 0x at the beginning. for example, 0x14 and 03cah are hexadecimal numbers. binary numbers are enclosed in single quotation marks when in text (for example, 11 designates a binary number). numbers not indicated by an h, 0x or quotation marks are decimal. registers are referred to by acronym, with bits list- ed in brackets separated by a hyphen (-) (for exam- ple, codr[0-7]), and are described in the ep7312 users manual , the use of tbd indicates values that are to be determined, n/a designates not available, and n/c indicates a pin that is a no connect. 1.4. pin description conventions abbreviations used for signal directions are listed in table 3 . symbol unit of measure c degree celsius fs sample frequency hz hertz (cycle per second) kbits/s kilobits per second kbyte kilobyte (1,024 bytes) khz kilohertz k w kilohm mbits/s megabits (1,048,576 bits) per second mbyte megabyte (1,048,576 bytes) mbyte/s megabytes per second mhz megahertz (1,000 kilohertz) m a microampere m fmicrofarad m wmicrowatt m s microsecond (1,000 nanoseconds) ma milliampere mw milliwatt ms millisecond (1,000 microseconds) ns nanosecond vvolt wwatt table 2. unit of measurement abbreviation direction i input o output i/o input or output table 3. pin description conventions
9 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 2. electrical specifications 2.1. absolute maximum ratings 2.2. recommended operating conditions 2.3. dc characteristics all characteristics are specified at v dd = 2.5 volts and v ss = 0 volts over an operating temperature of 0c to +70c for all frequencies of operation. the current consumption figures relate to typical condi- tions at 2.5 v, 18.432 mhz operation with the pll switched on. dc core, pll, and rtc supply voltage 2.9 v dc i/o supply voltage (pad ring) 3.6 v dc pad input current 10 ma/pin; 100 ma cumulative storage temperature, no power C40 c to +125 c table 4. absolute maximum ratings dc core, pll, and rtc supply voltage 2.5 v 0.2 v dc i/o supply voltage (pad ring) 2.3v - 3.6v dc input / output voltage oCi/o supply voltage operating temperature extended -20 c to +70 c; commercial 0 c to +70 c; industrial -40 c to +85 c table 5. recommended operating conditions symbol parameter min typ max unit conditions vih cmos input high voltage 1.7 v dd + 0.3 v v dd = 2.5 v vil cmos input low voltage -0.3 0.8 v v dd = 2.5 v vt+ schmitt trigger positive going thresh- old 1.6 (typ) 2.0 v vt- schmitt trigger negative going threshold 0.8 1.2 (typ) v vhst schmitt trigger hysteresis 0.1 0.4 v vil to vih voh cmos output high voltage output drive 1 output drive 2 v dd C 0.2 2.5 2.5 v v v ioh = 0.1 ma ioh = 4 ma ioh = 12 ma vol cmos output low voltage output drive 1 output drive 2 0.3 0.5 0.5 v v v iol = C0.1 ma iol = C4 ma iol = C12 ma iin input leakage current 1 1.0 a vin = v dd or gnd ioz output three-state leakage current 2 3 25 100 a vout = v dd or gnd cin input capacitance 8 10.0 pf table 6. dc characteristics
10 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface cout output capacitance 8 10.0 pf ci/o transceiver capacitance 8 10.0 pf idd startup startup current consumption 15.0 a initial 100 ms from power up, cache dis- abled, 32 khz oscillator not stable, por signal at vil, all other i/o static, vih = v dd 0.1 v, vil = gnd 0.1 v idd standby standby current consumption core, osc, rtc @2.5v i/o @ 2.5v core, osc, rtc @2.5v i/o @ 3.3v de-rat- ing curves to be added de-rat- ing curves to be added a just 32 khz oscillator running, cache dis- abled, all other i/o static, vih = v dd 0.1 v, vil = gnd 0.1 v idd idle idle current consumption at 13 mhz core, osc, rtc @2.5v i/o @ 2.5v core, osc, rtc @2.5v i/o @ 3.3v at 18 mhz core, osc, rtc @2.5v i/o @ 2.5v core, osc, rtc @2.5v i/o @ 3.3v at 36 mhz core, osc, rtc @2.5v i/o @ 2.5v core, osc, rtc @2.5v i/o @ 3.3 tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 4.2 6.0 12.0 ma both oscillators run- ning, cpu static, cache disabled, lcd refresh active, vih = v dd 0.1 v, vil = gnd 0.1 v symbol parameter min typ max unit conditions table 6. dc characteristics (cont.)
11 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface idd operatin operating current consumption at 13 mhz core, osc, rtc @2.5v i/o @ 2.5v core, osc, rtc @2.5v i/o @ 3.3v at 18 mhz core, osc, rtc @2.5v i/o @ 2.5v core, osc, rtc @2.5v i/o @ 3.3v at 36 mhz core, osc, rtc @2.5v i/o @ 2.5v core, osc, rtc @2.5v i/o @ 3.3v at 49 mhz core, osc, rtc @2.5v i/o @ 2.5v core, osc, rtc @2.5v i/o @ 3.3v at 74 mhz core, osc, rtc @2.5v i/o @ 2.5v core, osc, rtc @2.5v i/o @ 3.3v tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd tbd 14 30 40 50 68 ma all system active, run- ning typical program, cache disabled, and lcd inactive symbol parameter min typ max unit conditions table 6. dc characteristics (cont.)
12 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface notes: 1) all power dissipation values can be derived from taking the particular idd current and multiplying by 2.5 v. 2) the rtc of the ep7312 should be brought up at room temperature. this is required because the rtc osc will not function properly if it is brought up at C40 c. once operational, it will continue to oper- ate down to C20 c extended and 0 c commercial. 3) a typical design will provide 3.3 v to the i/o supply (i.e., v dd io), and 2.5 v to the remaining logic. this is to allow the i/o to be compatible with 3.3 v powered external logic (i.e., 3.3 v drams). 4) pull-up current = 50 a typical at v dd = 3.3 volts. v ddstandby standby supply voltage tbd v minimum standby volt- age for state retention and rtc operation only 1 the leakage value given assumes that the pin is configured as an input pin but is not currently being driven. an input pin not driven will have a maximum leakage of 1 a. when the pin is driven, there will be no leakage. 2 assumes buffer has no pull-up or pull-down resistors. 3 the leakage value given assumes that the pin is configured as an output pin but is not currently being driven. an output pin not driven will have leakage between 25 a and 100 a. when the pin is driven, there will be no leakage. note that this applies to all output pins and all i/o pins configured as outputs. symbol parameter min typ max unit conditions table 6. dc characteristics (cont.)
13 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 2.4. ac characteristics all characteristics are specified at v dd = 2.3 to 2.7 volts and v ss = 0 volts over an operating tem- perature of 0 c to +70 c. those characteristics marked with a # will be significantly different for 13 mhz mode because the expclk is provided as an input rather than generated internally. these timings are estimated at present. the timing values are referenced to 1/2 v dd . symbol parameter 13 mhz 18/36 mhz units min max min max t1 falling cs to data bus hi-z 0 35 0 25 ns t2 address change to valid write data 0 45 0 35 ns t3 data in to falling expclk setup time 0 # 18ns t4 data in to falling expclk hold time 10 # 0 ns t5 exprdy to falling expclk setup time 0 # 18 ns t6 falling expclk to exprdy hold time 10 # 50 0 50 ns t7 rising nmwe to data invalid hold time 10 5 ns t8 sequential data valid to falling nmwe setup time C10 10 C10 10 ns t9 row address to falling nsdras setup time tbd - tbd - ns t10 falling nsdras to row address hold time tbd - tbd - ns t11 column address to falling nsdcas setup time tbd - tbd - ns t12 falling nsdcas to column address hold time tbd - tbd - ns t13 write data valid to falling nsdcas setup time tbd - tbd - ns t14 write data valid from falling nsdcas hold time tbd - tbd - ns t15 lcd cl2 low time 80 3,475 80 3,475 ns t16 lcd cl2 high time 80 3,475 80 3,475 ns t17 lcd falling cl[2] to rising cl[1] delay 0 25 0 25 ns t18 lcd falling cl[1] to rising cl[2] 80 3,475 80 3,475 ns t19 lcd cl[1] high time 80 3,475 80 3,475 ns t20 lcd falling cl[1] to falling cl[2] 200 6,950 200 6,950 ns t21 lcd falling cl[1] to frm toggle 300 10,425 300 10,425 ns t22 lcd falling cl[1] to m toggle C10 20 C10 20 ns t23 lcd rising cl[2] to display data change C10 20 C10 20 ns t24 falling expclk to address valid 33 # 5 ns table 7. ac timing characteristics
14 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface notes: all sdram 36 mhz timings are for sdram operation. the values for 36 mhz include 1 wait state, and the 18 mhz values have 0 wait states. t25 data valid to falling nmwe for non sequential access only 5 5ns t31 ssiclk period (slave mode) 0 512 0 512 khz t32 ssiclk high 925 1025 925 1025 ns t33 ssiclk low 925 1025 925 1025 ns t34 ssiclk rise / fall time 7 7 ns t35 ssiclk rising to rx and / or tx frame sync 528 528 ns t36 ssiclk rising edge to frame sync low 448 448 ns t37 ssiclk rising edge to tx data valid 80 80 ns t38 ssirxda data set-up time 30 30 ns t39 ssirxda data hold time 40 40 ns t40 ssitxfr and / or ssirxfr period 750 750 ns t ncsrd negative strobe (ncs[0-5]) zero wait state read access time tbd tbd tbd t ncswr negative strobe (ncs[0-5]) zero wait state write access time tbd tbd tbd t exbst sequential expansion burst mode read access time tbd tbd tbd t rc sdram cycle time tbd - tbd - tbd t rac access time from sdras tbd - tbd - tbd t rp sdras precharge time tbd - tbd - tbd t cas sdcas pulse width tbd - tbd - tbd t cp sdcas precharge in page mode tbd - tbd - tbd t pc page mode cycle time tbd - tbd - tbd t csr sdcas set-up time for auto refresh tbd - tbd - tbd t ras sdras pulse width tbd - tbd - tbd symbol parameter 13 mhz 18/36 mhz units min max min max table 7. ac timing characteristics (cont.)
15 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface tncsrd t3 tpcsrd t4 t3 tadrd t4 t5 t6 t1 data in bus held data in expclk ncs[5:0] nmoe a[27:0] word d[31:0] exprdy figure 2. consecutive memory read cycles with minimum wait states notes: 1) tncsrd = 50 ns at 36.864 mhz 70 ns at 18.432 mhz 120 ns at 13.0 mhz maximum values for minimum wait states. this time can be extended by integer multiples of the clock period (27 ns at 36 mhz, 54 ns at 18.432 mhz, and 77 ns at 13 mhz), by either driving exprdy low and/or by programming a number of wait states. exprdy is sampled on the falling edge of expclk before the data transfer. if low at this point, the transfer is delayed by one clock period where exprdy is sampled again. expclk need not be referenced when driving exprdy, but is shown for clarity. 2) consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential rom/expansion cycles. this improves perfor- mance so the sqaen bit should always be set where possible. 3) tncsrd = tadrd = tpcsrd 4) when the ep7312 device implements consecutive reads(e.g., use of the ldm instruction), regardless of the state of the sqaen bit, the signals nmoe and ncsx will always remain low through the entire multi-read access. they will not toggle in-between each different address access. in order to have these signals toggle, single access read instructions (e.g., ldr) must be used.
16 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface figure 3. sequential page mode read cycles with minimum wait states notes: 1) texbst = 35 ns at 36.864 mhz 35 ns at 18.432 mhz 55 ns at 13.0 mhz (value for 36.864 mhz assumes 1 wait state.) maximum values for minimum wait states. this time can be extended by integer multiples of the clock period (27 nsec at 36 mhz, 54 nsec at 18.432 mhz and 77 ns at 13 mhz), by either driving exprdy low and/or by programming a number of wait states. exprdy is sampled on the falling edge of expclk before the data transfer. if low at this point, the transfer is delayed by one clock period where exprdy is sampled again. expclk need not be referenced when driving exprdy, but is shown for clarity. 2) consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential rom/expansion cycles. this improves perfor- mance so the sqaen bit should always be set where possible. texbst texbst t3 texrd t4 t3 t4 t3 t4 t5 t6 t1 data in bus held data in data in 048 expclk ncs[5:0] nmoe a[27:4] a [ 3:0 ] word d[31:0] exprdy
17 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface tncswr tadwr t5 t6 t2 t7 t2 bus held write data write data expclk ncs[5:0] nmwe a[27:0] word d[31:0] n exprdy t8 figure 4. consecutive memory write cycles with minimum wait states notes: 1) tncswr = 35 nsec at 36.864 mhz 70 ns at 18.432 mhz 120 ns at 13.0 mhz maximum values for minimum wait states. this time can be extended by integer multiples of the clock period (27 nsec at 36 mhz, 54 nsec at 18.432 mhz, and 77 nsec at 13 mhz), by either driving exprdy low and/or by programming a number of wait states. exprdy is sampled on the falling edge of expclk before the data transfer. if low at this point, the transfer is delayed by one clock period where exprdy is sampled again. expclk need not be referenced when driving exprdy, but is shown for clarity. 2) consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential rom/expansion cycles. this improves perfor- mance so the sqaen bit should always be set where possible. 3) zero wait states for sequential writes is not permitted for memory devices which use nmwe pin, as this cannot be driven with valid timing under zero wait state conditions.
18 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface t1 t2 t3 t4 t5 t6 t7 t8 t9 clk nras / ncas / nwe nop act nop t0 read nop nop nop nop nop nop (act) cke ncs 1 dev 1 dev dqm dq di1 bank sel a10 ( p rech sel) addr cas lat 2 trcd trp tras trc auto precharge row col row bank bank nop t10 di2 di0 di3 figure 5. sdram read cycles sdcas latency = 2 notes: 1. trcd (delay time act to read/write command) = 30 ns or 2 cycles at 36 mhz. 2. trp (pre to act command period) = 30 ns or 2 cycles at 36 mhz. 3. tras (act to pre command period) = 60 ns or 3 cycles at 36 mhz. 4. trc (act to ref/act command period [operation]) = 90 ns or 4 cycles at 36 mhz. 5. for sdcas latency 3, there will be an extra cycle between t4 and t5.
19 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface t1 t2 t3 t4 t6 t7 t8 t9 t10 clk nras / ncas / nwe nop act nop t0 read nop nop nop nop nop nop (act) cke ncs 1 dev 1 dev dqm dq di0 di1 di2 di3 bank sel a10 (prech sel) addr cas lat 3 trcd trp tras trc auto precharge row col row bank bank nop t5 nop t11 figure 6. sdram read cycles sdcas latency = 3 t1 t2 t3 t4 t5 t6 t7 clk nras / ncas / nwe nop act nop t0 write nop nop nop nop nop cke ncs 1 dev 1 dev dqm dq bank sel a10 (prech sel) addr trcd trp tras trc tdpl do0 do1 do2 do3 (act) row col row bank bank auto precharge figure 7. sdram write cycles note: tdpl (data in to pre command period command) = 10 ns or 1 cycle at 36 mhz.
20 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface t1 t2 t3 t4 clk nras / ncas / nwe nop ref nop t0 nop nop (act) cke ncs all dqm dq bank sel a10 (prech sel) addr trp trc1 auto precharge figure 8. sdram refresh cycles note: trc1 (ref to ref/act command period [refresh]) = 90 ns or 4 cycles at 36 mhz. t15 t20 t16 t18 t19 t21 t17 t22 t23 cl[2] cl[1] frm m dd[3:0] figure 9. lcd controller timings notes: 1) the figure shows the end of a line. 2) if frm is high during the cl[1] pulse, this marks the first line in the display. 3) cl[2] low time is doubled during the cl[1] high pulse.
21 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 1 6 2 3 4 5 7 8 9 10 14 13 12 11 15 22 23 di5 di4 di3 di2 di1 di0 do1 do0 do9 do8 di9 di8 di7 di6 adcclk nadccs adcin adcout (sclk) (nrfs/tfs) (din) (dout) figure 10. ssi1 interface for ad7811/2 ssiclk ssi rx/txfr ssitxda ssirxda t31 t33 t32 t35 t37 t38 t39 t40 t36 d7 d2 d1 d0 d7 d2 d1 d0 figure 11. ssi2 interface timings
22 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 3. 208-pin lqfp package characteristics 3.1. 208-pin lqfp pin diagram 160 159 158 157 53 54 55 56 57 58 59 60 61 62 63 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 106 107 108 109 110 112 113 114 115 116 117 118 119 120 121 64 65 67 68 69 70 71 72 73 74 75 66 98 99 100 101 102 103 104 122 124 125 126 127 128 129 130 105 131 132 133 134 156 155 154 153 152 151 150 149 148 147 146 145 144 143 140 139 138 137 136 141 142 135 161 162 163 164 165 166 167 168 169 170 171 172 173 174 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 201 202 203 204 205 206 207 208 200 175 176 177 178 179 123 111 ep7312 208-pin lqfp (top view) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 51 50 52 1 nextpwr batok npor vssosc vddosc moscin moscout nureset wakeup a[6] d[6] a[5] d[5] vddio vssio a[4] d[4] a[3] d[3] npwrfl a[2] d[2] a[1] a[0] d[0] vddcore vssio vddio cl[2] cl[1] frm m dd[2] dd[1] dd[0] nsdcs[1] sdqm[3] sdqm[2] vddio vssio sdclk nmwe/nsdwe nmoe/nsdcas ncs[0] ncs[1] ncs[2] ncs[3] d[7] a[7] d[8] a[8] d[9] d[10] a[10] vssio vddio a[11] d[12] a[12] d[13] a[13]\dra[14] d[14] dd[3] d[17] d[15] a[17] /dra[10] ntrst vssio vddio d[18] a[18 /dra[9] d[19] a[19] /dra[8] d[20] vssio a[21] /dra[6] d[22] d[23] a[23] /dra[4] d[24] vssio vddio a[24] /dra[3] halfword a[14]/dra[13] nbatchg a[25]/dra[2] d[25] d[27] a[27]/dra[0] vssio d[28] d[29] d[30] d[31] buz col[0] col[1] tclk vddio col[2] col[3] col[4] col[5] col[6] col[7] fb[0] vssio fb[1] adcout adcclk drive[0] vddio pd[2] vssio vsscore nadccs adcin ssirxda ssirxfr ssitxda ssitxfr vssio ssiclk pd[0]/ledflsh pd[1] pd[3] a[22] /dra[5] pd[4] vddio pd[5] pd[6]/sdqm[0] drive[1] pd[7]/sdqm[1] d[26] a[15] /dra[12] d[16] a[16] /dra[11] ncs[4] vddcore a[26]/dra[1] d[21] tms a[20] /dra[7] smpclk d[11] a[9] d[1] vsscore nsdcs[0 ] sdcke vssio vssio vssio vssio expclk word write/nsdras run/clken exprdy pb[7] pb[6] pb[5] pb[4] pb[3] pb[2] pb[1]/prdy[2] vssio tdi vddio tdo pe[2]/clksel nextfiq pa[6] pa[5] pa[4] pa[3] pa[2] pa[1] pa[0] leddrv txd[2] phdin cts rxd[2] dcd dsr rtcout rtcin vssio pa[7] vddio vssio ncs[5] pb[0]/prdy[1] txd[1] rxd[1] ntest[1] ntest[0] eint[3] neint[2] neint[1] pe[1]bootsel[1] pe[0]bootsel[0] n/c vssrtc vddrtc figure 12. 208-pin lqfp (low profile quad flat pack) pin diagram notes: 1. n/c should not be grounded but left as no connects. 2. pin differences between the ep7212 and the ep7312 are bolded. nmedchg/nbrom
23 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 3.2. 208-pin lqfp package specifications pin 1 indicator 29.60 (1.165) 30.40 (1.197) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) 0.50 (0.0197) bsc 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 1.35 (0.053) 1.45 (0.057) 0 min 7 max 0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 0.45 (0.018) 0.75 (0.030) 0.05 (0.002) 1.00 (0.039) bsc pin 1 pin 208 1.60 (0.063) 0.15 (0.006) ep7312 208-pin lqfp notes: 1) dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) drawing above does not reflect exact package pin count. 3) before beginning any new design with this device, please contact cirrus logic for the latest package information. 4) for pin locations, please see figure 12 . for pin descriptions see the ep7312 users manual . figure 13. 208-pin lqfp package outline drawing
24 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 3.3. 208-pin lqfp numeric pin listing pin no. signal type strength reset state 1ncs[5] out 1 high 2 vddio pad pwr 3vssiopad gnd 4 expclk i/o 1 5 word out 1 low 6write/ nsdras out 1 low 7 run/clken o 1 low 8 exprdy in 1 9 txd[2] out 1 high 10 rxd[2] in 11 tdi in with p/u* 12 vssio pad gnd 13 pb[7] i/o 1 input 14 pb[6] i/o 1 input 15 pb[5] i/o 1 input 16 pb[4] i/o 1 input 17 pb[3] i/o 1 input 18 pb[2] i/o 1 input 19 pb[1]/ prdy2 i/o 1 input 20 pb[0]/ prdy1 i/o 1 input 21 vddio pad pwr 22 tdo out 1 three state 23 pa[7] i/o 1 input 24 pa[6] i/o 1 input 25 pa[5] i/o 1 input 26 pa[4] i/o 1 input 27 pa[3] i/o 1 input 28 pa[2] i/o 1 input 29 pa[1] i/o 1 input 30 pa[0] i/o 1 input 31 leddrv out 1 low 32 txd[1] out 1 high 33 vssio pad gnd 1 high 34 phdin in 35 cts in table 8. 208-pin lqfp numeric pin listing 36 rxd[1] in 37 dcd in 38 dsr in 39 ntest[1] in with p/u* 40 ntest[0] in with p/u* 41 eint[3] in 42 neint[2] in 43 neint[1] in 44 nextfiq in 45 pe[2]/ clksel i/o 1 input 46 pe[1]/ bootsel[1] i/o 1 input 47 pe[0]/ bootsel[0] i/o 1 input 48 vssrtc rtc gnd 49 rtcout out 50 rtcin in 51 vddrtc rtc power 52 n/c 53 pd[7]/ sdqm[1] i/o 1 low 54 pd[6]/ sdqm[0] i/o 1 low 55 pd[5] i/o 1 low 56 pd[4] i/o 1 low 57 vddio pad pwr 58 tms in with p/u* 59 pd[3] i/o 1 low 60 pd[2] i/o 1 low 61 pd[1] i/o 1 low 62 pd[0]/ ledflsh i/o 1 low 63 ssiclk i/o 1 input 64 vssio pad gnd 65 ssitxfr i/o 1 low 66 ssitxda out 1 low 67 ssirxda in 68 ssirxfr i/o input 69 adcin in 70 nadccs out 1 high pin no. signal type strength reset state table 8. 208-pin lqfp numeric pin listing (cont.)
25 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 71 vsscore core gnd 72 vddcore core pwr 73 vssio pad gnd 74 vddio pad pwr 75 drive[1] i/o 2 high / low 76 drive[0] i/o 2 high / low 77 adcclk out 1 low 78 adcout out 1 low 79 smpclk out 1 low 80 fb[1] in 81 vssio pad gnd 82 fb[0] in 83 col[7] out 1 high 84 col[6] out 1 high 85 col[5] out 1 high 86 col[4] out 1 high 87 col[3] out 1 high 88 col[2] out 1 high 89 vddio pad pwr 90 tclk in 91 col[1] out 1 high 92 col[0] out 1 high 93 buz out 1 low 94 d[31] i/o 1 low 95 d[30] i/o 1 low 96 d[29] i/o 1 low 97 d[28] i/o 1 low 98 vssio pad gnd 99 a[27]/dra[0] out 2 low 100 d[27] i/o 1 low 101 a[26]/dra[1] out 2 low 102 d[26] i/o 1 low 103 a[25]/dra[2] out 2 low 104 d[25] i/o 1 low 105 halfword out 1 low 106 a[24]/dra[3] out 1 low 107 vddio pad pwr 108 vssio pad gnd pin no. signal type strength reset state table 8. 208-pin lqfp numeric pin listing (cont.) 109 d[24] i/o 1 low 110 a[23]/dra[4] out 1 low 111 d[23] i/o 1 low 112 a[22]/dra[5] out 1 low 113 d[22] i/o 1 low 114 a[21]/dra[6] out 1 low 115 d[21] i/o 1 low 116 vssio pad gnd 117 a[20]/dra[7] out 1 low 118 d[20] i/o 1 low 119 a[19]/dra[8] out 1 low 120 d[19] i/o 1 low 121 a[18]/dra[9] out 1 low 122 d[18] i/o 1 low 123 vddio pad pwr 124 vssio pad gnd 125 ntrst in 126 a[17]/ dra[10] out 1 low 127 d[17] i/o 1 low 128 a[16]/ dra[11] out 1 low 129 d[16] i/o 1 low 130 a[15]/ dra[12] out 1 low 131 d[15] i/o 1 low 132 a[14]/ dra[13] out 1 low 133 d[14] i/o 1 low 134 a[13]/ dra[14] out 1 low 135 d[13] i/o 1 low 136 a[12] out 1 low 137 d[12] i/o 1 low 138 a[11] out 1 low 139 vddio pad pwr 140 vssio pad gnd 141 d[11] i/o 1 low 142 a[10] out 1 low 143 d[10] i/o 1 low 144 a[9] out 1 low 145 d[9] i/o 1 low 146 a[8] out 1 low 147 d[8] i/o 1 low 148 a[7] out 1 low pin no. signal type strength reset state table 8. 208-pin lqfp numeric pin listing (cont.)
26 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 149 vssio pad gnd 150 d[7] i/o 1 low 151 nbatchg in 152 nextpwr in 153 batok in 154 npor in schmitt 155 nmedchg/ nbrom in 156 nureset in schmitt 157 vddosc osc pwr 158 moscin osc 159 moscout osc 160 vssosc osc gnd 161 wakeup in schmitt 162 npwrfl in 163 a[6] out 1 low 164 d[6] i/o 1 low 165 a[5] out 1 low 166 d[5] i/o 1 low 167 vddio pad pwr 168 vssio pad gnd 169 a[4] out 1 low 170 d[4] i/o 1 low 171 a[3] out 2 low 172 d[3] i/o 1 low 173 a[2] out 2 low 174 vssio pad gnd 175 d[2] i/o 1 low 176 a[1] out 2 low 177 d[1] i/o 1 low 178 a[0] out 2 low 179 d[0] i/o 1 low 180 vss core core gnd 181 vdd core core pwr 182 vssio pad gnd 183 vddio pad pwr 184 cl[2] out 1 low 185 cl[1] out 1 low 186 frm out 1 low 187 m out 1 low pin no. signal type strength reset state table 8. 208-pin lqfp numeric pin listing (cont.) 188 dd[3] i/o 1 low 189 dd[2] i/o 1 low 190 vssio pad gnd 191 dd[1] i/o 1 low 192 dd[0] i/o 1 low 193 nsdcs[1] out 1 high 194 nsdcs[0] out 1 high 195 sdqm[3] i/o 2 low 196 sdqm[2] i/o 2 low 197 vddio pad pwr 198 vssio pad gnd 199 sdcke i/o 2 low 200 sdclk i/o 2 low 201 nmwe/nsdwe out 1 high 202 nmoe/ nsd- cas out 1 high 203 vssio pad gnd 204 ncs[0] out 1 high 205 ncs[1] out 1 high 206 ncs[2] out 1 high 207 ncs[3] out 1 high 208 ncs[4] out 1 high note: with p/u means with internal pull-up on the pin. pin no. signal type strength reset state table 8. 208-pin lqfp numeric pin listing (cont.)
27 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 3.4. jtag boundary scan signal ordering for 208-pin lqfp pin no. signal type position 1ncs[5]out1 4 expclk i/o 3 5wordout6 6writeout8 7 run/clken o 10 8 exprdy i 13 9 txd2 out 14 10 rxd2 in 16 13 pb[7] i/o 17 14 pb[6] i/o 20 15 pb[5] i/o 23 16 pb[4] i/o 26 17 pb[3] i/o 29 18 pb[2] i/o 32 19 pb[1]/prdy2 i/o 35 20 pb[0]/prdy1 i/o 38 23 pa[7] i/o 41 24 pa[6] i/o 44 25 pa[5] i/o 47 26 pa[4] i/o 50 27 pa[3] i/o 53 28 pa[2] i/o 56 29 pa[1] i/o 59 30 pa[0] i/o 62 31 leddrv out 65 32 txd1 out 67 34 phdin in 69 35 cts in 70 36 rxd1 in 71 37 dcd in 72 38 dsr in 73 39 ntest1 in 74 40 ntest0 in 75 41 eint3 in 76 42 neint2 in 77 43 neint1 in 78 44 nextfiq in 79 45 pe[2]/clksel i/o 80 46 pe[1]/bootsel1 i/o 83 47 pe[0]/bootsel0 i/o 86 table 9. jtag boundary scan signal ordering for 208- pin lqfp package 53 pd[7] i/o 89 54 pd[6] i/o 92 55 pd[5] i/o 95 56 pd[4] i/o 98 59 pd[3] i/o 101 60 pd[2] i/o 104 61 pd[1] i/o 107 62 pd[0]/ledflsh o 110 68 ssirxfr i/o 122 69 adcin in 125 70 nadccs out 126 75 drive1 i/o 128 76 drive0 i/o 131 77 adcclk out 134 78 adcout out 136 79 smpclk out 138 80 fb1 in 140 82 fb0 in 141 83 col7 out 142 84 col6 out 144 85 col5 out 146 86 col4 out 148 87 col3 out 150 88 col2 out 152 91 col1 out 154 92 col0 out 156 93 buz out 158 94 d[31] i/o 160 95 d[30] i/o 163 96 d[29] i/o 166 97 d[28] i/o 169 99 a[27]/dra[0] out 172 100 d[27] i/o 174 101 a[26]/dra[1] out 177 102 d[26] i/o 179 103 a[25]/dra[2] out 182 104 d[25] i/o 184 105 halfword out 187 106 a[24]/dra[3] out 189 109 d[24] i/o 191 110 a[23]/dra[4] out 194 111 d[23] i/o 196 112 a[22]/dra[5] out 199 113 d[22] i/o 201 pin no. signal type position table 9. jtag boundary scan signal ordering for 208- pin lqfp package (cont.)
28 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface notes: 1) see ep7312 users manual for pin naming / functionality. 2) for each pad, the jtag connection ordering is input, output, then enable as applicable. 114 a[21]/dra[6] out 204 115 d[21] i/o 206 117 a[20]/dra[7] out 209 118 d[20] i/o 211 119 a[19]/dra[8] out 214 120 d[19] i/o 216 121 a[18]/dra[9] out 219 122 d[18] i/o 221 126 a[17]/dra[10] out 224 127 d[17] i/o 226 128 a[16]/dra[11] out 229 129 d[16] i/o 231 130 a[15]/dra[12] out 234 131 d[15] i/o 236 132 a[14] out 239 133 d[14] i/o 241 134 a[13] out 244 135 d[13] i/o 246 136 a[12] out 249 137 d[12] i/o 251 138 a[11] out 254 141 d[11] i/o 256 142 a[10] out 259 143 d[10] i/o 261 144 a[9] out 264 145 d[9] i/o 266 146 a[8] out 269 147 d[8] i/o 271 148 a[7] out 274 150 d[7] i/o 276 151 nbatchg in 279 152 nextpwr in 280 153 batok in 281 154 npor in 282 155 nmedchg/brom in 283 156 nureset in 284 161 wakeup in 285 162 npwrfl in 286 163 a[6] out 287 164 d[6] i/o 289 165 a[5] out 292 166 d[5] i/o 294 169 a[4] out 297 170 d[4] i/o 299 pin no. signal type position table 9. jtag boundary scan signal ordering for 208- pin lqfp package (cont.) 171 a[3] out 302 172 d[3] i/o 304 173 a[2] out 307 175 d[2] i/o 309 176 a[1] out 312 177 d[1] i/o 314 178 a[0] out 317 179 d[0] i/o 319 184 cl2 out 322 185 cl1 out 324 186 frm out 326 187 m out 328 188 dd[3] i/o 330 189 dd[2] i/o 333 191 dd[1] i/o 336 192 dd[0] i/o 339 193 nsdras[1] out 342 194 nsdras[0] out 344 195 nsdcas[3] i/o 346 196 nsdcas[2] i/o 349 199 nsdcas[1] i/o 352 200 nsdcas[0] i/o 355 201 nmwe out 358 202 nmoe out 360 204 ncs[0] out 362 205 ncs[1] out 364 206 ncs[2] out 366 207 ncs[3] out 368 208 ncs[4] out 370 pin no. signal type position table 9. jtag boundary scan signal ordering for 208- pin lqfp package (cont.)
29 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 4. 256-pin pbga package characteristics 4.1. 256-pin pbga pin diagram a b c d e f g h j k l m n p r t 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 256-ball pbga (bottom view) note: for package specifications, please see figure 14 . figure 13. 256-ball pin diagram
30 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 4.2. ep7312 256-ball pbga (17 17 1.61-mm body) dimensions top view 17.00 (0.669) 15.00 (0.590) side view bottom view a b c d e f g h j k l m n p r 1.00 (0.040) pin 1 indicator pin 1 corner pin 1 corner 16 15 14 13 12 11 10 9 8 7 6 5 4 321 15.00 (0.590) 2 layer 17.00 (0.669) 17.00 (0.669) 1.00 (0.040) 1.00 (0.040) 1.00 (0.040) 30 typ ref ref 0.50 3 places 0.85 (0.034) 0.05 (.002) 0.40 (0.016) 0.05 (.002) 0.36 (0.014) 17.00 (0.669) r d1 e1 d e 0.20 (.008) 0.20 (.008) 0.20 (.008) 0.20 (.008) 0.09 (0.004) jedec #: mo-151 ball diameter: 0.50 mm 0.10 mm figure 14. 256-ball pbga package drawing notes: 1. for pin locations, please see figure 13 . for pin descriptions, see the ep7312 users manual. 2. dimensions are in millimeters (inches), and controlling dimension is millimeter. 3. before beginning any new ep7312 design, contact cirrus logic for the latest package information.
31 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 4.3. 256-ball pbga ball listing ball location name type a1 vddio pad power a2 ncs[4] o a3 ncs[1] o a4 sdclk o a5 nsdqm3 o a6 dd[1] o a7 m o a8 vddio pad power a9 d[0] i/o a10 d[2] i/o a11 a[3] o a12 vddio pad power a13 a[6] o a14 moscout o a15 vddosc oscillator power a16 vssio pad ground b1 ncs[5] o b2 vddio pad power b3 ncs[3] o b4 nmoe/nsdcas o b5 vddio pad power b6 nsdcs[1] o b7 dd[2] o b8 cl[1] o b9 vddcore core power b10 d[1] i/o b11 a[2] o b12 a[4] o b13 a[5] o b14 wakeup i b15 vddio pad power b16 nureset i c1 vddio pad power c2 expclk i c3 vssio pad ground c4 vddio pad power c5 vssio pad ground c6 vssio pad ground c7 vssio pad ground c8 vddio pad power c9 vssio pad ground c10 vssio pad ground c11 vssio pad ground table 10. 256-ball pbga ball listing c12 vddio pad power c13 vssio pad ground c14 vssio pad ground c15 npor i c16 nextpwr i d1 write/nsdras o d2 exprdy i d3 vssio pad ground d4 vddio pad power d5 ncs[2] o d6 nmwe/nsdwe o d7 nsdcs[0] o d8 cl[2] o d9 vssrtc core ground d10 d[4] i/o d11 npwrfl i d12 moscin i d13 vddio pad power d14 vssio pad ground d15 d[7] i/o d16 d[8] i/o e1 rxd[2] i e2 pb[7] i e3 tdi i e4 word o e5 vssio pad ground e6 ncs[0] o e7 sdqm[2] o e8 frm o e9 a[0] o e10 d[5] i/o e11 vssosc oscillator ground e12 vssio pad ground e13 nmed- chg/nbrom i e14 vddio pad power e15 d[9] i/o e16 d[10] i/o f1 pb[5] i f2 pb[3] i f3 vssio pad ground f4 txd[2] o f5 run/clken o f6 vssio pad ground ball location name type table 10. 256-ball pbga ball listing (cont.)
32 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface f7 sdcke o f8 dd[3] o f9 a[1] o f10 d[6] i/o f11 vssrtc rtc ground f12 batok i f13 nbatchg i f14 vssio pad ground f15 d[11] i/o f16 vddio pad power g1 pb[1]/prdy[2] i g2 vddio pad power g3 tdo o g4 pb[4] i g5 pb[6] i g6 vssrtc core ground g7 vssrtc rtc ground g8 dd[0] o g9 d[3] i/o g10 vssrtc rtc ground g11 a[7] o g12 a[8] o g13 a[9] o g14 vssio pad ground g15 d[12] i/o g16 d[13] i/o h1 pa[7] i h2 pa[5] i h3 vssio pad ground h4 pa[4] i h5 pa[6] i h6 pb[0]/prdy[1] i h7 pb[2] i h8 vssrtc rtc ground h9 vssrtc rtc ground h10 a[10] o h11 a[11] o h12 a[12] o h13 a[13]/dra[14] o h14 vssio pad ground h15 d[14] i/o h16 d[15] i/o j1 pa[3] i j2 pa[1] i j3 vssio pad ground ball location name type table 10. 256-ball pbga ball listing (cont.) j4 pa[2] i j5 pa[0] i j6 txd[1] o j7 cts i j8 vssrtc rtc ground j9 vssrtc rtc ground j10 a[17]/dra[10] o j11 a[16]/dra[11] o j12 a[15]/dra[12] o j13 a[14]/dra[13] o j14 ntrst i j15 d[16] i/o j16 d[17] i/o k1 leddrv o k2 phdin i k3 vssio pad ground k4 dcd i k5 ntest[1] i k6 eint[3] i k7 vssrtc rtc ground k8 adcin i k9 col[4] o k10 tclk i k11 d[20] i/o k12 d[19] i/o k13 d[18] i/o k14 vssio pad ground k15 vddio pad power k16 vddio pad power l1 rxd[1] i l2 dsr i l3 vddio pad power l4 neint[1] i l5 pe[2]/clksel i l6 vssrtc rtc ground l7 pd[0]/ledflsh i/o l8 vssrtc core ground l9 col[6] o l10 d[31] i/o l11 vssrtc rtc ground l12 a[22]/dra[5] o l13 a[21]/dra[6] o l14 vssio pad ground l15 a[18]/dra[9] o l16 a[19]/dra[8] o ball location name type table 10. 256-ball pbga ball listing (cont.)
33 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface m1 ntest[0] i m2 neint[2] i m3 vddio pad power m4 pe[0]/boot- sel[0] i m5 tms i m6 vddio pad power m7 ssitxfr i/o m8 drive[1] i/o m9 fb[0] i m10 col[0] o m11 d[27] i/o m12 vssio pad ground m13 a[23]/dra[4] o m14 vddio pad power m15 a[20]/dra[7] o m16 d[21] i/o n1 nextfiq i n2 pe[1]/boot- sel[1] i n3 vssio pad ground n4 vddio pad power n5 pd[5] i/o n6 pd[2] i/o n7 ssirxda i/o n8 adcclk o n9 smpclk o n10 col[2] o n11 d[29] i/o n12 d[26] i/o n13 halfword o n14 vssio pad ground n15 d[22] i/o n16 d[23] i/o p1 vssrtc rtc ground p2 rtcout o p3 vssio pad ground p4 vssio pad ground p5 vddio pad power p6 vssio pad ground p7 vssio pad ground p8 vddio pad power p9 vssio pad ground p10 vddio pad power p11 vssio pad ground ball location name type table 10. 256-ball pbga ball listing (cont.) p12 vssio pad ground p13 vddio pad power p14 vssio pad ground p15 d[24] i/o p16 vddio pad power r1 rtcin i/o r2 vddio pad power r3 pd[4] i/o r4 pd[1] i/o r5 ssitxda o r6 nadccs o r7 vddio pad power r8 adcout o r9 col[7] o r10 col[3] o r11 col[1] o r12 d[30] i/o r13 a[27]/dra[0] o r14 a[25]/dra[2] o r15 vddio pad power r16 a[24]/dra[3] o t1 vddrtc rtc power t2 pd[7]/sdqm[1] i/o t3 pd[6]/sdqm[0] i/o t4 pd[3] i/o t5 ssiclk i/o t6 ssirxfr C t7 vddcore core power t8 drive[0] i/o t9 fb[1] i t10 col[5] o t11 vddio pad power t12 buz o t13 d[28] i/o t14 a[26]/dra[1] o t15 d[25] i/o t16 vssio pad ground ball location name type table 10. 256-ball pbga ball listing (cont.)
34 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 5. ordering information the order number for the device is: ep7312 cv a product line: embedded processor part number temperature range: c = commercial package type: v = low profile quad flat pack b = plastic ball grid array (17 mm x 17 mm) revision ? note: ? contact cirrus logic for up-to-date information on revisions. go to the cirrus logic internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative. e = extended operating version i = industrial operating version
35 ds508pp1 ep7312 high-performance system-on-chip with sdram and digital audio interface 6. index a absolute maximum ratings 9 ac characteristics 13 c clock speeds list of 1 d dc charactteristics 9 e electrical specifications 9 j jtag boundary scan signal ordering 27 m memory interfaces 3 microwire 2 o operating conditions recommended 9 ordering information how to order 34 p package specifications 208-pin lqfp 23 256-ball pbga 30 packaging 3 pin diagram 22 pin diagrams 208 lqfp 22 256-pin pbga 29 pin listing 208-pin lqfp 24 power use description of 1 power management 3 s serial interface microwire compatible 2 spi compatible 2 serial interfaces 3 system design 3 t timing diagrams consecutive memory read cycles with minimum wait states 15 consecutive memory write cycles with minimum wait states 17 sdram read cycles sdcas latency=2 18 sdram read cycles sdcas latency=3 19 sdram refresh cycles 20 sdram write cycles 19 sequential page mode read cycles with minimum wait states 16 u uart 1 C 2

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