mds 508 e 1 revision 092904 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com pecl to cmos c onverter ics508 description the ics508 is the most cost effective way to generate a high quality, high frequency cmos clock output from a pecl clock input. the ics508 has separate vdd supplies for the pecl input buffer and the output buffer, allowing different voltages to be used. for example, the input clock could use a 3.3 v supply while the output operates from 2.5v. the device has an output enable pin that tri-states the clock output when the oe pin is taken low. the ics508 is a member of ics? clockblocks tm family. features ? packaged in 8 pin soic or die ? separate vdd supplies allow voltage translation ? clock frequency of 0 - 250 mhz ? duty cycle of 45/55 ? operating voltages of 2.375 to 5.5v ? tri-state output for board level testing ? 24ma output drive capability ? industrial temperature version available ? advanced, low power, sub-micron cmos process block diagram clk output buffer vddc vddp gnd gnd oe peclin peclin
pecl to cmos c onverter mds 508 e 2 revision 092904 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics508 pin assignment pin descriptions external components the ics508 requires two 0.01 f decoupling capacitors to be connected between vddp and gnd and between vddc and gnd. they must be connected clos e to the ics508 to minimize lead inductance. a 33 ? series terminating resistor can be used next to the clk pin. vddp peclin peclin clk gnd gnd oe vddc 1 2 3 4 8 7 6 5 8 pin (150 mil) soic pin number pin name pin type pin description 1 vddp output connect to 3.3v or 5v. supplies pecl input buffer. 2peclin input complementary pecl clock input. 3 peclin input pecl clock input. 4 gnd power connect to ground. 5 oe input output enable. tri-states clk output when low. internal pull-up to vddc. 6 gnd power connect to ground. 7 clk output clock output. 8 vddc power connect to 2.5v, or 3.3v, or 5v. supplies output buffer and oe pin.
pecl to cmos c onverter mds 508 e 3 revision 092904 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics508 absolute maximum ratings stresses above the ratings listed below can cause perma nent damage to the ics508. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions dc electrical characteristics vddp = vddc =3.3v 5% , ambient temperature 0 to +70 c, unless stated otherwise item rating supply voltage, vddp and vddc 7v pecl inputs -0.5v to vddp+0.5v clock output and oe pin -0.5v to vddc+0.5v ambient operating temperature, ics508 0 to +70 c ambient operating temperature, ics508mi -40 to +85 c storage temperature -65 to +150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature, ics508m 0 +70 c ambient operating temperature, ics508mi -40 +85 c power supply voltage (measured in respect to gnd) +3.15 +3.45 v reference crystal parameters refer to page 3 parameter symbol conditions min. typ. max. units operating voltage vdd vddp 3 5.5 v vdd vddc 2.375 5.5 v peak to peak input voltage peclin 0.3 1 v common mode range peclin vddp = 5v vddp - 3.7 vddp - 0.6 v peclin vddp = 3.3v vddp - 2.0 vddp - 0.6 v input high voltage v ih oe only 2 vddc v input low voltage v il oe only 0.8 v
pecl to cmos c onverter mds 508 e 4 revision 092904 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics508 note 1: vddp must always be greater than or equal to vddc ac electrical characteristics vddp = vddc = 3.3v5% , ambient temperature 0 to +70 c, unless stated otherwise output high voltage v oh vddc = 5v ioh = -24 ma vddc - 0.4 v vddc = 3.3v ioh = -18 ma vddc - 0.4 v vddc = 2.5v ioh = -8 ma vddc - 0.4 v output low voltage v ol vddc = 5v iol = 24 ma 0.4 v vddc = 3.3v iol = 18 ma 0.4 v vddc = 2.5v iol = 8 ma 0.4 v on chip pull-up resistor r pu oe 250 k ? operating supply current iddp 100 mhz, no load 1.5 ma iddc 100 mhz, no load 8 ma parameter symbol conditions min. typ. max. units input frequency f in 0250mhz output clock rise time 100mhz 0.8v to 2.0v, vddp=vddc = 5v 0.4 ns 100mhz 0.8v to 2.0v, vddp=vddc=3.3v 0.6 ns 100mhz 0.8v to 2.0v, vddp=vddc=2.5v 1 ns output clock fall time 100mhz 2.0v to 0.8v, vddp=vddc = 5v 0.4 ns 100mhz 2.0v to 0.8v, vddp=vddc=3.3v 0.6 ns 100mhz 2.0v to 0.8v, vddp=vddc=2.5v 1 ns output enable time 100mhz oe high to output on 0 - 100mhz 7 20 ns output disable time 100mhz oe lo w to tri-state 0 - 100mhz 7 20 ns propagation delay vddp = 5v, vddc = 5v, 4 6 ns 100 mhz vddp = 5v, vddc = 3.3v 4.5 7 ns 100 mhz vddp = 5v, vddc = 2.5v 5.5 9 ns 100 mhz vddp = 3.3v, vddc = 3.3v 4.5 7 ns vddp = 3.3v, vddc = 2.5v 5.5 9 ns output clock duty cycle 0 - 100 mhz any vdd combination 45 55 % parameter symbol conditions min. typ. max. units
pecl to cmos c onverter mds 508 e 5 revision 092904 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics508 thermal characteristics marking diagram notes: 1. ###### is the lot number 2. yyww is the last two digits of the year and the week number that the part was assembled output clock duty cycle 100 - 166 mhz vddp = 5v, vddc = 5v 45 55 % vddp = 5v, vddc = 3.3v 45 55 % vddp = 5v, vddc = 2.5v 40 60 % vddp = 3.3v, vddc = 3.3v 40 60 % vddp = 3.3v, vddc = 2.5v 45 55 % output clock duty cycle 166 - 250 mhz vddp = 5v, vddc = 5v 40 60 % vddp = 5v, vddc = 3.3v 40 60 % vddp = 5v, vddc = 2.5v 35 65 % vddp = 3.3v, vddc = 3.3v 35 65 % vddp = 3.3v, vddc = 2.5v 40 60 % parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 150 c/w ja 1 m/s air flow 140 c/w ja 3 m/s air flow 120 c/w thermal resistance junction to case jc 40 c/w parameter symbol conditions min. typ. max. units ics508m ###### yyww
pecl to cmos c onverter mds 508 e 6 revision 092904 integrated circuit systems 525 race street, san jose, ca 95126 tel (408) 295-9800 www.icst.com ics508 package outline and package dimensions (8 pin soic, 150 m il. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information while the information presented herein has been checked for both accuracy and reliability, integr ated circuit systems (ics) ass umes no responsibility for either its us e or for the infringement of any patents or other rights of third parties, which would result f rom its use. no other circuits, patents, or licenses are impl ied. this product is intended for use in no rmal commercial applications. any other appli cations such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recomme nded without additional processing by ics. ics reserves the right to change an y circuitry or specifications without notice. ics does not aut horize or warrant any ics product for use in life support de vices or critical medical instruments. part / order number marking shipping packaging package temperature ics508m ics508m tubes 8 pin soic 0 to +70 c ics508mt ics508m tape and reel 8 pin soic 0 to +70 c ics508mi ics508i tubes 8 pin soic -40 to +85 c ics508mit ics508i tape and reel 8 pin soic -40 to +85 c ics508-dwf - die on uncut, probed wafers 0 to +70 c ICS508-DPK - tested die in waffle pack 0 to +70 c index area 1 2 8 d e seating plane a1 a e - c - b .10 (.004) c c l h h x 45 millimeters inches symbol min max min max a 1.35 1.75 .0532 .0688 a1 0.10 0.25 .0040 .0098 b 0.330.51.013.020 c 0.19 0.25 .0075 .0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 .1497 .1574 e 1.27 basic 0.050 basic h 5.80 6.20 .2284 .2440 h 0.250.50.010.020 l 0.401.27.016.050 0 8 0 8
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