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ic-nql 13-bit sin/d converter with ssi interface rev d2, page 1/ 24 features ? resolution of up to 8192 angle steps per sine/cosine period ? binary and decimal resolution settings, e.g. 500, 512, 1000, 1024; programmable angle hysteresis ? conversion time of just 250 ns including ampli?er settling ? count-safe vector follower principle, realtime system with 70 mhz sampling rate ? direct sensor connection; selectable input gain ? front-end signal conditioning features offset (8 bit), amplitude ratio (5 bit) and phase (6 bit) calibration ? 250 khz input frequency ? absolute angle output via fast ssi interface ? a quad b incremental outputs with selectable minimum transition distance (e.g. 0.25 s for 1 mhz at a) ? index signal processing adjustable in position and width ? fault monitoring: frequency, amplitude, con?guration (crc) ? setup via serial eeprom ? esd protection and ttl-/cmos-compatible outputs applications ? interpolator ic for position data acquisition from analog sine/cosine sensors ? optical linear/rotary encoders ? mr sensor systems packages tssop20 block diagram copyright ? 2004, 2011 ic-haus http://www.ichaus.com
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 2/ 24 description ic-nql is a monolithic a/d converter which, by ap- plying a count-safe vector follower principle, converts sine/cosine sensor signals with a selectable resolu- tion and hysteresis into angle position data. this absolute value is output via a synchronous-serial ssi interface and trails a master clock rate of up to 4 mbit/s. at the same time any changes in output data are converted into incremental a quad b encoder sig- nals. here, the minimum transition distance can be adapted to suit the system on hand (cable length, ex- ternal counter). a synchronised zero index is gener- ated and output to z if enabled by the pzero and nzero inputs. the front-end ampli?ers are con?gured as instrumen- tation ampli?ers, permitting sensor bridges to be di- rectly connected without the need for external resis- tors. various programmable d/a converters are avail- able for the conditioning of sine/cosine sensor sig- nals with regard to offset, amplitude ratio and phase errors. front-end gain can be set in stages graded to suit all common differential sensor signals from approximately 20 mvpp to 1.5 vpp, and also single- ended sensor signals from 40 mvpp to 3 vpp respec- tively. the device reads its con?guration data via the serial eeprom interface when cycling power, respectively following an undervoltage reset. the read in cycle is repeated up to three times when data correctness is not con?rmed by a crc validation. a permanent crc error as well as the con?guration phase itself is displayed at the error message output nerr by a low level signal.
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 3/ 24 contents packages 4 absolute maximum ratings 5 thermal data 5 electrical characteristics 6 electrical characteristics: diagrams 8 operating requirements: ssi interface 8 parameters and registers 10 signal conditioning 11 converter functions 12 maximum possible converter frequency 13 serial data output . . . . . . . . . . . . . . . 13 incremental output to a, b and z . . . . . . . 14 incremental signals 15 signal monitoring and error messages 17 test functions 18 ssi interface 19 eeprom interface and startup behaviour 20 example of crc calculation routine . . . . . 20 application hints 21 principle input circuits . . . . . . . . . . . . . 21 basic circuit . . . . . . . . . . . . . . . . . . 22 design review: notes on chip functions 23
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 4/ 24 packages tssop20 (according to jedec standard) pin configuration tssop20 4.4 mm, lead pitch 0.65 mm pin functions no. name function 1 pcos input cosine + 2 ncos input cosine - 3 vdda +5 v supply voltage (analog) 4 gnda ground (analog) 5 vref reference voltage output 6 a incremental output a analog signal cos+ (tma mode) pwm signal for offset sine (calib.) 7 b incremental output b analog signal cos- (tma mode) pwm signal for offset cosine (calib.) 8 z output index z pwm signal for phase/ratio (calib.) 9 gnd ground 10 vdd +5 v supply voltage (digital) 11 test test input 12 clk ssi interface, clock line 13 data ssi interface, data output 14 sda eeprom interface, data line analog signal sin+ (tma mode) 15 scl eeprom interface, clock line analog signal sin- (tma mode) 16 nerr error input/output, active low 17 pzero input zero signal + 18 nzero input zero signal - 19 psin input sine + 20 nsin input sine - external connections linking vdda to vdd and gnd to gnda are required. the test input may remain unwired or can be linked to vdd (please note the hints given by chapter design review regarding the signal of pin data).
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 5/ 24 absolute maximum ratings these ratings do not imply operating conditions; functional operation is not guaranteed. beyond these ratings device damage may occur. item symbol parameter conditions unit no. min. max. g001 vdda voltage at vdda -0.3 6 v g002 vdd voltage at vdd -0.3 6 v g003 vpin() voltage at psin, nsin, pcos, ncos, pzero, nzero, vref, nerr, scl, sda, clk, data, a, b, z v() < vdda + 0.3 v -0.3 6 v v() < vdd + 0.3 v g004 imx(vdda) current in vdda -50 50 ma g005 imx(gnda) current in gnda -50 50 ma g006 imx(vdd) current in vdd -50 50 ma g007 imx(gnd) current in gnd -50 50 ma g008 imx() current in psin, nsin, pcos, ncos, pzero, nzero, vref, nerr, scl, sda, clk, data, a, b, z -10 10 ma g009 ilu() pulse current in all pins (latch-up strength) according to jedec standard no. 78; -100 100 ma ta = 25 c, pulse duration to 10 s, vcc = vccmax, vdd = vddmax, vlu() = (-0.5...+1.5) x vpin()max g010 vd() esd susceptibility at all pins hbm 100 pf discharged through 1.5 k
2 kv g011 tj junction temperature -40 150 c g012 ts storage temperature range -40 150 c thermal data operating conditions: vdda = vdd = 5 v 10 % item symbol parameter conditions unit no. min. typ. max. t01 ta operating ambient temperature range (extended temperature range of -40 to 125 c available on request) -25 85 c all voltages are referenced to ground unless otherwise stated. all currents ?owing into the device pins are positive; all currents ?owing out of the device pins are negative.
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 6/ 24 electrical characteristics operating conditions: vdda = vdd = 5 v 10 %, tj = -40 ... 125 c, unless otherwise stated item symbol parameter conditions unit no. min. typ. max. total device functionality and parameters beyond the operating conditions (with reference to independent voltage supplies, for instance) are to be veri?ed within the individual application using fmea methods. 001 vdda, vdd permissible supply voltage 4.5 5.5 v 002 i(vdda) supply current in vdda ?n() = 200 khz; a, b, z open 15 ma 003 i(vdd) supply current in vdd ?n() = 200 khz; a, b, z open 20 ma 004 von turn-on threshold vdda, vdd 3.2 4.4 v 005 vhys turn-on threshold hysteresis 200 mv 006 vc()hi clamp voltage hi at psin, nsin, pcos, ncos, pzero, nzero, vref vc()hi = v() - vdda; 0.3 1.6 v i() = 1 ma, other pins open 007 vc()lo clamp voltage lo at psin, nsin, pcos, ncos, pzero, nzero, vref, nerr, scl, sda, a, b, z i() = -1 ma, other pins open -1.6 -0.3 v 008 vc()hi clamp voltage hi at nerr, scl, sda, a, b, z vc()hi = v() - vdd; 0.3 1.6 v i() = 1 ma, other pins open input ampli?ers psin, nsin, pcos, ncos 101 vos() input offset voltage vin() and g() in accordance with table gain; g 20 -10 10 mv g < 20 -15 15 mv 102 tcos input offset voltage temperature drift see 101 10 v/k 103 iin() input current v() = 0 v ... vdda -50 50 na 104 ga gain accuracy g() in accordance with table gain 95 102 % 105 garel gain sin/cos ratio accuracy g() in accordance with table gain 97 103 % 106 fhc cut-off frequency g = 80 150 khz g = 2.667 630 khz 107 sr slew rate g = 80 2.3 v/s g = 2.667 8.0 v/s sin/d conversion: accuracy 201 aaabs absolute angle accuracy without calibration referred to 360 input signal, g = 2.667, vin = 1.5 vpp, hys = 0 -1.0 1.0 deg 202 aaabs absolute angle accuracy after calibration referred to 360 input signal, hys = 0, internal signal amplitude of 2 ... 4 vpp -0.5 0.35 +0.5 deg 203 aarel relative angle accuracy referred to output signal period of a/b, -10 10 % g = 2.667, vin = 1.5 vpp, selres = 1024, fctr = 0x0004 ... 0x00ff, ?n < ?n max (see table 14 ) reference voltage vref 801 vref reference voltage i(vref) = -1 ma ... +1 ma 48 52 % vdda oscillator a01 fosc() oscillator frequency presented at scl with subdivision of 2048; vdda = vdd = 5 v 10 % 52 90 mhz vdda = vdd = 5 v 60 72 83 mhz a02 tcosc oscillator frequency tempera- ture drift vdda = vdd = 5 v -0.1 %/k a03 vcosc oscillator frequency power sup- ply dependance +10.6 %/v
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 7/ 24 electrical characteristics operating conditions: vdda = vdd = 5 v 10 %, tj = -40 ... 125 c, unless otherwise stated item symbol parameter conditions unit no. min. typ. max. zero comparator b01 vos() input offset voltage v() = vcm() -20 20 mv b02 iin() input current v() = 0 v ... vdda -50 50 na b03 vcm() common-mode input voltage range 1.4 vdda- 1.5 v b04 vdm() differential input voltage range 0 vdda v incremental outputs a, b, z ssi interface output data d01 vs()hi saturation voltage hi vs()hi = vdd - v(); i() = -4 ma 0.4 v d02 vs()lo saturation voltage lo i() = 4 ma 0.4 v d03 tr() rise time cl() = 50 pf 60 ns d04 tf() fall time cl() = 50 pf 60 ns d05 rl() permissible load at a, b tma = 1 (calibration mode) 1 m
ssi interface: input clk e01 vt()hi threshold voltage hi 2 v e02 vt()lo threshold voltage lo 0.8 v e03 vt()hys hysteresis vt()hys = vt()hi - vt()lo 300 mv e04 ipu() pull-up current in clk v() = 0 ... vdd - 1 v -240 -120 -25 a e05 fclk() permissible clock frequency at clk 4 mhz e06 tp(clk- data) propagation delay: clk edge vs. data output all modes, rl(slo) 1 k
10 50 ns e07 tbusy() processing time 0 e08 ttos() timeout cfgtos = 0x01 ic-nql_x3 16 s cfgtos = 0x01, ic-nql_3 20 s eeprom interface, control logic: inputs sda, nerr f01 vt()hi threshold voltage hi 2 v f02 vt()lo threshold voltage lo 0.8 v f03 vt()hys hysteresis vt()hys = vt()hi - vt()lo 300 mv f04 tbusy()cfg duration of startup con?guration error free eeprom access 5 7 ms eeprom interface, control logic: outputs sda, scl, nerr g01 f() write/read clock at scl 20 100 khz g02 vs()lo saturation voltage lo i() = 4 ma 0.45 v g03 ipu() pull-up current v() = 0 ... vdd - 1 v -600 -300 -75 a g04 ft() fall time cl() = 50 pf 60 ns g05 tmin()lo error signal indication time at nerr (lo signal) clk = hi, no amplitude or frequeny error 10 ms g06 tpwm() duty cycle of error indication at nerr fosc() subdivided by 2 22 60.7 ms g07 t()lo duty cycle of error indication at nerr signal duration low to high; aerr = 0 (amplitude error) 75 % ferr = 0 (frequency error) 50 % g08 rl() permissible load at sda, scl tma = 1 (calibration mode) 1 m

ic-nql 13-bit sin/d converter with ssi interface rev d2, page 8/ 24 electrical characteristics: diagrams figure 1: de?nition of relative angle error. figure 2: de?nition of minimum transition distance. figure 3: typical residual absolute angle error after calibration. twhi()/t aarel 10% 60% 50% 40% 0% 110% aarel 10% 90% 100% 0% $ t mtd 0 90 180 270 360 -0.15 -0.1 -0.05 0 0.05 0.1 0.15
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 9/ 24 operating requirements: ssi interface operating conditions: vdd = 5 v 10 %, ta = -25 ... 85 c; input levels lo = 0 ... 0.45 v, hi = 2.4 v ... vdd item symbol parameter conditions fig. unit no. min. max. i001 t clk permissible clock period cfgtos = 0x01 4 250 2x t tos ns i002 t clkhi clock signal hi level duration 4 25 t tos ns i003 t clklo clock signal lo level duration 4 25 t tos ns figure 4: timing diagram of ssi output.
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 10/ 24 parameters and registers register description . . . . . . . . . . . . . . . . . . . . . . . page 10 signal conditioning . . . . . . . . . . . . . . . . . . . . . . . page 11 gain: gain select sinoffs: offset calibration sine cosoffs: offset calibration cosine refoffs: offset calibration reference ratio: amplitude calibration phase: phase calibration converter function . . . . . . . . . . . . . . . . . . . . . . . . page 12 selres: resolution hys: hysteresis fctr: max. permissible converter frequency incremental signals . . . . . . . . . . . . . . . . . . . . . . . page 15 cfgabz: output a, b, z rot: direction of rotation enresdel: output turn-on delay zpos: zero signal position cfgz: zero signal length cfgab: zero signal logic signal monitoring and error messages . . . . . . . . . . . . . . . . . . . . . . . page 17 selampl: amplitude monitoring, function ampl: amplitude monitoring, thresholds aerr: amplitude error ferr: frequency error test functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 18 tmode: test mode tma: analog test mode ssi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . page 19 cfgtos: interface timeout cfgssi: ssi output options overview adr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 0 0 0 selres(4:0) 0x01 hys(2:0) zpos(4:0) 0x02 enresdel 1 rot 0 cfgabz(1:0) cfgz(1:0) 0x03 cfgssi(1:0) cfgab(1:0) 0 0 aerr ferr 0x04 fctr(7:0) 0x05 0 fctr(14:8) 0x06 0 0 cfgtos(1:0) tmode(2:0) tma 0x07 0 0 0 0 0 0 0 0 0x08 gain(3:0) ratio(3:0) 0x09 sinoffs(7:0) 0x0a cosoffs(7:0) 0x0b phase(5:0) refoffs ratio(4) 0x0c 0 0 0 0 0 selampl ampl(1:0) 0x0d 0 0 0 0 0 0 0 0 0x0e 0 0 0 0 0 0 0 0 0x0f crc_e2p(7:0) - check value read from the eeprom for addresses 0x00 to 0x0e note registers not in use must be set to zero unless otherwise noted. table 5: register layout
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 11/ 24 signal conditioning input stages sin and cos are con?gured as instru- mentation ampli?ers. the ampli?er gain must be se- lected in accordance with the sensor signal level and programmed to register gain according to the follow- ing table. half of the supply voltage is output to vref as center voltage to help dc level adaptation. gain adr 0x08, bit 7:4 sine/cosine input signal levels vin() amplitude average value (dc) code ampli?cation differential single-ended differential single-ended 0x0f 80.000 up to 50 mvpp up to 100 mvpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.2 v 0x0e 66.667 up to 60 mvpp up to 120 mvpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.2 v 0x0d 53.333 up to 75 mvpp up to 0.15 vpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.2 v 0x0c 40.000 up to 0.1 vpp up to 0.2 vpp 1.2 v ... vdda - 1.2 v 1.3 v ... vdda - 1.3 v 0x0b 33.333 up to 0.12 vpp up to 0.24 vpp 1.2 v ... vdda - 1.2 v 1.3 v ... vdda - 1.3 v 0x0a 28.571 up to 0.14 vpp up to 0.28 vpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.3 v 0x09 26.667 up to 0.15 vpp up to 0.3 vpp 1.2 v ... vdda - 1.2 v 1.3 v ... vdda - 1.3 v 0x08 20.000 up to 0.2 vpp up to 0.4 vpp 0.7 v ... vdda - 1.2 v 0.8 v ... vdda - 1.3 v 0x07 14.287 up to 0.28 vpp up to 0.56 vpp 1.2 v ... vdda - 1.3 v 1.4 v ... vdda - 1.4 v 0x06 10.000 up to 0.4 vpp up to 0.8 vpp 1.2 v ... vdda - 1.3 v 1.4 v ... vdda - 1.5 v 0x05 8.000 up to 0.5 vpp up to 1 vpp 0.8 v ... vdda - 1.4 v 1.0 v ... vdda - 1.6 v 0x04 6.667 up to 0.6 vpp up to 1.2 vpp 0.8 v ... vdda - 1.4 v 1.1 v ... vdda - 1.7 v 0x03 5.333 up to 0.75 vpp up to 1.5 vpp 0.9 v ... vdda - 1.5 v 1.3 v ... vdda - 1.9 v 0x02 4.000 up to 1 vpp up to 2 vpp 1.2 v ... vdda - 1.6 v 1.7 v ... vdda - 2.1 v 0x01 3.333 up to 1.2 vpp up to 2.4 vpp 1.2 v ... vdda - 1.7 v 1.8 v ... vdda - 2.3 v 0x00 2.667 up to 1.5 vpp up to 3 vpp 1.3 v ... vdda - 1.8 v 2.0 v ... vdda - 2.6 v table 6: gain select sinoffs adr 0x09, bit 7:0 cosoffs adr 0x0a, bit 7:0 code output offset input offset 0x00 0 v 0 v 0x01 -7.8125 mv -7.8125* mv / gain ... ... ... 0x7f -0.9922 v -0.9922 v / gain 0x80 0 v 0 v 0x81 +7,8125 mv +7.8125 mv / gain ... ... ... 0xff +0.9922 v +0.9922 v / gain notes *) with refoffs = 0x00 und vdda = 5 v. table 7: offset calibration sine/cosine refoffs adr 0x0b, bit 1 code reference voltage 0x00 depending on vdda (example of application: mr sensors) 0x01 not depending on vdda (example of application: sin/cos encoders) table 8: offset calibration reference ratio adr 0x0b, bit 0, adr 0x08, bit 3:0 code cos / sin code cos / sin 0x00 1.0000 0x10 1.0000 0x01 1.0067 0x11 0.9933 ... ... ... ... 0x0f 1.1 0x1f 0.9000 table 9: amplitude calibration phase adr 0x0b, bit 7:2 code phase shift code phase shift 0x00 90 0x20 90 0x01 90.703125 0x21 89.296875 ... ... ... ... 0x12 102.65625 0x32 77.34375 ... 102.65625 ... 77.34375 0x1f 102.65625 0x3f 77.34375 table 10: phase calibration
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 12/ 24 converter functions selres adr 0x00, bit 4:0 code binary resolutions examples of permissible input frequencies ?n max (fctr 0x0004, 0x4304) 0x00 - 0x01 - 0x02 - 0x03 8192 158 hz, 635 hz 0x04 4096 317 hz, 1.27 khz 0x05 2048 634 hz, 2.54 khz 0x06 1024 1.27 khz, 5.1 khz 0x07 512 2.54 khz, 10.2 khz 0x08 256 5.1 khz, 20.3 khz 0x09 128 10.2 khz, 40.6 khz 0x0a 64 20.3 khz, 81.3 khz 0x0b 32 40.6 khz, 162.5 khz 0x0c 16 81.3 khz (max. 250 khz @ 0x4202) 0x0d 8 162 khz (max. 250 khz @ 0x4102) 0x0e - 0x0f - table 11: binary resolutions selres adr 0x00, bit 4:0 code decimal resolutions examples of permissible input frequencies ?n max (fctr 0x0004, 0x4304) 0x10 2000 650 hz, 2.6 khz 0x11 1600 812 hz, 3.3 khz 0x12 1000 1.3 khz, 5.2 khz 0x13 800 1.6 khz, 6.5 khz 0x14 500 2.6 khz, 10.4 khz 0x15 400 3.2 khz, 13 khz 0x16 250 *1 5.2 khz, 20.8 khz 0x17 125 *1,2 5.2 khz, 20.8 khz 0x18 320 4.1 khz, 16.3 khz 0x19 160 *2 4.1 khz, 16.3 khz 0x1a 80 *4 4.1 khz, 16.3 khz 0x1b 40 *8 4.1 khz, 16.3 khz 0x1c 200 6.5 khz, 26 khz 0x1d 100 *2 6.5 khz, 26 khz 0x1e 50 *1,4 6.5 khz, 26 khz 0x1f 25 *1,8 6.5 khz, 26 khz notes *1 not useful with incremental a quad b output. *2,4,8 the internal converter resolution is higher by a factor of 2, 4 or 8. table 12: decimal resolutions hys adr 0x01, bit 7:5 code hysteresis in degree hysteresis in lsb absolute angle error* 0x00 0 0x01 0.0879 1 lsb @ 12 bit 0.044 0x02 0.1758 1/2 lsb @ 10 bit 0.088 0x03 0.3516 1 lsb @ 10 bit 0.176 0x04 0.7031 1/2 lsb @ 8 bit 0.352 0x05 1.4063 1 lsb @ 8 bit 0.703 0x06 5.625 2.813 0x07 45 only recommended for calibration 22.5 notes *) the absolute angle error is equivalent to one half the angle hysteresis table 13: hysteresis
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 13/ 24 maximum possible converter frequency the converter frequency automatically adjusts to the value necessary for the input frequency and resolution. this value ranges from zero to a maximum dependent on the oscillator frequency which can be set using reg- ister fctr. serial data output for ssi output the maximum possible converter fre- quency can be adjusted to suit the maximum input fre- quency; an automatic converter resolution step-down feature can be enabled via the fctr register. should the input frequency exceed the frequency limit of the selected converter resolution, the lsb is kept stable and not resolved any further; the interpolation resolu- tion halves. if the next frequency limit is overshot, the lsb and the lsb+1 are kept stable and so on. when the input fre- quency again sinks below this frequency limit, the ?ne resolution automatically returns. max. possible converter frequency for serial data output resolution protocol max. input frequency restrictions examples* requirements at high input frequency ?n max [khz] at resol. fctr min. res. bin dec ssi ?n max 8192 1024 200 0x0004 x x x fosc()min / 40 / resolution C 0.16 1.27 6.5 0x4102 8 x x x fosc()min / 24 / resolution rel. angle error 2x increased 0.26 2.1 10.8 0x4202 16 x x x 2 x fosc()min / 24 / res. rel. angle error 4x increased 0.53 4.2 21.6 0x4304 32 x x x 4 x fosc()min / 40 / res. rel. angle error 8x increased 0.64 5.1 26.0 0x4602 64 x - x 4 x fosc()min / 24 / res. resolution lowered by factor of 2 1.1 8.5 - 0x4a02 128 x - x 8 x fosc()min / 24 / res. res. lowered by factor of 2-4 2.1 16.9 - 0x4e02 256 x - x 16 x fosc()min / 24 / res. res. lowered by factor of 2-8 4.2 33.8 - 0x5202 512 x - x 32 x fosc()min / 24 / res. res. lowered by factor of 2-16 8.5 67.7 - 0x5602 1024 x - x 64 x fosc()min / 24 / res. res. lowered by factor of 2-32 16.9 135 - 0x5a02 2048 x - x 128 x fosc()min / 24 / res. res. lowered by factor of 2-64 33.8 250 - 0x5e02 4096 x - x 256 x fosc()min / 24 / res. res. lowered by factor of 2-128 67.7 - - 0x6202 8192 x - x 512 x fosc()min / 24 / res. res. lowered by factor of 2-256 135 - - notes *) calculated with fosc()min taken from electrical characteristics item a01. table 14: maximum converter frequency for serial data output.
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 14/ 24 incremental output to a, b and z there are two criteria which must be considered when setting the maximum possible converter frequency via the fctr register: 1. the maximum input frequency 2. system limitations, e.g. due to slow counters or cable transmission when facing system limitations it is useful to prese- lect a minimum transition distance for the output sig- nals. a digital zero-delay glitch ?lter then takes care of a temporal edge-to-edge separation, guaranteeing spike-free output signals after an esd impact to the sensor, for instance. a serial data output is simultaneously possible at any time. however, for the transfer of angle data to the output register the incremental output is halted for one period of the clock signal applied to pin clk. 1. max. possible converter frequency de?ned by the maximum input frequency output frequency resolution maximum input frequency restrictions examples* fout @ ?n max requirem. at high input frequency ?n max [khz] at resol. fctr a, b bin dec ?n max 8192 1024 200 0x0004 325 khz x x fosc()min / 40 / resolution none 0.16 1.27 6.5 0x4102 542 khz x x fosc()min / 24 / resolution relative angle error 2x increased 0.26 2.1 10.8 0x4202 1.08 mhz x x 2 x fosc()min / 24 res. relative angle error 4x increased 0.53 4.2 21.6 0x4304 1.3 mhz x x 4 x fosc()min / 40 / res. relative angle error 8x increased 0.64 5.1 26.0 notes *) calculated with fosc()min taken from electrical characteristics item a01. table 15: max. converter frequency for incremental a/b/z output, de?ned by the max. input frequency 2. max. possible converter frequency de?ned by the minimum transition distance output frequency resolution minimum transition distance restrictions example* fout @ t mtd requirem. at a, b at high input frequency t mtd [sec] fctr a, b bin dec t mtd 0x00ff 11 khz x x 2048 / fosc()max none 22.8 0x00fe 11.03 khz x x 2040 / fosc()max none 22.7 0x00fd 11.07 khz x x 2032 / fosc()max none 22.6 ... ... ... ... ... ... ... 0x0006 402 khz x x 56 / fosc()max none 0.62 0x0005 536 khz x x 48 / fosc()max none 0.53 0x0004 562 khz x x 40 / fosc()max none 0.44 0x4102 938 khz x x 24 / fosc()max relative angle error 2x increased 0.27 0x4202 1.87 mhz x x 12 / fosc()max relative angle error 4x increased 0.13 0x4304 2.25 mhz x x 10 / fosc()max relative angle error 8x increased 0.11 notes *) calculated with fosc()max taken from el.char. item a01; the min. transition distance refers to output a vs. output b without reversing the sense of rotation. table 16: max. converter frequency for incremental a/b/z output, de?ned by the min. transition distance
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 15/ 24 incremental signals cfgabz adr 0x02, bit 3:2 code mode pin a pin b pin z 0x00 normal a b z 0x01 control signals for external period counters ca cb cz 0x02 calibration mode offset+phase the following settings are required additionally: selres = 0x0d zpos = 0x00 hys = 0x07 rot = 0x00 cfgab = 0x00 aerr = 0x00 figure 5: offset sin* figure 6: offs. cos* figure 7: phase* 0x03 calibration mode offset+amplitude the following settings are required additionally: selres = 0x0d zpos = 0x00 hys = 0x07 rot = 0x00 cfgab = 0x00 aerr = 0x00 figure 8: offset sin* figure 9: offs. cos* figure 10: amplit.* notes *) trimmed accurately when duty cycle is 50 %; recommended trimming order (after selecting gain): offset, phase, amplitude ratio, offset; table 17: outputs a, b, z rot adr 0x02, bit 5 code direction 0x00 not inverted 0x01 inverted table 18: direction of rotation enresdel adr 0x02, bit 7 code output* function 0x00 immediately an external counter displays the absolute angle following power on. 0x01 after 5 ms an external counter only displays changes vs. the initial power-on condition (moving halted to reapply power is precondition.) notes *) output delay after device con?guration and internal reset. table 19: output turn-on delay a, b, z
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 16/ 24 zpos adr 0x01, bit 4:0 code position 0x00 0 0x08 90 0x10 180 0x18 270 notes the zero signal is only output if released by the input pins (for instance with pzero = 5 v, nzero = vref). table 20: zero signal position cfgz adr 0x02, bit 1:0 code length 0x00 90 0x01 180 0x02.. 03 synchronization table 21: zero signal length cfgab adr 0x03, bit 5:4 code z = 1 for 0x00 b = 1, a = 1 0x01 b = 0, a = 1 0x02 b = 1, a = 0 0x03 b = 0, a = 0 table 22: zero signal logic figure 11: incremental output signals for various length of the zero signal. example for a resolution of 64 (selres = 0x0a), a zero signal position of 0 (zpos = 0x00, cfgab = 0x00) and no reversal of the rotational sense (rot = 0x00, cos leads sin). -180 -90 0 90 180 angle sin cos a b z (cfgz= 1) z (cfgz= 2) z (cfgz= 0)
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 17/ 24 signal monitoring and error messages selampl ampl adr 0x0c, bit 2 adr 0x0c, bit 1:0 max ( |sin| , |cos| ) code voltage threshold v th output amplitude* 0x00 0.60 x vdda 1.4 vpp 0x01 0.64 x vdda 2.0 vpp 0x02 0.68 x vdda 2.6 vpp 0x03 0.72 x vdda 3.1 vpp sin 2 + cos 2 code v thmin $ v thmax output amplitude* design ic-nql_x3: 0x04 (0.48 $ 0.68) x vdda 2.4 vpp $ 3.4 vpp 0x05 (0.56 $ 0.76) x vdda 2.8 vpp $ 3.8 vpp 0x06 (0.64 $ 0.84) x vdda 3.2 vpp $ 4.2 vpp 0x07 (0.72 $ 0.92) x vdda 3.6 vpp $ 4.6 vpp design ic-nql_3: 0x04 (0.20 $ 0.9) x vdda 1.0 v ss $ 4.5 v ss 0x05 (0.30 $ 0.9) x vdda 1.5 v ss $ 4.5 v ss 0x06 (0.40 $ 0.9) x vdda 2.0 v ss $ 4.5 v ss 0x07 (0.50 $ 0.9) x vdda 2.5 v ss $ 4.5 v ss notes *) entries are calculated with vdda = 5 v. table 23: signal amplitude monitoring aerr adr 0x03, bit 1 code amplitude error message 0x00 disabled 0x01 enabled table 24: amplitude error ferr adr 0x03, bit 0 code excessive frequency error message 0x00 disabled 0x01 enabled note input frequency monitoring is operational for resolutions 16 table 25: frequency error con?guration error - messaging always released table 26: con?guration error error indication at nerr failure mode pin signal nerr no error hi amplitude error lo/hi = 75 % frequency error lo/hi = 50 % con?guration lo undervoltage lo system error nerr = low by external error signal table 27: error indication at nerr figure 12: signal monitoring of minimum amplitude. figure 13: sin 2 + cos 2 signal monitoring. to enable the diagnosis of faults, the various types of error are signaled at nerr using a pwm code as given in the key table. two error bits are provided to enable communication via the ssi interface; these bits can decode four differ- ent types of error. if nerr is held at low by an external source, such as an error message from the system, for example, this can also be veri?ed via the ssi interface. error events are stored for the ssi data output and deleted afterwards. errors at nerr are displayed for a minimum of ca. 10 ms, as far as no ssi readout causes a deletion. if an error in amplitude occurs the conversion pro- cess is terminated and the incremental output signals halted. an error in amplitude rules out the possibility of an error in frequency. error messages ssi failure mode error bits e1, e0 (actice low) no error 1, 1 amplitude error 0, 1 frequency error 1, 0 con?guration 0, 0 system error 0, 0 (nerr pulled low by external signal) line signal slo ic-nql_3: data output is deactivated and slo permanently high in case of: con?guration phase, invalid con?guration, undervoltage. table 28: error messages ssi vpp vth vthmin vthmax
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 18/ 24 test functions tmode adr 0x06, bit 3:1 code signal at z description 0x00 z no test mode 0x01 a xor b output a exor b 0x02 enclk ic-haus device test 0x03 nlock ic-haus device test 0x04 clk ic-haus device test 0x05 divc ic-haus device test 0x06 pzero - nzero ic-haus device test 0x07 tp ic-haus device test condition cfgabz = 0x00 table 29: test mode tma adr 0x06, bit 0 code pin a pin b pin sda pin scl 0x00 a b sda scl 0x01 cos+ cos- sin+ sin- notes to permit the veri?cation of gain and offset settings, the input ampli?er outputs are available at the pins. to operate the converter a signal of 4 vpp is the ideal here and should not be exceeded. pin loads above 1 m
are adviceable for accurate measurements. table 30: analog test mode figure 14: calibrated signals with tma mode. parameter gain ideally adjusts the signal levels to ca. 4 vpp and should not be touched afterwards. both scope display modes are feasible for offs (pos- itive values) or ratio adjustments; regarding the ad- justment of phase the x/y mode may be preferred. for offs adjustment towards negative values the test signals cos- (pin b) and sin- (pin scl) are relevant. sda: sin+ a: cos+ 5 v x/y 0 v 1 v/div vert. 1 v/div hor. y/t 1 v/div vert.
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 19/ 24 ssi interface after each communication cycle the ssi interface re- turns to its idle state when the mono?op timeout t tos has elapsed. this temporal condition also determines up to which clock line pause duration the ic-nql re- tains the current data output cycle - the master may thus not undershoot a minimum clock frequency of f(clk)min. cfgtos adr 0x06, bit 5:4 code timeout t tos ref. clock counts f(clk) min* design ic-nql_x3: 0x00 typ. 128 s 256-259 11 khz 0x01 typ. 16 s 32-35 88 khz 0x02 typ. 4 s 8-11 352 khz 0x03 typ. 1 s 2-5 1.41 mhz design ic-nql_3: 0x00 typ. 20 s 46-46 50 khz 0x01 typ. 20 s 46-47 50 khz 0x02 typ. 1.5 s 3-4 660 khz 0x03 typ. 1.5 s 3-4 660 mhz notes a ref. clock count is equal to 32 fosc (see el. char., a01). the permissible max. clock frequency is speci?ed by e05. *) a low clock frequency can reduce the permissible maximum input frequency since conversion is paused after the ?rst falling edge on clk for a half clock cycle. table 31: mono?op time (ssi timeout) the ic-nql position data output contains the angle value (s) with a bit length of 2 to 13 bits (depending on selres), and up to 3 add-on bits (error messages e1 and e0 plus a zero bit). generally, the data output is in binary format starting with the msb. signal names name description s sensor data (s0 is lsb) e error messages stop low signal table 32: signal names the angle conversion is halted for a half clock cycle as soon as the interface receives the ?rst falling edge on clk, what is the trigger signal to output updated posi- tion data. the halt duration must be taken into consid- eration when calculating the maximum input frequency. cfgssi adr 0x03, bit 7:6 code additional bits ring register operation 0x00 e1, e0, zero bit no 0x01 none no 0x02 not permissible 0x03 none yes table 33: ssi output options figure 15: ssi output format during ring register operation. the example displays the transmission of a 13-bit angle value; er- ror messages are switched off herein (selres = 0x03, cfgssi = 0x03) ssi output formats res mode error crc t1 t2 t3 t4... t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 10 bit ssi x - s9 s8 s7 s6 ... s0 e1 e0 0 stop stop stop stop stop stop stop stop stop stop stop stop example 0 0 0 0 0 0 0 0 0 0 0 0 0 13 bit ssi *1 - - s12 s11 s10 s9 ... s3 s2 s1 s0 stop stop stop stop stop stop stop stop stop stop stop stop example 0 0 0 0 0 0 0 0 0 0 0 0 ssi-r *2 - - s12 s11 s10 s9 ... s3 s2 s1 s0 stop s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 example 0 con?guration cfgssi = 0x00; *1) cfgssi = 0x01; *2) cfgssi = 0x03 legend ssi = ssi protocol, ssi-r = ssi ring register operation table 34: ssi output formats clk da t a s12 s0 stop s12 s0 stop msb lsb msb lsb cycle latch t imeout
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 20/ 24 eeprom interface and startup behaviour serial eeprom components permitting operation from 3.3 v to 5 v can be connected (such as 24c02, for example). when the device is switched on the memory area of bytes 0 to 15 is mapped onto ic-nqls regis- ters. after the supply has been turned on (power on reset), ic-nql reads the con?guration data from the eep- rom and during this phase halts error pin nerr ac- tively on a low signal (open drain output). after a successful crc the data output to slo is re- leased and the error indication at pin nerr reset; an external pull-up resistor can supply a high signal. ic-nql then switches to normal operation and deter- mines the current angle position, providing that a sen- sor is connected up to it and there is no amplitude error (or this is deactivated). should the crc prove unsuccessful due to a data er- ror (disrupted transmission, no eeprom or the eep- rom is not programmed), the con?guration phase is automatically repeated. after a third failed attempt, the procedure is aborted and error pin nerr remains ac- tive, displaying a permanent low. after startup, ic-nql does not recognize a de?ned con?guration; the con?guration ram can contain any values. example of crc calculation routine unsigned char ucdatastream = 0 ; i n t icrcpoly = 0x127 ; unsigned char uccrc=0; i n t i = 0 ; uccrc = 0 ; / / s t a r t v a l u e ! ! ! f o r ( ireg = 0 ; ireg <15; ireg ++) { ucdatastream = ucgetvalue ( ireg ) ; f o r ( i =0; i <=7; i ++) { i f ( ( uccrc & 0x80 ) ! = ( ucdatastream & 0x80 ) ) uccrc = (uccrc << 1 ) ^ icrcpoly ; else uccrc = (uccrc << 1 ) ; ucdatastream = ucdatastream << 1 ; } } crc_e2p adr 0x0f, bit 7:0 code description 0x00 ... check value formed by crc polynomial 0x127 0xff table 35: check value for eeprom data
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 21/ 24 application hints principle input circuits figure 16: input circuit for voltage signals of 1 vpp with no ground reference. when grounds are not separated the connection nsin to vref must be omitted. figure 17: input circuit for current signals of 11 a. this circuit does not permit offset calibra- tion. figure 18: input circuit for single-sided voltage or current source signals with ground refer- ence (adaptation via resistors r3, r4). figure 19: simpli?ed input wiring for single-sided voltage signals with ground reference. figure 20: input circuit for differential current sink sensor outputs, eg. using opto encoder ic-wg. figure 21: combined input circuit for 11 a, 1 vpp (with 120
termination) or ttl encoder signals. rs3/4 and cs1 serve as protec- tion against esd and transients.
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 22/ 24 basic circuit figure 22: basic circuit for evaluation of magneto-resistor bridge sensors.
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 23/ 24 design review: notes on chip functions ic-nql x3 no. function, parameter/code description and application hints 1 zpos illegal settings: 0x01...0x07, 0x09...0x0f, 0x11...0x17, 0x19...0x1f illegal settings of zpos delay accurate converter operation following power on. depending on the sin/cos input signals (phase angle) the a/b outputs can provide pulses causing an external counter to alternately count up and down. this may disturb the startup of a drive if the motion controller tolerates only single a/b edges during standstill checking. the converter operation is again accurate when the sin/cos input signals have changed, by a maximum of 45 angular degrees. 2 pin data when cycling power pin data may show high or low level initially. with pin test = low (e.g. pin open) at least a single low pulse at pin clk is required to trigger pin data to show a high level after the timeout has elapsed. when continuing the clock signal after completion of data output, additional zero bits are output. with pin test = high (e.g. pin wired to vdd) only the timeout needs to elapse to trigger pin data showing high level. when continuing the clock signal after completion of data output, additional one bits are output. 3 m2s obsolete bits 5 to 7 of address 0x00 must be programmed to zero; period counting is not available. table 36: notes on chip functions ic-nql_x3 ic-nql 3 no. function, parameter/code description and application hints 1 pin data when cycling power pin data shows high level initially and remains on a permanent high if crc veri?cation does not con?rm the con?guration data. 3 m2s obsolete bits 5 to 7 of address 0x00 must be programmed to zero; period counting is not available. table 37: notes on chip functions ic-nql_3 ic-haus expressly reserves the right to change its products and/or speci?cations. an info letter gives details as to any amendments and additions made to the relevant current speci?cations on our internet website www.ichaus.de/infoletter ; this letter is generated automatically and shall be sent to registered users by email. copying C even as an excerpt C is only permitted with ic-haus approval in writing and precise reference to source. ic-haus does not warrant the accuracy, completeness or timeliness of the speci?cation and does not assume liability for any errors or omissions in these materials. the data speci?ed is intended solely for the purpose of product description. no representations or warranties, either express or implied, of merchantability, ?tness for a particular purpose or of any other nature are made hereunder with respect to information/speci?cation or the products to which information refers and no guarantee with respect to compliance to the intended use is given. in particular, this also applies to the stated possible applications or areas of applications of the product. ic-haus conveys no patent, copyright, mask work right or other trade mark right to this product. ic-haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. as a general rule our developments, ips, principle circuitry and range of integrated circuits are suitable and speci?cally designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. in principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the bureau of statistics in wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in hanover (hannover-messe). we understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to.
ic-nql 13-bit sin/d converter with ssi interface rev d2, page 24/ 24 ordering information type package order designation ic-nql tssop20 4.4 mm ic-nql tssop20 for technical support, information about prices and terms of delivery please contact: ic-haus gmbh tel.: +49 (61 35) 92 92-0 am kuemmerling 18 fax: +49 (61 35) 92 92-192 d-55294 bodenheim web: http://www.ichaus.com germany e-mail: sales@ichaus.com appointed local distributors: http://www.ichaus.com/sales_partners

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