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1 ? fn6068.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2004. all rights reserved. "ipot" and the "ipot design" are trademarks of intersil americas. all other trademarks mentioned are the property of their respective owners. isl45021 256-tap non-volatile digital potentiometer the ipot? isl45021 dcp is a 256-tap, single-channel non-volatile digital potentiometer available in 10k ? , 50k ? and 100k ? end-to-end resistances. these devices can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications. the output of the potentiomete r is determined by the wiper position, which varies linearly between va and vb terminal according to the content stored in the volatile tap register (tr). the settings of the tr can be provided either directly by the user through the industry standard spi interface, or by the non-volatile memory (nvmem0~3) where the previous settings are stored. when changes are made to the tr to establish a new wiper posi tion, the value of the setting can be saved into any non-volatile memory location (nvmem0~3) by executing a nvmem save operation. upon powerup the content of the nvme m0 is automatically loaded to the tap register. the isl45021 contains a single potentiometer in 8-pin pdip, soic, msop or 10 pin tssop packages and can operate over a wide operating voltage range from 2.7v to 5.5v. a selectable output buffer is bu ilt-in for those applications where an output buffer is required. features ? 256 taps for the potentiometer ? end-to-end resistance available in 10k ? , 50k ? and 100k ? ? selectable output buffer for each channel ? spi serial interface for data transfer and potentiometer control ? daisy-chain operation for mu ltiple devices (10-pin tssop package only) ? nonvolatile storage of four wiper positions per channel with power-on recall from nvmem0 ? low standby current (1a max. with output buffer inactive) ? endurance 100k typical stores per bit ? register data retention 100 years ? industrial temperature range: -40c ~ 85c ? wide operating voltage range: 2.7v ~ 5.5v ? package options: - 8-pin msop, 8-pin soic, 8-pin pdip ordering information output buffer end-to-end resistance soic pdip msop temp. range (c) yes 10k ISL45021IB01 isl45021ip01 isl45021iu01 -40 to 85 50k isl45021ib05 isl45021ip05 isl45021iu05 -40 to 85 100k isl45021ib10 isl45021ip10 isl45021iu10 -40 to 85 data sheet march 2004
2 pinouts (msop) top view (pdip) top view (soic) top view cs clk sdi v ss 1 2 3 4 8 7 6 5 v dd va1 vw1 vb1 cs clk sdi v ss 1 2 3 4 8 7 6 5 v dd va1 vw1 vb1 cs clk sdi v ss 1 2 3 4 8 7 6 5 v dd va1 vw1 vb1 pin description pin name pin no i/o description clk 2 i serial clock pin. data shifts in one bit at a time on positive clock (clk) edges cs 1i chip select pin. when cs is high, isl45021 is deselected and the sdo pin is at high impedance, and (unless an internal write cycle is underway) t he device will be in the standby state. cs low enables isl45021, placing it in the active power mode. it shoul d be noted that after a power-up, a high to low transition on cs is required prior to the start of any operation. sdi 3 i serial data input pin. all opcodes, byte addresses and data to be written to the registers are input on this pin. data is latched by the rising edge of the serial clock. sdo (note) nc o serial data output pin with open-drain output. during a read cycle, data is shifted out on this pin. data is clocked out by the falling edge of the serial clock except for the 1 st bit, which is clocke d out by the falling edge of cs . also can be used to daisy-chain several parts. wp (note) nc i hardware write protect pin. when active low wp prevents any changes to the present contents except retrieving nvmem contents. (only 10-pin tssop package) v dd 8 - power supply v ss 4 - ground pin, logic ground reference va1 7 - a terminal of potentiometer ?1?, equivalent to t he hi terminal connection on a mechanical potentiometer vb1 5 - b terminal of potentiometer ?1?, equivalent to t he lo terminal connection on a mechanical potentiometer vw1 6 o wiper terminal of potentiometer ?1?, equivalent to the wiper terminal of a mechanical potentiometer note: available in 10-pin tssop packages only. isl45021
3 block diagram note: available in 10-pin tssop packages only. figure 1. isl45021 block diagram serial interface tap register decoder power on/preset mem tap nv memory nv memory control cs sdi v dd clk vb1 v ss vw1 va1 + - (note) wp (note) sdo mux 9 th bit 3 addressable preset tap values 9 th bit isl45021
4 absolute maximum rati ngs thermal information voltage applied to any pad . . . . . . . . .(v ss ? 0.3v) to (v dd + 0.3v) v dd ? v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 7.0v operating conditions industrial operating temperature . . . . . . . . . . . . . . .-40c to +85c supply voltage (vdd) . . . . . . . . . . . . . . . . . . . . . . . . +2.7v to +5.5v ground voltage (vss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v thermal resistance (typical) ja (0m/s air velocity) msop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 maximum junction temperature (plastic package) . . . . . . . . 150c maximum storage temperature range . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 235c (soic, lead tips only) caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. electrical specifications v dd : 2.7v ~ 5.5v; temp: -40c ~ 85c; typical values: v dd = 5v and t = 25c, unless otherwise specified parameter symbol conditions min. typ max. units rheostat mode nominal resistance r t = 25c, v w open -20 +20 % different non linearity dnl -1 0.3 +1 lsb integral non linearity inl -1 0.5 +1 lsb rheostat tempco (note 1) ? r ab / ? t 200 ppm/ c wiper resistance (note 2) r w v dd = 5v, i = v dd /r total 50 100 ? v dd = 2.7v, i = v dd /r total 80 120 ? potentiometer mode resolution (note 1) n 8 bits different non line arity (note 2) dnl -1 +1 lsb integral non linearity inl -1 +1 lsb potentiometer tempco (note 1) ? v w / ? t code = 80h +20 ppm/ c full scale error v fse code = full scale -1 0 lsb zero scale error v zse code = zero scale 0 1 lsb resistor terminal voltage range (note 1) v a ,v b ,v w v ss v dd v terminal capacitance (note 1) c a , c b 30 pf wiper capacitance (note 1) 30 pf dynamic characteristics (note 1) bw 10k v dd = 5v, v b = v ss code = full scale 1.5 mhz bandwidth ?3db bw 50k code = 80h 300 khz bw 100k cl = 30pf 200 khz settling time to 1 lsb t s v dd = 5.5v = v a , v b = v ss 80 100 s analog output (buffer enabled) amp output current (note 2) i out v o = 1/2 scale 3 ma amp output resistance (note 2) rout 1 10 ? total harmonic distortion (note 1) thd v a = 2.5v, v dd = 5v, f = 1khz, v in = 1v rms 0.08 % isl45021
5 functional description the isl45021 series, a family of 256-tap, nonvolatile digitally programmable potentiometers is designed to operate as both a potentiometer or a variable resistor depending upon the output configuration selected. the chip can store four 9-bit words in nonvolatile memory (nvmem0 ~ nvmem3) and the word stored in the nvmem0 will be used to set the tap register values when the device is powered up. the isl45021 is controlled by a serial spi interface that allows setting tap register value as well as storing data in the nonvolatile memory. potentiometer and rheostat modes the isl45021 can operate as either a rheostat or as a potentiometer (voltage divider). when in the potentiometer configuration there are two po ssible modes. one is without the output buffer and the ot her mode is with the output buffer. selecting the mode is done by controlling bit d8 of the data register. d8 = 0 sets the output buffer off and d8 = 1 sets it on. note that this bit can only be set by loading the value to the nvmem with instructions #5 and then loading the tap register with instruction #6 from nvmem. this bit cannot be controlled by directly writing the value to the chip when the tap register is set. rheostat configuration the isl45021 acts as a two terminal resistive element in the rheostat configuration where one terminal is either one of the end point pins of the resist or (va and vb) and the other terminal is the wiper (vw) pin. this configuration controls the resistance between the two termi nals and the resistance can be adjusted by sending the corresponding tap register setting commands to the isl45021 or loading a pre-set tap register value from nonvolatile memory nvmem0 ~ mvmem3. potentiometer configuration in potentiometer conf iguration an input vo ltage is connected to one of the end point pins (va or vb). the voltage on the wiper pin will be proportional to the voltage difference between va and vb and the wiper setting. the resistance cannot be directly measured in this configuration. digital inputs/outputs input high voltage v ih 0.7v dd v input low voltage v il 0.3v dd v output low voltage v ol i ol = 2ma 0.4 v input leakage current i li cs = v dd , vin = vss ~ v dd -1 +1 a output leakage current i lo cs = v dd , vin = v ss ~ v dd -1 +1 a input capacitance (note 1) c in v dd = 5v, fc = 1mhz code = 80h 25 pf output capacitance (note 1) c out v dd = 5v, fc = 1mhz code = 80h 25 pf power requirements operating voltage (note 1) v dd 2.7 5.5 v operating current i ddr all ops except nvmem program 1 1.8 ma operating current i ddw during non-volatile memory program 1 2 ma standby current i sa buffer is active, no load 0.5 1 ma i sb (note 2) buffer is inactive, power down, no load 0.1 1 a power supply rejection ratio psrr v dd = 5v 10%, code = 80h 1 lsb/v notes: 1. not subject to production test. 2. only on final test. 3. v dd = +2.7v to 5.5v, v ss = 0v, t = 25c, unless otherwise noted. electrical specifications v dd : 2.7v ~ 5.5v; temp: -40c ~ 85c; typical values: v dd = 5v and t = 25c, unless otherwise specified (continued) parameter symbol conditions min. typ max. units isl45021
6 programming modes two program modes are available for the isl45021: direct program mode . the tap register setting can be changed either by loading a predetermined value from an external microcontroller or by using the up/down command. the up and down commands change the tap register setting incrementally i.e., 1 lsb at a time. the up and down commands will not wr ap around at the ends of the scale. nvmem restore mode . one of the previously stored settings can be loaded into the tr register from the non- volatile memory. four 9-bit non-volatile memories, are available for to store the tap register settings. the first register, nvmem0, stores the fa vorite or default tap register setting that will be loaded into the tap register at system power up or software power on reset operation. non-volatile memory (nvmem) the isl45021 has four nvmem positions available for storing the output buffer operating mode and the potentiometer setting. these nvmem positions can be directly written through the spi using a write command (#5) with address and data bytes. another command (#7) is available that stores the curr ent output buffer operating mode and potentiometer settings into the selected nvmem position. bit a3 and a2 in the instruction byte decide which nvmem position is used. (see table 4). the potentiometer is loaded with the value stored in the nvmem position 0 on power up. write protect of nvmem write-protect (wp ) disables any changes of current content in the nvmem regardless of the commands, except that nvmem setting can be retrieved using commands 4, 6 of table 4. therefore, write-protect (wp ) pin provides hardware nvmem protection feature with wp tied to vss. wp , which is active at logic low, should be tied directly to v dd if it is not being used. this function is only available on the 10-pin package. flow control reading and writing to nvmem requires an internal access cycle to complete before the next command can be sent. ? read tap register (#2) ? read nvmem (#4) ? program nvmem (#5) ? load tap register (#6) ? program nvmem with tap register (#7) daisy chain multiple devices can be controlled by the same bus without the need for extra cs lines from the microcontroller by daisy chaining the devices with th e sdo of the first device connected to sdi of the next device as shown in figure 3 when using the 10-pin package. a complete command is 24 bits including the instruction and the two data bytes. when shifting 24 bits in to the first device in the chain, the 24 bits of the previous command will be shifted out. so to set up two devices in a daisy chain, a total of 48 bits must be sent where t he first 24 bits will be shifted out to the second device and the 24 bits shifted in last will remain in the first device. 1. command and data for device 2 is shifted into device 1, this will propagate to device 2 when the next 24 bits are shifted in. 2. command and data for device 1 is shifted into device 1. now device 1 and 2 are correctly set up. 10-pin tssop package only. figure 2. device 2 device 1 xx xx xx data 2 b data 2 a command 1 device 1 device 2 data 2 b data 2 a command 1 data 1 b data 1 a command 2 cs clk v dd sdo sdi sdo clk cs cs clk sdo sdi cs clk sdo sdi device 1 device 2 device n micro controller figure 3. daisy chain configuration (10 pin tssop package only) isl45021
7 serial data interface the isl45021 contains a four-wire spi interface: ? sdo (serial data output) used for reading out the internal register contents and for daisy chaining multiple devices on the 10-pin package. ? sdi (serial data input) used for clocking in commands and potentiometer settings. ? cs (chip select) this pin must be pulled low before starting to send a command and pulled high to signal the end of the command; this pin can be used to control multiple devices on the bus. ? clk (clock) the sdi bits are shifted in on the rising edge of the clock and sdo data is shifted out on the falling edge of the clock. the key features of this interface include: ? independently programmable r ead & write to all registers ? direct parallel refresh of tap register from corresponding internal nvmem registers ? increment and decrement instruction for tap register ? nonvolatile storage of the present tap register values into one of the four nvmem registers available ? configurable output buffer amplifier to allow both the functions of a potentiometer and a variable resistor ? four 9-bit non-volatile registers store four preset wiper positions and the first one will be recalled to set the wiper position during power up. the serial interface uses an spi compatible uniform 24-bit word format as shown in table 3. this format is used for all members of the isl45021 family. the data is sent msb first. c3-c0 are the command bits that control the operation of the digital potentiometer accordin g to the command instructions shown in table 4 in the instruction set section. a1 and a0 are the address bits that determine which channel is activated in the wm s720x family as shown in the table below. for the isl45021 a0 and a1 are always set to 0. a3 and a2 are the address bits that decide which nvmem memory to be accessed, as shown in table 2. d7-d0 are the data values to be loaded into the tap register to set the wiper position, while d8 is used to set the output mode. d8 has to be loaded into the nvmem0~3 first and then the ? load tap register ? command (#6) has be executed to load d8 into the output-selection mux to set the output mode. d8 = 0 sets the output to buffer off mode while d8 = 1 sets to buffer on mode. table 1. a1 and a0 address bit decode table [a1 a0] [0 0] [0 1] [1 0] [1 1] channel 0 1 2 3 table 2. a3 and a2 address bit decode table [a3 a2] [0 0] [0 1] [1 0] [1 1] nvmem 0 1 2 3 table 3. 24-bit data word format msb lsb c3 c2c1c0a3a2a1a0xxxxx x xd8d7d6d5d4d3d2d1 d0 figure 4. spi command waveforms notes: 4. a multiple of 24 bits must always be sent or the command will not be valid. 5. bits marked ?x? are don?t care bits. sdi clk 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 d1 d3 d4 d5 d6 d7 d8 x x x x x x a1 a3 c0 c1 c2 c3 cs is taken high after command is sent cs is taken low before command starts cs a2 a0 x d0 d2 isl45021
8 instruction set basic operation this chapter describes the sequences of commands to send to the isl45021 and how to use the different features. sending a command 1. take the chip out of sleep mode. 2. check that the write protect is set correctly if writing to nvmem (10-pin tssop package only). 3. pull the cs pin low before sending data to the device. 4. 24 clock pulses are sent for each command. sdi must be valid on the rising edge of the clock, sdo is valid on the falling edge of the clock or cs . 5. take cs high after the command has completed 6. if command 2, 4, 5, 6 or 7 is sent, wait t sv time before sending the next command. table 4. instruction set inst no. instruction byte c3 c2 c1 c0 a3 a2 a1 a0 data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 data byte 2 d7 d6 d5 d4 d3 d2 d1 d0 operation 1 0 0 0 0 x x x x x x x x x x x x x x x x x x x x no operation (nop). do nothing 2 1 1 0 0 x x a1 a0 x x x x x x x x x x x x x x x x read tap register and output selection mux register 3 0 1 0 0 x x a1 a0 x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 write to tap register with d7-d0 4 1 0 1 0 a3 a2 a1 a0 x x x x x x x x x x x x x x x x read nvmem pointed to by a3-a0 5 0 0 1 0 a3 a2 a1 a0 x x x x x x x d8 d7 d6 d5 d4 d3 d2 d1 d0 program nvmem pointed to by a3- a0 with d8-d0 6 1 0 1 1 a3 a2 a1 a0 x x x x x x x x x x x x x x x x load tap register and output selection mux register with the contents of nvmem pointed to by a3-a0 7 0 0 1 1 a3 a2 a1 a0 x x x x x x x x x x x x x x x x program nvmem pointed to by a3- a0 with the contents of tap register and output selection mux register 8 0 1 1 1 x x a1 a0 x x x x x x x x x x x x x x x x up : increment setting of tr by one tap 9 1 1 1 1 x x a1 a0 x x x x x x x x x x x x x x x x down : decrement setting of tr by one tap 10 1 0 0 0 x x x x x x x x x x x x x x x x x x x x sleep : discontinue clock supply to the logic and memories 11 0 0 0 1 x x x x x x x x x x x x x x x x x x x x wake up : clock supply to the logic and memories 12 1 1 0 1 a3 a2 a1 a0 x x x x x x x x x x x x x x x xy byte-erase nvmem pointed to by a3-a0 13 1 0 0 1 x x x x x x x x x x x x x x x x x x x x power on reset : software reset the part to the power up state note: c3-c0 are the command op-code; a3, a2 are the nvmem address; a1, a0 are the channel address. isl45021
9 wake up/sleep/power commands the chip is in sleep mode after: ?v dd is applied ? a power on reset command is sent ? a sleep command is sent before any operations can be performed the wake up command must be sent. when a sleep command is sent, the chip retains its resistor setti ngs as long as the chip is powered up but cannot accept any other commands than a wake up command. write to tap register (tr) the microcontroller can write a value directly into the tap regist er or send an increment or decr ement command to control the t ap register. alternatively, the co ntents of an nvmem location can be written to th e tap register. the only way to change the outpu t buffer mode is to write the desired value of bit d8 into an nvme m location and then load the corresponding nvmem location into the tap register. programming non-volatile memory (nvmem) the value stored in the nvmem location is 9 bits, the 8 bits (d7- d0) of the tap register plus 1 bit (d8) of the output buffer m ode. the nvmem position must be erased bef ore writing to it. there are two wa ys to program a value into nvmem. write a value directly fr om the microcontroller. load the current potentiometer setting into nvmem. table 5. power related commands inst. no. command name command byte data byte 1 data byte 2 comment 11 wake up 0 0 0 1 x x x x x x x x x x x x x x x x x x x x wake up entire chip 10 sleep 1 0 0 0 x x x x x x x x x x x x x x x x x x x x send chip into power save mode 13 power on reset 1 0 0 1 x x x x x x x x x x x x x x x x x x x x reset chip 1 nop 0 0 0 0 x x x x x x x x x x x x x x x x x x x x dummy instruction the commands above control the entire chip. table 6. writing to the tap registers inst. no. command name command byte data byte 1 data byte 2 comment 3 write to tap register 0 1 0 0 x x 0 0 x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 writes a value to the tap register. 8 up 0 1 1 1 x x 0 0 x x x x x x x x x x x x x x x x increment tap register value by one 9 down 1 1 1 1 x x 0 0 x x x x x x x x x x x x x x x x decrement tap register value by one 6 load tap register 1 0 1 1 a3 a2 0 0 x x x x x x x x x x x x x x x x load the selected nvmem location into the tap register table 7. programming nvmem inst. no command name command byte data byte 1 data byte 2 comment 12 erase nvmem 1 1 0 1 a3 a2 0 0 x x x x x x x x x x x x x x x x erases the 9 bit word pointed to by a3, a2, a1 and a0. 5 program nvmem 0 0 1 0 a3 a2 0 0 x x x x x x x d8 d7 d6 d5 d4 d3 d2 d1 d0 writes a value to the nvmem register. 7 program nvmem with tap register 0 0 1 1 a3 a2 0 0 x x x x x x x x x x x x x x x x takes the current potentiometer settings and saves in the selected nvmem location. for programming nvmem, the following sequence must be followed: 1. erase word at nvmem location. 2. program word at nvmem location. isl45021
10 reading tap register and nvmem locat ion (10-pin tssop package only) the contents of the tap register or any nv mem location can be read back through the sdo pin. when a command is sent, the data i s clocked out on the falling edge of the clock. since daisy-chain operation requires data from one command to be clocked out when the next command arrives, any read command must be followed by another command to get the correct data on the sdo pin. timing diagrams table 8. reading the tap register inst. no. command name command byte data byte 1 data byte 2 comment 4 read nvmem 1 0 1 0 a3 a2 0 0 x x x x x x x x x x x x x x x x read the value of the selected nvmem location 2 read tap register 1 1 0 0 x x 0 0 x x x x x x x x x x x x x x x x read the value of the selected tap register 1 nop to read register 0 0 0 0 x x x x x x x x x x x d8 d7 d6 d5 d4 d3 d2 d1 d0 output data to sdo pin to read the contents of either the t ap register or a nvmem location, the following sequence must be followed. 1. send the desired read command (#2 or #4) 2. send another command such as nop and read the sdo pin on the falling edge of the clock. the other command could be any command, but to make sure that the chip does not change anything, send either another read command or a nop command (#1). figure 5. isl45021 timing diagram notes: 6. internal signal only. 7. only on 10-pin tssop package. t lead t cyc t wl t wh t lag t cs t dh t dsu t lac t pd t lrl t rsu t st t sv clk cs sdi sdo r/b t wpsu t wph wp msb lsb msb lsb (note 6) (note 7) isl45021
11 timing parameters parameter symbol min max unit spi clock high time t wh 50 ns spi clock low time t wl 50 ns lead time t lead 100 ns lag time t lag 100 ns sdi setup time t dsu 20 ns sdi hold time t dh 20 ns cs to sdo ? spi line acquire (note 9) t lac 5 ns cs to sdo ? spi line r elease (note 9) t lrl 5 ns clk to sdo propagation delay (note 9) t pd 1ns store to nvmem save time t sv 2 ms cs deselect time t cs 600 ns startup time t st 0.1 ms wp setup time (note 9) t wpsu 10 ns wp hold time (note 9) t wph 10 ns notes: 8. the interface timing characteristics apply to all parts bu t are guaranteed by design and not subject to production test. 9. 10 pin package only. isl45021
12 test circuits figure 6. potentiometer divider nonlinearity error test circuit (inl, dnl) figure 7. power supply sensitivity test circuit (pss, psrr) figure 8. resistor positi on nonlinearity error test circuit (rheostat operation: r-inl, r-dnl) figure 9. capacitance test circuit figure 10. wiper resistance test circuit figure 11. gain vs frequency test circuit v w v a isl45021 v b v+ = v dd 1 lsb = v+/255 v ms * v+ *assume infinite input impedance v w v a isl45021 v b v + = v dd 10% v ms * *assume infinite input impedance v + psrr(db) 20log ? v ms ? v dd ----------------- = pss(%%) ? v ms ? v dd ----------------- = v w v a isl45021 v b v ms * *assume infinite input impedance i w no connection v out 2.5v dc offset +5v ~ v in v w v b v a isl45021 w v w v a isl45021 v b v ms * *assume infinite input impedance i w i w = v dd /r total r w = v ms /i w offset gnd v out 2.5v dc +5v ~ v in v w v b v a isl45021 isl45021
13 i typical application circuits figure 12. programmable in verting gain amplifier using the isl45021 figure 13. programmable non-inverting gain amplifier using the isl45021 figure 14. isl45021 trimming voltage reference figure 15. isl45021 rf amp control r ab = total resistance of potentiometer. w = wiper setting for isl45021 v out v ? in r b r a --------- - = r a r ab 256-d () 256 ----------------------------------- - , r b r ab d ? 256 --------------------- - = = v in r a r b isl45021 v out op amp + _ r ab = total resistance of potentiometer. w = wiper setting for isl45021 v out v in 1 r b r a --------- - + ?? ?? ?? = r a r ab 256-d () 256 ---------------------------------- , r b r ab d ? 256 --------------------- - = = v in r a r b isl45021 v out op amp + _ gnd v ref = 5.0v v+ isl45021 v refh i = 32ma clk sdi cs c2 c1 0.1f rf power amp q1 rf out rf input va1 v dd vw1 vb1 cs clk sdi v ss isl45021 l1 choke filter 1 2 3 45 6 7 8 vdd isl45021
14 layout considerations a 0.1 f bypass capacitor as close as possible to the v dd pin is recommended for best per formance. often this can be done by placing the surface mount capacitor on the bottom side of the pc board, directly between the v dd and v ss pins. care should be taken to separate the analog and digital traces. sensitive traces should not run under the device or close to the bypass capacitors. a dedicated plane for analog ground helps in reducing ground noise for sensitive analog signals. figure 16. isl45021 layout isl45021
15 mini small outline pl astic packages (msop) 8 lead 3mm msop isl45021
16 dual-in-line plastic packages (pdip) 8 lead 300mil pdip 1.63 1.47 0.064 0.058 symbol min nom max max nom min dimension in inch dimension in mm a b c d e a l s a a 1 2 e 0.060 1.52 0.175 4.45 0.010 0.125 0.016 0.130 0.018 0.135 0.022 3.18 0.41 0.25 3.30 0.46 3.43 0.56 0.008 0.120 0.375 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.255 0.250 0.245 6.48 6.35 6.22 9.53 7.62 7.37 7.87 0.300 0.290 0.310 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 0.360 0.380 9.14 9.65 0 15 0.045 1.14 0.355 0.335 8.51 9.02 15 0 seating plane e a 2 a c e base plane 1 a 1 e l a s 1 e d 1 b b 8 5 1 4 isl45021
17 small outline plast ic packages (soic) 8 lead 150mil soic e 1 8 5 4 control demensions are in milmeters . e e millimeters. isl45021
18 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality ce rtifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that da ta sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com isl45021 thin shrink small outlin e plastic packages (tssop) 10 lead tssop n e e d g r a p h i c

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