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| vrs51l3xxx datasheet rev 2.01 ramtron international corporation ? http://www.ramtron.com 1850 ramtron drive colorado springs ? mcuinfo@ramtron.com colorado, usa, 80921 ? 1-800-545-fram, 1-719-481-7000 page 1 of 115 high-performance 8051 mcu + f-ram overview the vrs51l3xxx constitute a family of high performance, 8051- based microcontrollers coupled with a fully integrated array of peripherals for addressing a br oad range of embedded design applications. based on a powerful 40-mips, single-cycle, 8051 microprocessor, these mcu?s memory sub-system features 64kb of flash and 4352 bytes of sram and 8192 or 2048 bytes of nonvolatile fram (ferroelectric random access memory ) memory. support peripherals include a hardwar e based arithmetic unit capable of performing complex mathematical operations, a jtag interface for flash programming and non-intrusive in-circuit debugging/emulation, an internal oscillator, and a watchdog timer. communication and control of external devices is facilitated via an assortment of digital peripher als such as an enhanced, fully configurable spi bus, an i2c interf ace, dual uarts with dedicated baud rate generators, three 16-bit timers, 8 pwm controllers each with a 16-bit timer, and 2 pulse width counter modules. the vrs51l3xxx devices operate fr om 3.0 to 3.6 volts over the industrial temperature range and are available in qfp-64 (30xx) and qfp-44 (31xx) packages. f igure 1: vrs51l30 xx / 31 xx f unctional d iagram feature set o 8051 high performance single cycle processor (operation up to 40 mips) o 64kb flash program memory (in-system/ln-application programmable) o 4352 bytes of sram (4kb + 256) (ext. 4kb can be used for program or data memory) o 8192 / 2048 bytes of on-chip f-ram memory o jtag interface for flash programming and non-intrusive debugging/in-circuit emulation o mult/div/accu unit including barrel shifter o 56 / 40 general purpose i/os (64/44-pin version) o 2 serial uarts/2 baud rate generators (20-bit) o enhanced spi interface (fully configurable word size) o fully configurable i 2 c interface (master/slave) o 16 external interrupt pins/interrupt on port pin change o 16-bit general purpose timer/counters o 2 pulse width counter modules o 8 pwm controller outputs with individual timers o pwms can be used as g eneral purpose timers o internal oscillator o dynamic system clock frequency adjustment o power saving features o power-on reset/brown-out detect o watchdog timer o operating voltage: 3.0v to 3.6v o operating temperature -40c to +85c f igure 2: vrs51l30 xx ( qfp-64 ) / vrs51l31 xx (qfp-44)
vrs51l3xxx datasheet rev 2.01 ramtron international corporation ? http://www.ramtron.com 1850 ramtron drive colorado springs ? mcuinfo@ramtron.com colorado, usa, 80921 ? 1-800-545-fram, 1-719-481-7000 page 2 of 115 vrs51l30xx (qfp-64) pin description t able 1: vrs51l30 xx p in d escriptions for qfp-64 package qfp - 64 name i/o function p1.5 i/o port 1.5 1 sdo o spi data output p1.6 i/o port 1.6 sck o spi clock scl* i/o i2c clock (alternate pin) 2 pc1.3 i pulse counter pc1 input 3 p1.7 i/o port p1.7 sdi i spi data input 3 sda* i/o i2c data (alternate pin) 4 reset i reset p3.0 i/o port 3.0 rxd0 i uart0 rx pin 5 pc0.1 i pulse counter pc0 input 1 p4.5 i/o port 4.5 6 t0out o timer 0 output p5.0 i/o port 5.0 7 pwm0* o pwm0 output (alternate pin) p5.1 i/o port 5.1 8 pwm1* o pwm1 output (alternate pin) p5.2 i/o port 5.2 9 pwm2* o pwm2 output (alternate pin) p5.3 i/o port 5.3 10 pwm3* o pwm3 output (alternate pin) 11 vss gnd device ground p3.1 i/o port 3.1 12 txd0 o uart0 tx pin p3.2 i/o port 3.2 int0 i interrupt 0 input 13 pc0.0 pulse counter pc0 input 0 p3.3 i/o port 3.3 int1 i interrupt 1 input 14 pc1.0 pulse counter pc1 input 0 p3.4 i/o port 3.4 scl i/o i2c clock t0in i timer 0 input pc0.3 i pulse counter pc0 input 3 15 exbr0 i uart0 external baud rate input p3.5 i/o port 3.5 sda i/o i2c data t1in i timer 1 input 16 exbr1 i uart1 external baud rate input p3.6 i/o port 3.6 17 wr o ext data memory access write signal (active low) p3.7 i/o port 3.7 18 rd o ext data memory access read signal (active low) 19 vdd vdd positive supply p5.4 port 5.4 20 pwm4* o pwm4 output (alternate pin) p5.5 port 5.5 21 pwm5* o pwm5 output (alternate pin) p5.6 port 5.6 22 pwm6* o pwm6 output (alternate pin) p5.7 port 5.7 23 pwm7* o pwm7 output (alternate pin) qfp - 64 name i/o function xtal1 o crystal oscillator (output) 24 p4.6 i/o port 4.6 xtal2 i crystal oscillator (input) 25 p4.7 i/o port 4.7 26 vss gnd device ground p4.0 i/o port 4.0 27 t1out o timer 1 output p2.0 i/o port 2.0 pwm0 o pwm0 output 28 a8 o ext. address bus a8 p2.1 i/o port 2.1 pwm1 o pwm1 output 29 a9 o ext. address bus a9 p2.2 i/o port 2.2 pwm2 o pwm2 output 30 a10 o ext. address bus a10 p2.3 i/o port 2.3 pwm3 o pwm3 output txd0* o uart0 tx pin (alternate pin ) 31 a11 o ext. address bus a11 p2.4 i/o port 2.4 pwm4 o pwm4 output rxd0* i uart0 rx pin (alternate pin) pc0.2 i pulse counter pc0 input 2 a12 o ext. address bus a12 32 dbcs0 o ext. data bus dbcs0 p2.5 i/o port 2.5 pwm5 o pwm5 output t1ex i timer 1 ex input a13 o ext. address bus a13 33 dbcs1 o ext. data bus dbcs1 p2.6 i/o port 2.6 pwm6 o pwm6 output t0ex i timer 0 ex input a14 o ext. address bus a114 34 dbcs2 o ext. data bus dbcs2 p2.7 i/o port 2.7 pwm7 o pwm7 output tck i jtag tck input 35 dbcs3 o ext. data bus dbcs3 p4.1 i/o port 4.1 36 tms i jtag tms input cm0 i jtag program mode 37 ale o ext address latch enable p4.2 i/o port 4.2 38 tdo o jtag tdo line p4.3 i/o port 4.3 39 tdi i jtag tdi line txd1* o uart1 tx pin (alternate pin) 40 t1ex i timer 1 ex input rxd1* i uart1 rx pin (alternate pin) t0ex i timer 0 ex input 41 pc1.2 i pulse counter pc1 input 2 p6.7 i/o port 6.7 42 a7 o ext. address 7 (non-multiplexed mode) p6.6 i/o port 6.6 43 a6 o ext. address 6 (non-multiplexed mode) p6.5 i/o port 6.5 44 a5 o ext. address 5 (non-multiplexed mode) vrs51l3xxx datasheet www.ramtron.com page 3 of 115 qfp - 64 name i/o function p0.7 i/o port 0.7 45 ad7 i/o ext. address/data bus ad7 p0.6 i/o port 0.6 46 ad6 i/o ext. address/data bus ad6 p0.5 i/o port 0.5 47 ad5 i/o ext. address/data bus ad5 p0.4 i/o port 0.4 48 ad4 i/o ext. address/data bus ad4 p0.3 i/o port 0.3 49 ad3 i/o ext. address/data bus ad3 p0.2 i/o port 0.2 50 ad2 i/o ext. address/data bus ad2 p0.1 i/o port 0.1 51 ad1 i/o ext. address/data bus ad1 p0.0 i/o port 0.0 52 ad0 i/o ext. address/data bus ad0 p6.4 i/o port 6.4 53 a4 o ext. address 4 (non-multiplexed mode) p6.3 i/o port 6.3 54 a3 o ext. address 3 (non-multiplexed mode) p6.2 i/o port 6.2 55 a2 o ext. address 2 (non-multiplexed mode) p6.1 i/o port 6.1 a1 o ext. address 1 (non-multiplexed mode) 56 t2in* i timer 2 input (alternate) p6.0 i/o port 6.0 a0 o ext. address 0 (non-multiplexed mode) 57 t2ex* i timer 2 ex input (alternate) 58 vdd positive supply p4.4 i/o port 4.4 59 t2out o timer 2 output p1.0 i/o port 1.0 cs0 o spi chip select 0 60 t2in i timer 2 input p1.1 i/o port 1.1 cs1 o spi chip select 1 61 t2ex i timer 2 ex input p1.2 i/o port 1.2 cs2 o spi chip select 2 rxd1 i uart1 rx line pc1.1 i pulse counter pc1 input 1 62 t2out o timer 2 output pin (alternate pin) p1.3 i/o port 1.3 cs3 o spi chip select 3 63 txd1 o uart1 tx line p1.4 i/o port 1.4 ss i spi slave select input 64 t1out* o timer 1 output (alternate pin) vrs51l3xxx datasheet www.ramtron.com page 4 of 115 vrs51l31xx (qfp-44) pin description t able 2: vrs51l31 xx p in d escriptions for qfp-44 package qfp - 44 name i/o function p1.5 i/o port 1.5 1 sdo o spi data output p1.6 i/o port 1.6 sck o spi clock scl* i/o i2c clock (alternate pin) 2 pc1.3 i pulse counter pc1 input 3 p1.7 i/o port p1.7 sdi i spi data input 3 sda* i/o i2c data (alternate pin) 4 reset i/o reset p3.0 i/o port 3.0 rxd0 i uart0 rx pin 5 pc0.1 i pulse counter pc0 input 1 p4.5 i/o port 4.5 6 t0out o timer 0 output p3.1 i/o port 3.1 7 txd0 o uart0 tx pin p3.2 i/o port 3.2 int0 i interrupt 0 input 8 pc0.0 p3.3 i/o port 3.3 int1 i interrupt 1 input 9 pc1.0 pulse counter pc1 input 0 p3.4 i/o port 3.4 scl i/o i2c clock t0in i timer 0 input pc0.3 i pulse counter pc0 input 3 10 exbr0 i uart0 external baud rate input p3.5 i/o port 3.5 sda i/o i2c data t1in i timer 1 input 11 exbr1 i uart1 external baud rate input p3.6 i/o port 3.6 12 wr o ext data memory access write signal (active low) p3.7 i/o port 3.7 13 rd o ext data memory access read signal (active low) xtal1 o crystal oscillator (output) 14 p4.6 i/o port 4.6 xtal2 i crystal oscillator (input) 15 p4.7 i/o port 4.7 16 vss gnd device ground p4.0 i/o port 4.0 17 t1out o timer 1 output p2.0 i/o port 2.0 pwm0 o pwm0 output 18 a8 o ext. address bus a8 p2.1 i/o port 2.1 pwm1 o pwm1 output 19 a9 o ext. address bus a9 p2.2 i/o port 2.2 pwm2 o pwm2 output 20 a10 o ext. address bus a10 p2.3 i/o port 2.3 pwm3 o pwm3 output txd0* o uart0 tx pin (alternate pin ) 21 a11 o ext. address bus a11 p2.4 i/o port 2.4 pwm4 o pwm4 output rxd0* i uart0 rx pin (alternate pin) pc0.2 i pulse counter pc0 input 2 a12 o ext. address bus a12 22 dbcs0 o ext. data bus dscs0 p2.5 i/o port 2.5 pwm5 o pwm5 output t1ex i timer 1 ex input a13 o ext. address bus a13 23 dbcs1 o ext. data bus dscs1 p2.6 i/o port 2.6 pwm6 o pwm6 output t0ex i timer 0 ex input a14 o ext. address bus a114 24 dbcs2 o ext. data bus dscs2 p2.7 i/o port 2.7 pwm7 o pwm7 output tck i jtag tck input 25 a15 o ext. address bus a15 dbcs3 o ext. data bus dscs3 p4.1 i/o port 4.1 26 tms i jtag tms input cm0 i jtag program mode 27 ale o ext address latch enable p4.2 i/o port 4.2 28 tdo o jtag tdo line p4.3 i/o port 4.3 29 tdi i jtag tdi line p0.7 i/o port 0.7 30 ad7 i/o ext. address/data bus ad7 p0.6 i/o port 0.6 31 ad6 i/o ext. address/data bus ad6 p0.5 i/o port 0.5 32 ad5 i/o ext. address/data bus ad5 p0.4 i/o port 0.4 33 ad4 i/o ext. address/data bus ad4 p0.3 i/o port 0.3 34 ad3 i/o ext. address/data bus ad3 p0.2 i/o port 0.2 35 ad2 i/o ext. address/data bus ad2 p0.1 i/o port 0.1 36 ad1 i/o ext. address/data bus ad1 p0.0 i/o port 0.0 37 ad0 i/o ext. address/data bus ad0 38 vdd positive supply p4.4 i/o port 4.4 39 t2out o timer 2 output p1.0 i/o port 1.0 cs0 o spi chip select 0 40 t2in i timer 2 input p1.1 i/o port 1.1 cs1 o spi chip select 1 41 t2ex i timer 2 ex input p1.2 i/o port 1.2 cs2 o spi chip select 2 rxd1 i uart1 rx line pc1.1 i pulse counter pc1 input 1 42 t2out o timer 2 output pin (alternate pin) p1.3 i/o port 1.3 cs3 o spi chip select 3 43 txd1 o uart1 tx line p1.4 i/o port 1.4 ss i spi slave select input 44 t1out* timer 1 output (alternate pin) vrs51l3xxx datasheet www.ramtron.com page 5 of 115 1 instruction set the following table describes the instruction set of the vrs51l3xxx. the instructions are binary code-compatible and perform the same functions as industry standard 8051s. t able 3: l egend for i nstruction s et t able symbol function a accumulator rn register r0-r7 direct internal register address @ri internal register pointed to by r0 or r1 (except movx) rel two's complement offset byte bit direct bit address #data 8-bit constant #data 16 16-bit constant addr 16 16-bit destination address addr 11 11-bit destination address t able 4: vrs51l3 xxx i nstruction s et mnemonic description size (bytes) instr. cycles hex code arithmetic instructions add a, rn add register to a 1 2 28h-2fh add a, direct add direct byte to a 2 3 25h add a, @ri add data memory to a 1 3 26h-27h add a, #data add immediate to a 2 2 24h addc a, rn add register to a with carry 1 2 38h-3fh addc a, direct add direct byte to a with carry 2 3 35h addc a, @ri add data memory to a with carry 1 3 36h-37h addc a, #data add immediate to a with carry 2 2 34h subb a, rn subtract register from a with borrow 1 2 98h-9fh subb a, direct subtract direct byte from a with borrow 2 3 95h subb a, @ri subtract data mem from a with borrow 1 3 96h-97h subb a, #data subtract immediate from a with borrow 2 2 94h inc a increment a 1 2 04h inc rn increment register 1 2 08h-0fh inc direct increment direct byte 2 3 05h inc @ri increment data memory 1 3 06h-07h dec a decrement a 1 2 14h dec rn decrement register 1 2 18h-1fh dec direct decrement direct byte 2 3 15h dec @ri decrement data memory 1 3 16h-17h inc dptr increment data pointer 1 2 a3h mul ab multiply a by b 1 2 a4h div ab divide a by b 1 2 84h da a decimal adjust a 1 4 d4h logical instructions anl a, rn and register to a 1 2 58h-5fh anl a, direct and direct byte to a 2 3 55h anl a, @ri and data memory to a 1 3 56h-57h anl a, #data and immediate to a 2 2 54h anl direct, a and a to direct byte 2 3 52h anl direct, #data and immediate data to direct byte 3 3 53h orl a, rn or register to a 1 2 48h-4fh orl a, direct or direct byte to a 2 3 45 orl a, @ri or data memory to a 1 3 46h-47h orl a, #data or immediate to a 2 2 44h orl direct, a or a to direct byte 2 3 42h orl direct, #data or immediate data to direct byte 3 3 43h xrl a, rn exclusive-or register to a 1 2 68h-6fh xrl a, direct exclusive-or direct byte to a 2 3 65h xrl a, @ri exclusive-or data memory to a 1 3 66h-67h xrl a, #data exclusive-or immediate to a 2 2 64h xrl direct, a exclusive-or a to direct byte 2 3 62h xrl direct, #data exclusive-or immediate to direct byte 3 3 63h clr a clear a 1 1 e4h cpl a compliment a 1 1 f4h swap a swap nibbles of a 1 1 c4h rl a rotate a left 1 1 23h rlc a rotate a left through carry 1 1 33h rr a rotate a right 1 1 03h rrc a rotate a right through carry 1 1 13h definitions rn: any of the register r0 to r7 @ri: indirect addressing using register r0 or r1 #data: immediate data provided with instruction #data16: immediate data included with instruction bit: address at the bit level rel: relative address to program counter from +127 to ?128 addr11: 11-bit address range addr16: 16-bit address range #d: immediate data supplied with instruction mnemonic description size (bytes) instr. cycles hex code boolean instruction clr c clear carry bit 1 1 c3h clr bit clear bit 2 4 c2h setb c set carry bit to 1 1 1 d3h setb bit set bit to 1 2 4 d2h cpl c complement carry bit 1 1 b3h cpl bit complement bit 2 4 b2h anl c,bit logical and between carry and bit 2 4 82h anl c,#bit logical and between carry and not bit 2 4 b0h orl c,bit logical orl between carry and bit 2 4 72h orl c,#bit logical orl between carry and not bit 2 4 a0h mov c,bit copy bit value into carry 2 4 a2h mov bit,c copy carry value into bit 2 3 92h data transfer instructions mov a, rn move register to a 1 2 e8h-efh mov a, direct move direct byte to a 2 3 e5h mov a, @ri move data memory to a 1 3 e6h-e7h mov a, #data move immediate to a 2 2 74h mov rn, a move a to register 1 1 f8h-ffh mov rn, direct move direct byte to register 2 3 a8h-afh mov rn, #data move immediate to register 2 2 78h-7fh mov direct, a move a to direct byte 2 3 f5h mov direct, rn move register to direct byte 2 3 88h-8fh mov direct, direct move direct byte to direct byte 3 3 85h mov direct, @ri move data memory to direct byte 2 3 86h-87h mov direct, #data move immediate to direct byte 3 3 75h mov @ri, a move a to data memory 1 2 f6h-f7h mov @ri, direct move direct byte to data memory 2 3 a6h-a7h mov @ri, #data move immediate to data memory 2 2 76h-77h mov dptr, #data move immediate to data pointer 3 3 90h movc a, @a+dptr move code byte relative dptr to a 1 3+1 93h movc a, @a+pc move code byte relative pc to a 1 3+1 83h movx a,{mpage, @ri} move external data (a8) to a 1 3* e2h-e3h movx a, @dptr move external data (a16) to a 1 2* e0h movx {mpage, @ri},a move a to external data (a8) 1 2* f2h-f3h movx @dptr, a move a to external data (a16) 1 1* f0h push direct push direct byte onto stack 2 3 c0h pop direct pop direct byte from stack 2 2 d0h xch a, rn exchange a and register 1 3 c8h-cfh xch a, direct exchange a and direct byte 2 4 c5h xch a, @ri exchange a and data memory 1 4 c6h-c7h xchd a, @ri exchange a and data memory lower nibble 1 4 d6h-d7h branching instructions acall addr 11 absolute call to subroutine 2 4+1 11h-f1h lcall addr 16 long call to subroutine 3 5+1 12h ret return from subroutine 1 3+1 22h reti return from interrupt 1 3+1 32h ajmp addr 11 absolute jump unconditional 2 2+1 01h-e1h ljmp addr 16 long jump unconditional 3 3+1 02h sjmp rel short jump (relative address) 2 3+1 80h jc rel jump on carry = 1 2 3+1 40h jnc rel jump on carry = 0 2 3+1 50h jb bit, rel jump on direct bit = 1 3 3 / 4 +1 20h jnb bit, rel jump on direct bit = 0 3 3 / 4 +1 30h jbc bit, rel jump on direct bit = 1 and clear 3 3 / 4 + 1 10h jmp @a+dptr jump indirect relative dptr 1 2+1 73h jz rel jump on accumulator = 0 2 3+1 60h jnz rel jump on accumulator 1= 0 2 3+1 70h cjne a , direct, rel compare a, direct jne relative 3 4 / 5 +1 b5h cjne a, #d, rel compare a, immediate jne relative 3 3 / 4 +1 b4h cjne rn, #d, rel compare reg, immediate jne relative 3 3 / 4 +1 b8h-bfh cjne @ri, #d, rel compare ind, immediate jne relative 3 4 / 5 + 1 b6h-b7h djnz rn, rel decrement register, jnz relative 2 3 / 4 +1 d8h-dfh djnz direct, rel decrement direct byte, jnz relative 3 3 / 4 +1 d5 miscellaneous instruction nop no operation 1 1 00h nop if pcon.4 is 0 (reset value): nop 1 1 a5h mov @ramptr,a if msb (@ramptr) == 0 accumulator value is written in sfr{1,@ramptr[6:0]} 2 3 a5h mov a,@ramptr if msb (@ramptr) == 1 sfr{1,@ramptr[6:0]} is written in accumulator 3 4 a5h notes on number of cycles: ?x / y? cycles denotes number of cycle without / with jump ?+1? indicates extra cycle that ma y be required because of flash access vrs51l3xxx datasheet www.ramtron.com page 6 of 115 2 special function registers (sfr) addresses 80h to ffh of the sfr address space can be access ed in direct addressing mode only. the following table lists the vrs51l3xxx special func tion registers. due to the vrs51l3xxx?s hi gh level of integration, the sfrs have been mapped onto two pages. the following tables summarize the sfr assignment. complete functional descriptions of each register will be provided throughout the datasheet. 2.1 sfr map page 0 t able 5: s pecial f unction r egisters (sfr) p age 0 sfr register sfr adrs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value p0 80h - - - - - - - - 1111 1111b sp 81h - - - - - - - - 0000 0111b dpl0 82h - - - - - - - - 0000 0000b dph0 83h - - - - - - - - 0000 0000b dpl1 84h 0000 0000b dph1 85h 0000 0000b dps 86h dpsel 0000 0000b pcon 87h oscstop intmoden devcfgen sfrindadr gf1 gf0 pdown idle 0110 0000b inten1 88h t1ien u1ien u0ien pchgien0 t0ien spirxovien spitxeien - 0000 0000b t0t1cfg 89h - t1gate t0gate t1clksrc t1outen t1mode8 t0outen t0mode8 0000 0000b tl0 8ah 0000 0000b th0 8bh 0000 0000b tl1 8ch 0000 0000b th1 8dh 0000 0000b tl2 8eh 0000 0000b th2 8fh 0000 0000b p1 90h - - - - - - - - 1111 1111b wdtcfg 91h wdtperiod3 wdtperiod2 wdtperiod1 wdtperiod0 wtimerf astimer wdtf wdtreset 0000 0000b rcap0l 92h 0000 0000b rcap0h 93h 0000 0000b rcap1l 94h 0000 0000b rcap1h 95h 0000 0000b rcap2l 96h 0000 0000b rcap2h 97h 0000 0000b p5* 98h 1111 1111b t0t1clkcfg 99h t1clkcfg3 t1clkcfg2 t1clkcfg1 t1clkcfg0 t0clkcfg3 t0clkcfg2 t0clkcfg1 t0clkcfg0 0000 0000b t0con 9ah t0ovf t0exf t0downen t0togout t0exten tr0 t0counten t0rlcap 0000 0000b t1con 9bh t1ovf t1exf t1downen t1togout t1exten tr1 t1counten t1rlcap 0000 0000b t2con 9ch t2ovf t2exf t2downen t2togout t2exten tr2 t2counten t2rlcap 0000 0000b t2clkcfg 9dh - - t2clksrc t2outen t2clkcfg3 t2clkcfg2 t2clkcfg1 t2clkcfg0 0000 0000b pwc0cfg 9eh pwc0if pwc0rst pwc0end pwc0start pwc0endsrc1 pwc0endsrc0 pwc0stsrc1 pwc0stsrc0 0000 0000b pwc1cfg 9fh pwc1if pwc1rst pwc1end pwc1start pwc1endsrc1 pwc1endsrc0 pwc1stsrc1 pwc1stsrc0 0000 0000b p2 a0h - - - - - - - - 1111 1111b uart0int a1h colen rxoven rxavailen txemptyen colenf rxovf rxavenf txemptyf 0000 0001b uart0cfg a2h bradj3 bradj2 bradj1 bradj0 brclksrc b9rxtx b9en stop2en 1110 0000b uart0buf a3h 0000 0000b uart0brl a4h 0000 0000b uart0brh a5h 0000 0000b uart0ext a6h u0timerf u0timeren u0rxstate multiproc reserved reserved reserved reserved 0010 0000b reserved a7h inten2 a8h pchgien1 auwdtien pwmt47ien pwmt03ien pwcien i2cuartci i2cien t2ien 0000 0000b pwmcfg a9h - pwmwait pwmclrall pwmlsbmsb pwmmidend pwmch2 pwmch1 pwmch0 0000 0000b pwmen aah pwm7en pwm6en pwm5en pwm4en pwm3en pwm2en pwm1en pwm0en 0000 0000b vrs51l3xxx datasheet www.ramtron.com page 7 of 115 pwmldpol abh pwm7ldpol pwm6ldpol pwm5ldpol pwm4ldpol pwm3ldpol pwm2ldpol pwm1ldpol pwm0ldpol 0000 0000b pwmdata ach 0000 0000b pwmtmren adh pwm7tmren pwm6tmren pwm5tmren pwm4tmren pwm3tmren pwm2tmren pwm1tmren pwm0tmren 0000 0000b pwmtmrf aeh pwm7tmrf pwm6tmrf pwm5tmrf pwm4tmrf pwm3tmrf pwm2tmrf pwm1tmrf pwm0tmrf 0000 0000b pwmclkcfg afh u4pwmclk3 u4pwmclk2 u4pwmclk1 u4pwmclk0 l4pwmclk3 l4pwmdclk2 l4pwmclk1 l4pwmclk0 0000 0000b p3 b0h - - - - - - - - 1111 1011b uart1int b1h colen rxoven rxavailen txemptyen colenf rxovf rxavenf txemptyf 0000 0001b uart1cfg b2h bradj3 bradj2 bradj1 bradj0 brclksrc b9rxtx b9en stop2en 1110 0000b uart1buf b3h 0000 0000b uart1brl b4h 0000 0000b uart1brh b5h 0000 0000b uart1ext b6h u1timerf u1timeren u1rxstate multiproc 0 0 0 0 0010 0000b not used b7h ipinflag1 b8h p37if p36if p35if p34if p31if p30if int1if int0if 0000 0000b portchg b9h pmonflag1 pchgmsk1 pchgsel1 pchgsel0 pmonflag0 pchgmsk0 pchgsel1 pchgsel0 0000 0000b p4 c0h 1111 1111b spictrl c1h spiclk2 spiclk1 spiclk0 spics1 spics0 spiclkph spiclkpol spimaster 0000 0001b spiconfig c2h spimancs spiunderc fsoncs3 spiloadcs3 spislow spirxoven spirxaven spitxeen 0000 0000b spisize c3h 0000 0111b spirxtx0 c4h 0000 0000b spirxtx1 c5h 0000 0000b spirxtx2 c6h 0000 0000b spirxtx3 c7h 0000 0000b p6* c8h 1111 1111b spistatus c9h spireverse - spiunderf sspinval spinocs spirxovf spirxavf spitxempf 0011 1001b psw d0h cy ac f0 rs1 rs0 ov f1 p 0000 0000b i2cconfig d1h mastrarb i2crxoven i2crxaven i2ctxeen i2cmastart i2cscllow i2crxstop i2cmode 0000 0100b i2ctiming d2h 0000 1100b i2cidcfg d3h i2cid6 i2cid5 i2cid4 i2cid3 i2cid2 i2cid1 i2cid0 i2cadvcfg 0000 0000b i2cstatus d4h i2cerror i2cnoack i2csdasync i2cackph i2cidlef i2crxovf i2crxavf i2ctxempf 0010 1001b i2crxtx d5h 0000 0000b ipininv1 d6h p37iinv p36iinv p35iinv p34iinv p33iinv p32iinv int1iinv int0iinv 0000 0000b ipininv2 d7h p07iinv p06iinv p05iinv p04iinv p03iinv p02iinv p01iinv p00iinv 0000 0000b ipinflag2 d8h p07if p06if p05if p04if p03if p02if p01if p00if 0000 0000b xmemctrl d9h extbuscfg extbuscs - - strech3 strech2 strech1 strech0 0000 0000b reserved dah - - - - - - - - 0000 0000b reserved dbh - - - - - - - - 0000 0000b framcfg1 dch freadidle 0 framclk1 framclk0 bursten framop1 framop0 runframop 1000 0000b framcfg2 ddh 0 0 0 0 frambp1 frambp0 framwel 0 0000 0000b reserved deh - - - - - - - - 0000 0000b reserved dfh - - - - - - - - 0000 0000b acc e0h - - - - - - - - 0000 0000b deviomap e1h reserved pwmaltmap i2caltmap u1altmap u0altmap t2altmap t1altmap t0altmap 0000 0000b intpri1 e2h t1p37pri u1p36pri u0p35pri pc0p34pri t0p31pri srp30pri stp33pri int0p32pri 0000 0000b intpri2 e3h pc1p00pri aup06pri pthp05pri ptlp04pri pwcp23pri i10p02pri i2cp01pri t2p00pri 0000 0000b intsrc1 e4h intsrc1.7 intsrc1.6 intsrc1.5 intsrc1.4 intsrc1.3 intsrc1.2 intsrc1.1 intsrc1.0 0000 0000b intsrc2 e5h intsrc2.7 intsrc2.6 intsrc2.5 intsrc2.4 intsrc2.3 intsrc2.2 intsrc2.1 intsrc2.0 0000 0000b ipinsens1 e6h p37isens p36isens p35isens p34isens p33isens p32isens int1isens int0isens 0000 0000b ipinsens2 e7h p07isens p06isens p05isens p04isens p03isens p02isens p01isens p00isens 0000 0000b geninten e8h - - - - - - clrpinint geninten 0000 0000b fpiconfig e9h fpilock1 fpilock0 fpiidle fpirdy 0 fpi8bit fpitask1 fpitask0 0000 0100b fpiaddrl eah 0000 0000b fpiaddrh ebh 0000 0000b fpidatal ech 0000 0000b vrs51l3xxx datasheet www.ramtron.com page 8 of 115 fpidatah edh 0000 0000b fpiclkspd eeh fpiclkspd3 fpiclkspd2 fpiclkspd1 fpiclkspd0 0000 0000b reserved efh - - - - - - - - 0000 0000b b f0h 0000 0000b mpage f1h 0000 0000b devclkcfg1 f2h softreset oscselect clkdiven fullspdint clkdiv3 clkdiv2 clkdiv1 clkdiv0 0110 0000b devclkcgf2 f3h cyoscen intoscen - - cyrange1 cyrange0 0 - 0100 1001b periphen1 f4h spicsen spien i2cen u1en u0en t2en t1en t0en 0000 0000b periphen2 f5h pwc1en pwc0en auen xram2code ioporten wdten pwmsfren fpien 0000 1000b devmemcfg f6h extbusen framen - - - - - sfrpage 0000 0000b portinen f7h reserved (0) p6inputen p5inputen p4inputen p3inputen p2inputen p1inputen p0inputen 0111 1111b userflags f8h 0000 0000b p0pincfg f9h p07in1out0 p06in1out0 p05in1out0 p04in1out0 p03in1out0 p02in1out0 p01in1out0 p00in1out0 1111 1111b p1pincfg fah p17in1out0 p16in1out0 p15in1out0 p14in1out0 p13in1out0 p12in1out0 p11in1out0 p10in1out0 1111 1111b p2pincfg fbh p27in1out0 p26in1out0 p25in1out0 p24in1out0 p23in1out0 p22in1out0 p21in1out0 p20in1out0 1111 1111b p3pincfg fch p37in1out0 p36in1out0 p35in1out0 p34in1out0 p33in1out0 p32in1out0 p31in1out0 p30in1out0 1111 1111b p4pincfg fdh p47in1out0 p46in1out0 p45in1out0 p44in1out0 p43in1out0 p42in1out0 p41in1out0 p40in1out0 1111 1111b p5pincfg* feh p57in1out0 p56in1out0 p55in1out0 p54in1out0 p53in1out0 p52in1out0 p51in1out0 p50in1out0 1111 1111b p6pincfg* ffh p67in1out0 p66in1out0 p65in1out0 p64in1out0 p63in1out0 p62in1out0 p61in1out0 p60in1out0 1111 1111b *vrs51l30xx (qfp-64) only vrs51l3xxx datasheet www.ramtron.com page 9 of 115 2.2 sfr map page 1 t able 6: s pecial f unction r egisters (sfr) p age 1 sfr register sfr adrs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value p0 80h - - - - - - - - 1111 1111b sp 81h - - - - - - - - 0000 0111b dpl0 82h - - - - - - - - 0000 0000b dph0 83h - - - - - - - - 0000 0000b dpl1 84h 0000 0000b dph1 85h 0000 0000b dps 86h dpsel 0000 0000b pcon 87h oscstop intmoden devcfgen sfrindadr gf1 gf0 pdown idle 0110 0000b inten1 88h t1ien u1ien u0ien pchgien0 t0ien spirxovien spitxeien - 0000 0000b t0t1cfg 89h - t1gate t0gate t1clksrc t1outen t1mode8 t0outen t0mode8 0000 0000b tl0 8ah 0000 0000b th0 8bh 0000 0000b tl1 8ch 0000 0000b th1 8dh 0000 0000b tl2 8eh 0000 0000b th2 8fh 0000 0000b p1 90h - - - - - - - - 1111 1111b wdtcfg 91h wdtperiod3 wdtperiod2 wdtperiod1 wdtperiod0 wtimerf astimer wdtf wdtreset 0000 0000b rcap0l 92h 0000 0000b rcap0h 93h 0000 0000b rcap1l 94h 0000 0000b rcap1h 95h 0000 0000b rcap2l 96h 0000 0000b rcap2h 97h 0000 0000b p5* 98h 1111 1111b t0t1clkcfg 99h t1clkcfg3 t1clkcfg2 t1clkcfg1 t1clkcfg0 t0clkcfg3 t0clkcfg2 t0clkcfg1 t0clkcfg0 0000 0000b t0con 9ah t0ovf t0exf t0downen t0togout t0exten tr0 t0counten t0rlcap 0000 0000b t1con 9bh t1ovf t1exf t1downen t1togout t1exten tr1 t1counten t1rlcap 0000 0000b t2con 9ch t2ovf t2exf t2downen t2togout t2exten tr2 t2counten t2rlcap 0000 0000b t2clkcfg 9dh - - t2clksrc t2outen t2clkcfg3 t2clkcfg2 t2clkcfg1 t2clkcfg0 0000 0000b reserved 9eh - - - - - - - - 0000 0000b reserved 9fh - - - - - - - - 0000 0000b p2 a0h - - - - - - - - 1111 1111b reserved a1h - - - - - - - - 0000 0000b aua0 a2h* 0010 0000b aua1 a3h* 0010 0000b auc0 a4h* 0010 0000b auc1 a5h* 0010 0000b auc2 a6h* 0010 0000b auc3 a7h* 0010 0000b inten2 a8h pchgien1 auwdtien pwmt47ien pwmt03ien pwcien i2cuartci i2cien t2ien 0000 0000b p3 b0h - - - - - - - - 1111 1011b aub0div b1h* 0010 0000b aub0 b2h* 0010 0000b aub1 b3h* 0010 0000b aures0 b4h* 0010 0000b aures1 b5h* 0010 0000b aures2 b6h* 0010 0000b aures3 b7h* 0010 0000b ipinflag1 b8h p37if p36if p35if p34if p31if p30if int1if int0if 0000 0000b vrs51l3xxx datasheet www.ramtron.com page 10 of 115 portchg b9h pmonflag1 pchgmsk1 pchgsel1 pchgsel0 pmonflag0 pchgmsk0 pchgsel1 pchgsel0 0000 0000b reserved bah - - - - - - - - 0001 0000b reserved bbh - - - - - - - - 0000 0000b reserved bch - - - - - - - - 0000 0000b reserved bdh - - - - - - - - 0000 0000b reserved beh - - - - - - - - reserved bfh - - - - - - - - p4 c0h 1111 1111b aushiftcfg c1h* shiftmode arithshift shift5 shift4 shift3 shift2 shift1 shift0 0010 0000b auconfig1 c2h* capprev capmode ovcapen readcap addsrc1 addsrc0 mulcmd1 mulcmd0 0000 0000b auconfig2 c3h* auregclr2 auregclr1 auregclr0 auinten - divoutrg auov16 auov32 0000 0000b auprev0 c4h* 0000 0000b auprev1 c5h* 0000 0000b auprev2 c6h* 0000 0000b auprev3 c7h* 0000 0000b p6* c8h 0000 0000b reserved c9h - - - - - - - - 0000 0000b reserved cah - - - - - - - - 0000 0001b reserved cbh - - - - - - - - 0000 0000b reserved cch - - - - - - - - 0000 0000b reserved cdh - - - - - - - - 0000 0000b reserved ceh - - - - - - - - 0000 0000b reserved cfh - - - - - - - - psw d0h cy ac f0 rs1 rs0 ov - p 0000 0000b reserved d1h - - - - - - - - reserved d2h - - - - - - - - reserved d3h - - - - - - - - reserved d4h - - - - - - - - reserved d5h - - - - - - - - ipininv1 d6h p37iinv p36iinv p35iinv p34iinv p33iinv p32iinv int1iinv int0iinv 0000 0000b ipininv2 d7h p07iinv p06iinv p05iinv p04iinv p03iinv p02iinv p01iinv p00iinv 0000 0000b ipinflag2 d8h p07if p06if p05if p04if p03if p02if p01if p00if 0000 0000b xmemctrl d9h extbuscfg extbuscs - - strech3 strech2 strech1 strech0 0000 0000b reserved dah - - - - - - - - 0000 0000b reserved dbh - - - - - - - - 0000 0000b reserved dch - - - - - - - - 0000 0000b reserved ddh - - - - - - - - 0000 0000b reserved deh - - - - - - - - 0000 0000b reserved dfh - - - - - - - - 0000 0000b acc e0h - - - - - - - - 0000 0000b deviomap e1h reserved pwmaltmap i2caltmap u1altmap u0altmap t2altmap t1altmap t0altmap 0000 0000b intpri1 e2h t1p37pri u1p36pri u0p35pri pc0p34pri t0p31pri srp30pri stp33pri int0p32pri 0000 0000b intpri2 e3h pc1p00pri aup06pri pthp05pri ptlp04pri pwcp23pri i10p02pri i2cp01pri t2p00pri 0000 0000b intsrc1 e4h intsrc1.7 intsrc1.6 intsrc1.5 intsrc1.4 intsrc1.3 intsrc1.2 intsrc1.1 intsrc1.0 0000 0000b intsrc2 e5h intsrc2.7 intsrc2.6 intsrc2.5 intsrc2.4 intsrc2.3 intsrc2.2 intsrc2.1 intsrc2.0 0000 0000b ipinsens1 e6h p37isens p36isens p35isens p34isens p33isens p32isens int1isens int0isens 0000 0000b ipinsens2 e7h p07isens p06isens p05isens p04isens p03isens p02isens p01isens p00isens 0000 0000b geninten e8h - - - - - - clrpinint geninten 0000 0000b fpiconfig e9h fpilock1 fpilock0 fpiidle fpirdy 0 fpi8bit fpitask1 fpitask0 0000 0100b fpiaddrl eah 0000 0000b fpiaddrh ebh 0000 0000b fpidatal ech 0000 0000b fpidatah edh 0000 0000b fpiclkspd eeh fpiclkspd3 fpiclkspd2 fpiclkspd1 fpiclkspd0 0000 0000b vrs51l3xxx datasheet www.ramtron.com page 11 of 115 reserved efh - - - - - - - - 0000 0000b b f0h 0000 0000b mpage f1h 0000 0000b devclkcfg1 f2h softreset oscselect clkdiven fullspdint clkdiv3 clkdiv2 clkdiv1 clkdiv0 0110 0000b devclkcgf2 f3h cyoscen intoscen - - cyrange1 cyrange0 0 - 0100 1001b periphen1 f4h spicsen spien i2cen u1en u0en t2en t1en t0en 0000 0000b periphen2 f5h pwc1en pwc0en auen xram2code ioporten wdten pwmsfren fpien 0000 1000b devmemcfg f6h extbusen framen - - - - - sfrpage 0000 0000b portinen f7h reserved (0) p6inputen p5inputen p4inputen p3inputen p2inputen p1inputen p0inputen 0111 1111b userflags f8h 0000 0000b p0pincfg f9h p07in1out0 p06in1out0 p05in1out0 p04in1out0 p03in1out0 p02in1out0 p01in1out0 p00in1out0 1111 1111b p1pincfg fah p17in1out0 p16in1out0 p15in1out0 p14in1out0 p13in1out0 p12in1out0 p11in1out0 p10in1out0 1111 1111b p2pincfg fbh p27in1out0 p26in1out0 p25in1out0 p24in1out0 p23in1out0 p22in1out0 p21in1out0 p20in1out0 1111 1111b p3pincfg fch p37in1out0 p36in1out0 p35in1out0 p34in1out0 p33in1out0 p32in1out0 p31in1out0 p30in1out0 1111 1111b p4pincfg fdh p47in1out0 p46in1out0 p45in1out0 p44in1out0 p43in1out0 p42in1out0 p41in1out0 p40in1out0 1111 1111b p5pincfg* feh p57in1out0 p56in1out0 p55in1out0 p54in1out0 p53in1out0 p52in1out0 p51in1out0 p50in1out0 1111 1111b p6pincfg* ffh p67in1out0 p66in1out0 p65in1out0 p64in1out0 p63in1out0 p62in1out0 p61in1out0 p60in1out0 1111 1111b *vrs51l30xx (qfp-64) only 2.3 bit accessible registers as is the case with standard 8051s, all sfr registers in which the lower nibble of address is x0 or x8, are bit- addressable. the bit-addressable register s allow bit-oriented instructions to alter individual register bit values. t able 7:b it addressable sfr r egisters sfr register sfr adrs bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset value p0 80h - - - - - - - - 1111 1111b inten1 88h t1ien u1ien u0ien pchgien0 t0ien spirxovien spitxeien - 0000 0000b p1 90h - - - - - - - - 1111 1111b p5 98h 1111 1111b p2 a0h - - - - - - - - 1111 1111b inten2 a8h pchgien1 auwdtien pwmt47ien pwmt03ien pwcien i2cuartci i2cien t2ien 0000 0000b p3 b0h - - - - - - - - 1111 1011b ipinflag1 b8h p37if p36if p35if p34if p31if p30if int1if int0if 0000 0000b p6 c8h 1111 1111b psw d0h cy ac f0 rs1 rs0 ov - p 0000 0000b ipinflag2 d8h p07if p06if p05if p04if p03if p02if p01if p00if 0000 0000b acc e0h - - - - - - - - 0000 0000b geninten e8h - - - - - - geninten 0000 0000b b f0h 0000 0000b userflags f8h 0000 0000b vrs51l3xxx datasheet www.ramtron.com page 12 of 115 3 sfr registers 3.1 accumulator, b and user flags register the vrs51l3xxx accumulator is located at address e0h on sfr pages 0 and 1. the accumulator is the source and destination for many 8051 instructions. t able 8: t he a ccumulator - acc or a sfr e0 h 7 6 5 4 3 2 1 0 r/w, reset = 0x00 acc[7:0] the b register is mainly used for mul and div instructions, holding the msb of the mul instruction and the remainder of the div in struction. it can also be used as a general purpose register that is bit- addressable. it is accessible on both sfr pages 0 and 1 at address f0h. t able 9: b r egister - sfr f0 h 7 6 5 4 3 2 1 0 r/w, reset = 0x00 b[7:0] 3.2 psw register the psw register is a bit-addressable register that contains the status flags (c y, ac, ov, p), user flag (f0) and register bank select bits (rs1, rs0) of the 8051 processor. t able 10:t he psw sfr register - psw sfr d0 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 cy carry bit flag. indicates that the last addition/subtraction resulted in a carry or borrow. the cy bit is cleared by other arithmetic instructions, the jbc and clr c instructions. 6 ac auxiliary carry bit flag. indicates that the last addition/subtraction resulted in a carry or borrow from the higher nibble. the ac bit is cleared by other arithmetic instru ctions and by the jbc instruction. 5 f0 user general purpose flag 4:3 rs1:rs0 register select address bank for r0 ? r7 00 r0 to r7 from 00h to 07h 01 r0 to r7 from 08h to 0fh 10 r0 to r7 from 10h to 17h 11 r0 to r7 from 17h to 1fh 2 ov overflow flag indicates that the last addition/subtraction resulted in a carry/borrow/overflow. the ov bit is cleared by other arithmetic instructions and the jbc instruction. 1 f1 user general purpose flag 0 p parity flag 3.3 data pointers the vrs51l3xxx includes two 16-bit data pointers that are described in the following tables. the active data pointer is controlled via a dps register located at sfr address 86h (see below). t able 11: d ata p ointer 0 h igh - dph0 sfr 83 h 7 6 5 4 3 2 1 0 r/w, reset = 0x00 dptr0[15:8] t able 12: d ata p ointer 0 low - dpl0 sfr 82 h 7 6 5 4 3 2 1 0 r/w, reset = 0x00 dptr0[7:0] t able 13: d ata p ointer 1 h igh - dph1 sfr 85 h 7 6 5 4 3 2 1 0 r/w, reset = 0x00 dptr1[15:8] t able 14: d ata p ointer 1 low - dpl1 sfr 84 h 7 6 5 4 3 2 1 0 r/w, reset = 0x00 dptr1[7:0] t able 15: d ata p ointer s elect r egister - dps sfr 86 h 7 6 5 4 3 2 1 0 r r r r r r r r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:1 unused 0 dpsel dps value 0 : selects dptr 0 1 : selects dptr 1 3.4 stack pointer the stack pointer is a regi ster located at address 81h of the sfr register area whose value corresponds to the address of the last item that was put on the processor stack. each time new data is put on the processor stack, the value of the stack pointer is incremented. t able 16: s tack p ointer - sp sfr 81 h 7 6 5 4 3 2 1 0 r/w, reset = 0x07 sp[7:0] by default, the stack pointer value is 07h. the stack can be set anywhere in the internal sram from address 00h to ffh. each time a function call is performed or an interrupt is serviced, the 16-bit return add ress (2 bytes) is stored on the stack. data can be manually placed on the stack by using the push and pop functions. vrs51l3xxx datasheet www.ramtron.com page 13 of 115 3.5 sfr structure the vrs51l3xxx peripheral registers are accessible through two sfr pages mapped directly into the 80h to ffh address range in the 256 bytes of memory. most peripherals are accessible via both sfr pages. the following peripherals are only accessible via sfr page 0: o i2c interface o spi interface o pwc interface o f-ram memory configuration the enhanced arithmetic unit is only mapped onto sfr page 1. to access sfr page 1 registers, set the sfrpage bit of devmemcfg register to 1, as shown below: orl devmemcfg,0x01 ; select sfr page 1 returning to sfr page 0 is done by clearing sfrpage bit of the devmemcfg register. anl devmemcfg,0xfeh ;select sfr page 0 3.6 indirect addressing of the sfr it is possible to access the sfr register in indirect addressing mode. unique to the vrs51l3xxx, this feature enables efficient sf r content data transfers. when the sfrindadr bit 4 of the pcon register is set to 1, the a5h (nop) instruction functions as an indirect sfr access. indirect sfr addressing uses the accumulator as well as the four bank rn registers of sram memory area 00h to 1fh to indirectly transfer the data to and from the sfr memory space. indirect sfr register write for an indirect sfr write operation, perform the following steps after the sfrindadr bit of the pcon register is set to 1: o write the data value into the accumulator. o hold the sfr address where the write operation is performed in the internal sram memory from address 00h to 1fh. the same sram memory area [00h to 1fh] holds four sets of 8x rn registers that are used for indirect addressing. only one set of rn registers is active at any given time and is defined by the value of the bits rs1 and rs0 of the psw register. for an indirect sfr write operation, bit 7 of the sfr address written into rn must be cleared. for example, to write to the spitx0 regist er located at address c4h, 44h should be written into the rn register. example using the bank 1, r0 register: mov r0,#44 ;target is sfr c4h (with bit 7 stripped) example using the bank 1, r3 register: mov r3,#44 ;target is sfr c4h (with bit 7 stripped) the next step involves calling the sfr indirect addressing function. this is a two-step process composed of the a5h instruct ion itself followed by the physical address of the rn register, where the sfr address is stored. if the r0 register of bank 1 has been used, the next instructions should be: db. 0xa5 db. 0x00 if the r3 register of bank 0 has been used, the next instructions should be: db. 0xa5 db. 0x03 this would also work for the rn registers located in bank 4. for example, if t he r0 register of bank 4 contains the target sfr addr ess, the instruction should be: db. 0xa5 db. 0x18 once the a5h instruction is executed, the processor will take the value stored in the accumulator and put it into the sfr address identif ied by the rn register address. ;// perform indirect write of value 0xaa ;// into userflags sfr address (0xf8) using indirect sfr write orl 0x87, #0x10; ;set a5 for indirect sfr addressing mov 0xf8,#00 ;clear userflags mov a, #0xaa ;acc = aah mov r0, #0x78 ;r0 (bank1) = address userflags (f8h) ;with bit 7 cleared .db 0xa5 ;perform the indirect sfr write .db 0x00 ;after the second .db instruction, ;p2 contains the value 0xaa anl 0x87, #0xef; ;set a5 for nop operation indirect sfr read indirect sfr address read functions similarly to indirect sfr write, the main differences being that the sfr target address stored in the rn register is the actual sfr address (bit 7 = 1) with the accumulator containing the current sfr data. ;// perform indirect read of value in userflags sfr address (0xf8) ;// into acc using indirect sfr read function orl 0x87, #0x10; ;set a5 for indirect sfr addressing mov a,#0x00 ;acc = 00h mov r0, #0xf8 ;r0 (bank1) = address p2 with bit 7 cleared .db 0xa5 ;perform the indirect sfr write .db 0x00 ;after the second .db instruction, ;acc contain the value 0xaa anl 0x87, #0xef; ;set a5 for nop operation 3.7 user flags register the user flags register is a bit-addressable register used for condition testing or as a general purpose storage register. t able 17: userflags r egister - userflags sfr f8 h 7 6 5 4 3 2 1 0 userflags, reset = 0x00 userflags[7:0] vrs51l3xxx datasheet www.ramtron.com page 14 of 115 4 memory architecture the following is an overview of the vrs51l3xxx?s memory structure: f igure 3: vrs51l3 xxx d ata and p rogram m emory s tructure upper 128 bytes sram (indirect addressing only) lower 128 bytes sram program memory 64kb flash (no external program memory access) 0fffh 0000h 8000h ffffh ffh 80h 7fh 00h 4096 bytes of sram (accessible using movx instruction) 0fffh 0000h sfr page 1 (devmemcfg.0=1) sfr page 0 (devmemcfg.0=0) 80h ffh 80h ffh external data bus access (upper 32kb) (devmemcfg.7 = 1 (devmemcfg.6 = 0) 8000h ffffh fram vrs51l3x74 = 8kb vrs51l3x72 = 2kb (devmemcfg.7 = 1 devmemcfg.6 = 1) 8000h 9fffh (8kb) / 87ff (2kb) ffffh a000h (8kb) / 8800h (2kb) the vrs51l3xxx devices include 64kb of on-chip flash memory that can be used as program memory or as nonvolatile data storage. the flash memory is programmed via the jtag or the fpi interface. the vrs51l3xxx members cannot be programmed in parallel mode (check fpi interface section for details). 4.1 internal scratch pad sram (256 b) as in standard 8051s, all vrs51l3xxx family members include 256 bytes of internal scratch pad sram: the lower 128 bytes are accessed by either direct or indirect addres sing; the upper 128 bytes are accessed by indirect addressing only. using direct addressing for the upper 128 bytes of scratch pad sram will access the sfr register area. 4.2 integrated 4kb sram block the vrs51l3xxx devices include a 4kb block of sram that is mapped from address 0000h to 0fffh on the external memory bus. this sram can be used for general purpose data memory or program memory. the 4kb sram memory is always active and it is accessed using movx instructions. although the sram is mapped on the external memory, accessing it will have no impact on the i/o pins used for the external data memory bus. 4.3 running programs from the external 4kb sram block the vrs51l3xxx processors can execute code directly from the external 4kb of sram. running the program from the sram memory can significantly save power, especially at lower operating frequencies. this is because sram power consumption is directly proportional to the access frequency, while power consumption of the flash memory is less dependant of the device operating frequency. to execute code from the 4kb sram block: 1. copy the code from the flash to the sram and apply the appropriate address shifting, if required. 2. before switching to an xram operation, the program must execute from a flash address higher than 0fffh. 3. set the xram2code bit (bit 4) of the periphen2 register. 4. jump to the code copied into xram. code example: copies code from the flash memory to the xram memory and switches the program execution to the xram. ;--------vrs51l3xxx - running prog ram into xram --------------- ;- description: this program gives an examples on how ;- to switch code execution from flash to xram ;----------------------------------------------------------------------------------- include vrs51l3074_ride.inc ;---------- variable definition -------------- cptr equ 030h org 00000h ljmp init ;------------------------------------------------------------------------ ;---------------------- main program begins ------------ ;------------------------------------------------------------------------ init: mov periphen2,#08h ;enable io mov p1pincfg,#00h ;configure p1 as output mov periphen1,#00000000b; mov periphen2,#00001000b ;bit4 - xram2code = 0 ;--copy code from flash into xram memory clr dps mov dptr,#01000h ;set dptr0 (point to code) mov dps,#01h ;switch to dptr1 mov dptr,#0000h ;set dptr1 (point to xram) copyloop: mov dps,#00 ;point to dptr0 (flash) clr a movc a,@a+dptr ; inc dptr ;inc dptr0 (flash) mov dps,#01h ;switch to dptr1 (xram) movx @dptr,a ;write value into xram inc dptr ;inc dptr1 (xram) mov a,dph1 ;check if dptr1 (xram) reach address 0300h cjne a,#03,copyloop ljmp outsidexram ;jump to flash location outside xram area vrs51l3xxx datasheet www.ramtron.com page 15 of 115 ;-------------------------------------------------------------- ;- section of code outside the xram ;--------------------------------------------------------------- org 2000h outsidexram: mov periphen2,#18h ;activate xram2code bit and ioports ;any jump to the 0000h - 0fffh area should execute from xram ljmp 0100h ;jump to the p1 toggle loop copied into xram mov p1,#00 ;force p1 = 0x00h if stuck into the flash loop: ljmp loop ;infinite loop ;----------------------------------------------------------------------------------- ;- code to be moved into xram from address 0000h to 02ffh ; assumed code contained from 1000h to 12ffh... ; will be copied from 0000h to 02ffh into xram ;------------------------------------------------------------------------------------ ;-------------------------------------- ;- xram_port_toggle: ;-------------------------------------- org 1100h toggle: mov p1,#00h ;set port 1 = 00h lcall 0200h ;call delay function mov p1,#0ffh ;set port 1 = ffh lcall 0200h ;call delay function ljmp 0100h org 1200h ;---------------------------------------------------------------- ;- delay1msto : 1ms delay using timer0 ;--------------------------------------------------------------- delay1ms: mov cptr,#1 mov a,periphen1 ;load periphen1 reg orl a,#00000001b ;enable timer 0 mov periphen1,a delay1mslp: mov th0,#063h ; timer0 reload value for 1ms at 40mhz mov tl0,#0c0h mov t0t1clkcfg,#00h ;no prescaler for timer 0 clock mov t0con,#00000100b ;start timer 0, count up dwaitovt0: mov a,t0con ;read timer 0 control, wait for overflow anl a,#080h ;isolate timer overflow flag jz dwaitovt0 ;loop as long as timer 0 dont overflow mov t0con,#00h ;stop timer 0 djnz cptr,delay1mslp ; mov a,periphen1 ;load periphen1 reg anl a,#11111110b ;disable timer 0 mov periphen1,a ret 4.4 enabling f-ram & external data memory bus the vrs51l3xxx devices provide access to the external data bus memory, enabling direct interfacing of the chip to external devices such as sram, data converters, etc. activation of the external data memory bus, the f-ram (ferroelectric random access memory) memory and the active sfr page is controlled via the devmemcfg register. t able 18:d evice memory c onfiguration r egister - devmemcfg sfr f6 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 extbusen when set this bit ac tivates the external data bus access through port 0, port 2, p3.6 and p3.7 6 framen to activate the f-ram memory module both extbusen and the framen bit must be set to 1. 5:2 not used 0 sfrpage when set, sfr page 1 is selected the extbusen bit of the devmemcfg register controls the access devices connected to the external data memory bus shared with ports p0, p2, p3.6 and p3.7. when the extbusen bit is set to 1 and the framen bit is set to 0, an y movx instructions with an address >= 0x8000 will activate the external data memory bus pins. to activate the f-ram memory module, set both the framen and the extbusen bits to 1. any movx instructions with a target address from 0x8000 to 0x9fff will then target the f-ram memory and there will be no activity on ports p0, p2, p3.6 and p3.7. a roll-over to 0x8000 will occur if read or write operations to f-ram are performed with a target address larger than 0x9fff. bit 0 of the devmemcfg defines the active sfr page. accessing the f-ram memory has no impact on the i/o pins associated with the external data memory bus. vrs51l3xxx datasheet www.ramtron.com page 16 of 115 4.5 integrated f-ram memory the vrs51l3x74 devices include 8192 bytes of f- ram mapped into 8000h to 9fffh of the external memory address space. the vrs51l3x72 devices include 2048 bytes of f- ram mapped into 8000h to 87ffh of the external memory address space. f-ram memory is ideal for applications that require nonvolatile data storage. two sfr registers (framcfg1 and framcfg2) located at address dch and ddh on sfr page 0 (respectively) configure the f-ram module?s operation. t able 19:f-ram c onfiguration r egister 1 ? framcfg1 sfr dc h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w w w w w 1 0 0 0 0 0 0 0 bit mnemonic description w: 1: further accelerate f-ram read when burst mode is activated (bursten = 1) 0: normal read mode 7 freadidle r: 0: f-ram module is busy 1: f-ram module is idle 6 reserved this bit must bit must be kept to 0 5:4 framclk[1:0] f-ra m module operation speed 00: sysclk/2 01: sysclk/3 10: sysclk/4 11: sysclk/8 w: 1: activate burst mode operation. the movx operations to f-ram space are frozen until data has been read/written 0: normal mode operation 3 bursten r: read as 0 w: f-ram operation 00: enable transfer of framcfg2 defined parameters to f-ram module. 01: disable write operations from framcfg2 to the f-ram module 10: prepare for read framcfg2 register 11: write framcfg2 register to f-ram module 2:1 framop[1:0] r: read as 00 w : when this bit is set to 1, the selected f- ram operation is executed 0 runframop r: read as 0 bit 7 of the framcfg1 register (freadidle) when read, indicates the status of the f-ram module. reading a 1 indicates that the f-ram module is idle and ready to receive commands. writing a 1 into the freadidle bit will activate fast read burst mode, as long as the bursten bit is also set to 1. framclk[1:0] bit 5,4 of the framcfg1 register controls the f-ram module operating clock frequency. by default, the f-ram module operates at system clock/2. however, in certai n cases it is preferable to lower the f-ram memory m odule operating frequency to reduce burst speed operations allowing more time for data processing between f-ram burst mode access. t able 20:framclk[1:0] setting vs . f-ram module clock framclk[1:0] setting f-ram module clock speed f-ram module frequency ( fosc =40mhz) 00 sysclk/2 20mhz 01 sysclk/3 13.3mhz 10 sysclk/4 10mhz 11 sysclk/8 5mhz bit 6 of the framcfg1 register is reserved and must be written as 0 when write operations are performed. when set to 1, bit 3 of the framcfg1 register (bursten) will activate burst mode, enabling faster data transfers to/from the f-ram for both read/write operations to/from consecutive addresses (see the section on burst mode operations for more detail). when burst mode is activated, writing a 1 to the freadidle bit will activate fast burst read mode, which further accelerates f-ram memory read operations. the framop[1:0] and runframop bits of the framcfg1 register are used to: 1. initiate f-ram module operations related to the activation/deactivation of the write protection feature on the f-ram memory. 2. read the status of the f-ram?s write enable latch. there are four operations controlled by the framop[1:0] bits, as described in the following table: t able 21:f-ram operation according to framop[1:0] setting framop[1:0] f-ram operation 00 enables transfer of framcfg2 defined parameters to f-ram module 01 disables write operations from framcfg2 to the f-ram module 10 updates the framcfg2 register contents (read) 11 transfers the contents of the framcfg2 register to the f-ram module the framop[1:0] and the runframop bits work in conjunction with the framcfg2 register. the framop[1:0] bits define which operation will be performed. when set to 1, the runframop bit will initiate the operation select ed by the framop[1:0] bit. the framop[1:0] and runframop bits can be written simultaneously or sequentially. vrs51l3xxx datasheet www.ramtron.com page 17 of 115 the f-ram module requires a number of cycles to execute each operation. during that time, the processor continues to operate. in cases where read or write access to the f-ra m is initiated soon after a framop is executed, we recommend waiting until the framidle bit is set to 1 before performing the operation. the framcfg2 register is used to enable the write protect option and monitor the current state of the block protect configuratio n and f-ram write enable latch flag (framwel bit ). framwel is a read-only flag. t able 22:f-ram c onfiguration register 2 ? framcfg2 sfr dd h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 0 6 0 5 0 4 0 3:2 frambp[1:0] f-ram memory block protect 00: none 01: 8800h ? 8fffh (upper ? on vrs51l3x74) 10: 9000h ? 9fffh (upper ? on vrs51l3x74) 11: 8000h ? 9fffh (all) 1 framwel r: indicates the state of the wel flag 0 0 framcfg2 sfr mirrors the protection configuration register in the f-ram memory. as such, the following steps are required to access the framcfg2 register: 1) write the configuration value into the framcfg2 register. 2) activate the write to framcfg2 register operation by writing 07h into the framcfg1 register. example: mov framcfg2,#value to be written; mov framcfg1,#0x07; similarly, before reading the framcfg2 register, its contents should be refreshed by performing the following operations: 1) activate the read from framcfg2 register operation by writing 05h into the framcfg1 register. 2) read the contents of the framcfg2 register. example: mov framcfg1,#0x05; mov destination,framcfg2; the freadidle bit of the framcfg1 register should be monitored to ensure that the f-ram module is in idle mode before initiating a read or write operation. example: waitilde: mov a,framcfg1; anl a,#0x80; jz waitidle; 4.6 f-ram normal mode access access to the f-ram memory requires using the movx instruction in th e f-ram memory address range. before the f-ram can be accessed, it must first be activated by setting both extbusen bit 7 and framen bit 6 of the devmemcfg register located at address f6h on sfr page 0 to 1. the f-ram access time, during which the processor is stopped, depends on the operat ing frequency of the processor, as well as the configuration of the framclk[1:0] bit of the framcfg1 register. the following table provides typical durations of read/write operations in various operating modes: t able 23:f-ram r ead and w rite time framclk[1:0] = 00 (sysclk/2) framclk[1:0] = 10 (sysclk/4) mode read write read write normal 1.9us 2.6us 3.6us 4.9us burst* 1.1us 0.4us 2.3us 0.7us read burst* 0.7us 0.4us 1.6us 0.7us *based on 100 consecutive read and write operations in burst mode the processor?s program counter will stop at the movx instruction while a f-ram read or write is performed. as such, it is unnecessary to verify whether the device is idle (freadidle = 1) before initiating a f-ram read/write, unless an access to framcfg2 was previously initiated. note: an interrupt that occurs during a f-ram access will be serviced upon completion of the access operation. vrs51l3xxx datasheet www.ramtron.com page 18 of 115 code example: performing a f-ram read operation the following assembly code provides an example of a f-ram memory read: ;----f-ram initialization orl devmemcfg,#c0h ;activate the f-ram module mov framcfg1,#00h ;--check f-ram module is ready optional and needed only if a f-ram operation through ; framop[1:0] have been initiated before. framrdy: mov a,framcfg1 anl a,#80h ;isolate freadidle bit jz framrdy ;loop until freadidle = 1 ;--performing a read operation at address 8100h framwrite: mov dptr,#8100h movx a,@dptr code example: performing a f-ram write operation ;----f-ram initialization orl devmemcfg,#c0h ;activate the f-ram module mov framcfg1,#01h ;set the write enable latch ;--check f-ram module is ready optional and needed only if a f-ram operation through ; framop[1:0] have been initiated before. framrdy: mov a,framcfg1 anl a,#80h ;isolate freadidle bit jz framrdy ;loop until freadidle = 1 mov a,data ;retrieve data to be written in f-ram ;--performing a write operation at address 8100h mov dptr,#8100h mov x @dptr,a 4.7 f-ram burst mode operation the access to the f-ram memory can be configured to operate in burst mode, enabling faster data transfers from/to the f-ram memory for consecutive address read/write operations. f-ram burst write for write operations, burst mode is activated by setting the bursten bit of the framcfg1 register to 1. the burst mode operation takes advantage of the double buffering capability of the f-ram memory module. this allows the processor to write the next data byte to the f-ram memory module before completion of the current write cycle. operating in burst write mode requires that the following conditions be met: ? ? ? vrs51l3xxx datasheet www.ramtron.com page 19 of 115 f-ram burst read the f-ram memory module offers two burst read modes (basic and fast). the basic f-ram burst read mode is activated by setting the bursten bit of the framcfg1 register to 1. fast f-ram burst read mode is activated by setting both the bursten and the freadidle bits of the framcfg1 register to 1. the burst mode operation takes advantage of the double buffering capability of the f-ram memory module. this allows the f-ram module to prepare the next data byte to be read before the current read cycle is complete. as is the case for f-ram burst write mode, burst read mode requires the following similar conditions to be met: ? ? ? ? ? vrs51l3xxx datasheet www.ramtron.com page 20 of 115 4.8 f-ram write protect two methods can be employed to enable the f-ram write protect feature. the fi rst involves configuring the f-ram access as read-only when the device is programmed. this can be executed via the options menu in versa ware jtag software. this method supersedes the f-ram block protection feature. the second method is via t he processor, by accessing the framcfg1 and framcfg2 registers. the values written to the frambp[1:0] bits of the framcfg2 register define which region of the f-ram memory will be protected: t able 26:f-ram b lock p rotect frambp[1:0] protected f-ram addresses 00 none 01 8800h ? 8fffh (upper ? on vrs51l3x74) 10 9000h ? 9fffh (upper ? on vrs51l3x74) 11 8000h ? 9fffh (all) the following steps are required to apply f-ram memory protection from the processor: 1. write 01h to the framcfg1 register to activate the framwel bit (enables update of framcfg2 register). 2. read the freadidle bit 7 of the framcfg1 register and wait until it reaches 1, indicating that the fram module is idle. 3. configure the value of the framcfg2 register: set the frambp[1:0] bits to select which zone of the f-ram should be write- protected and set the framwp bit to 1. 4. write 0x07 to the framcfg1 register to execute the f-ram module write protect operation. 5. read the freadidle bit 7 of the framcfg1 register and wait until it reaches 1, indicating that the f-ram module is idle. 6. write 03h into the framcfg1 register to deactivate access to write to the framcfg2, (protection from inadvertent writes). 7. read the framcfg2 register to verify that the block protect operation was successful. code example: f-ram block protect the following is a code example to perform a f-ram memory block protect: //-----------------------------------------------------------------------------------------------------// // void framprotect(char frambp) // //---------------------------------// // description: apply block protect on v3k f-ram // // input parameters: // char value corresponding to the frambp[1:0] of framcfg2 register // // output parameters: // none //------------------------------------------------------------------------------------------------------// void framprotect(char frambp) { frambp &= 0x03; //frambp is 2 bit only frambp = frambp << 2; //shift frambp value to position at bits 3:2 framcfg1 = 0x01; //set framwel = 1 enable write (framop = 00) while(!(framcfg1&0x80)); //wait freadidle == 1 (fram idle) framcfg2 = frambp; //transfer frambp value into framcfg2 framcfg1 = 0x07; //execute transfer of framcfg2 register content //to f-ram module while(!(framcfg1&0x80)); //wait freadidle == 1 (fram idle) framcfg1 = 0x03; //clear framwel (framop = 01) while(!(framcfg1&0x80)); //wait freadidle == 1 (fram idle) // reading the wel and the bp bits (optional) //framcfg1 = 0x05; //read framcfg2 //while(!(framcfg1&0x80)); //wait freadidle == 1 (f-ram idle) }//end of framprotect code example: f-ram access in c example: the following program provi des examples of f-ram access in c. //-------------------------------------------------------------------------------------------------------// // v3k_fram_use_example_sdcc.c // //---------------------------------------------------// // // this program show how to perform the following operations: // // -enables the f-ram memory // -deactivate the f-ram protecti on (this step is optional) // -fill the f-ram with 0x55 // -read f-ram address 0x8100 // -write 0x23 at f-ram address 0x8100 // -read content of address 0x8100 // - activate f-ram write protect // -"try" clearing the (protected) f-ram // -deactivate the f-ram protection // -clear the f-ram // -show how to read the f-ram block protect configuration //-------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 21 of 115 while(!(framcfg1&0x80)); //wait freadidle == 1 (f-ram idle) framcfg1 = 0x03; //disable the write operations //from f-ramcfg2 to the f-ram module while(!(framcfg1&0x80)); //wait freadidle == 1 (f-ram idle) //--fill the f-ram with 0x55 for(cptr = 0; cptr < 0x2000; cptr++) *(framptr+cptr) = 0x55; //--read content of address 0x8100 and place it into framread framread = *(framptr + 0x0100) //framread will contain 0x55 //--write 0x23 at address 0x8100 in f-ram (offset of 0x0100) *(framptr + 0x0100) = 0x23; //--read content of address 0x8100 and place it into framread framread = *(framptr + 0x0100); //framread will contain 0x23 framread = *(framptr + 0x0101); //framread will contain 0x55 //-- activate f-ram write protect framcfg1 = 0x01; //set framwel = 1 enable write //(framop = 00) while(!(framcfg1&0x80)); //wait freadidle == 1 (f-ram idle) framcfg2 = 0x0c; //configure framcfg2 to protect //the entire f-ram framcfg1 = 0x07; //execute transfert of framcfg2 module //to f-ram module while(!(framcfg1&0x80)); //wait freadidle == 1 (fram idle) framcfg1 = 0x03; //clear framwel (framop = 01) while(!(framcfg1&0x80)); //wait freadidle == 1 (f-ram idle) //--clear the f-ram content (will not work if f-ram protected) for(cptr = 0; cptr < 0x2000; cptr++) *(framptr+cptr) = 0x00; //-- deactivate f-ram write protect (not needed if f-ram not initially protected) framcfg1 = 0x01; //set framwel = 1 //enable write (framop = 00) while(!(framcfg1&0x80)); //wait freadidle == 1 (f-ram idle) framcfg2 = 0x00; //configure f-ramcfg2 to remove //f-ram content protection framcfg1 = 0x07; //execute transfer of framcfg2 module to //f-ram module while(!(framcfg1&0x80)); //wait freadidle == 1 (f-ram idle) framcfg1 = 0x03; //disable the write operations //from framcfg2 to the f-ram module while(!(framcfg1&0x80)); //wait freadidle == 1 (f-ram idle) //--clear the f-ram content (will work unless f-ram is configured as read only at programming time ) for(cptr = 0; cptr < 0x2000; cptr++) *(framptr+cptr) = 0x00; while(1); //--optional read of the f-ram block protect configuration //framcfg1 = 0x05; //read framcfg2 //while(!(framcfg1&0x80)); //wait freadidle == 1 (f-ram idle) //x = framcfg2 //read the framcfg2 register //(...) }//end of main vrs51l3xxx datasheet www.ramtron.com page 22 of 115 4.9 external data bus access for vrs51l30xx devices (qfp-64) the vrs51l30xx provides external memory bus access on the upper 32kb block of the 64kb external memory [8000h to ffffh]. three external data memory bus access operati ng modes are available: ? ? ? vrs51l3xxx datasheet www.ramtron.com page 23 of 115 the diagram below shows the timing of the external data memory bus when configured in multiplexed mode. f igure 6: m ultiplexed e xternal data memory access assuming that the system clock operates at 40mhz, typical cycles for the external memory bus are as follows: parameter description typical value for system clock = 40mhz t ale ale high time 25ns t addr time between addr[14:8] and ale rising edge 10ns t ad time a[7:0] is stable after ale falling edge 20ns t ard time between ale falling edge and rd falling edge 50ns t wr wr signal low time 50ns t rd rd signal low time 50ns non-multiplexed external data memory access the vrs51l3xxx external address and data memory bus can operate in non-multiplexed mode. this mode is activated by setting the extbuscfg bit of the xmemctrl register to 1. in this case: o d7:d0 will be mapped into port 0 o a7:a0 will be mapped into port 6 o a15:a8 will be mapped into port 2 f igure 7: n on -m ultiplexed e xternal data memory access representation the diagram below shows the timing of the external data memory bus when configured in non-multiplexed mode. f igure 8: n on -m ultiplexed e xternal data memory access assuming that the system clock operates at 40mhz, typical cycles for the external memory bus are as follows: parameter description typical value for system clock = 40mhz t adat time between a[14:0] stable and data stable 15ns t ard time between d[7:0] stable and wr falling edge 20ns t wr wr signal low time 50ns t ard time between a[14:0] stable and rd falling edge 50ns t rd rd signal low time 50ns vrs51l3xxx datasheet www.ramtron.com page 24 of 115 4.10 external data bus access for vrs51l31xx devices (qfp-44) the vrs51l31xx (qfp-44) family members also provide external memory bus access on the upper 32kb block of the 64kb external memory [8000h to ffffh]. two external data memory bus access operating modes are available: ? ? vrs51l3xxx datasheet www.ramtron.com page 25 of 115 in multiplexed addressing mode, external glue logic is required to multiplex lower addresses and data. typically, a 74x373 or 74x573 can be used for this purpose. the ale-cm0 pin serves to latch the lower 8 bits of the address. f igure 10: m ultiplexed e xternal data memory access representation vrs51l31xx ?373 ale p2[6:0] p0[7:0] d[7:0] a[14:8] a[7:0] d[7:0] the diagram below shows the timing of the external data memory bus when configured in multiplexed mode. f igure 11: m ultiplexed e xternal data memory access assuming that the system clock operates at 40mhz, typical cycles for the external memory bus are as follows: parameter description typical value for system clock = 40mhz t ale ale high time 25ns t addr time between addr[14:8] and ale rising edge 10ns t ad time a[7:0] is stable after ale falling edge 20ns t ard time between ale falling edge and rd falling edge 50ns t wr wr signal low time 50ns t rd rd signal low time 50ns 4.11 external data bus cs (dbcs) control lines in some applications, only a few external memory addresses are required to perform high speed data transfers between the microcontroller and peripherals, such as parallel access data converters. in this case, only a few address locations on the external data memory bus have to be accessed. the vrs51l3xxx provides a feature that can simplify interfacing to these peripherals . setting the extbuscs bit of the devmemcfg register to 1 will activate t he external bus control lines external bus cs mode can also work in standard 8051 external data memory buss access mode where lower 8 bits of address a[7: 0] and data d[7:0] are multiplexed. when both the extbuscs bit of the xmemctrl register and the extbusgen bit of the devmemcfg register are set to 1, the p2[7:4] pins of the vrs51l3xxx will act as an active high chip select pin named dbcsb[3:0]. the value of bits 13 and 12 of the target address will define the active dbcs line. a11:a0 carries the rest of the address bits. this is r epresented at the register level as follows: a15 a14 a13 a12 ? a0 x x cs1 cs0 ? as such, when the cs bus control mode is activated, the upper 32kb of the external data memory bus is seen as two overlapping blocks of 16kb. t able 29: e xternal memory bus cs control mode address range active as csbx pin 0000h- 7fffh none (4kb sram from 0000h to 0fffh) 8000h-8fffh dbcs0 (p2.4) 9000h-9fffh dbcs1 (p2.5) a000h-afffh dbcs2 (p2.6) b000h-bfffh dbcs3 (p2.7) c000h-cfffh dbcs0 (p2.4) overlap d000h-dfffh dbcs1 (p2.5) overlap e000h-efffh dbcs2 (p2.6) overlap f000h-ffffh dbcs3 (p2.7) overlap setting the extbuscfg bit of the xmemctrl register has no impact on the operation in external bus cs mode. the table on next page summarizes the mapping and the activity of the i/o pins associated with the external data memory bus when configured in external bus cs mode. vrs51l3xxx datasheet www.ramtron.com page 26 of 115 t able 30: p in mapping in e xternal m emory b us mode signal in ext. bus cs mode mapping / activity when extbuscfg = 0 multiplexed mapping / activity when extbuscfg = 1 non-multiplexed ale active inactive dbcs[3:0] p2[7:4] p2[7:4] address[11:8] p2[3:0] p2[3:0] address[7:0] p0[7:0] p6[7:0] (vrs51l30xx, qfp- 64 devices only data[7:0] p0[7:0] p0[7:0] p6 available as regular i/o address[7:0] (vrs51l30xx, qfp- 64 devices only rd active active wr active active us of the external memory bus in chip select mode with the extbuscfg bit set to 0 can be useful in applications where p6 may be required to function as an i/o port. signal timing associated with the external bus mode is represented below: f igure 12: e xternal data memory b us in chip select m ode (n on -m ultiplexed ) assuming that the system clock operates at 40mhz, typical cycles for the external memory bus are as follows: t able 31: timing associated with e xternal d ata m emory bus access parameter description typical value for system clock = 40mhz t adat time delay between address stable and data[7:0] in non- multiplexed mode 15ns t dwr1 time between data[7:0] stable and wr falling edge in non-multiplexed mode 20ns t ale ale high time 25ns t addr time between addr[14:8] and ale rising edge 15ns t a[7:0] time a[7:0] is stable after ale falling edge 50ns t dwr2 time between data[7:0] stable and wr falling edge. 20ns t wr wr signal low time 50ns 4.12 page addressing of the external sram using the mpage register the mpage register provides access to the entire external memory using indirect addressing through registers r0 and r1. the mpage register can be used to hold the upper 8 bit of the target address when using the movx @ri instruction which by definition is limited to a 256 bytes range. t able 32: m emory p age r egister - mpage sfr f1 h 7 6 5 4 3 2 1 0 r/w, reset = 0x00 mpage[7:0] = upper address byte 4.13 slowing down th e external data memory bus access the stretch[3:0] bit of the xmemctrl register allows the user to add cycles to the rd and wr signals. the ale signal is not affected by the stretch[3:0] configuration. for application requiring lower overall bus speed, we suggest lowering the system clock speed using the devclkcfg[3:0] register. the table below shows the impact of stretch[3:0] and the devclkcfg[3:0] on the external data memory bus access cycle time, assuming the vrs51l3xxx operates from the 40mhz internal oscillator. t able 33: i mpact of devclkcfg & s tretch [3:0] on e xt . d ata memory bus timings devclkcfg[3:0] stretch[3:0] rd/wr ale 0 0 50ns 25ns 0 1 75ns 25ns 0 2 100ns 25ns 0 8 250ns 25ns 4 0 800ns 400ns 4 8 4us 400ns the stretch[3:0] configur ation does not affect access to the 4kb sram and the 8kb f-ram. vrs51l3xxx datasheet www.ramtron.com page 27 of 115 5 device configuration 5.1 clock configuration register the vrs51l3xxx clock system is highly configurable. all vrs51l3xxx family members feature an internal 40mhz oscillator, eliminating the need for an external oscillator or crystal. however, an external standard parallel at or bt cut crystal can be used (frequency range of 4mhz to 40mhz). two sfr registers control the configuration of the clock source and the division ratio applied to the system clock source. the devclkcfg1 register selects either the internal oscillator or the external crystal oscillator as the system clock source. when the oscselect bit is cleared, the devices system clock comes from the external cr ystal oscillator (please see the next section). t able 34:d evice c lock c onfiguration r egister 1 - devclkcfg1 sfr f2 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 1 1 0 0 0 0 0 bit mnemonic description 7 softreset soft reset control bit 6 oscselect oscillator select 0 = external oscillator is selected 1 = internal oscillator is selected 5 clkdiven internal oscillator output clock divisor enable bit 0 = disable clock divisor 1 = enable clock division 4 fullspdint full speed interrupt mode 0 =processor will run with selected clock division during interrupts 1 = processor will run at full speed during interrupts 3:0 clkdiv[3:0] clkdiv value/clock division 0 = /1 1 = /2 2 = /4 3 = /8 4 = /16 5 = /32 6 = /64 7 = /128 8 = /256 9 = /512 a = /1024 b = /2048 c = /4096 d = /8192 e = /16384 f= /32768 soft reset operation a software reset can be performed on the vrs51l3xxx. this is executed via two consecutive instruction: the first instruction is to clear the softreset bit and the second is to set softreset bit to 1: examples of soft reset in asm: anl devclkcfg,#7fh; orl devclkcfg,#80h; in c : devclkcfg &= 0x7f; devclkcfg |= 0x80; when using a c compiler verify the compiler does convert the abovementioned instructions on two consecutive instructions performing a write into the devclkcfg register. the devclkcfg2 register activates the on-chip oscillator and the crystal osc illator. both oscillators can be activated independently, however, as previously mentioned, only one can be used as the vrs51l3xxx system clock source. t able 35:d evice c lock c onfiguration r egister 2 - devclkcfg2 sfr f3 h 7 6 5 4 3 2 1 0 r/w r/w r r r/w r/w r/w r 0 1 0 0 1 0 0 1 bit mnemonic description 7 cyoscen crystal oscillator enable 0 = crystal oscillator is disabled (default) 1 = crystal oscillator is enabled 6 intoscen internal oscillator enable 0 = internal oscillator is disabled 1 = internal oscillator is enabled (default) 5 reserved 4 reserved 3:2 cyrange[1:0] crystal oscillator range 00 = 25mhz ? 40mhz 01 = 4mhz to 25mhz 10 = 32khz to 100khz 11 = 32khz to 100khz 1 reserved 0 reserved always read as 1 the crystal oscillator is activated by setting the cyoscen bit of the devclkcfg2 register to 1 and selecting the cyrange value according to the frequency of the crystal used. the cyrange parameter controls the drive of the crystal oscillator circuit. the internal oscilla tor is activated by setting the intosen bit to 1. before switching from one os cillator source to another, it is important to make su re that both oscillators are active and stable at the moment the transition is made. the minimum period required for the crystal oscillator to stabilize depends on the type of crystal and the frequency used. in general, it is recommended to wait at least 1ms for the crystal oscillator to stabilize before switching to it. the stabilization time of the internal oscillator is much shorter than that of the crys tal oscillator. whenever the internal oscillator is reactivated, wait >2us before switching the system clock back to the internal oscillator. vrs51l3xxx datasheet www.ramtron.com page 28 of 115 5.2 switching from the internal to the external oscillator the following steps represent the recommended procedure for switching from the internal oscillator to the crystal oscillator: f igure 13: s witching from i nternal oscillator to external oscillator switching from internal to external oscillator activate crystal oscillator switch system operation to crystal oscillator wait for stabilization turn off the internal oscillator code example: internal to external devclkcfg2 = 0xc4; //enable the external oscillator: //range 4 to 25mhz and keep //the internal oscillator active delay(1); //stabilization time devclkcfg1 &= 0xbf; //select external oscillator devclkcfg2 &= 0xbf; //deactivate the internal oscillat o it is important to allow the crystal oscillator to stabilize before using it as the syst em clock. an instable oscillator may result in an operating frequency error or device volatility. 5.3 switching from the external oscillator back to the internal oscillator it is possible to switch system clock source to the internal oscillator while the device is running from the external oscillator. note that before switching the internal oscillator, it must be active. the following the sequence below is recommended in order to switch from the crystal oscillator back to the internal oscillator: f igure 14: s witching from e xternal oscillator to internal oscillator switching from external to internal oscillator activate internal oscillator switch system operation to internal oscillator wait for stabilization (2us) turn off the external oscillator code example: external to internal devclkcfg2 |= 0x40; //enable the internal oscillator: //and keep the external oscillat o //active delay(); //stabilization time (>2us) devclkcfg1 |= 0x40; //select internal oscillator delay(); //stabilization time (facultative) devclkcfg2 &= 0x7f; //deactivate the external oscillat o 5.4 system clock prescaler between the internal and the external oscillator modules and the main system clock tree, the vrs51l3xxx devices include a clock prescaler module enabling a dynamic division adjustment of the system clock frequency from fosc /1 to fosc/32768. this feature can be useful for saving power in battery- operated applications, in which the device clock speed can be adjusted to suit the processing power requirements. after a reset, the processor will boot up from the internal oscillator and the selected operating speed will be set to 20mhz i.e.. clkdiven is set to 1 and the clkdiv value is 1 (clk = fosc/2). clearing the clkdiven bit will deactivate the main clock prescaler. 5.5 interrupt processing speed configuration the vrs51l30xxx devices include a feature that allows interrupts to be processed at full speed, while the main program executes at a lower speed, as defined by the fullspdint value when the clkdiven bit is set to 1.this mode of operation can be useful for applications where high processing power is required for short periods of time. significant power saving can be achieved by dynamically adjusting the system clock frequency according to the processing power required. vrs51l3xxx datasheet www.ramtron.com page 29 of 115 code example: switching from internal to external oscillator example program /---------------------------------------------------------------------------------------------------------// //vrs51l3074_int_to_ext_to_int_osc_switching_test2-sdcc.c /---------------------------------------------------------------------------------------------------------// // // description: // test switching from internal osc to the external oscillator // then back to the internal oscillator...forever // 1) the program start from the internal oscillator with // duty = 50 / 50 for 100 cycles // 2) then it switch to external oscillator with a // duty of 50/20for 100 cycles // 3) it then switch to internal oscillator // 4) then it execute 100 cycles with a // duty of 20/50 for 100 cycles // 5) return to step 2 //--------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 30 of 115 5.6 processor mode control register the vrs51l3xxx devices provide two power saving modes: idle and power-down, which are controlled by the pdown and idle bits of the pcon register at address 87h. t able 36:p ower contro l r egister - pcon sfr 87 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 1 1 0 0 0 0 0 bit mnemonic description 7 oscstop oscillator stop control when this bit is set to 1, the vrs51l3xxx oscillator stops. a reset pulse or a power-on reset is required to restart the device 6 intmoden interrupt module enable 0 = interrupt module is disabled 1 = interrupt module is enabled (default) 5 devcfgen device configuration module enable 0 = device configuration module is disabled 1 = device configuration module is enabled 4 sfrindadr sfr indirect addressing enable 0 = nop instruction a5h behaves normally 1 = nop instruction a5h acts as a sfr indirect addressing instruction 3 gf1 general purpose flag 2 gf0 general purpose flag 1 pdown power-down mode enable when this bit is set to 1, the processor goes into power-down mode. a reset is required to exit power-down mode 0 idle idle mode enable when this bit is set to 1, the processor goes into power-idle mode. a reset or an interrupt is required to exit idle mode oscillator stop mode the oscillator stop mode goes one step further than the pdown mode. when the oscstop bit is set, all the oscillators are stopped, achieving maximum power saving, while maintaining the i/os in their current state. note that in this mode, the watchdog timer will stop functioning. in order to stop the oscilla tor of the vrs51l3xxx, clear the oscstop bit of the pcon register and then immediately set it to 1, as shown below: pcon &= 0x7f pcon |= 0x80 sfr indirect addressing capability the sfr registers on the vrs51l3xxx can be accessed via indirect addre ssing. this is accomplished by setting the sfrindadr bit of the pcon register. when sfrindadr is set, the a5h instruction functions as an sfr indirect addressing instruction (the default at reset is the nop instruction). pdown and idle power saving mode in idle mode, the processor clock is stopped, however the peripherals remain active. the contents of the sram, the state of the i/os and the sfr registers are maintained, as are the timer, external interrupt and uart operations. idle mode is useful for applications in which stopping the processor to save power is required. the processor will be activated when an external event, triggering an interrupt, occurs. in power-down mode, the vrs51l3xxx oscillator is stopped. while the clock to all the peripherals is deactivated, the contents of the sram and the sfr registers is maintained. the only way to exit power- down mode is via a hardware reset. in power-down and idle modes the watchdog timer continues to function. vrs51l3xxx datasheet www.ramtron.com page 31 of 115 5.7 peripherals enable register the vrs51l3xxx peripheral s can be individually activated. the periphen1 and periphen2 registers are used for this purpose. with the exception of the i/o ports, all peripherals and communication interfaces are in the disable state upon reset. when a given peripheral is inactive, read and write operations to its sfr registers will have no effect. to activate a given peripheral, the corresponding enable bit in the periphenx registers must be set to 1. the periphen1 register controls the activation of the: ? ? ? ? ? ? ? ? ? vrs51l3xxx datasheet www.ramtron.com page 32 of 115 5.8 peripheral i/o mapping and priority the pin locations of the following peripherals can be remapped to alternate pin positions: o timer 2 output o i2c o uart0 o uart1 o pwms this feature has been included to provide access to all peripherals. the following table lists the peripherals whose i/o positions are configurable: table 39: deviomap register - sfr e1h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 reserved 6 pwmaltmap pwm alternate mapping configuration 0 = pwm output on p2[7:0] 1 = pwm output on p5[7:0] 5 i2caltmap i2c alternate mapping configuration 0 = i2c scl, sda on p3.4, p3.5 1 = i2c scl, sda on p1.6, p1.7 4 u1altmap uart1 alternate mapping configuration 0 = uart1 rxd1, txd1 on p1.2, p1.3 1 = uart1 rxd1, txd1 on pin 41, pin 40 of qfp-64 package* 3 u0altmap uart0 alternate mapping configuration 0 = uart0 rxd0, txd0 on p3.0, p3.1 1 = uart0 rxd0, txd0 on p2.4, p2.3 timer 2 alternate mapping configuration t2 pin t2altmap = 0 t2altmap = 1 t2 p4.4 p1.2 t2in p1.0 p6.1* 2 t2altmap t2ex p1.1 p6.0* 1 t1altmap timer 1 output alternate mapping configuration 0 t0altmap timer 0 output alternate mapping configuration * only on vrs51l30xx, qfp-64 devices when the spi interface is enabled, the spi cs0 line is reserved for the spi interfac e, independent of the state of the spicsen bit. uart1 has priority over the spicsen bit of the periphen1 register. as such, even if the spi cs1, cs2 and cs3 lines are activated by setting the spicsen bit to 1, when uart 1 is used, it will override cs2 and cs3. additionally, when activated, the spi interface, has priority over the timer 2 input, even if timer 2 is enabled. 6 input/output ports the vrs51l30xx devices includes 56 i/o pins grouped into seven ports. the vrs51l31xx includes 40 i/o pins grouped into 5 ports to offer the maximum number of i/o pins, the pins typically reserved for exter nal program memory access can also be used as i/o interface pins. in addition, when the internal oscillator is enabled, the crystal oscillator pins can be used as regular i/os. all i/os are 5v-tolerant except for p4.6 and p4.7, which can endure a maximum input voltage of vdd+0.5v. 6.1 structure of the i/o ports all i/o ports on have the same structure. their main difference resides in the drive capability of the i/o ports, as shown in the following diagram: f igure 15: g eneral s tructure of the i/o pins ic pin oen input output provide 5v toltrance when i/o is configured as input it w ill be pulled up at 2.5v instead of 3.3v when the i/o ports are configured as inputs, the pin is pulled high to a voltage of about 2.50v, instead of the device voltage, which is 3.3v. an external pull-up resistor can be added to pull the i/o pin up to 3.3 volts or to 5 volts. vrs51l3xxx datasheet www.ramtron.com page 33 of 115 6.2 i/o ports direction configuration registers each i/o port on the vrs51l3xxx has dedicated sfr registers for read/write operations and for i/o pin direction. the pin directi on configuration registers allow the user to configure the direction of each individual i/o pin. writing a 1 to these register bit positions configures the corresponding i/o port as an input. to configure an i/o pin as an output, the corresponding bit in the pin direction configuration register must be cleared. because the pin direction configuration registers are not located at addresses that are multiples of x0h or x8h, they are not bit-addres sable. when a peripheral is activated, it takes control of the i/o pins and the i/o pin direction is conf igured automatically. the user can monitor the activity of any peripheral module input pin current state by configuring the corresponding i/o pin as an input and reading the port pin value. t able 40:p ort 0 pin direction config uration register - p 0 pincfg -sfr f9 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7 p07in1out0 when: 1 = i/o pin acts as a input (reset value) 0 = i/o pin acts as a output 6 p06in1out0 same as bit 7 5 p05in1out0 same as bit 7 4 p04in1out0 same as bit 7 3 p03in1out0 same as bit 7 2 p02in1out0 same as bit 7 1 p01in1out0 same as bit 7 0 p00in1out0 same as bit 7 when the external data memory bus access is activated, port 0 functions as d7:d0 and/or address a7:a0. t able 41:p ort 1 pin direction config uration register - p 1 pincfg -sfr fa h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7 p17in1out0 1 = i/o pin act as a input (reset value) 0 = i/o pin act as a output 6 p16in1out0 same as bit 7 5 p15in1out0 same as bit 7 4 p14in1out0 same as bit 7 3 p13in1out0 same as bit 7 2 p12in1out0 same as bit 7 1 p11in1out0 same as bit 7 0 p10in1out0 same as bit 7 t able 42:p ort 2 pin direction config uration register - p 2 pincfg -sfr fb h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7 p27in1out0 when: 1 = i/o pin acts as a input (reset value) 0 = i/o pin act as a output 6 p26in1out0 same as bit 7 5 p25in1out0 same as bit 7 4 p24in1out0 same as bit 7 3 p23in1out0 same as bit 7 2 p22in1out0 same as bit 7 1 p21in1out0 same as bit 7 0 p20in1out0 same as bit 7 when the external data memory bus is activated, except when in external bus cs mode, port 2 functions as address bus bits a15:a8. t able 43:p ort 3 pin direction config uration register - p 3 pincfg -sfr f ch 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7 p37in1out0 when: 1 = i/o pin act as a input (reset value) 0 = i/o pin act as a output 6 p36in1out0 same as bit 7 5 p35in1out0 same as bit 7 4 p34in1out0 same as bit 7 3 p33in1out0 same as bit 7 2 p32in1out0 same as bit 7 1 p31in1out0 same as bit 7 0 p30in1out0 same as bit 7 when the external data memory bus is activated, p3.6 and p3.7 function as wr and rd. t able 44:p ort 4 pin direction config uration register - p 4 pincfg -sfr fd h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7 p47in1out0 when: 1 = i/o pin acts as a input (reset value) 0 = i/o pin acts as a output 6 p46in1out0 same as bit 7 5 p45in1out0 same as bit 7 4 p44in1out0 same as bit 7 3 p43in1out0 same as bit 7 2 p42in1out0 same as bit 7 1 p41in1out0 same as bit 7 0 p40in1out0 same as bit 7 vrs51l3xxx datasheet www.ramtron.com page 34 of 115 t able 45:p ort 5 pin direction config uration register - p 5 pincfg -sfr fe h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7 p57in1out0 when: 1 = i/o pin acts as a input (reset value) 0 = i/o pin acts as a output 6 p56in1out0 same as bit 7 5 p55in1out0 same as bit 7 4 p54in1out0 same as bit 7 3 p53in1out0 same as bit 7 2 p52in1out0 same as bit 7 1 p51in1out0 same as bit 7 0 p50in1out0 same as bit 7 *vrs51l30 xx (qfp-64) devices only . o n vrs51l31 xx (qfp-44) devices the p5pincfg sfr can be used as user scratchpad register t able 46:p ort 6 pin direction config uration register - p 6 pincfg -sfr ff h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7 p67in1out0 when: 1 = i/o pin acts as a input (reset value) 0 = i/o pin acts as a output 6 p66in1out0 same as bit 7 5 p65in1out0 same as bit 7 4 p64in1out0 same as bit 7 3 p63in1out0 same as bit 7 2 p62in1out0 same as bit 7 1 p61in1out0 same as bit 7 0 p60in1out0 same as bit 7 *vrs51l30 xx (qfp-64) devices only . o n vrs51l31 xx (qfp-44) devices the p5pincfg sfr can be used as user scratchpad register 6.3 i/o ports input enable register upon reset, all the i/os are configured as inputs and the input control logic of all ports is activated. a given i/o port?s input logic can be deactivated by clearing the corresponding bit in the portinen register. t able 47:p orts i nput e nable register - portinen sfr f7 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7 reserved (0) keep this bit at 0 6 p6inputen* port 6 input enable register 0 = port 6 input logic is deactivated 1 = port 6 input logic is activated 5 p5inputen* port 5 input enable register 0 = port 5 input logic is deactivated 1 = port 5 input logic is activated 4 p4inputen port 4 input enable register 0 = port 4 input logic is deactivated 1 = port 4 input logic is activated 3 p3inputen port 3 input enable register 0 = port 3 input logic is deactivated 1 = port 3 input logic is activated 2 p2inputen port 2 input enable register 0 = port 2 input logic is deactivated 1 = port 2 input logic is activated 1 p1inputen port 1 input enable register 0 = port 1 input logic is deactivated 1 = port 1 input logic is activated 0 p0inputen port 0 input enable register 0 = port 0 input logic is deactivated 1 = port 0 input logic is activated *on vrs51l30xx, qfp-64 devices only 6.4 i/o ports sfr registers as is the case for standard 8051 devices, the i/o ports are mapped into sfr registers that are bit- addressable. at reset, the i/o ports are activated and configured as inputs. the i/o output drivers, unlike the original standard 8051 i/o output drivers, are of the push-pull type. therefore the i/o pins have the same output drive capability whether they are driving a logic high or a logic low, versus the standard 8051s, which feature an active low driver with a pull-up resistor. from a software point of view, the difference is that whenever the configuration of a given i/o has to be changed, the corresponding bit in the port direction configuration register must be set accordingly. vrs51l3xxx datasheet www.ramtron.com page 35 of 115 the following tables describe the sfr registers associated with the vrs51l3xxx i/o ports. on the vrs51l31xx (qfp-44) devices, the sfr associated to i/o port p5 and p6 are accessible, but not pinned out. these sfr can be used as bit addressable scratch pad registers if needed. t able 48:p ort 0 register - p0 sfr 80 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7:0 p0[7 :0] port 0 t able 49:p ort 1 register - p1 sfr 90 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7:0 p1[7 :0] port 1 t able 50:p ort 2 register - p2 sfr a0 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7:0 p2[7 :0] port 2 t able 51:p ort 3 register - p0 sfr b0 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7:0 p3[7 :0] port 3 t able 52:p ort 4 register - p4 sfr c0 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7:0 p4[7 :0] port 4 t able 53:p ort 5 register - p5 sfr 98 h (vrs51l30 xx (qfp-64) devices only ) 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7:0 p5[7 :0] port 5 t able 54:p ort 6 register - p6 sfr c8 h (vrs51l30 xx (qfp-64) devices only ) 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 bit mnemonic description 7:0 p6[7 :0] port 6 6.5 i/o port drive capability the current drive capability of the i/o ports is not the same for all ports. most i/o pins can drive 2ma and others can drive more in ei ther current source or current sink and can be used for direct led drive. the following table summarizes the vrs51l3xxx i/o port drive capabilities: t able 55:i/o p orts driving capability i/o port max current on individual pin port 0[7:0] 2ma port 1[7:5] port 1[4:0] 4ma 2ma port 2[7:0] 8ma port 3[7:6] port 3[5:4] port 3[3:0] 2ma 4ma 2ma port 4[7:0] 2ma port 5[7:0]* 16ma port 6[7:0]* 2ma *vrs51l30xx devices only it is not recommended to exceed the sink current specified in the table above. doing so will likely cause the low-level output voltage to exceed device specifications and affect device reliability. the recommended total dc load on the i/o ports should not exceed 100ma. vrs51l3xxx datasheet www.ramtron.com page 36 of 115 6.6 i/o port software specifics some instructions allow the user to read the logic state of the output pin, while others allow the user to read the contents of the associ ated port register. these instructions are called read-modify-write instructions. a list of these instructions may be found in the following table. upon executing these instructions, the content of the port register (at least 1 bit) is modified. the other read instructions take the present state of the input into account. for example, instruction anl p3,#01h obtains the value in the p3 register; performs the desired logic operation with the constant 01h and recopies the result into the p3 register. in order to monitor the present state of the inputs of an i/o port bit, first, read the port, and second, perform an and or an or operation, as required by the program: mov a, p3; state of the inputs in the accumulator anl a, #01; and operation between p3 and 01h when the port is used as an output, the register contains information on the state of the output pins. measuring the state of an out put directly on the pin is inaccurate because the voltage level depends mostly on the type of charge that is applied to it. the functions below perform the operation on the value of the port register rather than the actual port pin itself. t able 56: l ist of i nstructions that r ead and m odify the p ort u sing r egister v alues instruction function anl logical and ex: anl p0, a orl logical or ex: orl p2, #01110000b xrl exclusive or ex: xrl p1, a jbc jump if the bit of the port is set to 0 cpl complement 1 bit of the port inc increment the port register by 1 dec decrement the port register by 1 djnz decrement by 1 and jump if the result is not equal to 0 mov p.,c copy the held bit c to the port clr* p.x set the port bit to 0 setb p.x set the port bit to 1 * note : even though the cpu does not read in this case, it is considered a read-modify-write instruction. in mov dir, dir has an extra cycle when doing an sfr read during a debugger interrupt. the debugger memory is synchronous and is mapped into the sfr bus and, therefore, require s an extra read cycle. instruction a5, which is considered an nop in a standard 8051, has been redefined to perform write and read sfr indirect addressing. therefore, during a debugger interrupt, the a5 indirect read sfr addressing requires an extra cycle. 6.7 i/o port example programs code example : i/o ports toggle example this program shows the activation and configuration of ports p0 to p4 as outputs. the program continuously toggles their values. ;************************************************* ;* vrs51l3074 i/o ports toggle example * ;************************************************* start: mov periphen2,#08h ;enable io mov p0pincfg,#00h ;configure p0 as output mov p1pincfg,#00h ;configure p1 as output mov p2pincfg,#00h ;configure p2 as output mov p3pincfg,#00h ;configure p3 as output mov p4pincfg,#00h ;configure p4 as output mov periphen2,#00001000b ;bit7 - pwc1en ;bit6 - pwc0en ;bit5 - auen ;bit4 - xram2code ;bit3 - ioporten ;bit2 - wdten ;bit1 - pwmsfren ;bit0 - fpien // i/o output toggle loop loop: mov p0,#00h ;force p0 = 00h mov p1,#00h ;force p1 = 00h mov p2,#00h ;force p2 = 00h mov p3,#00h ;force p3 = 00h mov p4,#00h ;force p4 = 00h mov a,#100 ;wait 100ms using timer 0 acall delay1mst0 ;see timer section mov p0,#0ffh ;force p0 = ffh mov p1,#0ffh ;force p1 = ffh mov p2,#0ffh ;force p2 = ffh mov p3,#0ffh ;force p3 = ffh mov p4,#0ffh ;forc e p4 = ffh mov a,#100 ;wait 100ms using timer0 acall delay1mst0 ;see timer section ljmp loop the delay1ms function is described in the timers section. code example: i/o port read example ;------------------------------------------------------------------------------ ;* vrs51l3074 i/o ports read and write example ;------------------------------------------------------------------------------ portread equ 021h ;genreal variable start: mov periphen2,#08h ;enable io mov p0pincfg,#00h ;configure p0 as intput mov p1pincfg,#00h ;configure p2 as output ; note that the port input logic is activated by default mov periphen2,#00001000b ;bit7 - pwc1en ;bit6 - pwc0en ;bit5 - auen ;bit4 - xram2code ;bit3 - ioporten ;bit2 - wdten ;bit1 - pwmsfren ;bit0 - fpien ;*** read port 0 and copy the value to p2 loop: mov portread, p0 ;read prt 0 and store the value in a variable mov p2, portread ;write the variable content to p2 ajmp loop in this example, the port p0 value is stored in a variable before writing it to p2, but the user can also directly transfer p0 to p2 in one operation: loop: mov p2,p0 ;would do the same operation more efficiently ajmp loop vrs51l3xxx datasheet www.ramtron.com page 37 of 115 6.8 i/o port pin change monitoring the vrs51l3xxx includes an i/o port pin change monitoring subsystem. this module is used to monitor the activity on the selected i/o ports. when enabled, if a pin state changes on the selected i/o port, the pmonflag will be set to 1 by the system. it must be cleared manually by the software. the port pin change monitoring feature is very useful for monitoring events that can occur on a given group of i/os without having to constantly read the i/o state. since it is connected to the vrs51l3xxx interrupt subsystem, the port pin change monitoring system frees the processor resources for other tasks. t able 57:p ort c hange m onitoring register - portchg sfr b9 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 pmonflag1 port change monitoring flag1 when set, monitored port state has changed 6 pchgmsk1 port change mask register 1 0 = port monitoring is deactivated 1 = port monitoring is activated 5:4 pchgsel1[1:0 ] port change monitoring register select 1 00 = p4 change is monitored 01 = p5 change is monitored** 10= p6 change is monitored** 11 = p4[3:0] change is monitored 3 pmonflag0 port change monitoring flag 0 when set, monitored port state has changed 2 pchgmsk0 port change mask register 0 0 = port monitoring is deactivated 1 = port monitoring is activated 1:0 pchgsel0[1:0 ] port change monitoring register select 0 00 = p0 change is monitored 01 = p1 change is monitored 10 = p2 change is monitored 11 = p3 change is monitored **available on vrs51l30xx (q fp-64) devices only the port pin change monitoring flags, pmonflagx, are active at all times, ev en if the port change masks are not activated. the pchgmskx bits serve to connect the port change module to the vrs51l3xxx interrupt system. the port change monitoring flags must be cleared manually. i/o port pin change interrupt example programs 6.9 i/o port pin change monitoring code example code example: numeric keypad interface //--------------------------------------------------------------------------------------------------------------------// // vrs51l3074_keypadp0_lcdp1.c / //--------------------------------------------------------------------------------------------------------------------// // // description: character lcd and numeric keypad interface example program. // // this program initialize and sends lcd strings and numeric values // to a character based lcd display. // the program also demonstrate the use of the port change interrupt // feature of the vrs51l3074 to simplify the interface with a numeric keypad // on port 0. // the numeric keypad is a standard phone keypad which to connected to port 0 // as shown below: // column 3 - p0.7 // column 2 - p0.6 // column 1 - p0.5 // row 4 - p0.3 // row 3 - p0.2 // row 2 - p0.1 // row 1 - p0.0// // no external pull-up / pull down resistors are required, thank to the // presence of internal pull-up on the vrs51l3074 i/o ports. // // the interface to the lcd done through the vrs51l3074 port 1. // the lcd is initialized to operate in 4 bit data bus mode // // lcd interface structure: // ======================== // p1.0 = lcd rs // p1.1 = lcd rw // p1.2 = lcd e // p1.3 = (not used) // p1[7:4] = lcd data (4 bit mode) // notes about standard character lcd display interface to the vrs51l3074 // -most lcd displays operates on a 4.5v to 5.5v supply. // they won't work with the 3.3v supply the vrs51l3074 operate from // -on the digital side make sure the lcd module logic high level lower limit // is below 3v. // -the vrs51l3074 i/os are 5v tolerant, so there is no need to add interface // circuit between the lcd module's i/o and the vrs51l3074 i/o //--------------------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 38 of 115 //--------------------------------------------------------------------------------------------------------------------// // main function //--------------------------------------------------------------------------------------------------------------------// void main (void) { periphen1 = 0x01; //enable timer 0 lcdportdir = 0x00; //config lcd port as output //--configure keypad port and port change monitor keypadportdir = 0x0f; //keypadport bit 3:0 -> configured as input (lines) //keypadport bit 7:5->configured as output (columns) keypadport = 0x0f; //clear the columns driver outputs v2kdelay1ms(100); //put a 100 milliseconds delay portchg = 0x04; //disable port change monitoring module 1 //enable port change monitoring module 0 //clear the port change monitoring flag //port 0 change is monitored //-- activate port change interrupt intsrc1 &= 0xef; //force interrupt vector 4 to be routed to port change //module 0 inten1 |= 0x10; //enable the port change 0 module interrupt geninten = 0x01; //activate the global interrupts //--initialize the lcd initlcd(); //initialise the lcd module sendlcdcmd(lcd_l1c1); //place lcd cursor on line 1, column 1 cptr = 0; while( msg1[cptr] != '\0') //display "vrs51l3074" on first line of lcd display sendlcdchar( msg1[cptr++]); sendlcdcmd(lcd_l2c1); //place lcd cursor on line 2, column 1 cptr = 0; while( msg2[cptr] != '\0') //displ ay "waiting for key.\0" on 2 line of lcd display sendlcdchar( msg2[cptr++]); v2kdelay1ms(1000); //put a 1 seconds delay //--loop waiting for keys to be pressed while(1); //infinite loop }// end of main //----------------------------------------------------------------------------------------// //----------------------port change interrupt function(s //----------------------------------------------------------------------------------------// void portchange0int(void) interrupt 4 { unsigned char keypressed = 0x00; //var holding ascii value of the last key //pressed (could be global) unsigned char keylines = 0x00; //variable to read the actual i/o port unsigned char keyrow = 0x00; //row position of the pressed key unsigned char keycol = 0x00; //column position of the pressed key // rows and columns association table const char code keyrowmap[] = {0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x03,0x0f,0x0f,0x0f,0x02,0x0f,0x01,0x00,0x0f}; const char code keycolmap[]={0x0f,0x0f,0x0f,0x02,0x0f,0x01,0x00,0x0f}; // ascii code associated with pressed key const char code keyascii[4][3] = { {'1','2','3'}, {'4','5','6'}, {'7','8','9'}, {'*','0','#'}}; geninten = 0x00; //disable the global interrupts //--retrieve the line number keypadport = 0x00; //send 0 on each column v2kdelay1ms(10); //put a 10 millisecond delay keylines = keypadport; //read keypad port keylines &=0x0f; //isolate lower nibble if(keylines != 0x0f) { //-retrieve the line value keyrow = keyrowmap[keylines]; //--retrieve column number keypadportdir = 0xf0; //columns are input / rows are output keypadport = 0x00; //send 0 on each row v2kdelay1ms(10); //put a 10 millisecond delay keylines = keypadport; //read keypad port b = keylines; keylines &=0xe0; //isolate upper 3 bit (columns) keylines = (keylines >> 5); //position columns to lower portion //-retrieve the line value keycol = keycolmap[keylines]; if((keyrow != 0x0f)&& (keycol != 0xff)) { //--get the ascii value of the key keypressed = keyascii[keyrow][keycol]; sendlcdcmd(lcd_l2c1); /place lcd cursor on line 2, column 1 cptr = 0; while( msgkey[cptr] != '\0') //display "last key: \0" sendlcdchar( msgkey[cptr++]) //on second line of lcd display //display the key value on the lcd display sendlcdcmd(lcd_l2c10); //place lcd cursor on line 2, column 10 sendlcdchar(keypressed); }//end of if key row / col //--wait for the key to be released do{ b= keypadport; b &= 0xe0; }while(b != 0xe0 ); //--set keypadport as before keypadportdir = 0x0f; //columns are input / rows are output keypadport = 0x0f; //clear the columns driver outputs v2kdelay1ms(10); // put a 10 millisecond delay }//end of if keylines != 0xff portchg = 0x04; //disable port change monitoring module 1 //enable port change monitoring module 0 //clear the port change monitoring flag //port 0 change is monitored geninten = 0x01; //activate the global interrupts }//end of port change interrupt //--------------------------------------------------------------------------------------------------------------------// // individuals functions //--------------------------------------------------------------------------------------------------------------------// (see demonstration programs? ) vrs51l3xxx datasheet www.ramtron.com page 39 of 115 7 timers the vrs51l3xxx devices incl ude three 16-bit timers: timer 0, timer 1 and timer 2. the timers include much more functionality and features than standard 8051 timers: o timers 0, 1 can operate as one 16-bit timer or two 8-bit timers o timers can count up/count down o each timer includes a configurable divisor o timers can be chained together to form 24-, 32- or 48-bit timer/counters o each timer features an output that can generate a pulse or toggle when the timer overflows o each timer provides counter input o each timer provides a gating pin vrs51l3xxx devices timers include a number of parameters that can be adjusted independently, enabling countless configurations to suit a diversity of timing/counting applications. the structure of the timer configuration registers has been simplified compared to standard 8051 timer control registers. the architecture of the registers controlling the three timers is the same for timer 0 and timer 1 and almost the same for timer 2. on the vrs51l31xx devices (qfp-44) the following timer inputs are not accessible: ? ? ? ? vrs51l3xxx datasheet www.ramtron.com page 40 of 115 7.3 the t0con and t1con registers the t0con and t1con sfr registers control the following: o timer operation mode (timer or counter) o advanced gating features of timer 0 and timer 1 o timer overflow flag o counting direction (up/down) o timer reload and capture o timer output mode (pulse/toggle) these registers are fully orthogonal, which means that for a given timer operating mode, the registers function in the same manner. t able 61:t imer 0 c onfiguration register - t0con sfr 9a h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 t0ovf timer 0 overflow flag set to 1 when timer overflow from ffffh to 0000h. must be cleared by software. (t0 must be activated and running (tr0 = 1) to clear t0ovf). writing 1 into this bit will trigger a timer interrupt, if enabled 6 t0exf timer 0 external flag gating flag set to 1 when timer reload of capture is caused by an high to low transition on the t0ex pin, if t0exen is set to 1 5 t0downen timer 0 count down enable 0 = timer 0 count up 1 = timer 0 counts down 4 t0togout timer 0 output toggle enable 0 = timer 0 output outputs a pulse when it overflow occurs 1 = timer 0 output toggle when it overflow occurs 3 t0exten timer 0 external gating enable 0 = t0ex pin is not active 1 = enable timer 0 capture or reload upon a high to low transition on the t0ex pin when the timer 0 is configured in counter mode. 2 tr0 timer 0 run 0 = timer 0 is stopped 1 = timer 0 is running 1 t0counten timer 0 counter enable 0 = timer 0 acts as a timer 1 = timer 0 acts as a counter that is incremented (decremented) by a high to low transition on t0in pin 0 t0rlcap timer 0 capture enable 0 = auto reload value is loaded in timer 0, if a high to low transition occurs on t0ex, if t0exten is set to 1. 1 = timer 0 current value is captured when a high to low transition occurs on the t0ex pin, if t0exten is set to 1 t able 62:t imer 1 c onfiguration register - t1con sfr 9b h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 t1ovf timer 1 overflow flag get set to 1 when timer overflow from occurs. set to 1 when timer overflow occurs. must be cleared by software. (t1 must be activated and running (tr1 = 1) to clear t1ovf). writing 1 into this bit will trigger a timer interrupt, if enabled 6 t1exf timer 1 external flag gating flag get set to 1 when timer reload of capture is caused by an high to low transition on the t1ex pin, if t1exen is set to 1 5 t1downen timer 1 count down enable 0 = timer 1 count up 1 = timer 1 counts down 4 t1togout timer 1 output toggle enable 0 = timer 1 output outputs a pulse when timer overflow occurs 1 = timer 1 output toggle when it overflow from ffffh to 0000h 3 t1exten timer 1 external gating enable 0 = t1ex pin is not active 1 = enable timer 1 capture or reload upon a high to low transition on the t1ex pin when the timer 1 is configured in counter mode. 2 tr1 timer1 run 0 = timer 1 is stopped 1 = timer 1 is running 1 t1counten timer 1 counter enable 0 = timer 1 acts as a timer 1 = timer 1 acts as a counter that is incremented (decremented) by a high to low transition on t1in pin 0 t1rlcap timer 1 capture enable 0 = auto reload value is loaded in timer 1, if a high to low transition occurs on t1ex, if t1exten is set to 1 1 = timer 1 current value is captured when a high to low transition occurs on the t1ex pin, if t1exten is set to 1. the txovf bit of the txcon register indicates that the timer count has rolled over from ffffh to 0000h (or 0000h to ffffh). if the corresponding timer interrupt has been enabled, the txovf will raise the interrupt. txovf will not get set when the timer is configured in auto reload mode. the txexf flags are set to 1 when a high to low transition occurs on the corresponding txex pin, provided that the txexen pin is set to 1. timer 0 and timer 1 can count up or down. by default, the timers count up. however setting the txdownen bit to 1 will make the timer count down . the txcounten bit allows the timer to be configured as an external event counter. by default, the timers derive their source from the system clock or a prescaled source. setting the txcounten bit to 1, will c onfigure the corresponding timer to derive its source from the timer input pin (txin). a high to low transition on the timer input pin vrs51l3xxx datasheet www.ramtron.com page 41 of 115 will make the timer count one step up or one step down, depending on the value of the corresponding txdownen bit. the txrlcap bit defines the function of the timer capture/reload register upon a high to low transition on the txex timer trigger input pin. o txrlcap = 0 : auto reload value is loaded in timer x o txrlcap = 1 : timer x current value will be captured the functions associated with the txrlcap bit are only activated when the corresponding txexten bit is set to 1. 7.4 timer 0 / 1 current value register two sfr registers provide ac cess to the current 16-bit value of timer 0 and timer 1. t able 63:t imer 0 l ow - tl0 sfr 8a h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 tl0[7:0] t able 64:t imer 0 h igh - th0 sfr 8b h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 th0[7:0] t able 65:t imer 1 l ow - tl1 sfr 8c h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 tl1[7:0] t able 66:t imer 1 h igh - th0 sfr 8d h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 th0[7:0] 7.5 timer 0 reload and capture registers both timer 0 and timer 1 have an auxiliary 16-bit reload/capture register, which is accessible through two sfr registers as follows: t able 67:t imer 0 r eload and c apture l ow - rcap0l sfr 92 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 rcap0l[7:0] t able 68:t imer 0 r eload and c apture h igh - rcap0h sfr 93 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 rcap0h[7:0] t able 69:t imer 1 r eload and c apture l ow ? rcap1l sfr 94 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 rcap1l[7:0] t able 70:t imer 1 r eload and c apture h igh ? rcap1h sfr 95 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 rcap1h[7:0] the content of the timer reload capture registers (rcapxh / rcapxl) will be reloaded into the timer when the timer overflow occurs. vrs51l3xxx datasheet www.ramtron.com page 42 of 115 7.6 timer 0 / 1 output timer 0 and timer 1 outputs can be routed to an external pin. this feature is activated by setting the txouten bit of the txclkcfg register to 1. by default, the timer outputs, when enabled, will generate a pulse upon timer overflow. the duration of the pulse equals 1/ sys clk. setting the txtogout bit of the txcon register to 1 will configure the timer x output to toggle upon a timer overflow instead of generating a pulse. f igure 16: t imer 0, t imer 1 o utput modes timer 0/1 overflow txouten = 1 txtogout = 1 txouten = 1 txtogout = 0 7.7 timer 0 / 1 alternate mapping bits 0 and 1 of the deviomap register (sfr e1h) control the mapping of the timer 0 and timer 1 peripherals as shown in the following tables. t able 71: t imer 0 pin mapping deviomap.0 bit value t0in mapping t0ex mapping t0out mapping 0 (reset) p3.4 p2.6 p4.5 1 - pin 41 (vrs51l30xx) - t able 72: t imer 1 pin mapping deviomap.1 bit value t1in mapping t1ex mapping t1out mapping 0 (reset) p3.5 p2.5 p4.0 1 - pin 40 (vrs51l30xx) p1.4 vrs51l3xxx datasheet www.ramtron.com page 43 of 115 7.8 timer 0 / 1 functional diagram the following diagram represents the main features of timers 0 and 1 f igure 17: t imer 0, t imer 1 f unctional d iagram vrs51l3xxx datasheet www.ramtron.com page 44 of 115 7.9 timer 0 / 1 example programs code example: timer 0 1ms delay function ;******************************************************** ;* delay1msto : 1ms delay using timer0 ;*; *calibrated for 40mhz ;******************************************************** delay1mst0: mov cptr,a ;get number of cycles mov a,periphen1 ;load periphen1 reg orl a,#00000001b ;enable timer 0 mov periphen1,a delay1mslp: mov th0,#063h ;t0 reload value for 1ms at 40mhz mov tl0,#0c0h ;mov th0,#0a9h ;t0 reload value for 1ms at 22.11mhz ;mov tl0,#058h mov t0t1clkcfg,#00h ;no prescaler for t0 clock mov t0con,#00000100b ;start t0, count up dwaitovt0: mov a,t0con ;read t0 control, wait for ;overflow anl a,#080h ;isolate timer overflow flag jz dwaitovt0 ;loop as long as t0 don?t overflow mov t0con,#00h ;stop timer 0 djnz cptr,delay1mslp ;out loop mov a,periphen1 ;load periphen1 reg anl a,#11111110b ;disableble timer 0 mov periphen1,a ret code example: timer 0, timer 1 and timer 2 output toggle ;******************************************************************************* ;- timer 0, timer 1 and tmer 2, output toggle example * ;******************************************************************************* include vrs51l3xxx datasheet www.ramtron.com page 45 of 115 7.10 timer 2 the architecture of timer 2 is very similar to that of timers 0 and 1, the main difference being that timer 2 cannot operate as two 8-bit timers. 7.11 timer 2 configuration registers the t2con register controls: o timer operation mode (timer or counter) o timer 2 advanced gating features o timer 2 overflow flag o timer 2 counting direction (up/down) o timer 2 reload and capture o timer 2 output mode (pulse/toggle) the t2con register has the same structure as the t0con and t1con registers. t able 73:t imer 2 c onfiguration register - t2con sfr 9c h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 t2ovf timer 2 overflow flag set to 1 when timer overflow from ffffh to 0000h. must be cleared by software. (t2 must be activated and running (tr2 = 1) to clear t2ovf). writing 1 into this bit will trigger a timer interrupt, if enabled 6 t2exf timer 2 external flag gating flag set to 1 when timer reload of capture is caused by an high to low transition on the t2ex pin, if t2exen is set to 1 5 t2downen timer 2 count down enable 0 = timer 2 count up 1 = timer 2 counts down 4 t2togout timer 2 output toggle enable 0 = timer 2 output outputs a pulse when it overflows from ffffh to 0000h 1 = timer 2 output toggles when it overflows from ffffh to 0000h 3 t2exten timer 2 external gating enable 0 = t2ex pin is not active 1 = enable timer 2 capture or reload upon a high to low transition on the t2ex pin when the timer 2 is configured in counter mode. 2 tr2 timer2 run 0 = timer 2 is stopped 1 = timer 2 is running 1 t2counten timer 2 counter enable 0 = timer 2 acts as a timer 1 = timer 2 acts as a counter that is incremented (decremented) by a high to low transition on t2in pin 0 t2rlcap timer 2 capture enable 0 = auto reload value is loaded in timer 2 if a high to low transition occurs on t2ex, if t2exten is set to 1 1 = timer 2 current value is captured when a high to low transition occurs on the t2ex pin, if t2exten is set to 1 the t2ovf bit of the t2con register indicates whether the timer count has rolled over from ffffh to 0000h. if the corresponding timer interrupt has been activated, the t2ovf will ra ise the timer 2 interrupt.. the t2exf flags are set to 1 when a high to low transition occurs on the t2ex pin, provided that the t2exe pin is set to 1. as is the case for timers 0 and 1, timer 2 can be configured to count up or down. by default, timer 2 counts up. however setting the t2downen bit to 1 will configure timer 2 to count down. when the timer counts downwards, the overflow flag will be set when the timer counts from 0000h to ffffh. the t2counten bit- enables the configuration of timer 2 as a external event counter. by default, timer 2 derives its source from the system clock or a prescaled system clock. setting the t2counten bit to 1 will configure timer 2 to derive its source from the t2in input pin. a high to low transition on the t2in pin will initiate a timer count one step up or down, depending on the value of the corresponding t2downen bit. the t2rlcap bit controls the function of the timer capture/reload register when a high to low transition occurs on the t2ex timer trigger input pin. o t2rlcap = 0 : auto reload value is loaded in timer 2 o t2rlcap = 1 : timer 2 current value will be captured in the rcap2l and rcap2h registers the functions associated with the t2rlcap bit are only activated when the t2exten bit is set to 1. t able 74:t imer 2 l ow - tl2 sfr 8e h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 tl2[7:0] t able 75:t imer 2 h igh ? th2 sfr 8f h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 th2[7:0] vrs51l3xxx datasheet www.ramtron.com page 46 of 115 7.12 timer 2 reload and capture registers t able 76:t imer 2 r eload and c apture l ow ? rcap2l sfr 96 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 rcap2l[7:0] t able 77:t imer 2 r eload and c apture h igh ? rcap2h sfr 97 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 rcap2h[7:0] the content of the timer 2 reload capture registers (rcap2h / rcap2l) will be reloaded into the timer when the timer overflow occurs. 7.13 the timer 2 clock configuration register the t2clkcfg register is used to configure the clock source for timer 2. the source can be either a prescaled value of the system clock or the output of timer 1. the timer 2 clock source is also controlled by the t2clksrc bit. when this bit is set to 1, timer 2 derives its source from the timer 1 overflow. if t2clksrc is set to 0, timer 2 will derive its source from a prescaled value of the system clock. the division factor applied to the system clock is defined by t2clkcfg[3:0] t able 78:t imer 2 c lock c onfiguration r egister - t2clkcfg sfr 9d h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 - 6 - 5 t2clksrc timer 2 clock source 0 = timer 2 take its clock from system clock 1 = timer 2 takes its clock from timer 1 output 4 t2outen timer 2 output enable 0 = timer 2 output is deactivated 1 = timer 2 output is connected to a pin 3:0 t2clkcfg[3:0] timer 2 clock prescaler configuration see table below the following table outlines the timer 2 prescaler values according to the value of the t2clkcfg[3:0] bits. t able 79:t imer 2 c lock division ratio t2clkcfg (4 bit binary) timer clock div. ratio t2clkcfg timer clock div. ratio 0000 1 1000 256 0001 2 1001 512 0010 4 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 16384 7.14 timer 2 output as is the case for timers 0 and 1, timer 2?s output can be routed to an external pin. this feature is activated by setting the t2outen bit of the t2clkcfg register to 1. by default, the timer 2 output, when enabled, will generate a pulse upon timer 2 overflow. the duration of the pulse is (1/ sys clk). setting the t2togout bit of the t2con register to 1 will configure timer 2?s out put to toggle upon a timer 2 overflow instead of outputting a pulse. f igure 18: t imer 2 o utput modes timer2 overflow t2outen = 1 t2togout = 1 t2outen = 1 t2togout = 0 7.15 timer 2 alternate mapping bit 2 of the deviomap register (sfr e1h) controls the mapping of the timer 2 interface as shown in the following table: t able 80: t imer 2 pin mapping deviomap.2 bit value t2in mapping t2ex mapping t2out mapping 0 (reset) p1.0 p1.1 p4.4 1 p6.1** p6.0** p1.2 **only on vrs51l30xx (qfp-64) devices. alternate mapping allows timer 2?s output to be mapped into p1.2 instead of p4.4 this can be useful for applications where both uart0 and uart1 are required. vrs51l3xxx datasheet www.ramtron.com page 47 of 115 7.16 timer 2 functional diagram the following diagram describes the main features of timer 2. f igure 19: t imer 2 f unctional d iagram **the t2in alternate and t2ex alternate input are only accessible on vrs51l30xx (qfp-64) devices vrs51l3xxx datasheet www.ramtron.com page 48 of 115 7.17 timers chaining the three timers of the vrs51l3xxx devices can be chained together to form a 24-, 32- or 48-bit timer that can be used for very long delay timing. longer delays can be achieved by using t he system clock prescalers. the following provides an example of time delays that can be achieved by timer chaining: t able 81: t ime delays vs . t imer size for 40mh z s ystem c lock timer size time out period 16 bit 1.638 milliseconds 24 bit 419 milliseconds 32 bit 107 sec-seconds 48 bit 7.037x10e6 seconds (1954.6 hours) the following diagram provides a schematic representation of timer chaining. f igure 20: t imer chaining sys clk t0clkcfg div ratio: sys clk / 1 down to sysclk / 16384 t2clkcfg div ratio: sys clk / 1 down to sysclk / 16384 0 1 timer 2 timer 1 t1clkcfg div ratio: sys clk / 1 down to sysclk / 16384 0 1 timer 0 out out out t1clksrc t2clksrc note that timer chaining does not affect other timer features such as: o timer capture o timer auto-reload o timer output it is also possible to couple the timer chaining capability with the pulse width counter (see next section), to count long duration events. 8 pulse width counters (pwc) the vrs51l3xxx devices provide two independent pulse width counter modules associated with timers 0 and 1. the pulse width counter modules provide advanced timer control, the user to define which event will make the timer start and stop. contrary to standard timer capture module units, the pwc unit can be used to measure the duration of an event. the following two diagrams provide a schematic view of the pwc modules? structure and functionality. f igure 21: pwc0 m odule s tructure pwc0rst timer 0 timer 0 div ratio: sys clk / 1 downto sys clk / 16384 sys clk 015 00 01 10 11 edge detect edge detect 0 1 00 01 10 11 edge detect edge detect 0 1 pwc0stsrc pwc0endsrc p3.2-int0 pin p3.0-rxd0 pin p2.4-pwm4 pin p3.4-t0in-scl pin rst rst rst rst rst pwc0stpol pwc0endpol pwc0if pwc0rst (status) f igure 22: pwc1 m odule s tructure pwc1rst timer 1 timer 1 div ratio: sys clk / 1 downto sys clk / 16384 sys clk 015 00 01 10 11 edge detect edge detect 0 1 00 01 10 11 edge detect edge detect 0 1 pwc1stsrc pwc1endsrc p3.3-int1 pin p1.2-rxd1 pin rxd1 pin p1.6-sck pin rst rst rst rst rst pwc1stpol pwc1endpol pwc1if pwc1rst (status) note: the pc1.2 input is not accessible on the vrs51l31xx (qfp- 44) devices the pwc modules interact with timers 0 and 1. combining the pwc module configuration with the timer configuration provides added flexibility to the operating modes. two sfr registers (pwc0cfg and pwc1cfg located at addresses 9eh and 9fh, respectively) are dedicated to pwc configuration. vrs51l3xxx datasheet www.ramtron.com page 49 of 115 t able 82:p ulse w idth c ounter 0 c onfig . register - pwc0cfg sfr 9e h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 pwc0if pulse width counter module 0 interrupt flag 0 = no pwc0 interrupt occurred 1 = pwc0 interrupt occurred read: pulse width counter operation status 0 = pwc0 is waiting for start condition 1= pwc0 is currently counting 6 pwc0rst write: pulse width counter reset 0 = no action 1 = reset pwc0 operation and pwc0if pwc0 will wait for a start condition 5 pwc0endpol pwc0 end event polarity 0 = pwc0 end event is a rising edge 1 = pwc0 end event is a falling edge 4 pwc0stpol pwc0 start event polarity 0 = pwc0 start event is a rising edge 1 = pwc0 start event is a falling edge 3:2 pwc0endsrc [1:0] pwc0 end source 00 = p3.2 01 = p3.0 10 = p2.4 11 = p3.4 1:0 pwc0stsrc [1:0] pwc0 start source 00 = p3.2 01 = p3.0 10 = p2.4 11 = p3.4 t able 83:p ulse w idth c ounter 1 c onfig . register - pwc1cfg sfr 9f h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 pwc1if pulse width counter module 0 interrupt flag 0 = no pwc1 interrupt occurred 1 = pwc1 interrupt occurred read: pulse width counter operation status 0 = pwc1 is waiting for start condition 1= pwc1 is currently counting 6 pwc1rst write: pulse width counter reset 0 = no action 1 = reset pwc1 operation and pwc0if pwc0 will wait for a start condition 5 pwc1endpol pwc1 end event polarity 0 = pwc1 end event is a rising edge 1 = pwc1 end event is a falling edge 4 pwc1stpol pwc1 start event polarity 0 = pwc1 start event is a rising edge 1 = pwc1 start event is a falling edge 3:2 pwc1endsrc [1:0] pwc1 end source 00 = p3.3 01 = p1.2 10 = rxd1 (alternate) ** 11 = p1.6 1:0 pwc1stsrc [1:0] pwc1 start source 00 = p3.3 01 = p1.2 10 = rxd1 (alternate) ** 11 = p1.6 ** accessible on vrs51l30xx (qfp-64) devices only the configuration of the pwc module involves the following steps: o activate the pwc module o activate timer and configure in gating mode o configure pwc start and stop source o configure pwc start and stop event o initialize timer to 0x0002 o activate pwc interrupt, if required 8.1 pwc module initialisation the pwc0/1 modules operate in conjunction with timers 0/1. the timer must be activated and configured in gating mode immediately after the pwc modules have been enabled. to obtain a precise measurement of the event duration, the timer registers [thx,tlx] must be initialized to 00, 02h. once a stop event occurs, the event duration in terms of system cycles is stored in the timer registers. once the timer has been read, the software must clear it for the next event. // pwc0 timer initialization ptr = (char idata *) &result_dump_start_address_pwc0; periphen2 |= 0x40; //enable pwc0 (enabled first to gate timer //before timer enable !!!) periphen1 |= 0x01; //enable timer 0 t0t1cfg = 0x02; //set timer 0 in gate mode tl0 = 0x02; /initialize timer th0 = 0x00; pwc0cfg |= 0x15; //configure pwc0 module to start on a falling edge and //end on a rising edge on pin p3.0 for both events the timer start source can differ from the timer stop source and the start event can differ from the end event. the pwc start and end sources are defined by the pwcxstsrc bits of t he pwcxcfg register as shown in the following tables: t able 84:p ulse w idth c ounter 0 s tart / s top souce co nfiguration pwc0stsrc pwc0 start source pwc0endsrc pwc0 end source 00 p3.2 ? int0 00 p3.2 ? int0 01 p3.0 ? rxd0 default 01 p3.0 ? rxd0 default 10 p2.4 ? rxd0 alternate 10 p2.4 ? rxd0 alternate 11 p3.4 ? t0in 11 p3.4 ? t0in t able 85:p ulse w idth c ounter 1 s tart / s top souce co nfiguration pwc1stsrc pwc1 start source pwc1endsrc pwc1 end source 00 p3.3 ? int1 00 p3.3 ? int1 01 p1.2 ? rxd1 default 01 p1.2 ? rxd1 default 10 rxd1 alternate ** 10 rxd1 alternate ** 11 p1.6 11 p1.6 ** accessible on vrs51l30xx (qfp-64) devices only vrs51l3xxx datasheet www.ramtron.com page 50 of 115 start and stop events must be triggered by either a rising edge or a falling edge of the selected start and stop source. the pwc start source polarity is defined by the pwcxstpol and the stop source polarity is defined by the pwxcendpol. when these bits are cleared, the pwc module will be triggered by a rising edge (low to high). setting these bits to 1 configures the pwc to be triggered by a falling edge (high to low). 8.2 pwc module reset and interrupt flags the pwcxrst bit, when set to 1 will reset the pwc module and clear the pwcxif flag if it is set. the pwc module will then wait for the start condition. the pwcxrst flag provides the current state of the pwc module as follows: t able 86: d efinition of pwc x rst bit when read pwcxrst reads as then? 0 pwc module is waiting for a start condition 1 pwc module is currently counting the pwcxif bit will be set to 1 when a stop condition is encountered by the pwc module. the pwcxif must be cleared by the program. one interrupt vector (int 11) is allocated for the two pwc modules and its vector address is 005bh. note: o the pwcxif flag remains active even if the corresponding pwc interrupt is disabled. o the pwcxif flags are not automatically cleared when exiting the interrupt service routine. they must be cleared manually by the software. 8.3 pwc example program code example: the following example program demonstrates how to configure and use the pwc1 module in pooling mode. //-----------------------------------------------------------------------------------------------------------------// // v2k_pwc1p1in_t2out_sdcc.c // //---------------------------------------------------// // // description: for this demonstration program timer 2 is configured to // continuously run in output toggle mode on its alternate output (p1.2) and // is used to generate the stimuli required for the pwc1 module input. // the port 0 is used to monitor the activity of the pwc1 module. // // target: vrs51l2xxx/vrs51l3xxx /----------------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 51 of 115 9 uart serial ports the serial ports on the vrs51l3xxx devices operate in full duplex mode. however, the communication speed will be the same for transmission and reception. communication speed is derived from an internal 16- bit baud rate generator dedicated to each of the uarts. 9.1 uart0 rx / tx data buffer the serial port features double buffering on the receiving side. the sf r register, uart0buf, provides access to the transmit and receive registers of the serial port. when a read operation is performed on the uart0buf register, it will access the receive register double buffer. when a write operation is performed on the uart0buf, the transmit register will be loaded with the value to be transmitted. t able 87:uart0 data rx / tx r egister uart0buf sfr a3 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 uart0buf[7:0] read: uart0 receive buffer write: uart0 transmit buffer 9.2 uart0 configuration registers the configuration of the ua rt0 is controlled by the uart0cfg, the uart0brh and uart0blh registers and the uart 0ext registers. t able 88:uart0 configuration register - uart0cfg sfr a2 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 0 0 0 0 0 bit mnemonic description 7:4 bradj[3:0] uart0 baud rate fine adjustment * see formula below 3 brclksrc baud rate clock source 0 = baud rate generator uses oscillator 1 = baud rate generator uses external clock source 2 b9rxtx read: last received 9 th bit write: 9 th bit to transmit 1 b9en 9 th bit mode enable 0 = data transfer are in 8-bit format 1 = data transfer are in 9-bit format 0 stop2en enable two stop bit mode 0 = one stop bit 1 = two stop bit t able 89:uart0 b aud r ate r egister l ow ? uart0brl sfr a4 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 uart0brl[7:0] uart0 lsb of baud rate generator t able 90:uart0 b aud r ate r egister h igh ? uart0brh sfr a5 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 uart0brh[7:0] uart0 msb of baud rate generator t able 91:uart0 e xtensions c onfiguration - uart0ext sfr a6 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 1 0 0 0 0 0 bit mnemonic description 7 u0timerf uart0 timer flag 6 u0timeren uart0 timer enable 5 u0rxstate uart0 rx line state 4 multiproc when set, rx_available only raise if the ninth received bit is '1' 3 reserved leave as 0000 9.3 uart0 interrupt configuration the activation of the uart0 interrupt is a two-stage process that involves enabling the interrupts at the uart0 module level and then activating the uart0 interrupt at the system level through the inten1 register. the upper nibble of the uart0int register contains the uart0 interrupt activation bits and the lower nibble contains the uart0 interrupt flags in the same order. two interrupt vectors are as sociated with uart0. the first interrupt vector is at address 002bh and handles all uart0 interrupt conditions, except for the uart0 data collision interrupt (vector address 0053h), which is shared with the uart1 data collision and the i2c master lost arbitration interrupts. the interrupt flags allow the interrupt service routine to define which condition triggered the interrupt, and to react accordingly. note that the interrupt flags do not require the interrupt to be enabled in order to be operational. they can be monitored by the software at any time. vrs51l3xxx datasheet www.ramtron.com page 52 of 115 t able 92: uart0 i nterrupt r egister - uart0int sfr a1 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r, w r/w r, w r 0 0 0 0 0 0 0 1 bit mnemonic description 7 colen uart0 collision interrupt enable 0 = collision interrupt is deactivated 1 = collision interrupt is enabled 6 rxoven uart0 rx overrun interrupt enable 0 = rx overrun interrupt is deactivated 1 = rx overrun interrupt is enabled 5 rxavailen uart0 rx available interrupt enable 0 = rx available interrupt is deactivated 1 = rx available interrupt is enabled 4 txemptyen uart0 tx empty interrupt enable 0 = tx empty interrupt is deactivated 1 = tx empty interrupt is enabled (read) collision interrupt flag when this flag is set by the uart0 module, it indicates that a collision occurred 3 colenf (write) 0 = collision detection is disabled and the collision colenf is reset 1 = a bus collision stops the transmission and raises the colenf flag 2 rxovf uart0 rx overrun flag when set to 1 by the uart0 interface, it indicates that a data collision occurred in the uart0buf register 1 rxavenf r: uart0 rx available flag when set to 1 by the uart0 interface, it indicates that data has been received in the uart0buf register. will be automatically cleared when uart0buf is read w: uart rx enable writing 1 into this bit position will activate reception on uart0. clearing this bit 0 will deactivate the reception on uart0 0 txemptyf uart0 tx empty flag when set to 1, it indicates that the transmit portion of the uart0buf is ready to receive another byte 9.4 uart1 rx/tx data buffer the sfr register (uart1buf) provides access to the transmit and receive registers of the serial port. when a read operation is performed on the uart1buf register, it will access t he receive register. when a write operation is performed on the uart1sbuf, the transmit register will be loaded with the value to be transmitted. t able 93:uart1 data rx / tx r egister uart1buf sfr b3 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 uart1buf[7:0] read: uart1 receive buffer write: uart1 transmit buffer 9.5 uart1 configuration registers the configuration of the ua rt1 is controlled by the uart1cfg, uart1brh and uart1blh registers and the uart1ext registers. t able 94:uart1 configuration register - uart1cfg sfr b2 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 1 1 1 0 0 0 0 0 bit mnemonic description 7:4 bradj[3:0] uart1 baud rate fine adjustment * see formula below 3 brclksrc baud rate clock source 0 = baud rate generator uses oscillator 1 = baud rate generator uses external clock source 2 b9rxtx read: last received 9 th bit write: 9 th bit to transmit 1 b9en 9 th bit mode enable 0 = data transfer are in 8-bit format 1 = data transfer are in 9-bit format 0 stop2en enable two stop bit mode 0 = one stop bit 1 = two stop bit t able 95:uart1 b aud r ate r egister l ow ? uart1brl sfr b4 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 uart1brl[7:0] uart1 lsb of baud rate generator t able 96:uart1 b aud r ate r egister h igh ? uart1brh sfr b5 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 uart1brh[7:0] uart1 msb of baud rate generator vrs51l3xxx datasheet www.ramtron.com page 53 of 115 t able 97:uart1 e xtensions c onfiguration - uart1ext sfr b6 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 1 0 0 0 0 0 bit mnemonic description 7 u1timerf uart1 timer flag 6 u1timeren uart1 timer enable 5 u1rxstate uart1 rx line state 4 multiproc when set, rx_available, only raise if the ninth received bit is '1' 3:0 reserved reserved. leave these bit to 0 9.6 uart1 interrupt configuration the activation of uart1?s interrupt is a two stage process that involves enabling the interrupts at the uart1 module level and then activating the uart1 interrupt at the system level through the inten1 register. t able 98: uart1 i nterrupt r egister - uart1int sfr b1 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r, w r/w r, w r 0 0 0 0 0 0 0 1 bit mnemonic description 7 colen uart1 collision interrupt enable 0 = collision interrupt is deactivated 1 = collision interrupt is enabled 6 rxoven uart1 rx overrun interrupt enable 0 = rx overrun interrupt is deactivated 1 = rx overrun interrupt is enabled 5 rxavailen uart1 rx available interrupt enable 0 = rx available interrupt is deactivated 1 = rx available interrupt is enabled 4 txemptyen uart1 tx empty interrupt enable 0 = tx empty interrupt is deactivated 1 = tx empty interrupt is enabled (read) collision interrupt flag when this flag is set by the uart1 module, it indicates that a collision has occurred 3 colenf (write) 0 = collision detection is disabled and the collision colenf is reset 1 = a bus collision stops the transmission and raises the colenf flag 2 rxovf uart1 rx overrun flag when set to 1 by the uart1 interface, it indicates that a data collision has occurred in the uart0buf register 1 rxavenf r: uart1 rx available flag when set to 1 by the uart0 interface, it indicates that data has been received in the uart1buf register. will be automatically cleared when uart1buf is read w: uart rx enable writing 1 into this bit position will activate reception on uart1. clearing this bit 0 will deactivate the reception on uart0 0 txemptyf uart1 tx empty flag when set to 1, it indicates that the transmit portion of the uart1buf is ready to receive another byte 9.7 uart0, uart1 baud rate formula the uart0 baud rate is programmed using the following formula: baud rate = fclk 32x (uartxbr[15:0] + bradj[3:0]/16 + 1) the bradj[3:0] bits are used for fine adjustment of the baud rate. the following steps demonstrate using the uartxbr[15:0] and bradj[3:0] registers to set the appropriate baud rate. step 1: defining the optimal uartxbr[15:0] value use the following formula to set the uartxbr[15:0] register to the integer component of uartxbrideal: uartxbr ideal = fclk - 1 32x (baud rate ) note that the baud rate will likely contain a fractional component. valid uartxbr[15:0] values range from 0x0000 to 0xffff. step 2: defining the optimal bradj[3:0] value use the following formula to set the bradj[3:0]: bradj[3:0] = round[ (uartxbrideal ? uartxbr[15:0]) * 16] the bradj[3:0] register can only contain an integer value between 0x00 and 0x0f. step 3: calculating the error the actual baud rate vs. the ideal baud rate can be calculated using the following formula: error % = 100x [ (fclk /32*(uartxbr[15:0]+bradj[3:0]/16 +1))-baud rate] baud rate in order to achieve reliable communication, the error should be below 2 percent. vrs51l3xxx datasheet www.ramtron.com page 54 of 115 the following table provides configuration examples for typical baud rates when the internal 40mhz oscillator is used: t able 99: uarts b aud r ate configurat ion examples ( sys clk =40m hz ) com speed uartxbr [15:0] bradj [3:0] actual baud rate error (%) 230400bps 0004h 07h 229885.1 -0.22 115200bps 0009h 0eh 114942.5 -0.22 57600bps 0014h 0bh 57636.9 0.06 38400bps 001fh 09h 38387.7 -0.03 31250bps 0027h 00h 31250.0 0 28800bps 002ah 06h 28818.4 0.06 19200bps 0040h 02h 19193.9 -0.03 9600bps 0081h 03h 9601.5 0.01 4800bps 0103h 07h 4799.6 -0.01 2400bps 0207h 0dh 2400.1 0 1200bps 0410h 0bh 1200.0 0 300bps 1045h 0bh 300.0 0 9.8 uart0, alternate mapping upon reset, uart0?s rxd0 and txd0 signals are mapped into pins p3.0 and p3.1, respectively. it is possible to re-map the rxd0 and txd0 signals into pins p2.4 and p2.3. bit 3 of the deviomap register (sfr e1h) controls the mapping of the uart0 in terface, as shown in the following table: t able 100: uart0 rxd0 / txd0 pin mapping deviomap.3 bit value rxd0 mapping txd0 mapping 0 (reset) p3.0 p3.1 1 p2.4 p2.3 when alternate mapping for uart0 is used, the uart0 will have priority over the pwm3 and pwm4 outputs. 9.9 uart1, alternate mapping upon reset, uart1?s rxd1 and txd1 signal are mapped into pins p1.2 and p1.3, respectively. it is possible to map uart1?s rxd1 and txd1 signals into pins 41 and 40 of the vrs51l30xx (qfp-64) devices. bit 4 of the deviomap register (sfr e1h) controls the mapping of the uart1 in terface as shown in the following table: t able 101: uart1 rxd1 / txd1 pin mapping deviomap.3 bit value rxd1 mapping txd1 mapping 0 (reset) p1.2 p1.3 1 pin 41 ** pin 40 ** ** vrs51l30xx (qfp-64) devices only 9.10 uart example program configuration of uart0 is essentially the same as uart1 code example: uart echo and external interrupt configuration //-------------------------------------------------------------------------------------------------------------------// // v3k_uart0_echo_rxint_int0_int1_sdcc.c // //-----------------------------------------------------------------// // // this program initialise the uart0 at 115200 (running from 40mhz internal oscillator) // it then transmit "uart0 echo: waiting for char on rxd0...or int0\0" on txd0. // the uart, int0 and int1 are configured and the program enters in infinite loop waiting for an interrupt // as soon as a character is received it is transmitted back on txd0 // if int0 or int1 is received the program transmit "ext int0 received" or ext int1 received" // on txd0 depending on which interrupt was received. // while waiting for interrupts, the software toggle p4 every 10ms //---------------------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 55 of 115 }while(msgint0[cptr]!= '\0'); txmit0(13); //send carriage return txmit0(10); //send line feed inten1 = 0x23; //enable uart0 interrupt + int0 + int1 }//end of int0 interrupt //--------------------------------// //----- interrupt int1 ------// //-------------------------------// void int1interrupt(void) interrupt 1 { char cptr = 0x00; // init cptr to pint to message beginning inten1 = 0x00; //disable interrupt //-- send "ext int1 received" on uart0 do{ b = msgint1[cptr++]; txmit0(b); }while(msgint1[cptr]!= '\0'); txmit0(13); //send carriage return txmit0(10); //send line feed inten1 = 0x23; //enable uart0 interrupt + int0 + int1 }//end of int0 interrupt //-----------------------------------// //--- uart0 interrupt --------// //-----------------------------------// void uart0interrupt(void) interrupt 5 { char genvar; inten1 = 0x00; //disable uart0 interrupt //check if interrupt was caused by rx avail genvar = uart0int; if(genvar & 0x02) txmit0(uart0buf); //send back the received character //check if interrupt was caused by rx overrun if(genvar &= 0x04) { genvar = uart0buf; //read s0buf to clear rx ov condition... //***this is mandatory because otherwise //the rx ov condition keep //interrupt activated txmit0(' '); //send " ov!" on serial port txmit0('o'); // txmit0('v'); // txmit0('!'); // }if(genvar &= 0x04) inten1 = 0x23; //enable uart0 interrupt + int0 + int1 }//end of uart0 interrupt //----------------- individual functions --------------------- //----------------------------------------------------------------------------------------// // uart0 config // // configure the uart0 to operate in rs232 mode at 115200bps. // vrs51l2070 running from the internal 40mhz oscillator // //---------------------------------------------------------------------------------------// void uart0config() { //--initialize uart0 at 115200bps @ 40mhz uart0cfg = 0xe0; //fine adjustment on baud rate //use internal clock //9th bit not used //only one stop bit uart0int = 0x62; //enable rx av + rxo v int + enable reception uart0ext = 0x00; //not using uart0 extensions uart0brl = 0x09; //reload value for 115200 uart0brh = 0x00; // }//end of uart0ws0relcfg() function //------------------------------------------------------------------------------------// // txmit0 // // transmit one byte on the uart0 //------------------------------------------------------------------------------------// void txmit0( unsigned char charact){ uart0buf = charact; //send character while(!(uart0int & 0x01)); }//end of txmit0() function //;---------------------------------------------------------------- //;- delay1msto : 1ms delay using timer0 //;---------------------------------------------------------------- void delay(unsigned int dlais){ idata unsigned char x=0; idata unsigned int dlaisloop; periphen1 |= 0x01; //enable timer 0 dlaisloop = dlais; while ( dlaisloop > 0) { th0 = 0x63; //timer0 reload value for 1ms at 40mhz tl0 = 0xc0; t0t1clkcfg = 0x00; //no prescaler for timer 0 clock t0con = 0x04; //start timer 0, count up do{ t0con &= 0x80; }while(x==0); t0con = 0x00; //stop timer 0 dlaisloop = dlaisloop-1; }//end of while dlaisloop... periphen1 &= 0xfe; //disable timer 0 }//end of function delay vrs51l3xxx datasheet www.ramtron.com page 56 of 115 10 spi interface the spi interface of the vrs51l3xxx devices provide numerous enhancements compared to other vendor offerings. the spi interface?s key features include: ? ? ? ? ? ? ? ? vrs51l3xxx datasheet www.ramtron.com page 57 of 115 spi mode 1: f igure 25: spi m ode 1 msb lsb cs x sck sdi sdo spi mode 1: spickpol =0,spickph =0 (normal mode shown) *arrows indicate the edge where the data acquisition occurs spi mode 2: f igure 26: spi m ode 2 cs x sdo spi mode 2: spickpol =1,spickph =1 (normal mode shown) sck sdi msb lsb *arrows indicate the edge where the data acquisition occurs spi mode 3: f igure 27: spi m ode 3 cs x sdi sdo spi mode 3: spickpol =1,spickph =0 (normal mode shown) sck msb lsb *arrows indicate the edge where the data acquisition occurs 10.3 defining active chip select line as previously mentioned, only one chip select line is activated when communicating with an external spi slave device. the spics bits of the spictrl register are used to select which cs line will be activated during the transfer. note that with the except ion of the cs0 line, the spicsen bit of the periphen1 register must be set to 1 in order for the spi be able to control the spi cs lines. 10.4 setting the spi communication speed (master mode) in master mode, the spi interface communication speed is adjustable from ?system clock /2? down to ?system clock / 1024?. slower communication speeds can be useful for interfacing with slower devices or to adjust the communication speed to specific bus conditions. the spiclk[2:0] of the spictrl and the spislow bit of the of the spiconfig sfr register control the spi communication speed. the spi communication speed in master mode can be calculated using the following formula: spi speed = sys clk [ 2 (spiclk[2:0] +1) x 4 spislow ] where: o sys clk = processor operating clock o spislow = can be either 0 or 1 o spiclk[2:0] = from 0 to 7 the following tables provide example setting for spi communication speeds with various system clock and spiclk[2:0] and spislow bit settings. t able 103:spi c ommunication s peed example (spislow = 0) spiclk com speed @ 40mhz com speed @ 22.18mhz com speed @ 4mhz 000 20 mhz 11.05 mhz 2 mhz 001 10 mhz 5.53 mhz 1 mhz 010 5 mhz 2.76 mhz 500 khz 011 2.5 mhz 1.38 mhz 250 khz 100 1.25 mhz 691.2 khz 125 khz 101 625 khz 345.6 khz 62.5 khz 110 312.5 khz 172.8 khz 31.3 khz 111 156.3 khz 86.4 khz 15.6 khz t able 104:spi c ommunication s peed example (spislow = 1) spiclk com speed @ 40mhz com speed @ 22.18mhz com speed @ 4mhz 000 5 mhz 2.76 mhz 500 khz 001 2.50 mhz 1.38 mhz 250 khz 010 1.25 mhz 691.2 khz 125 khz 011 625 khz 345.6 khz 62.5 khz 100 312.5 khz 172.8 khz 31.3 khz 101 156.3 khz 86.4 khz 15.6 khz 110 78.1 khz 43.2 khz 7.8 khz 111 39.1 khz 21.6 khz 3.9 khz vrs51l3xxx datasheet www.ramtron.com page 58 of 115 10.5 spi configuration /status registers the spi configuration and st atus registers allow the activation and the monitoring of the spi interface interrupts. they also prov ide access to the advanced features of the spi interface such as: o frame select/load generation on cs3 o activating manual control of the chip select lines o bit reversed mode (bitwise endian control) o interrupt activation and monitoring o monitoring the state of the ss pin t able 105:spi c onfiguration register - spiconfig - c2 h 7 6 5 4 3 2 1 0 r/w w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 spimancs spi manual cs mode enable 0 = spi chip select control is fully automatic 1 = spi chip select will be brought low by the spi interface, and will stay low until 0 is written into spimancs bit 6 spiunderc spi clear tx underrun flag (spiunderf) writing a 1 into this bit will clear the spiunder bit of the spistatus register this bit always reads 0 5 fsoncs3 frame select pulse on cs3 0 = cs3 acts in standard ways 1 = the spi interface will send an active low frame select pulse on cs3 frame select has priority on spiload function 4 spiloadcs3 load pulse on cs3 0 = cs3 acts in standard way or as frame select pulse, if fsoncs3 is set to 1 1 = the spi interface sends an active low load pulse on the cs3 pin, if fsoncs3 is cleared 3 spislow spi slow speed mode 0 = spi transaction occurs at normal speed 1 = spi transaction is 4x slower 2 spirxoven spi rx overrun interrupt enable 0 = spi rx overrun interrupt is deactivated 1 = spi rx overrun interrupt is enabled 1 spirxaven spi rx available interrupt enable 0 = spi rx available interrupt is deactivated 1 = spi rx available interrupt is enabled 0 spitxeen spi tx empty interrupt enable 0 = spi tx empty interrupt is deactivated 1 = spi tx empty interrupt is enabled the spistatus register?s role is mainly for monitoring purposes. t able 106:spi s tatus register - spistatus sfr c9 h 7 6 5 4 3 2 1 0 r/w r r r r r r r 0 0 0 1 1 0 0 1 bit mnemonic description 7 spireverse spi reverse mode 0 = spi operates in normal mode (msb first) 1 = spi operates in reverse mode (lsb first) 6 - not used 5 spiunderf spi tx underrun flag 0 = no underrun condition noticed 1 = indicates that the sp i transmit buffer has not been fed in time. this condition is likely to occur when the transaction size is > 32 bits this bit is cleared by setting to 1, the spiundec of the spiconfig register. 4 sspinval slave select pin value 0 =ss pin is low 1 = ss pin is high 3 spinocs spi no chip select 0 = at least one chip select line is active 1 = indicates that all the chip select lines are inactive (high) 2 spirxovf spi rx overrun interruptflag 0 = no spi rx overrun condition detected 1 = spi data collision occurred 1 spirxavf spi rx available interrupt flag 0 = spi receive buffer is empty 1 = data is present in the spi rx buffer 0 spitxempf spi tx empty interrupt flag 0 = spi transmit buffer is full 1 = spi transmit buffer is ready to receive new data 10.6 spi transact ion directions the spi interface can perform transactions in the standard spi format (msb first) as well as in the reverse format (lsb first). in applications where data must be transmitted (or rece ived) in lsb first format, the user would normally need to perform bit reversal manually at the processor level and then send the data through the spi interface. the spi interface can automatically handle the bit reversal operations, unloading the processor for other tasks. when the spireverse bit of the spistatus register is set to 0, the spi transactions will take place in msb first format. vrs51l3xxx datasheet www.ramtron.com page 59 of 115 the following examples show the timing related to these transaction directions: f igure 28: spi msb f irst t ransaction msb lsb cs x sck sdo/sdi msb first spi transaction (mode 0 shown) when the spireverse is set to 1, the spi transactions are done in lsb first format, as shown in the next figure. f igure 29: spi lsb f irst t ransaction lsb msb cs x sck sdo/sdi lsb first spi transaction (mode 0 shown) 10.7 manual chip select control when the spimancs bit of the spiconfig register is set to 1, the active chip select line will stay at a logic low after the spi master mode transaction is completed, as shown in the following figure. f igure 30: spi m anual c hip select manual csx mode (spi mode 0 shown) *arrows indicate the edge where the data acquisition occurs msb lsb sck sdi sdo cs x note: csx stays low the chip select will rema in at logic 0 until the spimancs bit is cleared by the software. 10.8 spi interrupts the spi can trigger three in terrupt sources that are handled by two interrupt vectors, as shown in the following table: t able 107: spi i nterrupt sources interrupt interrupt number interrupt vector spi tx empty int_1 000bh spi rx available spi rx overrun int_2 0013h the tx empty interrupt is set when the spi transmit buffer is ready to receive more data. a double buffer is used in the spi transmitter. once transmission begins (after a write to the spirxtx0 register), the data is transferred to the final transmission buffer. this frees up the spirxtx sfr register, raises the spitxempf flag of the status register and triggers an spi tx empty interrupt if enabled. the spi tx empty interrupt is enabled by setting the spitxeen bit of the spiconfig register to 1. the priority of the spi tx empty interrupt is set high in order to avoid buffer overrun in 32-bit spi transfers. the spi rx available interrupt is activated when receive data has been transferred from the spi rx buffer to the spirxtx register. the spirxtx register must be read by the processor before the next spi bus data sequence is completed. the spi rx available interrupt is enabled by setting the spirxaven bit of the spiconfig register to 1. the spirxavf flag of the spistatus register, when set to 1, indicates that data can be read. the spirxavf flag is automatically reset when the spirxtx0 register is read. the spi rx overrun interrupt indicates that an overrun condition has taken place. the spi rx overrun interrupt is enabled by setting the spirxoven bit of the spiconfig register to 1. the spirxovf flag of the spistatus register, when set to 1, indicates that a data collision has occurred. all the spi interface interrupt flags are active even if the associated interrupt is not activated and they can be monitored by the user program at any time. please consult the interrupt section for more details on the spi interface interrupts and their interaction with other peripherals vrs51l3xxx datasheet www.ramtron.com page 60 of 115 10.9 alternate cs3 functions for external spi devices which require the use of a load or a frame select signal, the vrs51l3xxx can be configured to either generate an active low frame select or active high load signal when operating in master mode. frame select signal on cs3 when the foncs3 bit of the spiconfig register is set to 1, the spi interface will generate an active low frame select pulse on the cs3 pin (see the following timing diagram). f igure 31: spi f rame s elect p ulse t iming frame select pulse (spi mode 0 shown) *arrows indicate the edge where the data acquisition occurs msb lsb sck sdi sdo cs3 cs x frame select pulse width = 1 / sys clk load signal on cs3 when the spiloadcs3 bit of the spiconfig register is set to 1 and the fsoncs3 bit is cleared, an active low load signal will be generated on the cs3 line of the spi interface. f igure 32: spi l oad p ulse t iming load pulse (spi mode 0 shown) *arrows indicate the edge where the data acquisition occurs msb lsb sck sdi sdo cs3 cs x load pulse width = 1 / sys clk note that the frame select alternate function has priority over the load functi on. this means that if the fsoncs3 bit is set, the alternate function selected will be the frame select, independent of the value of the spiload bit. 10.10 spi activity monitoring the ability to monitor the state of communication of the spi interface can be useful in highly modular applications in which the spi interface is handled by interrupts. the spistatus register contains two flags that can be used to monitor the cs and ss signals of the spi interface. the spinocs bit of the spistatus register returns the logical and of all the spi cs lines. if all the cs lines are inactive (logic high), the spi interface sets the spinocs to 1. the spinocs bit is used to verify that the spi interface is idle before reconfiguring it or starting a new transaction. the spinocs bit of the spistatus register is valid four system clock cycles after the spi transmission begins. this delay is independent of the spi transaction speed. as such, after a write operation to the spirxtx0 register, which will trigger a spi transaction in master mode, a nop instruction (1 cycle) must be added before the mov rn, spistatus instruction (3 cycles). the sspinval bit of the spistatus register returns the logic level on the ss pin. 10.11 spi tx under run flag the spi interface provides an under run condition flag that can be used to flag whether the software has failed to update transmission buffer in time for the next transfer. this is especially useful when the spi interface is used to transmit packets greater than 32 bits in length. if an under run condition occurs, the spiunderf bit of the spi status register w ill be set to 1. this bit can be cleared by writing a 1 to the spiunderc bit of the spiconfig register. note that spi under run monitoring is not linked to any of the spi interrupts, therefore, this flag can only be cleared manually by software vrs51l3xxx datasheet www.ramtron.com page 61 of 115 10.12 spi transaction size the standard spi protocol is based on 8-bit transactions. however, many devices on the market, specifically a/d and d/a converters, require transactions greater than 8 bits. to communicate with these types of devices usi ng a standard spi interface, the user has no choice but to send multiple 8-bit streams and use i/o pins to control the chip select line. the spi interface supports 8-bit transactions and can also be configured to support transactions from 1 to 32 bits in both transmit and receive directions. the value written into the spisize register controls the transaction size. upon reset, the spi interface is configured for 8-bit transactions. the spi interface does also support transaction of more than 32 bit in size. for transaction > 32bit in size the granularity is 8 bit and the maximum transaction size is 228 bytes. care must be taken to avoid spi double data buffer over / under run condition when transaction size is > 32 bit. t able 108:spi t ransaction s ize ? spisize sfr c3 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 1 1 1 bit mnemonic description 7:0 spisize[7:0] spi transaction size if < 32 : transaction size = spisize + 1 if >= 32: transaction size = (spisize *8) - 216 default transaction size = 8 bits four formulas control the spi transaction size: for transactions size <= 32 bits transaction size = spisize[7:0] +1 or spisize[7:0] = transaction size - 1 for transactions size > 32 bits transaction size = [ (spisize[7:0] * 8) ?216] or it can be expressed by: spisize[7:0] = [ transaction size + 216 ] 8 the following table provides examples: t able 109: t ransaction size vs . spisize[7:0] spisize[7:0] transaction size 0x07 8-bit 0x0b 12-bit 0x0d 14-bit 0x10 17-bit 0x17 24-bit 0x1f 32-bit 0x20 40-bit 0x21 48-bit 0x23 64-bit the transaction size must also be configured when the operating the spi interface in slave mode. 10.13 spi rx/tx data registers four sfr registers provide access to the spi interface?s receive and transmit data buffer. performing a write operation to the spi rx/tx buffer transfers the data to the transmit portion of the spi interface, while a read oper ation reads the contents of the receive data buffer. the spi 32-bit receive and transmit data buffers are double buffered to minimize the risk of data collision and to achieve optimal performance. the spi rxtx0 register cont ains bits 7:0 of the spi interface rx/tx register. t able 110: spirxtx0 r egister content for normal and reversed t ransactions operation spi mode spirxtxx data is? msb first right justified read lsb first left justified msb first left justified write lsb first right justified when the spi is configured in master mode, writing to the spirxtx0 will trigger a dat a transmission. for this reason, when the transaction size is larger than 8 bits, the spirxtx0 register must be written last. vrs51l3xxx datasheet www.ramtron.com page 62 of 115 t able 111:spi rx / tx0 d ata r egister ? spirxtx0 sfr c4 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description read: spi rxdata[7:0] right justified in normal mode, left justified in bit reversed mode reading this register, clears the spiavf and spirxovf flags 7:0 spirxtx0[7:0 ] write: spi txdata[7:0] if spisize = 0x07 (8 bit) spitxdata[31:24] if spisize = 0x1f (32 bit) left justified in normal mode, right justified in bit reversed mode in master mode, writing to spirxtx0 triggers the transmission t able 112:spi rx / tx1 d ata r egister ? spirxtx1 sfr c5 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description read: spi rxdata[15:8] if sp isize = 0x1f (32 bit) right justified in normal mode, left justified in bit reverse mode 7:0 spirxtx1[7:0 ] write: spitxdata[23:16] if spisize = 0x1f (32 bit) left justified in normal mode, right justified in bit reverse mode t able 113:spi rx / tx2 d ata r egister ? spirxtx2 sfr c6 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description read: spi rxdata[23:16] if spisize = 0x1f (32 bit) right justified in normal mode, left justified in bit reverse mode 7:0 spirxtx2[7:0] write: spitxdata[15:8] if spisize = 0x1f (32 bit) left justified in normal mode, right justified in bit reverse mode t able 114:spi rx / tx3 d ata r egister ? spirxtx3 sfr c7 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description read: spi rxdata[31:24] right justified in normal mode, left justified in bit reverse mode 7:0 spirxtx3[7:0] write: spitxdata[7:0] if spisize = 0x1f (32 bit) left justified in normal mode, right justified in bit reverse mode 10.14 spi data input /output the spi interface has the ability to perform data transactions in msb first mode or lsb first. the spireverse bit of the spistatus register controls whether the data will be transmitted mbs first or lsb first. upon device reset, the spireverse bit equals 0 and data is transmitted in msb first format. the spireverse bit state will also affect the data transmission and the data reception buffer structure as shown in the following diagrams. f igure 33: spi transaction s tandard m ode (spireverse = 0 : msb f irst ) outgoing transaction lsb msb spirxtx3 70 spi transmission (standard mode) spirxtx2 0 7 spirxtx1 0 7 spirxtx0 0 7 sdo pin spirxtx3 70 spi reception (standard mode) sdi pin spirxtx2 0 7 spirxtx1 0 7 spirxtx0 0 7 incoming transaction msb lsb f igure 34: spi transaction b it r everse m ode (spireverse = 1: lsb f irst ) spi reception (bit reversed mode) spirxtx3 70 spirxtx2 0 7 spirxtx1 0 7 spirxtx0 0 7 sdi pin incoming transaction lsb msb spi transmission (bit reversed mode) spirxtx3 70 sdo pin spirxtx2 0 7 spirxtx1 0 7 spirxtx0 0 7 outgoing transaction msb lsb the next tables gives examples of spi transmission and reception in different modes if the spi sdo pin is connected to the sdi pin. spisize = 0x0f (16 bit) / spireverse= 0 (msb first spitx [3:0] spirx [3:0] xx xx d3h 42h xx xx 42h d3h xx xx 54h a6h xx xx a6h 54h spisize = 0x0f (32 bit) / spireverse= 0 (msb first spitx [3:0] spirx [3:0] 45h a3h b2h df dfh b2h a3h 45h c3h 8ah 49h 24h 24h 49h 8ah c3h spisize = 0x0f (32 bit) / spireverse= 1 (lsb first spitx [3:0] spirx [3:0] 45h a3h b2h df dfh b2h a3h 45h c3h 8ah 49h 24h 24h 49h 8ah c3h vrs51l3xxx datasheet www.ramtron.com page 63 of 115 10.15 non 8 bit multiple transmission for a non 8 bit multiple data transmission in master mode (when the data is not transmitted in multiples of 8 bits), the most signific ant bit of the data to be transmitted must first be placed at position 7 of the spirxtx0, with the remaining bits positioned as shown in the spi transaction figures on the previous page. for example if spisize = 0x0b and spireverse = 0, the data transaction will measure 12 bits, msb first. for the transmission to occur in the correct order, the lower 4 data bits must first be placed into bit positions 7:4 of the spirxtx1 register, with bits 11:4 written into bit position 7:0 of the spirxtx0 register. this will trigger the transmission. the following is a sequence of steps to transmit 12 bits of data contained in an integer variable called txmitdata . 1. clear the spirxtx3 and spirxtx2 registers (optional) 2. put the lower quartet of the 12-bit data (bits 3:0) into the upper quartet of the spirxtx1 register 3. write bit 7:0 of the 12-bit data into the spirxtx0 register 4. this will trigger a data transmission in c, this is expressed as follows: (?) spirxtx3 = 0x00; spirxtx2 = 0x00; spirxtx1 = (txmitdata << 4)&0xf0; //write the lower quartet of data //into the upper quartet of spirxtx1 register readflag = spirxtx0 //-dummy read the spi rx buffer to clear the rxav flag //(facultative if spinocs is monitored) spirxtx0 = dacdata >> 4; //writing to spirxtx0 will trigger the transmission for example to output 0x3a2 through the spi interface configured in master mode and msb first format, write 0x20 into the spirxtx1 sfr register and followed by 0x3a into the spirxtx0 register. the reception of non multiple of 8 data when the spi interface is configured to msb first transaction is very straight forward as the data enters into the receiving buffer through the bit 0 of the spirxtx0 register and propagates towards the bit 7 of spirxtx3 register. 10.16 spi example programs code example: uart to spi data transmission example //---------------------------------------------------------------------------------------------------// // spi transmit example.c //----------------------------------------------------------------------------------------------------// // this program sends characters received on the uart to the spi interface //----------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 64 of 115 code example: spi interface to 12-bit adc and dac the following example program shows the initialization and use of the spi module as an interface to serial adc and dac. .//----------------------------------------------------------------------------------------------------------------------// // vrs51l3xxx_generic_spi_based_adc_dac_interf1.c //----------------------------------------------------------------------------------------------------------------------// // description: // this program demonstrates the configuration and use of the spi interface // for interface to typical serial 12 bit a/d and d/a converters. // the program read the a/d and output the read value out on a d/a converter // to perform the conversion the adc requires 16 clock cycles and // the dac requires 12 clock cycles. //----------------------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 65 of 115 code example: performing > 32bit data transfer on spi the following demo program demonstrates the use of the spi interface to perform 131 bytes data transfer read / write on the spi interface. //------------------------------------------------------------------------------------------------------------------// // v2k_spi_131bcomm_fm25cl64_sdcc.c //-----------------------------------------------------------------------------------------------------------------// // description: // this program demonstrates the configuration and use of the spi interface // to access the fm25cl64. this demonstration program takes advantage of the // ability to perform > 32bit transactions. // in this demo program, transactions of 131 bytes are performed // // the program do the following operations // 1) initialize the spi interface // 2) init xram address 0x0000 - 0x007f with lsb of xram address // 3) init xram address 0x0080 to 0x0fff == 0x00 // 4) send a wren command // 5) copy xram address 0x0000 to 0x007f into address 0x0000 to 0x00f // of the fm25cl64 in one spi transaction // 6) read fm25cl64 address 0x0000 to 0x007f of the fm25cl64 and copy // the data read into xram from addres 0x0100 to 0x017f // in one spi transaction (by pooling) // 7) read back address 0115h //---------------------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 66 of 115 11 i2c interface all vrs51l3xxx include an i2 c interface that can operate in master and slave mode. in master mode, the communication speed on the i2c is programmable, optimizing communication bet ween i2c-based devices. long or heavily loaded i2c bus applications are likely to require slower communication speeds. 11.1 i2c bus pull-up resistors by definition, the i2c requir es that the user include external pull-up resistors on the scl and sda lines. the pull-up voltage can be either 3.3 or 5 volts. the i/o associated with scl and sda are 5v?tolerant, making it possible to interface 5v, i2c-based devices with the vrs51l3xxx. the proper value for the pull-up resistor and the proper communication speed depend on bus characteristics such as length and capacitive load. note that the pull-up resistor value should not be below 1.25k ohms if running the i2c bus at 5v; and 750 ohms if operating at 3.3v. this is required in order to limit the current to 4ma (maximum current of the i/o port connected to the i2c interface). 11.2 i2c interface alternate pins upon reset, the i2c interface signal scl and sda are mapped into pins p3.4 and p3.5, respectively. however it is also possible to map these signal into the p1.6 and p1.7 pins. bit 5 of the deviomap register (sfr e1h) is used to configure the mapping of the i2c interface at the i/o level, as shown in the following table: t able 115: i2c module mapping deviomap.5 bit value scl mapping sda mapping 0 (reset) p3.4 p3.5 1 p1.6 p1.7 11.3 i2c control and status registers four sfr registers are dedicated to the i2c interface. the i2c configuration register i2cconfig enables: ? ? ? ? ? vrs51l3xxx datasheet www.ramtron.com page 67 of 115 if the i2crxstop bit is set to 1, the i2c interface will not acknowledge it has rece ived the next data byte: it will generate a stop condition instead, which will end the transaction. when set to 1, the i2csc llow bit will force the i2c interface to pull the scl line low during the next data acknowledge phase. this feature enables the user to add the equivalent of wait states to the transfer in order to support ?slow? devices connected to the i2c bus. the state of the i2cscllow is sampled when the i2c interface enters the data phase. this bit must not be set during the data acknowledge phase, which can be monitored using the i2cackph bit of the i2cstatus register. the i2c interface includes support for four interrupt conditions via two interrupt vectors. ? ? ? ? vrs51l3xxx datasheet www.ramtron.com page 68 of 115 11.5 i2cstatus register monitoring of the i2c interface can be done via the i2cstatus register located at sfr address d4h. the i2cstatus register is read-only. t able 121: i2c s tatus register - i2cstatus sfr d4 h 7 6 5 4 3 2 1 0 r r r r r r r r 0 0 1 0 1 0 0 1 bit mnemonic description slave mode error flag: 0 = no error 1 = indicates that the i2c interface received an unexpected stop this flag is reset the next time the i2c interface exits from an idle state (see below) 7 i2cerror master mode 0 = no arbitration error 1 = i2c interface has lost arbitration this flag is reset the next time the i2c interface exits from an idle state (see below) 6 i2cnoack i2c acknowledge error flag 0 = acknowledge was received normally 1 = no acknowledge was received during the last acknowledge phase this flag is reset the next time the i2c interface exit from the idle state (see below) 5 i2csda i2c sda 4 i2cackph when set, this flag indicates that the i2c interface is in ?data acknowledge phase.? 5 phases of i2c protocol: 1. idle 2. device id 3. device id acknowledge 4. data 5. data acknowledge 3 i2cidlef i2c is idle 0 = i2c interface is communicating 1 = i2c interface is inactive (idle phase) and the scl and sda lines are high 2 i2crxovf i2c rx overrun interrupt flag 0 = no i2c rx overrun condition detected 1 = i2c data collision occurred 1 i2crxavf i2c rx available interrupt flag 0 = i2c receive buffer is empty 1 = data is present in the i2c rx buffer 0 i2ctxempf i2c tx empty interrupt flag 0 = i2c transmit buffer is full 1 = i2c transmit buffer is ready to receive new data the i2cerror flag indicates that an error condition has occurred on the i2c interf ace. in master mode, the i2cerror flag will be set by the i2c interface, if it loses bus arbitration. in slave mode, if an unexpected stop is received, the i2cerror flag will be set. the i2cerror flag will be automatically reset by the i2c interface the next time it exits an idle state. if the i2cnoack flag is set to 1, it signifies that the slave device did not acknowle dge the last data byte it received. the i2c interface also monitors the synchronization of the sda line. when synchronization is lost, the i2csdasync bit of the i2cstatus register will be set by the i2c interface. the i2csdasync bit of the i2cstatus register returns the value of the sda line the moment a read operation is performed on the i2cstatus register. when set, the i2cackph bit indicates that the i2c interface is currently in the data acknowledge phase. the i2csdasync and i2cckph bits can read to determine whether the slave device has acknowledged. if both bits are set to 1 at a given time, the slave device did not acknowledge. when set, the i2cidlef indicates that the i2c bus is idle and that a transaction can be initiated. before initiating an i2c data transfer, it is recommended to check the state of the i2cidlef bit. this bit indicates whether or not a data transfer is currently in progress. when new data is received in the i2c receive buffer, the i2crxavf interrupt flag will be set. data must be retrieved from the i2cr xtx buffer before the reception of the next data byte is complete. when set, the i2crxovf fl ag indicates an overrun condition in the i2c interface receive buffer and the data is potentially corrupted. the i2ctxempf interrupt flag is set by the i2c interface when the transmit data buffer is ready to receive another data byte. 11.6 i2crxtx register the i2c interface transmit and receive buffers are accessed via the i2crxtx sfr register, which is accessible at sfr address d5h. t able 122:i2c data rx / tx r egister i2crxtx - sfr d5 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description read: i2c receive buffer reading the i2crxtx register will clear the i2crxav and i2crxov flags 7:0 i2crxtx[7:0] write: i2c transmit buffer in master mode, writing into the i2crxtx register will trigger the transmission vrs51l3xxx datasheet www.ramtron.com page 69 of 115 the i2crxtx sfr is made up of two distinct registers set: one for data transmission and one for data reception. each register set features a double data buffer as shown in the diagram below. f igure 35: i2crxtx[7:0] data buffer structure when the i2c is configured in master mode, writing any data to the i2crxtx register will trigger a data transmission. unless the i2c interface is currently transmitting a byte, if the tx empty interrupt is activated, a tx empty interrupt will occur as soon as a new data byte is placed into the i2crxtx register. in order to read data from the i2c interface, when configured in master mode, the device id with the r/w bit set to 1 must first be sent to the device. then the program should wait for the i2crxav flag of the i2cstatus register to be set. at that point, the data can be read from the i2crxtx register. as previously mentioned, the data must be retrieved from the i2crxtx register before the next data byte reception is complete. otherwise, an i2c rx overrun condition will occur. reading the content of the i2crxtx register will automatically clear the i2 crxav and i2crxov flags, which are read-only. 11.7 checking presence of the i2c slave device when the i2c is configured in master mode, the bus master should check for the presence and the readiness of the slave i2c devices connected to the bus at least once after i2c bus initialization. it is also recommended to check whether the slave device is present and ready before issuing a i2c transaction. this would allow the i2c master to verify the i2c slave device connect ed to the bus is not busy accomplishing other tasks and not responding. this is especially true in the case of i2c eeprom devices, which will not respond to the master when they are busy performing data writing operations. it is unnecessary to check before each transaction whether f-ram memory devices are present and ready. if the slave device fails to respond to the device id sent by the master, the master will generate a stop condition immediately. the i2cackph flag of the i2cstatus register is set to 1 during the i2c data acknowledge phase. however, this flag will remain inac tive during the device id acknowledge phase. as a result, if the slave device fails to acknowledge following the transmission of the slave device id, the i2c interface will only detect the error condition after data acknowledge phase. the following diagram represents what could happen if the slave device fails to generate an ck signal following the device id sent by the master: f igure 36: i2c interface behavior when s lave device does not ack to device id to work around this situation, send a device id with r/w = 0 followed by a stop. if the device fails to respond the i2c id, the i2cnoack bit of the i2cstatus register will be set to 1 when the i2c bus becomes idle. vrs51l3xxx datasheet www.ramtron.com page 70 of 115 if the i2cnoack is not set, then the i2c master can proceed with the i2c transaction starting with the device id + r/w followed by the data to be written or read. f igure 37: c hecking presence and readiness if i2c s lave code example: slave i2c device presence check the function example below checks whether the device pointed to by the device id responds to the master command. as mentioned in the previous paragraph, this check should be done to ensure the targeted i2c slave device is present on the i2c bus and is ready. //---------------------------------------------------------------------------------------------------------------------// // function i2cslaveready(char) // //--------------------------------------// // descrition: // master i2c slave ready check function // check if the device pointed by the device id does respond to the master command // this check should be done to ensure the targeted i2c slave device is // present on the i2c bus and is ready. // the slave ready check should be performed at least once after i2c module // initialisation. // it should also be performed before each transactioln sequences to slow // devices such as eeprom. it is not necessary to perform a i2c slave ready // check when the target device is i2c f-ram device. //--------------------------------------------------------------------------------------------------------------------// char i2cslaveready(char id) { char addrtemp= 0x00; //temporary address holding variable i2cconfig = 0x01; i2crxtx = id; //write i2c device id + w waittxemp(); //--wait for i2c idle (this will generate a stop) waiti2cidle(); if((i2cstatus & 0x40)!= 0x00 ) //if i2cnoack == 1 -> no answer -> return 01 return 0x00; else return 0x01; }//end of i2cslaveready(char id); 11.8 i2c slave device id and advanced configuration when operating in slave mode, the device id on the i2c interface is configurable. the seven upper bits of the i2cidcfg register contain the user-selected device id. bit 0 of the i2cidcfg register has two distinct roles. t able 123:i2c d evice id c onfiguration - i2cidcfg sfr d3 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description [7:1] i2cid[6:0] slave i2c device id as selected by user read: indicates that the i2c slave has received id that is different from the i2cid[6:0]. this flag is cleared when the received id corresponds with the i2cid 0 i2cadvcfg writing: slave mode: 1= the i2crxav flag is not raised when the i2c slave receives a device id 0 = the i2crxav flag will be raised for each data byte on the i2c bus. however if the received device is does not match the i2cid[6:0] the i2c module will not acknowledge. master mode: 1 = the master will not enter in a ?wait state? if there is a mismatch between the expected scl state and what it should be. 0 = enables monitoring of the scl line in wait state mode in case of mi smatch of the scl line vs. the expected value the i2cavcfg provides advanced control on i2c interface operations. its functionality depends whether the i2c interface is configured in master or in slave mode. in master mode: when the i2c interface operates in master mode and the i2cadvcfg is cleared, the i2c interface module will continuously monitor the scl line. if the slave device drives the scl line in to an incorrect state, the i2c interface will enter wait state mode until the slave device releases the scl line. this mode can be useful for a i2c communication debug. when the i2cadvcfg bit is set and the device operates in master mode, no monitoring of the scl line will be executed by the i2c module and the transaction will proceed independently of the level of the scl line. vrs51l3xxx datasheet www.ramtron.com page 71 of 115 in slave mode when the i2c interface is configured in slave mode, the state of the i2cadvcfg bit when read indicates whether the id received matches the current device id. if the i2cidcfg reads as 1, then the received id corresponds to the i2cid[6:0] value. the value written to the i2cadvcfg bit will define whether the i2c interface w ill monitor the transactions on the i2c bus or not. when the i2cadvcfg bit is cleared, the i2c interface will monitor the activity on the i2c bus and will raise an rxav interrupt for each data byte received from the i2c bus, including the device id at the beginning of a transaction. setting the i2cadvcfg bit to 1 will deactivate the i2c interface transactions monitoring feature for transaction beginning with a device id that does not match the i2cid[6:0] value. independent of the value wri tten in the i2cadvcgf bit of the i2cidcfg register, if the i2c transaction device id does not match the i2cid[6:0] value, the i2c interface will not acknowledge the incoming data nor will it transmit data to the master. 11.9 i2c interface example programs code example: f-ram / eeprom interface programs the following program provides example code for i2c control of f-ram or eeprom devices. //----------------------------------------------------------------------------// // vrs2k-i2c _fram/eeprom.c // //----------------------------------// // this example program demonstrate the use of the i2c // interface to perform basic read and write operations on a // standard eeprom device. //----------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 72 of 115 void waitrxav() { wait(); do{ userflags = i2cstatus; userflags &= 0x02; //isolate the i2crxav flag }while( userflags == 0x00); //wait for i2c rx available }//end of void waitrxav() //---------------------------------------------------// //-------- function waiti2cidle() ---------// //---------------------------------------------------// void waiti2cidle() { wait(); do{ userflags = i2cstatus; userflags &= 0x08; //isolate the i2c idle flag }while( userflags == 0x00); }//end of void waiti2cidle() //----------------------------------------// //-------- function wait() ----------// //----------------------------------------// void wait(){ char i=0; while (i<25) {i++;}; } code example: i2c interface used in slave mode the following example program presents how to configure and use the i2c interface in slave mode to create an i/o port expander using the vrs51l3xxx. //-----------------------------------------------------------------------------------------------------------------------/ // v2k_i2c_slave_io_exp_sdcc.c // ///------------------------------------------------// // description: // // this demo program illustrate how to use the vrs51l3074 i2c interface configured // in slave mode to create an i2c based i/o expander. // // the memory map of slave i2c device as seen from the master i2c device is // as shown below. the address is constituted of 1 byte. // // i2c regs v3k // address register // -------- --------- // 0x00 p0 //io port 0 register // 0x01 p1 //io port 1 register // 0x02 p2 //io port 2 register // 0x03 p3 //io port 3 register // 0x04 p4 //io port 4 register // 0x05 p5 //io port 5 register // 0x06 p6 //io port 6 register // 0x07~0x0f ~~~~~~~~ //undefined / restricted // 0x10 p0pincfg //io port 0 configuration register (1= input, 0=output ) // 0x11 p1pincfg //io port 1 configuration register (1= input, 0=output ) // 0x12 p2pincfg //io port 2 configuration register (1= input, 0=output ) // 0x13 p3pincfg //io port 3 configuration register (1= input, 0=output ) // 0x14 p4pincfg //io port 4 configuration register (1= input, 0=output ) // 0x15 p5pincfg //io port 5 configuration register (1= input, 0=output ) // 0x16 p6pincfg //io port 6 configuration register (1= input, 0=output ) // >= 0x17 undefined / restricted // // multiple read or write operations can be performed in one access sequence // the first byte of each transaction does sets the address byte. // // the first byte of all i2c write operation is the address byte. // read operations are performed from the current address // when multiple byte read or write operation, the address value is incremented // after each data byte read from or written to the device. // // the address value at reset is 0x00 //-------------------------------------------------------------------------------------------/ #include vrs51l3xxx datasheet www.ramtron.com page 73 of 115 }//end of switch(address) state = 0x01; }//end of if state == 0x00 else if(bytecount!= 0x00) { //rxdata = i2crxtx; //retrieve data switch(address) { case 0x00: {p0 = i2crxtx; i2crxtx = p1; address++; break;} case 0x01: {p1 = i2crxtx; i2crxtx = p2; address++; break;} case 0x02: {p2 = i2crxtx; i2crxtx = p3; address++; break;} case 0x03: {p3 = i2crxtx; i2crxtx = p4; address++; break;} case 0x04: {p4 = i2crxtx; i2crxtx = p5; address++; break;} case 0x05: {p5 = i2crxtx; i2crxtx = p6; address++; break;} case 0x06: {p6 = i2crxtx; i2crxtx = p0pincfg; address = 0x10; //jump address value to point to p0pincfg break;} case 0x10: {p0pincfg = i2crxtx; i2crxtx = p1pincfg; address++; break;} case 0x11: {p1pincfg = i2crxtx; i2crxtx = p2pincfg; address++; break;} case 0x12: {p2pincfg = i2crxtx; i2crxtx = p3pincfg; address++; break;} case 0x13: {p3pincfg = i2crxtx; i2crxtx = p4pincfg; address++; break;} case 0x14: {p4pincfg = i2crxtx; i2crxtx = p5pincfg; address++; break case 0x15: {p5pincfg = i2crxtx; i2crxtx = p6pincfg; address++; break;} case 0x16: {p6pincfg = i2crxtx; i2crxtx = p0; address = 0x00; break;} }//end of switch }//end of if bytecount }//end of rx available flag handling //---case of i2c tx empty available if(status & 0x01) //tx empty { //data of current address already gone //must prepare tx portion of i2crxtxd for next data switch(address) { case 0x00: {i2crxtx = p1; break;} case 0x01: {i2crxtx = p2; break;} case 0x02: {i2crxtx = p3; break;} case 0x03: {i2crxtx = p4; break;} case 0x04: {i2crxtx = p5; break;} case 0x05: {i2crxtx = p6; break;} case 0x06: {i2crxtx = p0pincfg; address = 0x10; break;} case 0x10: {i2crxtx = p1pincfg; break;} case 0x11: {i2crxtx = p2pincfg; break;} case 0x12: {i2crxtx = p3pincfg; break;} case 0x13: {i2crxtx = p4pincfg; break;} case 0x14: {i2crxtx = p5pincfg; break;} case 0x15: {i2crxtx = p6pincfg; break;} case 0x16: {i2crxtx = p0; address = 0xff; break;} }//end of switch address++; }//end of if tx empty... if((status & 0x06)) //rx overrun -- this should not happen i2cvalue = i2crxtx; //empty rxtx buffer inten2 = 0x02; //enable i2c interrupt }//end of i2c interrupt //----------------- individual functions --------------------- //------------------------------------------------------------------// // auxiliary sub functions used by i2c functions //------------------------------------------------------------------// //-------- function waittxemp() ----------// void waittxemp() { wait(); do{ userflags = i2cstatus; userflags &= 0x01; //isolate the i2ctxempty flag }while( userflags == 0x00); //wait for i2c tx empty }//end of void waittxemp() //-------- function waitrxav() ----------// void waitrxav() { wait(); do{ userflags = i2cstatus; userflags &= 0x02; //isolate the i2crxav flag }while( userflags == 0x00); //wait for i2c rx availlable }//end of void waitrxav() //-------- function waiti2cidle() ----------// void waiti2cidle() { wait(); do{ userflags = i2cstatus; userflags &= 0x08; //isolate the i2c idle flag }while( userflags == 0x00); }//end of void waiti2cidle() //-------- function wait() ----------// void wait(){ char i=0; while (i<25) {i++;}; } vrs51l3xxx datasheet www.ramtron.com page 74 of 115 12 pulse width modulators (pwms) the vrs51l3xxx devices include eight independent pwm channels, each based on a 16-bit timer. all of the pwm modules can be configured to operate as a regular pwm with adjustable resolution, or as a general purpose 16-bit timer. the pwmen register is used to enable the different pwm modules. t able 124: pwm e nable register - pwmen sfr aa h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 pwm7en pwm7 channel enable 0 = pwm channel 7 is deactivated 1 = pwm channel 7 is activated 6 pwm6en pwm6 channel enable 0 = pwm channel 6 is deactivated 1 = pwm channel 6 is activated 5 pwm5en pwm5 channel enable 0 = pwm channel 5 is deactivated 1 = pwm channel 5 is activated 4 pwm4en pwm4 channel enable 0 = pwm channel 4 is deactivated 1 = pwm channel 4 is activated 3 pwm3en pwm3 channel enable 0 = pwm channel 3 is deactivated 1 = pwm channel 3 is activated 2 pwm2en pwm2 channel enable 0 = pwm channel 2 is deactivated 1 = pwm channel 2 is activated 1 pwm1en pwm1 channel enable 0 = pwm channel 1 is deactivated 1 = pwm channel 1 is activated 0 pwm0en pwm0 channel enable 0 = pwm channel 0 is deactivated 1 = pwm channel 0 is activated the following figure provides an overview of the pwm modules. f igure 38: pwm modules overview pwmldpol = 1 pwm timer x clr pwmx mid pwmx end pwmclrall pwmx pin 0 1 < pwm mid > pwm mid > pwm end pwmtmrfx pwmtmrpr div ratio: sys clk / 1 downto sys clk / 16384 sys clk 015 pwmldpolx pwmtmrenx to others pwm modules 12.1 pwm mid and end registers each pwm module includes two 16-bit registers: o pwm mid value register o pwm end value register the pwm mid register is a 16-bit register that configures the point at which the pwm output will change it?s polarity. the pwm end register is a 16- bit register that defines the maximum pwm internal timer count value, after which it rolls over to 0000h. see the following timing diagram. f igure 39: pwm p olarity setting start 0000h pwm mid value pwm end value cycle 1 cycle 2 pwmldpol = 0 pwmldpol = 1 pwm timer roll over here and the cycle repeats this configuration allows the user to adjust the resolution of the pwm up to 16 bits. access to the pwm internal registers and the pwm configuration is handled by the pwmcfg register located at address a9h. vrs51l3xxx datasheet www.ramtron.com page 75 of 115 t able 125:pwm c onfiguration register - pwmcfg sfr a9 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 - 6 pwmwait pwm waits before loading new configuration 0 = new pwm configuration is loaded at the end of pwm cycle 1 = the update of the pwm configuration only occurs when the end of the pwm is reached and the bit is set to 0 5 pwmclrall pwm clears all channels 0 = no action 1 = simultaneously clears all the flags and all the pwm channel timers this bit is automatically cleared by hardware 4 pwmlsbmsb pwm lsb/msb select 0 = selected pwm lsb sfr is addressed 1 = selected pwm msb sfr is addressed 3 pwmmidend pwm mid/end register 0 = selected pwm mid sfr is addressed 1 = selected pwm end sfr is addressed 2:0 pwmch[2:0] pwm channel select 000 = pwm0 on p2.0 or p5.0 001 = pwm1 on p2.1 or p5.1 010 = pwm2 on p2.2 or p5.2 011 = pwm3 on p2.3 or p5.3 100 = pwm4 on p2.4 or p5.4 101 = pwm5 on p2.5 or p5.5 110 = pwm6 on p2.6 or p5.6 111 = pwm7 on p2.7 or p5.7 the pwm channels are configured one at the time. this topology has been adopted in order to minimize the number of sfr registers required to access the pwm modules. in applications where multiple pwm channels need to be configured simultaneously, the user can set the pwmwait bit of the pwmcfg register, configure each one of the pwm channels, and then clear the pwmwait bit. the pwm configurations will then be updated at the end of the next pwm cycle, after the pwmwait bit has been cleared. t able 126:pwm d ata r egister sfr ac h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 pwmdata[7:0] pwm data register the pwm data register serves to configure the selected channel msb/lsb value of either the mid or end point, as specified in the pwmcfg register. the pwmidx defines the actual timer value and the pwmend defines the maximum timer count value before it rolls over. the pwmldpol register controls the output polarity of each one of the pwm modules or clears the timer?s value when the pwm modules operate as general purpose timers. t able 127:pwm p olarity and config l oad s tatus ? pwmldpol ab h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description read: 0 = last configuration has been loaded in pwm 1 = last configuration has not been loaded 7 pwmldpol7 write in pwm mode 0 = pwm 7 cycle starts with a low level 1 = pwm 7 cycle starts with a high level in timer mode 0 = no action 1 = pwm timer 7 value is cleared to 0 read: 0 = last configuration has been loaded in pwm 1 = last configuration has not been loaded 6 pwmldpol6 write in pwm mode 0 = pwm 6 cycle starts with a low level 1 = pwm 6 cycle starts with a high level in timer mode 0 = no action 1 = pwm timer 6 value is cleared to 0 read: 0 = last configuration has been loaded in pwm 1 = last configuration has not been loaded 5 pwmldpol5 write in pwm mode 0 = pwm 5 cycle starts with a low level 1 = pwm 5 cycle starts with a high level in timer mode 0 = no action 1 = pwm timer 5 value is cleared to 0 read: 0 = last configuration has been loaded in pwm 1 = last configuration has not been loaded 4 pwmldpol4 write in pwm mode 0 = pwm 4 cycle starts with a low level 1 = pwm 4 cycle starts with a high level in timer mode 0 = no action 1 = pwm timer 4 value is cleared to 0 read: 0 = last configuration has been loaded in pwm 1 = last configuration has not been loaded 3 pwmldpol3 write in pwm mode 0 = pwm 3 cycle starts with a low level 1 = pwm 3 cycle starts with a high level in timer mode 0 = no action 1 = pwm timer 3 value is cleared to 0 read: 0 = last configuration has been loaded in pwm 1 = last configuration has not been loaded 2 pwmldpol2 write in pwm mode 0 = pwm 2 cycle starts with a low level 1 = pwm 2 cycle starts with a high level in timer mode 0 = no action 1 = pwm timer 2 value is cleared to 0 vrs51l3xxx datasheet www.ramtron.com page 76 of 115 read: 0 = last configuration has been loaded in pwm 1 = last configuration has not been loaded 1 pwmldpol1 write in pwm mode 0 = pwm 1 cycle starts with a low level 1 = pwm 1 cycle starts with a high level in timer mode 0 = no action 1 = pwm timer 1 value is cleared to 0 read: 0 = last configuration has been loaded in pwm 1 = last configuration has not been loaded 0 pwmldpol0 write in pwm mode 0 = pwm 0 cycle starts with a low level 1 = pwm 0 cycle starts with a high level in timer mode 0 = no action 1 = pwm timer 0 value is cleared to 0 12.2 pwm module cl ock configuration register one system clock prescaler is associated with pwm modules 0 to 3, while another is associated with pwm modules 4 to 7. the pwm clock prescalers enables the pwm output frequency to be adjusted to match specific application needs, if required. the pwm clock prescalers are configured via the pwmclkcfg register. the four upper bits of this register control the clock for pmm modules 4 to 7, and the four lower bits control the clock source for pwm modules 0 to 3. the pwm module clock configur ation register controls the prescale value applied to the pwm modules? input clock, when the pwm modules are configured to operate as either pwms or general purpose timers. t able 128: pwm clock p rescaler c onfiguration r egister - pwmclkcfg af h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:4 u4pwmclk3[3:0] pwm timer 7, 6, 5,:4 clock prescaler * see table 3:0 l4pwmclk3[3:0] pwm timer 3, 2, 1,:0 clock prescaler * see table the following table shows the system clock division factor applied to the pwm modules for a given pwmclkcfg nibble. t able 129: pwm p rescaler values u4/l4pwmclk value (4 bit) clock prescaler u4/l4pwmclk value (4 bit) clock prescaler 0000 sys clk / 1 1000 sys clk / 256 0001 sys clk / 2 1001 sys clk / 512 0010 sys clk / 4 1010 sys clk / 1024 0011 sys clk / 8 1011 sys clk / 2048 0100 sys clk / 16 1100 sys clk / 4096 0101 sys clk / 32 1101 sys clk / 8192 0110 sys clk / 64 1110 sys clk/ 16384 0111 sys clk / 128 1111 sys clk/ 16384 12.3 pwm alternate mapping on the vrs51l30xxx (qfp-64) it is possible to output the pwm on the i/o port 5. the i/o port 5 has a greater current drive capability than i/o port 2. the bit 6 of the deviomap register (sfr e1h) controls the mapping of the pwm module outputs, as shown in the following table: t able 130: pwm modules output mapping deviomap.6 bit value pwm 7-0 0 (reset) p2.7 ? p2.0 1 p5.7 ? p5.0** **on vrs51l30xx devices only note that the pwm5 and pwm6 outputs have priority over the t0ex and t1ex inputs. vrs51l3xxx datasheet www.ramtron.com page 77 of 115 12.4 pwm example programs code example: pwm basic configuration the following example program shows the basic configuration of pwm modules #0, 1,2, 4 & 5 //-------------------------------------------------------------------------------------------------------------// // vrs51l3074-pwm_basic_sdcc.c // //-------------------------------------------------// // // description: vrs51l3074 pwms basic initialization demonstration program. // configure pwm0 as 8 bit resolution (25% duty) // configure pwm1 as 12 bit resolution (50% duty) // configure pwm2 as 16 bit resolution (75% duty) // configure pwm4 as 8 bit resolution and prescaler = 4 (25% duty) // configure pwm5 as 16 bit resolution and prescaler = 4 (75% duty) //-------------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 78 of 115 //------------------------------------------------------------------------ // --------- individual functions ------------------------- //------------------------------------------------------------------------ //--------------------------------------------------------------------------------------// // -- pwmconfig // -------------------------------------------------------------------------------------// // description: configure pwm channel //--------------------------------------------------------------------------------------// void pwmconfig(char channel,int endval,int midval) { char pwmch; char pwmready = 0x00; channel &= 0x07; //make sure pwm ch number <= 7 //wait last configuration to be loaded do{ pwmready = pwmldpol; }while(pwmready != 0x00); //define pwm enable section periphen2 |= 0x02; //enable pwm sfr //--define the value to put into the pwmen register switch(channel) { case 0x00 : pwmch = 0x01; break; case 0x01 : pwmch = 0x02; break; case 0x02 : pwmch = 0x04; break; case 0x03 : pwmch = 0x08; break; case 0x04 : pwmch = 0x10; break; case 0x05 : pwmch = 0x20; break; case 0x06 : pwmch = 0x40; break; case 0x07 : pwmch = 0x80; break; }//end of switch pwmen |= pwmch; //enable the selected channel //configure pwm end point pwmcfg = (channel + 0x58); //set pwm configuration register to point to //the msb of end value and set the pwmwait bit //to prevent the pwm configuration to be loaded //before the configure sequence is completed pwmdata = endval >> 8; pwmcfg &= 0xef; //set pwm configuration register to point to //the lsb of end value pwmdata = endval; //configure pwm mid point pwmcfg = (channel + 0x50); //set pwm configuration register to point to //the msb of mid value and set the pwmwait bit //to prevent the pwm configuration to be loaded //before the configure sequence is completed pwmdata = midval >> 8; pwmcfg &= 0xef; //set pwm configuration register to point to //the lsb of end value pwmdata = midval; pwmcfg &= 0x3f; //allows pwm update upon end of next pwm cycle }//end of pwmdata16bit() //--------------------------------------------------------------------------------------// // -- pwmdata8bit // -------------------------------------------------------------------------------------// // description: allow pwm channel data update // ( 8bit data )l //--------------------------------------------------------------------------------------// void pwmdata8bit(char channel,char pwmdata) { channel &= 0x07; //make sure pwm ch number <= 7 //--check that te last configuration has been loaded pwmcfg = (channel + 0x40); //write new value in pwm config //prevent pwm configuration to be loaded //before the configure sequence is completed pwmdata = pwmdata; //write new data into the pwm registers pwmcfg &= 0x3f; //allows pwm update upon end of next pwm cycle }//end of pwmdata8bit() //--------------------------------------------------------------------------------------// // -- pwmdata16bit // -------------------------------------------------------------------------------------// // description: allow pwm channel data update // ( 16bit data )l //--------------------------------------------------------------------------------------// void pwmdata16bit(char channel,int pwmdata) { channel &= 0x07; //make sure pwm ch number <= 7 pwmcfg = (channel + 0x50); //set pwm configuration register to point to //the msb of data value and set the pwmwait bit //and set the pwmwait bit to prevent the //pwm configuration to be loaded //before the configure sequence is completed pwmdata = pwmdata >>8; pwmcfg &= 0xef; //set pwm configuration register to point to //the lsb of data value pwmdata = pwmdata; pwmcfg &= 0x3f; //allows pwm update upon end of next pwm cycle }//end of pwmdata16bit() //;--------------------------------------------------------------------------------// //;- delay1msto : 1ms delay using timer0 // //; // //; calibrated for 40mhz // //;--------------------------------------------------------------------------------// void delay(unsigned int dlais){ idata unsigned char x=0; idata unsigned int dlaisloop; x = periphen1; //load periphen1 reg x |= 0x01; //enable timer 0 periphen1 = x; dlaisloop = dlais; while ( dlaisloop > 0) { th0 = 0x63; //timer0 reload value for 1ms at 40mhz tl0 = 0xc0; t0t1clkcfg = 0x00; //no prescaler for timer 0 clock t0con = 0x04; //start timer 0, count up do{ x=t0con; x= x & 0x80; }while(x==0); t0con = 0x00; //stop timer 0 dlaisloop = dlaisloop-1; }//end of while dlais... x = periphen1; //load periphen1 reg x = x & 0xfe; //disableble timer 0 periphen1 = x; }//end of function delais vrs51l3xxx datasheet www.ramtron.com page 79 of 115 12.5 using pwm modules as timers by appropriately configuring the pwmtmren sfr, the pwm modules can also operate as general purpose 16-bit timers. the following table describes the pwmtmren register: t able 131: pwm t imer m ode e nable register - pwmtmren sfr ad h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 pwm7tmren pwm 7 module operating mode 0 = pwm 7 module is configured as pwm 1 = pwm 7 module is configured as timer 6 pwm6tmren pwm 6 module operating mode 0 = pwm 6 module is configured as pwm 1 = pwm 6 module is configured as timer 5 pwm5tmren pwm 5 module operating mode 0 = pwm 5 module is configured as pwm 1 = pwm 5 module is configured as timer 4 pwm4tmren pwm 4 module operating mode 0 = pwm 4 module is configured as pwm 1 = pwm 4 module is configured as timer 3 pwm3tmren pwm 3 module operating mode 0 = pwm 3 module is configured as pwm 1 = pwm 3 module is configured as timer 2 pwm2tmren pwm 2 module operating mode 0 = pwm 2 module is configured as pwm 1 = pwm 2 module is configured as timer 1 pwm1tmren pwm 1 module operating mode 0 = pwm 1 module is configured as pwm 1 = pwm 1 module is configured as timer 0 pwm0tmren pwm 0 module operating mode 0 = pwm 0 module is configured as pwm 1 = pwm 0 module is configured as timer when operating in timer mode, the pwm module timer will count from 0000h up to the maximum pwm timer value defined by the pwm mid sub registers, which are accessible through the pwmcfg register. t able 132: s ummary of pwm mid sub registers access pwmcfg bit pwmlsbmsb pwmcfg bit pwmmidend pwm timer msb max count value 0 1 pwm timer msb max count value 1 1 once the pwm mid value is reached, the pwm timer overflow is set and the pwm timer rolls over to 0000h. the pwm timer flags are raised when the timer reaches the maximum val ue set by pwmmidh and pwmmidl. the pwmxtmrf bit must be cleared manually by the interrupt service routine. t able 133: pwm t imer f lags register - pwmtmrf sfr ae h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 pwm7tmrf pwm 7 module timer flag 0 = no overflow 1 = pwm timer 7 overflow 6 pwm6tmrf pwm 6 module timer flag 0 = no overflow 1 = pwm timer 6 overflow 5 pwm5tmrf pwm 5 module timer flag 0 = no overflow 1 = pwm timer 5 overflow 4 pwm4tmrf pwm 4 module timer flag 0 = no overflow 1 = pwm timer 4 overflow 3 pwm3tmrf pwm 3 module timer flag 0 = no overflow 1 = pwm timer 3 overflow 2 pwm2tmrf pwm 2 module timer flag 0 = no overflow 1 = pwm timer 2 overflow 1 pwm1tmrf pwm 1 module timer flag 0 = no overflow 1 = pwm timer 1 overflow 0 pwm0tmrf pwm 0 module timer flag 0 = no overflow 1 = pwm timer 0 overflow f igure 40: pwm as t imers overview pwmtmrpr(7:4) div ratio: sys clk / 1 downto sys clk / 16384 sys clk pwmtmrpr(3:0) div ratio: sys clk / 1 downto sys clk / 16384 pwm7 module pwm6 module pwm5 module pwm4 module pwm7 pin pwm6 pin pwm5 pin pwm4 pin pwm3 module pwm2 module pwm1 module pwm0 module pwm3 pin pwm2 pin pwm1 pin pwm0 pin pwm6en pwm5en pwm7en pwm4en pwm2en pwm1en pwm3en pwm0en pwmen periphen2 vrs51l3xxx datasheet www.ramtron.com page 80 of 115 12.6 configuring the pwm timers configuring the pwm modules to operate in pwm timer mode requires the following steps: 1. activate the pwmsfr register 2. configure the pwm clock prescaler (if required) 3. set the pwmldpol register to 00h 4. configure the pwm timer maximum count value by setting the pwm mid sub-registers 5. configure the pwm timer interrupts (if required) 6. configure the pwm modules as timers 7. enable the pwm modules follow the code example below to perform these seven steps : (?) periphen2 |= 0x02; //enable pwm sfr //--configure the pwm prescaler pwmclkcfg = 0x03; //apply a clock prescaler (div / 8) on pwm 3:0 //--configure pwm polarity pwmldpol = 0x00; //set all pwm in normal polarity //pwm output = 0 until //--configure pwm5 as timer // pwm timer 5 counts from 0000 to f000h pwmcfg = 0x15; //point to msb mid pwmdata = 0xf0; //set pwm as timer max msb pwmcfg = 0x05; //point to lsb mid pwmdata = 0x00; //set pwm as timer max lsb //--configure and enable pwm as timer interrupt to monitor pwm5 only intsrc2 &= 0xdf; //pwm7:4 timer module interrupt intpinsens1 = 0xdf; // sensitive on high level(0) intpininv1 = 0xdf; //set int0 pin sensitivity on normal level(0) inten2 |= 0x20; //enable pwm7:4 timer module interrupt //--activate the pwm module and cofigure the pwm modules 5 as timer pwmen |= 0x20; //enable pwm 5 pwmtmren |= 0x20; //enable pwm 5 as timer geninten = 0x03; //enable global interrupt 12.7 pwms as timers example programs code example: configuring pwm0 and pwm5 as timers the following example program demonstrates how to initialize pwm0 and pwm5 as general purpose timers, and how to monitor the pwm timer?s overflow flags by pooling or via an interrupt. //--------------------------------------------------------------------------------------------------------------// // vrs51l3074-pwm_as_timer1_sdcc.c.c //-------------------------------------------------------------------------------------------------------------// // description: pwm as timer example program // enable and configure pwm timer 0 // apply a clock prescaler on pwm timer 0 (div/8) // enable and configure pwm timer 5 // monitor pwm timer 0 ov flag by pooling // when pwm timer 0 overflow, toggle p1.0 pin // monitor pwm timer 5 ov flag by interrupt // when pwm timer 5 overflow interrupt occurs toggle p1.5 pin ///-------------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 81 of 115 13 enhanced arithmetic unit all members of the vrs51l3xxx device family include a hardware-based, calculati on engine that executes very fast arithmetic operati ons. with the exception of 16-bit division, which requires 5 cycles, the enhanced arithmetic unit performs multiplication, addition and data shifting in 1 sy stem clock cycle. this enables a tremendous performance gain of approximately 30% to 50% for multiplication and accumulation and 700% faster for 16-bit division compared to a standard c compiler when implementing mathematical and digital signal processing (dsp) operations. the enhanced arithmetic unit features: o hardware calculation engine o calculation result is ready as soon as the input registers are loaded o signed mathematical calculations o unsigned math operations are possible if the mul engine operands are limited to 15 bits in length o auto/manual reload of au result register o easy implementation of complex mathematical operations o 16-bit and 32-bit overflow flag o 32-bit overflow can set an interrupt o arithmetic unit operand registers can be cleared individually or simultaneously o overflow flags can be configured to stay active until manually cleared o can store and use results from previous operations o hardware arithmetic unit features a 32-bit barrel shifter in front of the aures register, which can be employed to scale up/down the result of the operation being performed o data shifting operation is performed within the 1 cycle required for multiplication/addition the arithmetic unit can be configured to perform the operations in the following figure. it can also perform data shifting. f igure 41: vrs51l3 xxx a rithmetic u nit o peration add32 + add32 mult16 + add32 (aua, aub) + auc = aures div16 (aua x auprev(16lsb) + auc = aures (aua x auprev(16lsb) + 0 = aures (aua x auprev(16lsb) + auprev = aures (aua x aua) + 0 (aua x aua) + auc = aures = aures (aua x aua) + auprev = aures (aua x aub) + 0 (aua x aub) + auc = aures = aures (aua x aub) + auprev = aures (aua / aub) = aures (1 cycle) (5 cycles) (1 cycle) (1 cycle) (1 cycle) (1 cycle) (1 cycle) (1 cycle) (1 cycle) (1 cycle) (1 cycle) where aua (multiplier), aub (multiplicand), auc (accumulator), aures (result) and auprev (previous result) are 16-, 16-, 32-, 32- and 32-bits wide, respectively. applications that requ ire arithmetic and dsp operations will benefit from the execution of such calculations on the enhanced arithmetic unit. these include digital filtering, dat a encryption, sensor output data processing, lookup table replacement, etc. more specifically, applications like fir filtering that require the repeated execution of 16-bit multiplication and accumulation will benefit tremendously from the arithmetic unit. 13.1 using the enhanced arithmetic unit the enhanced arithmetic unit operates in signed binary. access to its registers is executed via the sfr registers, located on sfr page 1. this page is accessed by setting the sfrpage bit of devmemcfg register to 0x01. the devmemcfg register is located at address f6h on both sfr pages. before accessing the enhanced arithmetic unit sfr registers, the module must be enabled. this is done by setting auen bit 5 of the periphen2 register to 1. auen bit 5 is located at address f5h on both sfr pages. vrs51l3xxx datasheet www.ramtron.com page 82 of 115 13.2 arithmetic unit control registers with the exception of the ba rrel shifter, the arithmetic unit?s operation is controlled by two sfr registers: o auconfig1 o auconfig2 the following tables describe these control registers: t able 134: a rithmetic c onfig r egister 1 ? auconfig1 sfr c2 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description read: always read as 0 7 capprev capture previous result enable 0 = previous result capture is disabled 1 = capture the previous result if capmode bit is set to 1 6 capmode 0 = the capture of previous result is automatic each time a write operation is done to the au0 1 = the capture of the previous result is manual and occurs when the capprev bit is set to 1 5 ovcapen capture result on 32-bit overflow 0 = no result capture is performed 1 = the au result is captured and stored when a 32-bit overflow condition occurs 4 readcap read stored result 0 = aures contains current operation result 1 = aures contains previous result 3:2 addsrc[1:0] au adder input n 32-bit addition source b input 00 = 0 (no add) 01 = c (std 32-bit reg) 10 = auprev 11 = auc (std 32-bit reg) a input 00=multiplication 01=multiplication 10=multiplication 11= concatenation of {a, b} + c for 32-bit addition 1:0 mulcmd[1:0] au mu ltiplication command 00 = aua x aub 01 = aua x aua 10 = aua x auprev (16 lsb) 11 = aua x aub notes in divider mode multa_in = mult_in = 0x0000 in multiplier mode diva_in = 0x0000 and divb_in = 0x0001 t able 135: a rithmetic c onfig r egister 2 ? auconfig2 sfr c3 h 7 6 5 4 3 2 1 0 w w w r/w r r r r 0 0 0 0 0 0 0 0 bit mnemonic description read: always read as 0 7:5 auregclr [2:0] arithmetic unit operand registers clear 000 = no clear 001 = clear aua 010 = clear aub 011 = clear auc 100 = clear auprev 101 = clear all au module registers and overflow flags 110 = clear overflow flags only 4 auinten arithmetic unit interrupt enable 0 = arithmetic unit interrupt is disabled 1 =-arithmetic unit interrupt is enabled in divider mode 3 - not used, read as 0 2 divoutrg au division is out of range flag this flag is set if aub = 0x0000 or (aua = 0x8000 and aub = 0xffff) 1 auov16 arithmetic unit 16-bit overflow flag 0 = no 16 bit overflow condition detected 1 = a 16-bit overflow occurred will occur if there is a carry on from bit 15 to bit 1,6 but also from bit 31 to bit 32 0 auov32 arithmetic unit 32-bit overflow flag 0 = no 16 bit overflow condition detected 1 = operation result is larger than 32 bits 13.3 arithmetic unit data registers the arithmetic unit data re gisters include operand and result registers that serv e to store the numbers being manipulated in mathematical operations. some of these registers are uniquely for addition (such as auc), while others can be used for all operations. the use of the arithmetic unit operation registers is described in the following sections. 13.4 aua and aub multiplication (addition) input registers the aua and aub registers serve as 16-bit input operands when performing multiplication. when the arithmetic unit is configured to perform 32-bit addition, the aua and the aub registers are concatenated. in this case, the aua register contains the upper 16 bits of the 32-bit operand and the aub contains the lower 16 bits. t able 136: a rithmetic u nit a register bit [7:0] - aua0 sfr a2 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 aua[7:0] lsb of the a operand register vrs51l3xxx datasheet www.ramtron.com page 83 of 115 t able 137: a rithmetic u nit a register bit [15:8]- aua1 sfr a3 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 aua[15:8] msb of the a operand register t able 138:a rithmetic u nit b register bit [7:0] - aub0 sfr b2 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 aub[7:0] lsb of the b oper and register for multiplication and addition operations t able 139:a rithmetic u nit d ivision m ode r egister ? aub0div sfr b1 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 aub0div[7:0] writing to this byte instead of aub0 will set the arithmetic unit to divisor mode t able 140: a rithmetic u nit b register bit [15:8] - aub1 sfr b3 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 aub[15:8] msb of the b operand register 13.5 auc input register the auc register is a 32-bit register used to perform 32-bit addition. the auprev register can be substituted with the auc regist er or by 0 in the 32-bit addition. t able 141:a rithmetic u nit c register bit [7:0] - auc0 sfr a4 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 auc[7:0] bit [7:0]of the c operand register t able 142: a rithmetic u nit c register bit [15:8] - auc1 sfr a5 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 auc[15:8] bit [15:8] of the c operand register t able 143:a rithmetic u nit c register bit [23:16] - auc2 sfr a6 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 auc[23:16] bit [23:16] of the c operand register t able 144:a rithmetic u nit c register bit [31:24] ? auc3 sfr a7 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 auc[31:24] bit [31:24] of the c operand register 13.6 the arithmetic unit aures register the aures register, which is 32 bits wide, is read-only and contains the result of the last arithmetic unit operation. the aures register is located at the output of the barrel shifter. when the arithmetic unit is configured to perform multiplication and/or addition, the aures operates as a 32-bit register that contains the result of the previous operation(s). however when the arithmetic unit has performed a 16- bit division, the upper 16 bits of the aures register contain the quotient of the operation, while the lower 16 bits contain the remainder of the division operation. the barrel shifter is deactivated when the arithmetic unit is performing 16-bit division. four sfr registers located in sfr page 1 provide access to the arithmetic unit aures register. t able 145: a rithmetic u nit result register bit [7:0] - aures0 sfr b4 h 7 6 5 4 3 2 1 0 r r r r r r r r 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 aures[7:0] bit [7:0]of the result register t able 146: a rithmetic u nit r esult register bit [15:8] - aures1 sfr 5 h 7 6 5 4 3 2 1 0 r r r r r r r r 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 aures[15:8] bit [15:8] of the result register t able 147: a rithmetic u nit result register bit [23:16] ? aures2 sfr b6 h 7 6 5 4 3 2 1 0 r r r r r r r r 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 aures[23:16] bit [23:16] of the result register t able 148: a rithmetic u nit result register bit [31:24] ? aures3 sfr b7 h 7 6 5 4 3 2 1 0 r r r r r r r r 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 aures[31:24] bit [31:24] of the result register vrs51l3xxx datasheet www.ramtron.com page 84 of 115 13.7 auprev register the auprev register can automatically or manually save the contents of the aures register and re-inject it into the calculation. this feature is especially useful in applications where the result of a given operation serves as one of the operands for the next one. as previously mentioned, there are two ways to load the auprev register. this is controlled by the capmode bit value as follows: capmode = 0: auto auprev load, by writing into the aua0 register. selected when capprev = 0. capmode = 1: manual load of auprev when the capprev bit is set to 1. auto loading of the auprev register is useful in fir filter calculations. for example, it is possible to save a total of eight mov operations per tap calculation. t able 149: a rithmetic u nit p revious r esult bit [7:0] - auprev0 sfr c4 h 7 6 5 4 3 2 1 0 r r r r r r r r 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 auprev[7:0] bit [7:0]of the previous result register t able 150:a rithmetic u nit p revious r esult bit [15:8] - auprev1 sfr c5 h 7 6 5 4 3 2 1 0 r r r r r r r r 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 auprev[15:8] bit [15:8] of the previous result register t able 151:a rithmetic u nit p revious r esult bit [23:16] ? auprev2 sfr c6 h 7 6 5 4 3 2 1 0 r r r r r r r r 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 auprev[23:16] bit [23:16] of the previous result register t able 152:a rithmetic u nit p revious r esult bit [31:24] ? auprev3 sfr c7 h 7 6 5 4 3 2 1 0 r r r r r r r r 0 0 0 0 0 0 0 0 bit mnemonic description 7:0 auprev[31:24] bit [31:24] of the previous result register 13.8 multiplication and accumulate operations the multiplication and accumulate operations of the arithmetic unit are defined by the mulcmd[1:0] and addsrc[1:0] bits of the auconfig1 register. t able 153: m ultiplication operations vs . mulcmd bit of the auconfig1 mulcmd[1:0] multip lication operation 00 aua x aub 01 aua x aua 10 aua x auprev (16lsb) 11 aua x aua t able 154: a ddition operations vs . addsrc bit of the auconfig1 addsrc[1:0] addition operation 00 no addition 01 auc 10 auprev[31:0] 11 32-bit addition of [aua,aub] + auc the following figure provides a block diagram representation of the arithmetic unit operation for multiplication and addition. f igure 42: a rithmetic u nit m ultiplication and a ddition overview x + msb lsb multiplicand 2 aub(1:0) aua(1:0) auprev(3:0) aub(1:0) mulcmd{1:0} aua1 aua0 msb lsb multiplicand 1 00 01 10 11 aub1 aub0 lsb aua1 aua0 msb adder1 = 0 auc(3:0) auprev(3:0) 32 bit add {aua,aub} + auc addsrc{1:0} 00 01 10 11 msb lsb adder msb lsb barrel shifter aures(3:0) aushiftcfg =11 addsrc{1:0} 10 01 00 the following table provides examples of the auconfig and aushiftcfg register values and the corresponding math operations performed by the arithmetic unit. it also provides the value that would be present in the aures register if the arithmetic unit input registers were initialized to the following values: ? ? ? ? vrs51l3xxx datasheet www.ramtron.com page 85 of 115 t able 155:c onfiguration of the a rithmetic u nit , operation and o utput result auconfig1 aushiftcfg operation aures 01h 00h aua x aua 0a369084h 00h 00h aua x aub 0d986d42h 03h 00h aua x aub 0d986d42h 02h 00h aua x auprev15:0 114563f0h 0ch,0dh,0eh ,0fh 00h (aua,aub) +auc] 32 bit addition 44335522h 04h, 07h 00h (aua x aub)+ auc 1ea97e53h 04h, 07h 01h ((aua x aub)+ auc) x 2 (shift 1 left) 3d52fca6h 04h, 07h 3eh ((aua x aub)+ auc) / 4 (shift 2 right) 7aa5f94h multiplication and accumulate operations take place within one system clock cycle. 13.9 division operation (aua / aub1:aub0div) the vrs51l3xxx arithmetic unit can be configured to perform 16-bit division operations: the division of aua by aub1,aub0div. the quotient of this operation is stored in the aures3, aur es2 registers, with the remainder stored in the aures1, aures0 registers the following figure represents a 16-bit division. f igure 43: a rithmetic u nit d ivision overview aub1 aub0div msb lsb aures3 aures2 msb lsb quotient remainder aures1 aures0 msb lsb aua1 aua0 msb lsb dividend divisor division operation is triggered by writing lsb of divisor into the aub0div register writing the lsb of the divisor into the aub0div register will trigger a division operation. once the division starts, the value written in the aub0div register will be automatically transferred into the aub0 register. this operation is neither affected by the barrel shifter nor the multiplication/addition operation, defined by the auconfig register. the division operation takes five system clock cycles to be complete. 13.10 barrel shifter the arithmetic unit includes a 32-bit barrel shifter at the output of the 32-bit addition unit. the barrel shifter is used to perform right/left shift operations on the arithmetic unit output. the shift operation takes only one cycle. the barrel shifter can be used to scale the output result of the arithmetic unit. the shifting range is adjustable from 0 to 16 in both directions. the ?shifted? value can be routed to: o aures o auprev o auov32 moreover, the shift left operation can be configured as an arithmetic or logical shift, in which the sign bit is discarded. t able 156: a rithmetic u nit s hift r egister config - aushiftcfg sfr c1 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 shiftmode au barrel shifter shift mode 0 = shift value is unsigned 1 = shift value is signed 6 arithshift au arithmetic shift enable 0 = left shift is considered as logical shift (sign bit is lost) 1 = left shift is arithmetic shift where sign bit is kept 5:0 shift[5:0] the value of sh ift[5:0] equals the amplitude of the shift performed on the arithmetic unit result register aures positive value represent shift to the left negative value represent shift to the right the barrel shifter section operates independently of the multiply and accumulate sections on the arithmetic unit. as such, if the aushiftc fg register bits 5:0 are set to a value other than 0, the value of auprev, if derived from the aures regist er either automatically or manually, will be affected by the barrel shifter. when the arithmetic unit is configured to perform multiplication and addition operations, the barrel shifter is active and the shift operation performed depends on the current value of the aushiftcfg register. when the arithmetic unit is configured to perform 16-bit division, the barrel shifter is deactivated. vrs51l3xxx datasheet www.ramtron.com page 86 of 115 13.11 arithmetic unit block diagram the following block diagram provides a hardware description of the registers and the other components that comprise the enhanced arithmetic unit. f igure 44: a rithmetic u nit f unctional d iagram aua1 (msb) aua0 (lsb) aub1 (msb) aub0 (lsb) sfr registers auc3 (msb) auc2 auc1 auc0 (lsb) aua aub mul (signed) mulcmd add msb add lsb addsrc auc auov32 shift rdstored aures auprev aua0 load capprev manloop aures (sfr regs) load shiftmode ov16a 0 (16 lsb) aures2 aures3 (msb) aures1 aures0 (lsb) sfr registers sfr registers auprev3 (msb) auprev2 auprev1 auprev0 (lsb) auconfig2 aushiftcfg auconfig1 arithmetic unit control sfr addsrc b b a a concatenation (a,b) auov16 stored result ovcapen auov32 aub0div (lsb) *for division operations only previous aua aub aua div by aub (signed) divoutrg aures(1:0) aures(3:2) quotient remainder vrs51l3xxx datasheet www.ramtron.com page 87 of 115 13.12 arithmetic unit example programs code example: basic arithmetic operations the following example program demonstrates the required arithmetic unit configuration to perform mathematical operations //--------------------------------------------------------------------------------------------------/ // vrs51l3074_multaccu1_sdcc.c // //--------------------------------------------------------------------------------------------------/ // // description: vrs51l3074 arithmetic unit demonstration program // //--------------------------------------------------------------------------------------------------/ #include vrs51l3xxx datasheet www.ramtron.com page 88 of 115 //---- functions declaration ----// //-- fir filter computation function void fircompute(void); void copyfircoef(void); //--gen_adc void readgen_adc(void); // //- gen_dac void writegen_dac(unsigned int ); //---generic functions prototype void v2kdelay1ms(unsigned int); //standard delay function // global variables definitions idata unsigned char cptr = 0x00; unsigned int adcdata = 0x00; //-----------------------------------------------------------// //--------- main function -----------------// //-----------------------------------------------------------// void main (void) { periphen2 |= 0x02; //enable pwm sfr p2pincfg = 0xf0; //p2[3:0] is output pwmclkcfg = 0x10; //pwm timer 7 prescaler = sys clock / 2 //--configure pwm7 as timer (will be monitored by interrupt) // pwm timer 7 counts from 0000 to a2c2h pwmcfg = 0x17; //point to msb mid pwmdata = 0xa2 pwmcfg = 0x07; //point to lsb mid pwmdata = 0xc2; //--configure and enable pwm as timer interrupt to monitor pwm5 only intsrc2 &= 0xdf; //pwm7:4 timer module interrupt intpinsens1 = 0xdf; // sensitive on high level(0) intpininv1 = 0xdf; //set int0 pin sensitivity on normal level(0) inten2 |= 0x20; //enable pwm7:4 timer module interrupt //-- copy fir filter coefficients to iram copyfircoef(); //--activate the pwm modules and configure the pwm modules as timers pwmen |= 0x80; //enable pwm 7 pwmtmren |= 0x80; //enable pwm 7 as timer geninten = 0x01; //enable global interrupt while(1); }// end of main //-----------------------------------------------------------------------------// //---------------------- interrupt function----- ----------------------// //-----------------------------------------------------------------------------// //------------------------------------------------------------------------------- // name: int13interrupt pwmtmr7:4 as timer //------------------------------------------------------------------------------- void int13interrupt(void) interrupt 13 { char flagread; inten2 = 0x00; //disable pwm7:4 timer module interrupt flagread = pwmtmrf; //read pwm timer ov flags flagread &= 0x80; //check if pwm timer 7 ov flag is active if(flagread != 0x00) { p2 = p2^0x01; //toggle p2.0 (test) readgen_adc(); //read the a/d converter fircompute(); //perform the fir filter computation and write into dac } pwmtmrf &= 0x7f; //clear the pwm timer 7 ov flag inten2 |= 0x20; //enable pwm7:4 timer module interrupt }//end of pwm as timer interrupt //-----------------------------------------------------------------------------// //---------------------- individual functions ---------------------------// //-----------------------------------------------------------------------------// //------------------------------------------------------------------------ // name: fircompute //----------------------------------------------------------------------- void fircompute() { char *coef = &fircoef; char *ydata = &datastack; char fircptr = 0x00; periphen2 |= 0x20; //enable the arithmetic unit p2 = 0xff; //set p2 = 0xff to monitor duration for fir loop *ydata = adcdata & 0x0ff; //store the lsb of adc read data ydata += 1; *ydata = (adcdata >> 8)&0x00ff; //store the msb of adc read data devmemcfg = 0x01; //switch to sfr page 1 auconfig1 = 0x08; //caprev = 0 : previous res capture is automatic //capmode = 1 : capture of previous result //occurs when aua0 is written into //ovcapen = 0 : capture on ov32 disabled //readcap = 0 : aures contains current result //addsrc = 10 : add scr = auc //mulcmd = 00 : mul cmd = aua x aub auconfig2 = 0xa0; //clear the arithmetic unit registers _asm mov r0,#0x30; //copy start address of fir coefficient table into r0 mov r1,#0x50; //copy start address of fir data table into r1 _endasm; // yn computation mostly in assembler -- faster... for(fircptr = 0; fircptr < 16; fircptr++) { _asm mov 0xa2,@r0; //copy lsb of pointed coefficient to aua0 inc r0; mov 0xa3,@r0; //copy msb of pointed coefficient to aua1 inc r0; mov 0xb2,@r1; //copy lsb of pointed coefficient to aub0 inc r1; mov 0xb3,@r1; //copy msb of pointed coefficient to aub1 inc r1; _endasm; }//end of for cptr //-- performing the data stack shifting allows to save 8.8us @ 40mhz _asm mov r0,#0x6f; mov r1,#0x71; _endasm; for(fircptr = 16; fircptr > 0; fircptr--) { _asm mov a,@r0; mov @r1,a; dec r0; dec r1; mov a,@r0; mov @r1,a; dec r0; dec r1; _endasm; }//end of shift for loop //-scale down the aures output by 16 using the barrel shifter // the coefficient had been scaled up by a factor of 65536 aushiftcfg = 0x30; _asm nop; _endasm; p2 = 0x00; //set p2 = 0x00 to signal the end of the fir loop dacdata = (aures1 << 8) + aures0; //reset the barrel shifter aushiftcfg = 0x00; // note: // in this case, 6 system clock cycles could be saved // by reading aures3 and aures2 directly devmemcfg = 0x00; //switch to sfr page 0 writegen_dac(dacdata); //write data to spi dac }//end of fircompute vrs51l3xxx datasheet www.ramtron.com page 89 of 115 //------------------------------------------------------------------------ // name: copyfircoef //----------------------------------------------------------------------- // description: copy the fir filter coefficient into // sram variable which is faster access // than flash //----------------------------------------------------------------------- void copyfircoef(void) { char cptr = 0x00; for(cptr = 0x00; cptr < 16; cptr++) fircoef[cptr]= flashfircoef[cptr]; }//end of copyfircoef //------------------------------------------------------------------------ // name: readgen_adc //----------------------------------------------------------------------- // description: read the gen_adc a/d // adc is connected to spi interface using cs0 // max clk speed is 3.2mhz, fosc = 40mhz assumed //------------------------------------------------------------------------ void readgen_adc() { int cptr = 0x00; char readflag = 0x00; //spi configuration section /(can be moved to main function if only one device is connected to the spi interface) periphen1 |= 0xc0; //make sure the spi interface is activated //--wait activity stops on the spi interface (monitor spinocs) while(!(spistatus &= 0x08)); spictrl = 0x65; //spiclk = /16 (2.5mhz) //cs0 active //spi mode 1 phase = 1, pol = 0 //spi master mode spiconfig = 0x40; //spi chip select is automatic //clear spiundefc flag //spiload = 0 -> manual cs3 behaviour //no spi interrupt used spistatus = 0x00; //spi transactions are in msb first format spisize = 0x0e; //spi transaction size are 15-bit //-dummy read the spi rx buffer to clear the rxav flag readflag = spirxtx0; //-perform the spi read spirxtx0 = 0x00; //writing to the spirxtx0 will trigger the spi //transaction //wait for the spi rx av flag being set while(!(spistatus &= 0x02)); /* // -- it is possible to monitor the spinocs flag instead of the spirxav flag //the code piece below shows how to do it. however in that case, //no that the reading of the spistatus register must be done at //least 4 system clock cycles after the write operation to the spirxtx0 register //-wait for spinocs flag have time to be updated _asm nop; _endasm; //--wait activity stops on the spi interface while(!(spistatus &= 0x08)); */ //read spi data adcdata= (spirxtx1 << 8); adcdata+= spirxtx0; adcdata&= 0x0fff; //isolate the 12 lsb of the read value }//end of readgen_adc //------------------------------------------------------------------------------------------// // name: writegen_dac //------------------------------------------------------------------------------------------// // description: write 12bit data into the gen_dac device // adc is connected to spi interface using cs1 // max clk speed is 12.5mhz, fosc = 40mhz assumed // we will set the spi prescaler to sysclk / 8 // void writegen_dac(unsigned int dacdata) { char subdata = 0x00; char readflag = 0x00; periphen1 |= 0xc0; //make sure the spi interface is activated //--wait activity stops on the spi interface (monitor spinocs) while(!(spistatus &= 0x08)); //spi configuration section //can be moved to main function if only one device is connected to the spi interface spictrl = 0x4d; //spiclk = /8 (mhz) //cs1 active //spi mode 1 phase = 1, pol = 0 //spi master mode spiconfig = 0x40; //spi chip select is automatic //clear spiundefc flag //spiload = 0 -> manual cs3 behaviour //no spi interrupt used spistatus = 0x00; //spi transactions are in msb first format spisize = 0x0b; //spi transaction size are 12 bit //-format the 12 bit data so data bit 11 is positioned on bit 7 of spirxtx0 // and data bit 0 is positioned on bit 4 of spirxtx1 and perform the spi write operation dacdata &= 0x0fff; //make sure dacdata is <= 0fffh (12 bit) spirxtx3 = 0x00; spirxtx2 = 0x00; spirxtx1 = (dacdata << 4)& 0xf0; //-dummy read the spi rx buffer to clear th e rxav flag (facultative if spinocs is monitored) readflag = spirxtx0; spirxtx0 = (dacdata >> 4); //writing to spirxtx0 will trigger the transmission //--wait the spi transaction completes // this section can be omitted if a check of activity on the spi interface // is made before each access to it in master mode //wait for the spi rx av flag being set while(!(spistatus &= 0x02)); // -- it is possible to monitor the spin ocs flag instead of the spirxav flag //the code piece below shows how to do it. however in that case, //no that the reading of the spistatus register must be done at //least 4 system clock cycles after the wr ite operation to the spirxtx0 register /* //-wait for spinocs flag have time to be updated _asm nop; _endasm; //--wait activity stops on the spi interface (monitor spinocs flag) while(!(spistatus &= 0x08)); */ }//end of writegen_dac //------------------------------------------------------------------------------------------// // name: v2kdelay1ms //------------------------------------------------------------------------------------------// // description: vrs3074 specific 1 millisecond delay function // using timer 0 and calibrated for 40mhz oscillator //------------------------------------------------------------------------------------------// void v2kdelay1ms(unsigned int dlais){ idata unsigned char x=0; idata unsigned int dlaisloop; periphen1 |= 0x01; //load periphen1 reg dlaisloop = dlais; while ( dlaisloop > 0) { th0 = 0x63; //timer0 reload value for 1ms at 40mhz tl0 = 0xc0; t0t1clkcfg = 0x00; //no prescaler for timer 0 clock t0con = 0x04; //start timer 0, count up do{ x=t0con; x= x & 0x80; }while(x==0); t0con = 0x00; //stop timer 0 dlaisloop = dlaisloop-1; }//end of while dlais... periphen1 &= 0xfe; //disable timer 0 }//end of function v2kdelay1ms vrs51l3xxx datasheet www.ramtron.com page 90 of 115 14 watchdog timer the vrs51l3xxx devices in clude a watchdog timer . the watchdog timer is composed of a 14-bit prescaler, which derives its source from the active system clock. an overflow of the watchdog timer resets the processor. the wdtcfg sfr register controls the watchdog timer operations. t able 157: t he w atchdog t imer register - wdtcfg 91 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:4 wdtperiod watchdog timer period configuration *see table below 3 wtimerovf wdt as timer overflow flag 0 = wdt as timer as not expired 1 = wdt as timer has overflow 2 astimer watchdog as timer 0 = wdt mode 1 = wdt operate as a regular timer (no reset) writing to this bit will clear the timer read: 0 = watchdog is counting 1 = watchdog timer period has expired 1 wdtovf write: 0 = no action 1 = clear the watchdog timer flag read: no action 0 wdtreset watchdog timer reset to reset the watchdog timer, two consecutive writes to the wdtreset bit must be made: first clear the wdtreset bit and second, set it to 1 14.1 wdt timeout period the watchdog timer timeout period is controlled by adjusting bit 7:4 of the wdtcfg register. the following table provides the approximate timeout vs. the selected wdtperiod. the wdt timeout period is not affected by the clock divider. t able 158: w atchdog t imer register t imeout period wdtperiod value (4 bit) actual wdt period** approx timeout** (40mhz) 0000 0x3fff* 819-1000 us 0001 0x3ffe 1.23 ? 1.36 ms 0010 0x3ffd 2.05 ? 2.2 ms 0011 0x3ffb 4.92 ms 0100 0x3ff4 9.83 ms 0101 0x3fe8 20.07 ms 0110 0x3fcf 49.97 ms 0111 0x3f86 74.96 ms 1000 0x3f49 99.94 ms 1001 0x3f0c 249.86 ms 1010 0x3e9e 500.12 ms 1011 0x3b3b 749.98 ms 1100 0x38d9 999.83 ms 1101 0x3677 2.99 s 1110 0x2364 6.71s 1111 0x0000 13.4 s *not available in timer mode the watchdog timer timeout period is calculated as follows: wdt period* = 2*16384*(0x4000 ? wdtperiod[3:0]) fosc *for a given configuration, the timeout period of the watchdog timer may vary by about 200us. this delay is caused by internal timing of the watchdog timer module. 14.2 resetting the watchdog timer to reset the watchdog timer, two consecutive write operations to the wdtcfg register must be performed. during the first write operation, the wdtreset bit must be cleared. during the second write operation, the wdtreset should be set to 1. this sequence is also required to set a new value for wdtperiod. for example, if the watchdog period is set to 100ms, the following sequence of operations will reset the watchdog timer: mov wdtcfg,#92h mov wdtcfg,#93h vrs51l3xxx datasheet www.ramtron.com page 91 of 115 errata: resetting the watchdog timer when running from an external crystal there is an issue in the cl ock setting of the wdt that prevent the program to reset the wdt properly when the clock divider setting of the versa ware jtag software device option is set to off and the vrs51l3xxx operates from an external crystal or oscillator. whenever the vrs51l3 xxx is running from an external crystal or oscillator and the wdt module is to be used, you must set the clock divider setting of the device option in versa ware to either fosc/2, fosc/4 or fosc/8. in order to run the program at ?full? speed, add the instruction: devclkcfg1 &= 0xf0; somewhere at the beginning of the code to force the system clock speed back to fosc/1 this work around is only required for application using the wdt and running from an external crystal or oscillator and it does not apply if the internal 40mhz oscillator is used 14.3 wdt example programs code example: wdt configuration and reset example when using the internal 40mhz oscillator the following demo program shows how to configure and use the wdt module of the vrs51l3xxx when running from the internal oscillator //-------------------------------------------------------------------------------------------------------------------// // v3k_wdt_demo_int_40mhzosc_sdcc.c // //-------------------------------------------------------------------------------------------------------------------// // description: // vrs51l2070/3074 watchdog timer demonstration program // when using the internal oscillator. // program operation: // *this program set p1 as output // *p1 is set to 0xff for 100ms // *initialize the watchdog timer with a timeout period of 20ms // *clear p1 // *start a delay function // *if the delay parameter of the delay function is larger than the // timeout period of the watchdog timer, the wdt will reset the vrs2000 // which will bring back p1 to high level // note/errata: // please refer to the "v2k_wdt_demo_w_cy_osc_sdcc.c" demo program if you want // to use the wdt in a application running from the external crystal // or an oscillator module. //--------------------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 92 of 115 code example: wdt configuration and reset example when using an external oscillator the following demo program show the configuration and use of the wdt module when the vrs51l3xxx is running from an external crystal or an oscillator. //-------------------------------------------------------------------------------------------------------------------// // v3k_wdt_demo_w_ext_osc_sdcc.c // //-------------------------------------------------------------------------------------------------------------------// // // description: // vrs51l2070/3074 watchdog timer demonstration program when using an // the crystal oscillator or an external oscillator module. // // errata: // in order for the wdt to work properly when the vrs51l2070/3074 // operates from an external crystal or oscillator module, // the clock divider setting in the device option of the versa ware jtag // programming interface must be configured to either fosc/2, fosc/4 // or fosc/8 // // in order to run the application at "full speed", the devclkcfg1 // sfr register must be manually reconfigured to the fosc/1 // from within the code. ) // program operation: // // *this program set p1 as output // *reconfigure the devclkcfg1 register to fosc/1 // (if system must operate at "full" speed) // *activate the wdt module // *p1 is set to 0xff for 10ms (still running from 40mhz) // *activate external crystal oscillator and switch processor operation to it // *initialize the watchdog timer and configure the timeout period // *clear p1 // *start a delay function // *if the delay parameter of the delay function is larger than the // timeout period of the watchdog timer, the wdt will reset the processor // which will bring back p1 to high level //-----------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 93 of 115 14.4 using the watchdog as a timer the watchdog timer module can also be used as a timer. in this case, the timeout period is defined by the watchdog timer period value. due to the presence of the 14-bit prescaler, long timeout periods can be achieved. configuring the watchdog timer operation as a general purpose timer is achieved by: o setting the astimer bit of the wdtcfg register to 1 o selecting the timer maximum time value of wdtperiod o performing a watchdog timer reset sequence to clear the timer and apply the timer configuration the wtimerflag bit of the wdtcfg register is used to monitor the timer overflow. when configured in timer mode, the watchdog timer does not reset the processor and cannot trigger an interrupt. 14.5 watchdog as timer example program code example: initialization and reset of the watchdog timer //---------------------------------------------------------------------------------------------------------------------// // vrs51l3074-wdt_demo_sdcc.c // //---------------------------------------------------------------------------------------------------------------------// // description: vrs51l3074 watchdog timer demonstration program // *this program set p1 as output // *p1 is set to 0xff for 100ms // *initialize t he watchdog timer with a timeout period of 20ms // *clear p1 // *start a delay function // *if the delay parameter of the delay function is larger than the // timeout period of the watchdog timer, the wdt will reset the vrs51l3074 // which will bring back p1 to high level //---------------------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 94 of 115 15 interrupts the vrs51l3xxx devices f eature a comprehensive set of 49 interrupt sources and have 16 interrupt vectors to handle them. the interrupts are categorized in two distinct groups: ? ? vrs51l3xxx datasheet www.ramtron.com page 95 of 115 f igure 46: i nterrupt s ources overview 1 0 not used p3.2 - int0 pin 1 0 spi tx empty p3.3 - int1 pin 1 0 spi rx av/ov p3.0 pin 1 0 timer 0 p3.1 pin 1 0 port chg 0 p3.4 pin 1 0 uart0 p3.5 pin 1 0 uart1 p3.6 pin 1 0 timer 1 p3.7 pin 1 0 timer 2 p0.0 pin 1 0 i2c p0.1 pin 1 0 uart collision i2c m lost arbitration p0.2 pin 1 0 pwc modules p0.3 pin 1 0 pwm3:0 timer p0.4 pin 1 0 pwm7:4 timer p0.5 pin 1 0 wdt timer / arithmetic unit p0.6 pin 1 0 port chg 1 p0.7 pin interrupt number interrupt vector natural priority int 0 0003h 1 int 1 000bh 2 int 2 0013h 3 int 3 001bh 4 int 4 0023h 5 int 5 002bh 6 int 6 0033h 7 int 7 003bh 8 int 8 0043h 9 int 9 004bh 10 int 10 0053h 11 int 11 005bh 12 int 12 0063h 13 int 13 006bh 14 int 14 0073h 15 int 15 007bh 16 1 0 module 1 0 pin intpinfx.y bit intsrcx.y bit intpininvx.y bit intenx.y bit interrupt source config module i/o pin details of module / pin controller vrs51l3xxx datasheet www.ramtron.com page 96 of 115 the interaction between the interrupt management configuratio n registers is summarized in the following table. the paragraphs below describe each one of these registers in detail. t able 159:vrs51l3 xxx i nterrupt c onfiguration s ummary int # priority interrupt vector interrupt enable interrupt priority interrupt source connected modules connected pin pin inversion pin sensitivity pin interrupt flag int 0 1 0003h inten1.0 intpri1.0 intsrc1.0 none p3.2-int0 ipintinv1.0 ipinsens1.0 ipinflag1.0 int 1 2 000bh inten1.1 intpri1.1 intsrc1.1 spi tx empty p3.3-int1 ipintinv1.1 ipinsens1.1 ipinflag1.1 int 2 3 0013h inten1.2 intpri1.2 intsrc1.2 spi rx available spi rx overrun p3.0 ipintinv1.2 ipinsens1.2 ipinflag1.2 int 3 4 001bh inten1.3 intpri1.3 intsrc1.3 timer 0 p3.1 ipintinv1.3 ipinsens1.3 ipinflag1.3 int 4 5 0023h inten1.4 intpri1.4 intsrc1.4 port change 0 p3.4 ipintinv1.4 ipinsens1.4 ipinflag1.4 int 5 6 002bh inten1.5 intpri1.5 intsrc1.5 uart0 tx empty uart0 rx available uart0 rx overrun uart0 timer ov p3.5 ipintinv1.5 ipinsens1.5 ipinflag1.5 int 6 7 0033h inten1.6 intpri1.6 intsrc1.6 uart1 tx empty uart1 rx available uart1 rx overrun uart1 timer ov p3.6 ipintinv1.6 ipinsens1.6 ipinflag1.6 int 7 8 003bh inten1.7 intpri1.7 intsrc1.7 timer 1 p3.7 ipintinv1.7 ipinsens1.7 ipinflag1.7 int 8 9 0043h inten2.0 intpri2.0 intsrc2.0 timer 2 p0.0 ipintinv2.0 ipinsens2.0 ipinflag2.0 int 9 10 004bh inten2.1 intpri2.1 intsrc2.1 i2c tx empty i2c rx available i2c rx overrun p0.1 ipintinv2.1 ipinsens2.1 ipinflag2.1 int 10 11 0053h inten2.2 intpri2.2 intsrc2.2 uart0 collision uart1 collision i2c master lost arbitration p0.2 ipintinv2.2 ipinsens2.2 ipinflag2.2 int 11 12 005bh inten2.3 intpri2.3 intsrc2.3 pwc 0 end condition pwc 1 end condition p0.3 ipintinv2.3 ipinsens2.3 ipinflag2.3 int 12 13 0063h inten2.4 intpri2.4 intsrc2.4 pwm3 as timer ov pwm2 as timer ov pwm1 as timer ov pwm0 as timer ov p0.4 ipintinv2.4 ipinsens2.4 ipinflag2.4 int 13 14 006bh inten2.5 intpri2.5 intsrc2.5 pwm7as timer ov pwm6as timer ov pwm5as timer ov pwm4as timer ov p0.5 ipintinv2.5 ipinsens2.5 ipinflag2.5 int 14 15 0073h inten2.6 intpri2.6 intsrc2.6 watchdog as timer ov arithmetic unit ov p0.6 ipintinv2.6 ipinsens2.6 ipinflag2.6 int 15 16 007bh inten2.7 intpri2.7 intsrc2.7 port change 1 p0.7 ipintinv2.7 ipinsens2.7 ipinflag2.7 vrs51l3xxx datasheet www.ramtron.com page 97 of 115 15.1 interrupt enable registers the interrupt enable and the general interrupt enable registers establish the link between the peripheral module/pin interrupt signals and the processor interrupt system. the geninten register controls activation of the global interrupt. the geninten register is similar to the standard 8051 ea bit. when the geninten bit is set to 1, all the enabled in terrupts emanating from the modules/pins will reach the interrupt controller. the clrpinint bit is used to initialize the pin interrupt subsystem. it is recommended to set the clrpinint bit before enabling the pin interrupt. this will avoid receiving a pin interrupt right after the pin interrupt is enabled. t able 160:geninten sfr register - n ame sfr e8 h 7 6 5 4 3 2 1 0 - - - - - - w r/w 0 bit mnemonic description 7:2 unused 1 clrpinint it is recommended to set this bit to 1 before enabling a pin interrupt to avoid receiving an interrupt right after geninten bit is set 0 geninten general interrupt enable 0 = all enabled interrupts are masked (deactivated) 1 = all enabled interrupt can raise an interrupt when a given interrupt bit is set to 1, the corresponding interrupt path is activated. t able 161: i nt e nable 1 register - inten1 (m odules /p in /i nt v ector ) sfr 88 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description t1ien timer 1 interrupt enable p3.7 pin p3.7 pin if interrupt source is set to pin 7 int 7 interrupt vector 7 at address 003bh u1ien uart1 interrupt enable o uart1 tx empty o uart1 rx available o uart1 rx overrun o uart1 baud rate generator as timer overflow p3.6 pin p3.6 pin if interrupt source is set to pin 6 int 6 interrupt vector 6 at address 0033h u0ien uart0 interrupt enable o uart0 tx empty o uart0 rx available o uart0 rx overrun o uart0 baud rate generator as timer overflow p3.5 pin p3.5 pin if interrupt source set to pin 5 int 5 interrupt vector 5 at address 0002bh pchgien0 port change interrupt module 0 enable p3.4 pin p3.4 pin if interrupt source is set to pin 4 int 4 interrupt vector 4 at address 0023h t0ien timer 0 interrupt enable p3.3 pin p3.3 pin if interrupt source is set to pin 3 int 3 interrupt vector 3 at address 001bh spirxovien spi interrupt enable spi rx available spi rx overrun p3.0 p3.0 pin if interrupt source is set to pin 2 int 2 interrupt vector 2 at address 0013h spitxeien spi tx empty interrupt enable p3.3 pin p3.3 pin if interrupt source is set to pin 1 int 1 interrupt vector 0 at address 000bh no module unused p3.2 pin p3.2 pin if interrupt source is set to pin 0 int 0 interrupt vector 0 at address 0003h vrs51l3xxx datasheet www.ramtron.com page 98 of 115 t able 162: i nt e nable 2 register inten2 (m odules /p in /i nt v ector ) sfr a8 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description pchgien1 port change interrupt module 1 enable p0.7 pin p0.7 pin if interrupt source is set to pin 7 int 15 interrupt vector 15 at address 007bh auwdtien watchdog timer and arithmetic unit interrupt enable o watchdog as timer overflow o arithmetic unit 32-bit overflow p0.6 pin p0.6 pin if interrupt source is set to pin 6 int14 interrupt vector 14 at address 0073h pwmt74ien pwm as timer 7 to 4 overflow interrupt enable o pwm as timer module 7 overflow o pwm as timer module 6 overflow o pwm as timer module 5 overflow o pwm as timer module 4 overflow p0.5 pin p0.5 pin if interrupt source set to pin 5 int 13 interrupt vector 13 at address 006bh pwmt30ien pwm as timer 3 to 0 overflow interrupt enable o pwm as timer module 3 overflow o pwm as timer module 2 overflow o pwm as timer module 1 overflow o pwm as timer module 0 overflow p0.4 pin p0.4 pin if interrupt source is set to pin 4 int 12 interrupt vector 12 at address 0063h pwcien pulse width counter interrupt enable o pwc0 end condition occurred o pwc1 end condition occurred p0.3 pin p0.3 pin if interrupt source set to pin 3 int 11 interrupt vector 11 at address 005bh i2cucolien i2c and uarts interrupts enable o i2c master lost arbitration o uart0 collision interrupt o uart1 collision interrupt p0.2 pin p0.2 pin if interrupt source is set to pin 2 int 10 interrupt vector 10 at address 0053h i2cien i2c interrupts enable o tx empty o rx available o rx overrun p0.1 pin p0.1 pin if interrupt source set to pin 1 int 9 interrupt vector 9 at address 004bh t2ien timer 2 interrupt enable (intscr p0.0 pin p0.0 pin if interrupt source is set to pin 0 int 8 interrupt vector 8 at address 0043h 15.2 interrupt source each one of the 16 interrupt vectors on the vrs51l3xxx can be configured to function as either a peripheral module or a pin change interrupt. the selection of the interrupt source is handled by the intsrc1 and the intsrc2 registers. by default, the interrupt source is set to peripheral module. however, setting the intsrc bit to 1 will ?associate? the corresponding interrupt vector to the corresponding pin interrupt. when a given interrupt vector is associated with a module, the corresponding bit of the ipinsensx must be set to 0, so it is level sensitive (reset value). t able 163:i nterrupt s ource 1 register - intsrc1 sfr e4 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 intsrc1.7 interrupt 7 source 0 = timer 1 1 = p3.7 6 intsrc1.6 interrupt 6 source 0 = uart1 1 = p3.6 5 intsrc1.5 interrupt 5 source 0 = uart0 1 = p3.5 4 intsrc1.4 interrupt 4 source 0 = port change 0 1 = p3.4 3 intsrc1.3 interrupt 3 source 0 = timer 0 1 = p3.1 2 intsrc1.2 interrupt 2 source 0 = spi rxav, spi rxov 1 = p3.0 1 intsrc1.1 interrupt 1 source 0 = spi tx empty 1 = int1 (p3.3) 0 intsrc1.0 interrupt 0 source 0 = - 1 = int0 (p3.2) vrs51l3xxx datasheet www.ramtron.com page 99 of 115 t able 164:i nterrupt s ource 2 register - intsrc2 sfr e5 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 intsrc2.7 interrupt 15 source 0 = port change 1 1 = p0.7 6 intsrc2.6 interrupt 14 0 = wdt timer ov, au ov 1 = p0.6 5 intsrc2.5 interrupt 13 source 0 = pwm7:4 timer 1 = p0.5 4 intsrc2.4 interrupt 12 source 0 = pwm3:0 timer ov 1 = p0.4 3 intsrc2.3 interrupt 11 source 0 = pwc0, pwc1 1 = p0.3 2 intsrc2.2 interrupt 10 source 0 = uarts coll, i2c lost arbitration 1 = p0.2 1 intsrc2.1 interrupt 9 source 0 = i2c 1 = p0.1 0 intsrc2.0 interrupt 8 source 0 = timer 1 = p0.0 15.3 interrupt priority the intprix registers enable the user to modify the interrupt priority of eit her the module or the pin interrupts. when the intprix is set to 0, the natural priority of module/pin interrupts prevails. setting the intprix register bit to 1 will set the corresponding module/pin priority to high. if more than two module/pin interrupts are simultaneously set to high priority, the natural priority order will apply: priority will be give to the module/pin interrupts with high priority, over normal priority. t able 165:i nterrupt p riority 1 register - intpri1 sfr e2 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 t1p37pri interrupt 7 priority level (timer 1 / p3.7) 0 = normal priority 1 = high priority 6 u1p36pri interrupt 6 priority level (uart1 / p3.6) 0 = normal priority 1 = high priority 5 u0p35pri interrupt 5 priority level (uart0 / p3.5) 0 = normal priority 1 = high priority 4 pc0p34pri interrupt 4 priority level (port chg 0 / p3.4) 0 = normal priority 1 = high priority 3 t0p31pri interrupt 3 priority level (timer 0 / p3.1) 0 = normal priority 1 = high priority 2 srp30pri interrupt 2 priority level (spi rx / p3.0) 0 = normal priority 1 = high priority 1 stp33pri interrupt 1 priority level (spi tx / p3.3) 0 = normal priority 1 = high priority 0 int0p32pri interrupt 0 priority level (int0 / p3.2) 0 = normal priority 1 = high priority t able 166:i nterrupt p riority 2 register - intpri2 sfr e3 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 pc1p07pri interrupt 15 priority level (port chg 1 / p0.0) 0 = normal priority 1 = high priority 6 aip06pri interrupt 14 priority level (wdt, au / p0.6) 0 = normal priority 1 = high priority 5 pwhp05pri interrupt 13 priority level (pwm7:4 timer / p0.5) 0 = normal priority 1 = high priority 4 pwlp04pri interrupt 12 priority level (pwm3:0 timer / p0.4) 0 = normal priority 1 = high priority 3 pwcp02pri interrupt 11 priority level (pwc0, pwc1 / p0.3) 0 = normal priority 1 = high priority 2 int10p01pri interrupt 10 priority level (uarts coll, i2c lost arbitration / p0.2) 0 = normal priority 1 = high priority 1 i2cp01pri interrupt 9 priority level (i2c / p0.1) 0 = normal priority 1 = high priority 0 t2p00pri interrupt 8 priority level (timer 2 / p0.0) 0 = normal priority 1 = high priority vrs51l3xxx datasheet www.ramtron.com page 100 of 115 15.4 pin inversion setting t able 167: i mpact of p in i nversion setting on p in i nterrupt s ensitivity pin inversion interrupt condition 0 normal interrupt polarity sensitivity 1 inverted interrupt polarity sensitivity t able 168:i nterrupt p in i nversion 1 register - ipininv1 sfr d6 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 p37iinv interrupt 7 pin polarity 0 = p3.7 1 = p3.7 inverted 6 p36iinv interrupt 6 pin polarity 0 = p3.6 1 = p3.6 inverted 5 p35iinv interrupt 5 pin polarity 0 = p3.5 1 = p3.5 inverted 4 p34iinv interrupt 4 pin polarity 0 = p3.4 1 = p3.4 inverted 3 p31iinv interrupt 3 pin polarity 0 = p3.1 1 = p3.1 inverted 2 p30iinv interrupt 2 pin polarity 0 = p3.0 1 = p3.0 inverted 1 int1iinv interrupt 1 pin polarity 0 = int1 (p3.3) 1 = int1 (p3.3) inverted 0 int0iinv interrupt 0 pin polarity 0 = int0 (p3.2) 1 = int0 (p3.2) inverted t able 169: i nterrupt p in i nversion 2 register - ipininv2 sfr d7 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 p07iinv interrupt 15 pin polarity 0 = p0.7 1 = p0.7 inverted 6 p06iinv interrupt 14 pin polarity 0 = p0.6 1 = p0.6 inverted 5 p05iinv interrupt 13 pin polarity 0 = p0.5 1 = p0.5 inverted 4 p04iinv interrupt 12 pin polarity 0 = p0.4 1 = p0.4 inverted 3 p03iinv interrupt 11 pin polarity 0 = p0.3 1 = p0.3 inverted 2 p02iinv interrupt 10 pin polarity 0 = p0.2 1 = p0.2 inverted 1 p01iinv interrupt 9 pin polarity 0 = p0.1 1 = p0.1 inverted 0 p00iinv interrupt 8 pin polarity 0 = p0.0 1 = p0.0 inverted 15.5 pin interrupt sensitivity setting the pin interrupt can be conf igured as level sensitive or edge triggered. the pin interrupt sensitivity is set via the ipinsensx and ipininvx registers. the following table summarizes the pin interrupt trigger condition settings for ipinsenx and ipininvx. t able 170:i mpact of p in s ensitivity and p in i nversion setting on p in i nterrupt pin sensitivity pin inversion interrupt condition 0 0 high level on pin 0 1 low level on pin 1 0 rising edge on pin 1 1 falling edge on pin the following tables provide the bit definitions for the ipinsens1 and ipinsens2 registers. it is assumed that the corresponding ipininvx bit is set to 0. if the corresponding ipininvx bit is set to 1, the corresponding interrupt event will be inverted. t able 171:i nterrupt p in s ensitivity 1 register - ipinsens1 sfr e6 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 p37isens interrupt 7 pin sens itivity (ipi ninv1.7 = 0) 0 = p3.7 high level 1 = p3.7 rising edge 6 p36isens interrupt 6 pin sensitivity (ipininv1.6 = 0) 0 = p3.6 high level 1 = p3.6 rising edge 5 p35isens interrupt 5 pin sensitivity (ipininv1.5 = 0) 0 = p3.5 high level 1 = p3.5 rising edge 4 p34isens interrupt 4 pin sensitivity (ipininv1.4 = 0) 0 = p3.4 high level 1 = p3.4 rising edge 3 p31isens interrupt 3 pin sensitivity (ipininv1.3 = 0) 0 = p3.1 high level 1 = p3.1 rising edge 2 p30isens interrupt 2 pin sensitivity (ipininv1.2 = 0) 0 = p3.0 high level 1 = p3.0 rising edge 1 int1isens interrupt 1 pin sensitivity (ipininv1.1 = 0) 0 = int1 (p3.3) high level 1 = int1 (p3.3) rising edge 0 int0isens interrupt 0 pin sensitivity (ipininv1.0 = 0) 0 = int0 (p3.2) high level 1 = int0 (p3.2) rising edge vrs51l3xxx datasheet www.ramtron.com page 101 of 115 t able 172:i nterrupt p in s ensitivity 2 register - ipinsens2 sfr e7 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 p07isens interrupt 7 pin sensitivity (ipininv2.7 = 0) 0 = p0.7 high level 1 = p0.7 rising edge 6 p06isens interrupt 6 pin sensitivity (ipininv2.6 = 0) 0 = p0.6 high level 1 = p0.6 rising edge 5 p05isens interrupt 5 pin sensitivity (ipininv2.5 = 0) 0 = p0.5 high level 1 = p0.5 rising edge 4 p04isens interrupt 4 pin sensitivity (ipininv2.4 = 0) 0 = p0.4 high level 1 = p0.4 rising edge 3 p03isens interrupt 3 pin sensitivity (ipininv2.3 = 0) 0 = p0.3 high level 1 = p0.3 rising edge 2 p02isens interrupt 2 pin sensitivity (ipininv2.2 = 0) 0 = p0.2 high level 1 = p0.2 rising edge 1 p01isens interrupt 1 pin sensitivity (ipininv2.1 = 0) 0 = p0.1 high level 1 = p0.1 rising edge 0 p00isens interrupt 0 pin sensitivity (ipininv2.0 = 0) 0 = p0.0 high level 1 = p0.0 rising edge 15.6 pin interrupt flags for each pin interrupt there is an interrupt flag that can be monitored. when the selected interrupt event is detected on a given pin, the corresponding pin interrupt flag is set to 1 by the system. the interrupt pin flags should be cleared before any pin interrupt is activated. the pin interrupt flag are not automatically cleared by the interrupt service routine reti instruction. for this reason they must be cleared by the software before exiting the interrupt service routine. the pin interrupt flags can be monitored via the software, even if the corresponding pin interrupt is not activated. if all the corres ponding interrupts are routed to modules and all the interrupts are disabled, the ipinflagx registers can be used as general purpose scratchpad registers. however this is not recommended. t able 173:i nterrupt p in f lag 1 register - ipinflag1 sfr b8 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 p37if interrupt 7 pin flag set to 1 if p3.7 pin interrupt occurs 6 p36if interrupt 6 pin flag set to 1 if p3.6 pin interrupt occurs 5 p35if interrupt 5 pin flag set to 1 if p3.5 pin interrupt occurs 4 p34if interrupt 4 pin flag set to 1 if p3.4 pin interrupt occurs 3 p31if interrupt 3 pin flag set to 1 if p3.1 pin interrupt occurs 2 p30if interrupt 2 pin flag set to 1 if p3.0 pin interrupt occurs 1 int1if interrupt 1 pin flag set to 1 if int1 (p3.3) pin interrupt occurs 0 int0if interrupt 0 pin flag set to 1 if int0 (p3.2) pin interrupt occurs t able 174:i nterrupt p in f lag 2 register - ipinflag2 sfr d8 h 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7 p07if interrupt 15 pin flag set to 1 if p0.7 pin interrupt occurs 6 p06if interrupt 14 pin flag set to 1 if p0.6 pin interrupt occurs 5 p05if interrupt 13 pin flag set to 1 if p0.5 pin interrupt occurs 4 p04if interrupt 12 pin flag set to 1 if p0.4 pin interrupt occurs 3 p03if interrupt 11 pin flag set to 1 if p0.3 pin interrupt occurs 2 p02if interrupt 10 pin flag set to 1 if p0.2 pin interrupt occurs 1 p01if interrupt 9 pin flag set to 1 if p0.1 pin interrupt occurs 0 p00if interrupt 8 pin flag set to 1 if p0.0 pin interrupt occurs vrs51l3xxx datasheet www.ramtron.com page 102 of 115 16 jtag interface the vrs51l3xxx devices include a jtag interface that enables programming of the onboard flash as well as code debugging. to free up as many i/os as possible, the jtag interface pins are shared with regular i/o pins that can be used as general purpose i/os when the jtag interface is not being used. the jtag interface is mapped into the following pins: t able 175: jtag i nterface p in m apping jtag pin function corresponding pin tdi jtag data input p4.3 tdo jtag data output p4.2 cm0 chip mode 0 ale tms test mode select p4.1 tck jtag clock p2.7 activation of the jtag interface is controlled by the cm0-ale pin. the cm0-ale pin includes an internal pull-up resistor and its state is sampled when a power- on reset occurs. forcing the cm0-ale pin to 0 (logic low) during the power-on reset will activate the jtag interface and put the vrs51l3xxx into jtag mode. when the device is in jtag mode, the code will not execute after a power-on reset or a regular reset: to start the code, a ?program run? command must be sent through the jtag interface. this is handled by the versa ware jtag software developed by ramtron and available on ramtron?s web site at www.ramtron.com . this software provides an easy- to-use interface for device programming and in-circuit debugging. for more information on the debugger?s features and use, please consult the versa ware jtag software help. 16.1 impact of jtag interface activation when the jtag interface is activated, it has the following consequences on the vrs51l3xxx?s operation: ? ? ? vrs51l3xxx datasheet www.ramtron.com page 103 of 115 17 flash programming interface (fpi) the fpi module allows the processor to perform in- application management of the flash memory content. the following operations are supported by the fpi module : ? ? ? ? vrs51l3xxx datasheet www.ramtron.com page 104 of 115 used to read the flash, the read value is returned via the fpidatal register. when the fpi8bit bit is cleared, the fpi module will operate in 16-bit mode. in this case, the address range is defined by a 15-bit address (0000h to 7fffh) and must be written into the fpiaddrh and fpiaddrl registers. when a 16-bit fpi write operation is performed, the 16-bit data must be stored in the fpidatah and fpidatal registers. when a flash memory read operation is performed, the 16-bit data will be returned to the fpidatah and fpidatal registers. 17.2 fpi flash address and data registers the fpiaddrh and fpiaddrl registers are used to specify the address where the iap function will be performed. t able 178: fpi a ddress h igh fpiaddrh sfr eb h 7 6 5 4 3 2 1 0 r/w, reset = 0x00 fpiaddr[15:8] the fpiaddrh register contains the msb of the destination address. for page erase operations, it contains the page number where page erase operations are performed. t able 179:fpi a ddress l ow -fpiaddrl sfr ea h 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 r/w fpiaddr[7:0] the fpiaddrl register contains the lsb of the destination address where the operation is performed. for page erase operations, it must contain the value 0x00. the fpidatah and fpidatal registers contain the data byte(s) required to pe rform the fpi function. t able 180: fpi d ata h igh - fpidatah sfr ed h 7 6 5 4 3 2 1 0 r/w, reset = 0x00 fpidata[15:8] when read: msb of last wo rd read[15:8] from flash when write: byte[15:8] to write in flash t able 181:fpi data l ow - fpidatal sfr e ch 7 6 5 4 3 2 1 0 r/w, reset = 0x00 fpidata[7:0] read: last read byte[7:0] from flash writing to this byte in 'fpi write mode' triggers the fpi state machine to start the write action. 17.3 fpi clock speed control register the fpi clock speed control register sets the fpi module to an optimal speed based on the speed of the system clock. t able 182:fpi c lock s peed c ontrol r egister - fpiclkspd sfr ee h 7 6 5 4 3 2 1 0 r r r r r/w r/w r/w r/w 0 0 0 0 0 0 0 0 bit mnemonic description 7:4 unused 3:0 fpiclkspd [3:0] specifies speed of the system clock entering the fpi module frequency range: 0000 : 20mhz to 40 mhz 0001 : 10mhz to 20 mhz 0010 : 5mhz to 10 mhz 0011 : 2.5mhz to 5 mhz 0100 : 1.25mhz to 2.5 mhz 0101 : 625khz to 1.25 mhz 0110 : 312.5khz to 625 khz 0111 : 156.25khz to 312.5 khz 1000 : 78.12khz to 156.25 khz 1001 : 39.06khz to 78.125 khz 1010 : 19.53khz to 39.0625 khz others : 9.76khz to 19.53125 khz use the settings found in the following table when using the fpi at a speed other than the nominal speed of the internal oscillator. t able 183: s etting the fpiclkspd register range value minimum maximum 0 (default) 20.000 mhz 40.000 mhz 1 10.000 mhz 20.000 mhz 2 5.000 mhz 10.000 mhz 3 2.500 mhz 5.000 mhz 4 1.250 mhz 2.500 mhz 5 625.000 khz 1.250 mhz 6 312.500 khz 625.000 khz 7 156.250 khz 312.500 khz 8 78.125 khz 156.250 khz 9 39.063 khz 78.125 khz 10 19.531 khz 39.063 khz other 9.766 khz 19.531 khz the fpiclkspd register must be set to the corresponding system clock speed for proper operation of the fpi module. for example, a 20.0 mhz clock requires fpiclkspd to be se t to 1, while a 20.1 mhz clock requires fpiclkspd to be set to 0. if fpiclkspd is set incorrectly, the flash write operation may not process correctly, causing data corruption. vrs51l3xxx datasheet www.ramtron.com page 105 of 115 17.4 fpi write protection the vrs51l3xxx provides a safety mechanism to prevent accidental writing or erasing of the flash. the following sequence must be written to the fpidatal register to unlock the fpi module each time a write is performed. fpidatal ? aah fpidatal ? 55h not performing the above sequence will lock the fpi module until a reset of the vrs51l3xxx is performed. bit 7 and 6 of the fpiconfig provide the status of the fpi write protection circuitry. 17.5 flash read operations there are three ways to read directly from the vrs51l3xxx flash memory: 1. use the movc instruction 2. use the fpi in 8-bit mode 3. use the fpi in 16-bit mode it may be preferable to use the fpi over the movc instruction, because some compilers will optimize code that repeatedly checks the flash content. to do a flash read using the fpi interface, perform the following steps: o make sure the fpi module is enabled. o set fpiaddrh and fpiaddrl to the appropriate address (see section 1.1.4). o write 00000x00 to the fpiconfig register, where x = 1 if reading in 8-bit mode, and x = 0 if reading in 16-bit mode. o loop until fpiidle is raised. o get the results from fpidatah and fpidatal if in 16-bit mode, or from fpidatal if in 8-bit mode. 48: fpi f lash r ead (8 bit ) algorithm enable fpi module flash read using fpi (8 bit) set read address into fpiadrh fpiadrl write 0x04 into fpiconfig read data from fpidatal yes fpiidle == 1 ? no done read data on next address? example 1: fpi flash read in 8-bit mode : the following code sequence follows the above algorithm to read address abcdh in 8-bit mode: orl perhiphen2, #1 ; enable fpi mov fpiaddrh, #0abh ; move in upper address mov fpiaddrl, #0cdh ; move in lower address mov fpiconfig, #04h ; trigger the read in 8-bit mode wait: mov a, fpiconfig ; get the fpi status jnb acc.4, wait ; jump if not ready ; the read is now done. the result in fpidatal example 2: fpi flash read in 16-bit mode example the following code sequence will read 16 bits from address abcd: #include vrs51l3xxx datasheet www.ramtron.com page 106 of 115 17.6 fpi flash page erase when storing nonvolatile data into flash memory, it is necessary to erase the flash before writing to it. programming is done by byte or word boundary, while erase is done by page boundary. a page is a contiguous block of 512 addresses. page numbers can be calculated from the following formula: page = address / 512 page 0 contains all the addresses from 0000h to 01ffh, page 1 contains all the addresses from 0200h to 03ffh, and so on. there are 128 flash pages on the vrs51l3xxx (64kb flash).to erase a page, follow these steps: 1. ensure that the fpi module is enabled. 2. write aah to the fpidatal register. 3. write 55h to the fpidatal register. 4. write 0 to the fpiaddrl register. 5. write the page number to the fpiaddrh register. 6. write 2 to the fpiconfig register. 7. wait for fpiidle to go high. f igure 49: fpi f lash p age e rase algorithm done enable fpi module flash page erase fpiidle == 1 ? write aah, then 55h into fpidatal write 00h, into fpiadrl write flash page number , into fpiadrh write 0x02 into fpiconfig 20ms no example1: fpi page erase this code sequence will erase page 64: orl perhiphen2, #1 ; enable fpi mov fpidatal, #0aah ; unlock 1 mov fpidatal, #055h ; unlock 2 mov fpiaddrl, #0 ; move in 0 mov fpiaddrh, #64 ; move in page number mov fpiconfig, #2 ; trigger the page erase wait: mov a, fpiconfig ; get the fpi status jnb acc.4, wait ; jump if not ready ; the page is now erased 17.7 fpi flash mass erase it is possible to completely erase the flash memory from within a program. to do so, the following steps must be performed: 1. make sure that the fpi module is enabled. 2. write aah to the fpidatal register. 3. write 55h to the fpidatal register. 4. write 1 to the fpiconfig register. 5. if still possible, wait for fpiidle to go high. warning: at this point, the flash should be totally erased. if running from external memory, ensure that the program is copied back to its locations in flash with write commands. step 5 can only be performed if executing code from external sram. vrs51l3xxx datasheet www.ramtron.com page 107 of 115 17.8 flash write operations there are two methods to write to the flash: o 8-bit double buffered o 16-bit double buffered depending on the complexity and the amount of flash to be written, one mode may be more efficient than the other: 8-bit mode is more suited to programming a few bytes of data, while 16-bit mode is more suited to memory dumping. 17.9 fpi flash write - 8-bit mode follow the steps below to write in 8-bit mode: 1. make sure the fpi module is enabled. 2. write 7 to the fpiconfig register. 3. set fpiaddrh and fpiaddrl to the appropriate addresses. 4. write aah to the fpidatal register. 5. write 55h to the fpidatal register. 6. write data to the fpidatal register (this triggers the operation). 7. if complete, wait for fpidle to go high. if there are more bytes to be written at a different address, return to step 3. if the next address is contiguous, go to step 4 instead. f igure 50: fpi f lash b yte w rite algorithm 20us done enable fpi module flash write (8 bit) fpiidle == 1 ? write 07h into fpiconfig set write address into fpiadrh fpiadrl write aah, then 55h into fpidatal write data into fpidatal data on next address? yes no note that the ad dress the data is written to will be automatically incremented for the next byte. as such, the address only needs to be written once per data stream (assuming that a contiguous block is written), as shown in the following example. code example: fpi flash write in 8-bit mode example: //********************************************* //* fpi flash write 8bit mode example * //********************************************* #include vrs51l3xxx datasheet www.ramtron.com page 108 of 115 17.10 fpi flash write - 16-bit mode follow the steps below to write in 16-bit mode: 1. make sure the fpi module is enabled. 2. write 3 to the fpiconfig register. 3. set fpiaddrh and fpiaddrl to the appropriate addresses (remember to convert to 16-bit addressing). 4. write aah to the fpidatal register. 5. write 55h to the fpidatal register. 6. write data to the fpidatal register (this triggers the operation). 7. if complete, wait for fpi_idle to go high. if there are more bytes to be written at a different address, return to step 3. if the next address is contiguous, go to step 4 instead. note that the add ress the data is written to will be automatically incremented for the next byte. as such, the address only needs to be set once per data stream (assuming a contiguous region is written), as shown in the following example. code example: fpi flash write in 16-bit mode example: this routine copies 512 bytes (1 page) of external sram to the flash memory at address e000h + xram. the r0 and r1 registers contain the starting address of the page to copy. //********************************************* //* fpi flash write 16-bit mode example * //********************************************* write_page: push dph0 ;push the data pointer push dpl0 push acc ;push the var. to be used push b mov acc, r2 push acc mov dph0, r1 ;load the data pointer mov dpl0, r0 mov r2, #255 ;loop counter (511 bytes) orl perhiphen2, #1 ;enable fpi module mov fpiconfig, #3 ;en able writing in 16 bit ;mode ; set the address must be 16 bits (address / 2) clr c ;clear the carry flag mov a, r1 rrc a ;check if there will be a carry clr a ;does not affect carry bit rrc a ;sets a to 80h if r1 was odd, or ;keeps it 0 mov fpiadrl, a ;set lower address mov a, r1 rr a ;divide address by 2 add a, #7 ;adds e000h to the address ;(e000 / 2 = 7000) mov fpiadrh, a ; set upper address write_page_loop: mov fpidatal, #0aah ;unlock step 1 mov fpidatal, #055h ;unlock step 2 movx a, @dptr mov b, a inc dptr ;next byte movx a, @dptr inc dptr ;next byte mov fpidatah, a ;set the upper value mov fpidatal, b ;set the lower value ;and start the write write_page_loop_wait: mov a, fpiconfig ;check to see if the ;buffer is ready ;jump if fpi_ready is not high jnb acc.4 ,write_page_loop_wait djnz r2 ,write_page_loop ;now write the last word (byte 511 and 512) mov fpidatal, #0aah ;unlock step 1 mov fpidatal, #055h ;unlock step 2 movx a, @dptr mov b, a inc dptr ;next byte movx a, @dptr inc dptr ;next byte ;(not necessary) mov fpidatah, a ;set the upper value mov fpidatal, b ;set the lower value ;and start the write write_page_last_wait: mov a, fpiconfig ;check to see if the ;buffer is ready jump if fpi_idle is not high (last word) jnb acc.4 , write_page_last_wait ;restore variables used pop b pop acc mov r3, acc pop acc pop dpl0 pop dph0 ret ;return to caller vrs51l3xxx datasheet www.ramtron.com page 109 of 115 code example: fpi flash write, read, sector erase example //------------------------------------------------------------------------------------------------------------// // v2k_fpi_flash_wr_rd_serase_8bit_sdcc.c // ///------------------------------------------------------------------// // // description: vrs51l2070 / vrs51l3074 // fpi 8 bit write, 8 bit read & sector erase demonstration program. //------------------------------------------------------------------------------------------------------------// #include vrs51l3xxx datasheet www.ramtron.com page 110 of 115 18 external crystal by default, the vrs51l3xxx devices derive its clock from its internal 40mhz oscillator . it is also possible to use external crystal as device?s clock source. the crystal connected to the oscillator input should be parallel cut type, operating in fundamental mode. the addition of 15 to 20pf load capacitors is recommended. see the following figure for a connection diagram. note: oscillator circuits may differ with different crystals or ceramic resonators in higher oscillation frequency. crystals or ceramic resonator characteristics may also vary from one manufacturer to another. the user should review the technical literature associated with specific crystal or ceramic resonator or contact the manufacturer to select the appropriate values for the external components. f igure 51: vrs51l3 xxx e xternal c rystal o scillator configuration vrs51l3xxx xtal1 xtal2 xtal c1 c2 19 power-on reset time upon a power on reset, the start up time of the device is 46 to 52us vrs51l3xxx datasheet www.ramtron.com page 111 of 115 20 operating conditions 20.1 absolute maximum ratings parameter min. max. unit notes supply voltage input (vdd ? vss) 0 3.6 v i/o input voltage all except p4.6 & p4.7 -0.5v 5.5v v i/o input voltage p4.6 & p4.7 only vss-0.5 vcc+0.5 v maximum i/o current (sink/source) qfp-64 package 100 ma preliminary storage temperature -55 125 oc 20.2 nominal operating conditions t able 184: o perating c onditions symbol description min. typ. max. unit remarks ta operating temperature -40 +85 oc vccv supply voltage 3.0 3.3 3.6 v bov brown-out voltage 2.9 3.0 v fextosc 40 ext. oscillator frequency 0 - 40 mhz 4 40 mhz fextcy ext. crystal frequency 32 100 khz internal oscillator operating frequency 39.7 40 40.3 mhz at 25c internal oscillator temperature stability +/-2 % 0 to +70oc internal oscillator temperature stability +/- 3.25 % -40 to +85oc f-ram data retention 45 - - years f-ram byte write 1.1 us f-ram byte read 0.4 us flash endurance(erase / write cycles) 20k cycles flash data retention 100 years at room temperature flash page erase duration 20 ms flash byte/word programming time 20 us 20.3 dc characteristics vcc = 3.3v, temp = 25oc, no load on i/os t able 185: dc c haracteristics symbol parameter valid min. typ max. unit test conditions vil1 input low voltage p o r t 0 ,1,2,3,4,5,6 -0.35 0.80 v vcc=3.3v vil2 input low voltage reset, xtal1 -0.35 0.80 v vcc=3.3v vih1 input high voltage p o r t 0,1,2,3,4,5,6 2.0 5.5 v vcc=3.3v vi h2 input high voltage res, xtal1 2.0 5.5 v vcc=3.3v vol1 output low voltage p o r t 0 , 1,2,3,4,5,6,ale 0.4 v iol = rated i/o max current voh2 output high voltage p o r t 0 , 1,2,3,4,5,6,ale 2.4v vcc ? 0.3v v max rated i/o current ili input leakage current p o r t 0 , 1,2,3,4 10 ua (+/-) r res reset equivalent pull- up resistance res 74 104 177 kohm c - 10 pin capacitance 10 pf freq=1 mhz, ta=25 c 17 32 ma active mode, 40mhz (int. oscillator) 7.9 12 ma active mode, 10mhz (int. oscillator) 6.2 8.5 ma active mode 5 mhz (ext. crystal) ic c supply current vdd 3.6 11 ma idle mode, oscillator running 40mhz vrs51l3xxx datasheet www.ramtron.com page 112 of 115 20.4 timing requirement of the external clock the following diagram shows the timing of an external clock driving the vrs51l3xxx input. f igure 52: t iming r equirement of e xternal c lock (vss= 0.0v is assumed ) clkper clkhigh clkrt clkft clklow vdd - 0.5v 0.5v t able 186: e xternal c lock t iming requirements variable fosc symbol parameter min. typ max. unit clkper ext. clock period 25 ns clklow ext. clock low duration 12.5 ns clkhigh ext. clock high duration 12.5 ns clkft ext. clock fall time ns clkrt ext. clock rise time ns vrs51l3xxx datasheet www.ramtron.com page 113 of 115 21 vrs51l30xx qfp-64 package f igure 53: vrs51l30 xx qfp-64 p ackage drawings a2 a1 c e b 17 32 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 123456789101112131415 16 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 e1 d1 vrs51l30xx qfp-64 d e l d3 d1 d2 t able 187: d imensions of qfp-64 p ackages symbol description dimension (mm) tolerance (mm, o) / notes d footprint 17.2 +/- 0.25 d1 body size 14 +/- 0.10 e footprint 17.2 +/- 0.25 e1 body size 14 +/- 0.10 a1 stand-off 0.25 max a2 body thickness 2.00 l lead length 0.88 +0.15 / -0.10 b lead width 0.35 +/- 0.05 c l/c thickness 0.17 max e lead pitch 0.8 d1 body edge angle 10o d2 lead angle 6o +/- 4o d3 lead angle 0o to 7o vrs51l3xxx datasheet www.ramtron.com page 114 of 115 22 vrs51l31xx qfp-44 package f igure 54: vrs51l31 xx qfp-44 p ackage drawings a2 a1 c e b e1 d1 d e l d3 d1 d2 1 2 3 4 5 6 7 8 9 10 11 34 35 36 37 38 39 40 41 42 43 44 22 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 32 33 vrs51l31xx qfp-44 t able 188: d imensions of qfp-44 p ackages symbol description dimension (mm) tolerance (mm, o) / notes d footprint 13.2 +/- 0.25 d1 body size 10 +/- 0.10 e footprint 13.2 +/- 0.25 e1 body size 10 +/- 0.10 a1 stand-off 0.25 max a2 body thickness 2.00 l lead length 0.88 +0.15 / -0.10 b lead width 0.35 +/- 0.05 c l/c thickness 0.17 max e lead pitch 0.8 d1 body edge angle 10o d2 lead angle 6o +/- 4o d3 lead angle 0o to 7o vrs51l3xxx datasheet www.ramtron.com page 115 of 115 23 ordering information 23.1 device number structure 23.2 vrs51l3xxx orde ring options t able 189: vrs51l3 xxx 4 p art numbering device number flash size f-ram size sram size package option voltage temperature frequency vrs51l3074-40-qg 64kb 8kb 4352 qfp-64 3.0v to 3.6v -40c to +85c 40mhz vrs51l3072-40-qg 64kb 2kb 4352 qfp-64 3.0v to 3.6v -40c to +85c 40mhz vrs51l3174-40-qg 64kb 8kb 4352 qfp-44 3.0v to 3.6v -40c to +85c 40mhz VRS51L3172-40-QG 64kb 2kb 4352 qfp-44 3.0v to 3.6v -40c to +85c 40mhz errata: ? readback of the content in the thx/tlx and rcapxh/rc apxl timer registers will return to 0x00 unless the corresponding timer is running or, for the timers 0 and 1, the timer gating bit is set. ? there is a problem with the watchdog timer reset th at occurs when the vrs51l3xxx is running from an external crystal or an oscillator and the device have been programmed with clock divisor set to off in the device options settings of versa ware jtag. the work around this problem is simple: o program the device with clock divider set to either fosc/2, fosc/4 or fosc/8 o in the beginning of user code, add the line: devclkcfg = 0x00; disclaimers right to make change - ramtron reserves the right to make changes to its products - including circuitry, software a nd services - without notice at any time. customers should obtain the most current and relevant information before placing orders. use in applications - ramtron assumes no responsibility or liability for the use of any of its products, and conveys no license or title under any patent, copyright or mask work right to these products and makes no representations or warranties that these products are free from patent, copyright or mask work right infringement unless otherwise s pecified. customers are respons ible for product design and applicat ions using ramtron parts. ramtron assumes no liability for applicat ions assistance or customer product design. life support ? ramtron products are not designed for use in life support system s or devices. ramtron customer s using or selling ramtron?s products for use in such applications do so at their own risk and agree to fully indemnify ramtron for any damages resulting fr om such applications. i2c is a trademark of koninklijke philips electronics nv. |
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