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sii-ds-0070-b2 revision b2 june, 2003 sii3112a pci to serial ata controller msl tm technology datasheet silicon image, inc. 1060 e arques ave sunnyvale ca 94085 (408) 616-4000 www.s iliconimage.com
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 2 subject to change without notice copyright ? 2003, silicon image, inc. all rights reserved. no part of this publication maybe reproduced, transmitted, transcribed, or translated into any language or computer format, in any form or by any means without prior written permission of: silicon image, inc. 1060 e arques ave sunnyvale ca 94085, usa. silicon image, inc. reserves the right to make changes to the product(s) or specifications to improve performance, reliability, or manufacturability. information furnished is believed to be accurate and reliable, but silicon image, inc. will not be responsible for any errors that may appear in this document. silicon image, inc. makes no commitment to update or keep current the information contained in this document. however, no responsibility is assumed for its use; nor any infringement of patents or other rights of third parties which may result from its use. no liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. silicon image, inc. products are not designed or intended for use in life support systems. a life support system is a product or system intended to support or sustain life, which if it fails, can be reasonably expected to result in significant personal injury or death. if buyer or any of its direct or indirect customers applies any product purchased or licensed from silicon image, inc. to any such unauthorized use, buyer shall indemnify and hold silicon image, inc., its affiliates and their respective suppliers, harmless against all claims, costs, damages and expenses arising directly or indirectly, out of any such unintended or unauthorized use, even if such claims alleges that silicon image, inc. or any other person or entity was negligent in designing or manufacturing the product. specifications are subject to change without notice.
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 3 subject to change without notice table of contents 1 overview ....................................................................................................................... ............... 7 1.1 key benefits ................................................................................................................... .......................... 7 1.2 features....................................................................................................................... ............................. 7 1.2.1 overall features ............................................................................................................... ................................. 7 1.2.2 pci features................................................................................................................... ................................... 7 1.2.3 serial ata features ............................................................................................................ .............................. 7 1.2.4 other features................................................................................................................. .................................. 7 1.3 applications ................................................................................................................... .......................... 8 1.4 references ..................................................................................................................... .......................... 8 1.5 functional description......................................................................................................... ................... 8 1.6 functional block diagram ....................................................................................................... ............... 8 1.7 pci interface.................................................................................................................. ........................... 9 1.8 pci initialization ............................................................................................................. .......................... 9 1.9 pci bus operations ............................................................................................................. .................... 9 1.10 pci configuration space ........................................................................................................ .............. 10 1.11 deviations from the specification.............................................................................................. .......... 10 2 electrical characteristics..................................................................................................... ..... 11 2.1 device electrical characteristics .............................................................................................. ........... 11 2.2 sata interface timing specifications........................................................................................... ...... 12 2.3 sata interface transmitter output jitter characteristics ................................................................ 13 2.4 clki serdes reference clock input requirements........................................................................... 13 2.5 pci 33 mhz timing specifications ............................................................................................... ........ 13 2.6 pci 66 mhz timing specifications ............................................................................................... ........ 14 3 pin definition ................................................................................................................. ............ 15 3.1 sii3112a pin listing ........................................................................................................... ................... 15 3.2 sii3112a pin diagram ........................................................................................................... ................. 20 3.3 sii3112a pin descriptions ...................................................................................................... .............. 21 3.3.1 pci 66mhz 32-bit ............................................................................................................... ............................. 21 3.3.2 miscellaneous i/o .............................................................................................................. .............................. 23 3.3.3 serial ata signals............................................................................................................. .............................. 24 4 block diagram .................................................................................................................. ......... 27 5 auto-initialization ............................................................................................................ .......... 28 5.1 auto-initialization from flash................................................................................................. ............ 28 5.2 auto-initialization from eeprom ................................................................................................ ......... 29 6 ata command supported ........................................................................................................ 31 6.1 data modes ..................................................................................................................... ....................... 31 6.2 ata commands ................................................................................................................... .................. 31 7 power sequencing 1.8v and 3.3v supplies............................................................................. 34
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 4 subject to change without notice table of tables table 2-1 absolute maximum ratings............................................................................................ ........................................ 11 table 2-2 dc specifications .................................................................................................... ................................................ 11 table 2-3 sata interface dc specifications..................................................................................... ...................................... 12 table 2-4 sata interface timing specifications ................................................................................. .................................... 12 table 2-5 sata interface transmitter output jitter characteristics............................................................. ........................... 13 table 2-6 clki serdes reference clock input requirements ....................................................................... ........................ 13 table 2-7 pci 33 mhz timing specifications ..................................................................................... ..................................... 13 table 3-1 sii3112a pin listing ................................................................................................. ............................................... 18 table 3-2 pin types ............................................................................................................ .................................................... 19 table 5-1 auto-initialization from flash timing ................................................................................ ....................................... 28 table 5-2 flash data description ............................................................................................... ............................................. 29 table 5-3 auto-initialization from eeprom timing............................................................................... .................................. 30 table 5-4 auto-initialization from eeprom timing symbols....................................................................... ........................... 30 table 5-5 eeprom data description .............................................................................................. ....................................... 30 table 10-1 supported ata commands .............................................................................................. .................................... 31
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 5 subject to change without notice table of figures figure 1-1 : sii3112a block diagram ............................................................................................ ............................................ 8 figure 1-2: address lines during configuration cycle ........................................................................... ................................ 10 figure 3-1. sii3112a pin diagram............................................................................................... ............................................ 20 figure 3-2: package drawing ? 144 tqfp......................................................................................... ..................................... 26 figure 4-1: sii3112a block diagram ............................................................................................ .......................................... 27 figure 5-1 auto-initialization from flash timing ............................................................................... ....................................... 28
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 6 subject to change without notice revision history: version comment date rev. a first draft (derived from sii3112 data sheet) 7/23/02 rev. a1 changed absolute maximum rating voltage for vdddo, vddd and vddi - table 2-1 ? added vddd for the dc specification ? table 2-2 ? changed vddi (1.8 +/- 0.09 volt) form (1.8 +/- 0.2 volt) ? pin descriptions - 8/27/02 rev. a2 revised power supply current value added pin 4 description revised table 3-1 sii3112a pin listing 10/28/02 rev. a3 added table 2-3 sata interface dc specifications added table 2-4 sata interface timing specifications added table 2-5 sata interface transmitter output jitter characteristics added table 2-6 clki serdes reference clock input requirements removed section 2-7 power supply bypass considerations changed pin name for pin number 4 from scan_ck to nc 11/25/02 rev. b removed cleanupandrequestsense command code 13h in supported command list defined rj 250ui , dj 250ui in table 2-5 sata interface transmitter output jitter characteristics removed memory write and invalidate (memory write) support from pci bus target operations 1/15/03 rev. b1 removed writefpdmaqueued and readfpdmaqueued command from supported command list corrected inconsistence sentence (minor fixed including miss typing) 4/8/03 rev. b2 changed the rating for vin in table 2-1 absolute maxmum rating 6/30/03
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 7 subject to change without notice 1 overview the silicon image sii3112a is a single-chip solution for a pci to serial ata controller. it accepts host commands through the pci bus, processes them and transfers data between the host and serial ata devices. it can be used to control two independent serial ata channels. each channel has its own serial ata bus and will support one serial ata device. the sii3112a supports a 32-bit 66 mhz pci bus and the serial ata generation 1 transfer rate of 1.5 gb/s (150 mb/s). 1.1 key benefits the silicon image sii3112a pci to serial ata controller is the perfect single-chip solution for designs that need to accommodate storage peripherals with the new serial ata interface. any system with a pci bus interface can simply add the serial ata interface by adding a card with the sii3112a and loading the driver into the system. the sii3112a comes complete with drivers for windows 98, windows millennium, windows nt 4.0, windows 2000, xp, netware and linux. 1.2 features 1.2.1 overall features ? standalone pci to serial ata host controller chip ? compliant with pci specification, revision 2.2. ? compliant with programming interface for bus master ide controller, revision 1.0. ? driver support for win98, winme, nt4, win2k, xp, netware and linux ? supports up to 4mbit external flash or eprom for bios expansion. ? supports an external eeprom, flash or eprom for programmable device id, subsystem vendor id, subsystem product id and pci sub-class code. ? supports the silicon image specific driver for special chip functions. ? fabricated in a 0.18 cmos process with a 1.8 volt core and 3.3 volt (5v tolerant) i/os. ? supports plug and play ? supports sata active signal for led implementation ? available in a 144-pin tqfp package. 1.2.2 pci features ? supports 66 mhz pci with 32-bit data. ? supports pci perr and serr reporting. ? supports pci bus master operations: memory read, memory read multiple, and memory write. ? supports pci bus target operations: configuration read, configuration write, i/o read, i/o write, memory read, memory write, memory read line (memory read) and memory read multiple (memory read) ? supports byte alignment for odd-byte pci address access. ? supports jumper configurable pci class code. ? supports programmable and eeprom, flash and eprom loadable pci class code. ? supports base address register 5 in memory space. 1.2.3 serial ata features ? integrated serial ata link and phy logic ? compliant with serial ata 1.0 specifications ? supports two independent serial ata channels. ? supports serial ata generation 1 transfer rate of 1.5gb/s. ? supports spread spectrum in receiver ? single pll architecture, 1 pll for both ports ? programmable drive strengths for backplane applications 1.2.4 other features ? features independent 256-byte fifos (32-bit x 64 deep) per serial ata channel for host reads and writes. ? features serial ata to pci interrupt masking. ? features watch dog timer for fault resiliency.
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 8 subject to change without notice 1.3 applications ? pc motherboards ? serial ata drive add on cards ? serial ata raid controllers 1.4 references for more details about the serial ata technology, the reader is referred to the following industry specifications: ? serial ata / high speed serialized at attachment specification, revision 1.0 ? pci local bus specification revision 2.2 ? advanced power management specification revision 1.0 ? pci ide controller specification revision 1.0 ? programming interface for bus master ide controller, revision 1.0 1.5 functional description sii3112a is a pci-to-serial ata controller chip that transfers data between the pci bus and storage media (e.g. hard disk drive, etc). the sii3112a consists of the following functional blocks: ? pci interface. provides the interface to any system that has a pci bus. instructions and system clocks are based on this interface. ? serial ata interface. two separate channels (primary and secondary) to access storage media such as hard disk drive, floppy disk drive, cd-rom. 1.6 functional block diagram figure 1-1 : sii3112a block diagram sataclkin pci interface host transport link sdif phy pll ref fb txclk host transport link sdif phy fifo ring buffer host ata interface host ata interface ata interface fifo ring buffer ata interface pciclkin pciclk (33~66 mhz) pciclk (33~66 mhz) 1.5 gbs serial interface 1.5 gbs serial interface txclk pci i/f sataclkin pci interface host transport link sdif phy pll ref fb txclk host transport link sdif phy fifo ring buffer host ata interface host ata interface ata interface fifo ring buffer ata interface pciclkin pciclk (33~66 mhz) pciclk (33~66 mhz) 1.5 gbs serial interface 1.5 gbs serial interface txclk pci i/f
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 9 subject to change without notice 1.7 pci interface the sii3112a pci interface is compliant with the pci local bus specification (revision 2.2). the sii3112a can act as a pci master and a pci slave, and contains the sii3112a pci configuration space and internal registers. when the sii3112a needs to access shared memory, it becomes the bus master of the pci bus and completes the memory cycle without external intervention. in the mode when it acts as a bridge between the pci bus and the serial ata bus it will behave as a pci slave. 1.8 pci initialization generally, when a system initializes a module containing a pci device, the configuration manager reads the configuration space of each pci device on the pci bus. hardware signals select a specific pci device based on a bus number, a slot number, and a function number. if a device that is addressed (via signal lines) responds to the configuration cycle by claiming the bus, then that function's configuration space is read out from the device during the cycle. since any pci device can be a multifunction device, every supported function's configuration space needs to be read from the device. based on the information read, the configuration manager will assign system resources to each supported function within the device. sometimes new information needs to be written into the function's configuration space. this is accomplished with a configuration write cycle. 1.9 pci bus operations sii3112a behaves either as a pci master or a pci slave device at any time and switches between these modes as required during device operation. as a pci slave, the sii3112a responds to the following pci bus operations: ? i/o read ? i/o write ? configuration read ? configuration write ? memory read ? memory write all other pci cycles are ignored by the sii3112a. as a pci master, the sii3112a generates the following pci bus operations: ? memory read multiple ? memory read ? memory write
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 10 subject to change without notice 1.10 pci configuration space this section describes how the sii3112a implements the required pci configuration register space. the intent of pci configuration space definition is to provide an appropriate set of configuration registers that satisfy the needs of current an d anticipated system configuration mechanisms, without specifying those mechanisms or otherwise placing constraints on their use. these registers allow for: ? full device relocation (including interrupt binding) ? installation, configurations, and booting without user interventions ? system address map construction by device-independent software figure 1-2: address lines during configuration cycle sii3112a only responds to type 0 configuration cycles. type 1 cycles, which pass a configuration request on to another pci bus, are ignored. the address phase during a sii3112a configuration cycle indicates the function number and register number being addressed which can be decoded by observing the status of the address lines ad[31:0]. the value of the signal lines ad[7:2] during the address phase of configuration cycles selects the register of the configuratio n space to access. valid values are between 0 and 15, inclusive. accessing registers outside this range results in an all-0s value being returned on reads, and no action being taken on writes. the class code register contains the class code, sub-class code, and register-level programming interface registers. all writable bits in the configuration space are reset to 0 by the hardware reset, pci reset (rst#) asserted. after reset, sii3112a is disabled and will only respond to pci configuration write and pci configuration read cycles. 1.11 deviations from the specification the sii3112a product has been developed and tested to the specification listed in this document. as a result of testing and customer feedback, we may become aware of deviations to the specification that could affect the component's operation. to ensure awareness of these deviations by anyone considering the use of the sii3112a, we have included an errata section at the end of this specification. please ensure that the errata section is carefully reviewed. it is also important that you have the most current version of this specification. if there are any questions, please contact silicon image, inc. 31 11 10 8 7 2 1 0 bit number don?t care bit number 3-bit function number 6-bit register number 2-bit type number
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 11 subject to change without notice 2 electrical characteristics 2.1 device electrical characteristics specifications are for commercial temperature range, 0 o c to +70 o c, unless otherwise specified. symbol parameter ratings unit vddo i/o supply voltage 4.0 v vddi, vddd analog supply voltage digital supply voltage 2.15 v v in input voltage -0.3 ~ vdd+0.3 v i out dc output current 16 ma ja thermal resistance (junction to ambient) 39 c/w t stg storage temperature -65 ~ 150 o c table 2-1 absolute maximum ratings limits symbol parameter condition type min typ max unit vddi , vddd supply voltage (digital, analog) 1.71 1.8 1.89 v vddo supply voltage(i/o) - - 3.0 3.3 3.6 v idd 1.8v 1.8v supply current 236 1 285 2 ma idd 3.3v 3.3v supply current c load = 20pf 12 1 30 2 ma - 3.3v pci 0.5xvdd - - v ih input high voltage - non-pci 2.0 - - v - 3.3v pci - - 0.3xvdd v il input low voltage - non-pci - - 0.8 v v+ input high voltage - schmitt - 1.8 2.3 v v- input low voltage - schmitt 0.5 0.9 - v v h hysteresis voltage - schmitt 0.4 - - v i ih input high current v in = vdd - -10 - 10 a i il input low current v in = vss - -10 - 10 a v oh output high voltage - - 2.4 - - v v ol output low voltage - - - - 0.4 v i oz 3-state leakage current - - -10 - 10 a notes: 1 using the random data pattern (read/write operation) at 1.8v or 3.3v power supply, pci interface = 33mhz 2 using the maximum toggling data pattern (read/write operation) at 1.89v or 3.6v power supply , pci interface = 66mhz table 2-2 dc specifications
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 12 subject to change without notice limits symbol parameter condition min typ max unit v dout tx+/tx- differential peak-to- peak voltage swing. terminated by 50 ohms. tx swing value = 00 400 500 600 mv v din rx+/rx- differential peak-to- peak input sensitivity 325 mv v dih rx+/rx- differential input common-mode voltage 200 300 450 mv v doh tx+/tx-differential output common-mode voltage 200 300 450 mv z din differential input impedance rext = 1k 1% for 25mhz serdes ref clk rext = 4.99k 1% for 100mhz serdes ref clk 85 100 115 ohms z dout differential output impedance rext = 1k 1% for 25mhz serdes ref clk rext = 4.99k 1% for 100mhz serdes ref clk 85 100 115 ohms table 2-3 sata interface dc specifications 2.2 sata interface timing specifications limits symbol parameter condition min typ max unit t tx_rise_fall rise and fall time at transmitter 20%-80% 133 274 ps t tx_skew tx differential skew 20 ps t tx_dc_freq tx dc clock frequency skew -350 +350 ppm t tx_ac_freq tx ac clock frequency skew serdes ref clk = ssc ac modulation, subject to the "downspread ssc" triangular modulation (30- 33khz) profile per 6.6.4.5 in sata 1.0 specification -5000 +0 ppm table 2-4 sata interface timing specifications
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 13 subject to change without notice 2.3 sata interface transmitter output jitter characteristics limits symbol parameter condition min typ max unit rj 5ui 5ui later random jitter measured at tx output pins 1sigma deviation 3.6 ps rms rj 250ui 250ui later random jitter measured at tx output pins 1sigma deviation 4.7 ps rms dj 5ui 5ui later deterministic jitter measured at tx output pins peak to peak phase variation random data pattern 20 ps dj 250ui 250ui later deterministic jitter measured at tx output pins peak to peak phase variation random data pattern 25 ps table 2-5 sata interface transmitter output jitter characteristics 2.4 clki serdes reference clock input requirements limits symbol parameter condition min typ max unit t clki_freq norminal frequency rext = 1k 1% rext = 4.99k 1% 25 100 mhz t clki_j clki frequency tolerance -100 +100 ppm t clki_rise_fall rise and fall time at clki 25mhz reference clock, 20%-80% 100mhz reference clock, 20%-80% 4 2 ns t clki_rc_duty clki duty cycle 20%-80% 40 60 % table 2-6 clki serdes reference clock input requirements 2.5 pci 33 mhz timing specifications limits symbol parameter min max unit t val clk to signal valid ? bussed signals 2.0 11.0 ns t val (ptp) clk to signal valid ? point to point 2.0 11.0 ns t on float to active delay 2.0 - ns t off active to float delay - 28.0 ns t su input setup time ? bussed signals 7.0 - ns t su (ptp) input setup time ? point to point 10.0 - ns t h input hold time 0.0 - ns table 2-7 pci 33 mhz timing specifications
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 14 subject to change without notice 2.6 pci 66 mhz timing specifications limits symbol parameter min max unit t val clk to signal valid ? bussed signals 2.0 6.0 ns t val (ptp) clk to signal valid ? point to point 2.0 6.0 ns t on float to active delay 2.0 ns t off active to float delay 14.0 ns t su input setup time ? bussed signals 3.0 ns t su (ptp) input setup time ? point to point 5.0 ns t h input hold time 0.0 ns table 2-8 pci 66 mhz timing specifications
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 15 subject to change without notice 3 pin definition 3.1 sii3112a pin listing this section describes the pin-out of the sii3112a pci-to-serial ata host controller. table 3-1 gives the pin numbers, pin names, pin types, drive types where applicable, internal resistors where applicable, and descriptions. pin # pin name type drive internal resistor description 1 vss gnd - - ground 2 scan_en i - pd ? 60k internal scan enable 3 vddo pwr 3.3power 4 nc 5 gndd gnd - - digital ground 6 vddd pwr - - 1.8v serdes power 7 gndd gnd - - digital ground 8 gnda gnd - - analog ground 9 rxp2 i channel 2 differential receive +ve 10 rxn2 i channel 2 differential receive -ve 11 gnda gnd - - analog ground 12 vddd pwr - - 1.8v serdes power 13 gndd gnd - - digital ground 14 gnda gnd - - analog ground 15 txn2 o channel 2 differential transmit -ve 16 txp2 o channel 2 differential transmit +ve 17 gnda gnd - - analog ground 18 gndd gnd - - digital ground 19 vddd pwr - - 1.8v serdes power 20 gndd gnd - - digital ground 21 gnda gnd - - analog ground 22 txp1 o channel 1 differential transmit +ve 23 txn1 o channel 1 differential transmit -ve 24 gnda gnd - - analog ground 25 vddd pwr - - 1.8v serdes power 26 gndd gnd - - digital ground 27 gnda gnd - - analog ground 28 rxn1 i channel 1 differential receive -ve 29 rxp1 i channel 1 differential receive +ve 30 gnda gnd - - analog ground 31 gndd gnd - - digital ground 32 vddd pwr - - 1.8v serdes power
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 16 subject to change without notice pin # pin name type drive internal resistor description 33 rext i external reference resistor input 34 gnda gnd - - analog ground 35 xtali/clki i crystal oscillator input or external clock input 36 xtalo o crystal oscillator output 37 vddo pwr 3.3v supply for crystal oscillator 38 vss gnd - - ground 39 vddi pwr - - 1.8v volt internal core power 40 eeprom_sdat i/o pu ? 70k eeprom serial data 41 eeprom_sclk i/o pu ? 70k eeprom serial clock 42 fl_addr[00] / ide_cfg i/o pu ? 70k flash memory address 0 / ide-raid configuration 43 fl_addr[01] / ba5_en i/o pu ? 70k flash memory address 1 / base address register 5 enable 44 fl_addr[02] o flash memory address 2 45 fl_wr_n o - flash memory write strobe 46 vddo pwr - - 3.3 volt power 47 vss gnd - - ground 48 fl_rd_n o - flash memory read strobe 49 fl_addr[03] o flash memory address 3 50 fl_addr[04] o flash memory address 4 51 fl_addr[05] o flash memory address 5 52 fl_addr[06] o flash memory address 6 53 fl_addr[07] o flash memory address 7 54 fl_addr[08] o flash memory address 8 55 fl_addr[09] o flash memory address 9 56 vddi pwr - - 1.8v internal core power 57 vss gnd - - ground 58 fl_addr[10] o flash memory address 10 59 fl_addr[11] o flash memory address 11 60 fl_addr[12] o flash memory address 12 61 fl_addr[13] o flash memory address 13 62 fl_addr[14] o flash memory address 14 63 fl_addr[15] o pu ? 70k flash memory address 15 64 fl_addr[16] o pu ? 70k flash memory address 16 65 fl_addr[17] o pu ? 70k flash memory address 17 66 fl_addr[18] o pu ? 70k flash memory address 18 67 test_mode i - pd ? 60k test mode enable 68 fl_data[00] i/o pu ? 70k flash memory data 0 69 fl_data[01] i/o pu ? 70k flash memory data 1 70 fl_data[02] i/o pu ? 70k flash memory data 2
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 17 subject to change without notice pin # pin name type drive internal resistor description 71 fl_data[03] i/o pu ? 70k flash memory data 3 72 vddo pwr - - 3.3 volt power 73 vss gnd - - ground 74 fl_data[04] i/o pu ? 70k flash memory data 4 75 fl_data[05] i/o pu ? 70k flash memory data 5 76 fl_data[06] i/o pu ? 70k flash memory data 6 77 fl_data[07] i/o pu ? 70k flash memory data 7 78 vss gnd - - ground 79 vddi pwr - - 1.8v internal core power 80 vss gnd - - ground 81 vddi pwr - - 1.8v internal core power 82 pci_inta_n od pci - pci interrupt 83 pci_rst_n i-schmitt - - pci reset 84 pci_clk i - - pci clock 85 pci_gnt_n i - - pci bus grant 86 pci_req_n t pci - pci bus request 87 vddo pwr - - 3.3 volt power 88 vss gnd - - ground 89 pci_ad31 i/o pci - pci address/data 90 pci_ad30 i/o pci - pci address/data 91 pci_ad29 i/o pci - pci address/data 92 pci_ad28 i/o pci - pci address/data 93 pci_ad27 i/o pci - pci address/data 94 pci_ad26 i/o pci - pci address/data 95 pci_ad25 i/o pci - pci address/data 96 pci_ad24 i/o pci - pci address/data 97 pci_cbe3 i/o pci - pci command/byte enable 98 vddi pwr - - 1.8 volt core power 99 vss gnd - - ground 100 pci_idsel i - - pci id select 101 pci_ad23 i/o pci - pci address/data 102 pci_ad22 i/o pci - pci address/data 103 pci_ad21 i/o pci - pci address/data 104 pci_ad20 i/o pci - pci address/data 105 pci_ad19 i/o pci - pci address/data 106 pci_ad18 i/o pci - pci address/data 107 pci_ad17 i/o pci - pci address/data 108 vddo pwr - - 3.3 volt power 109 vss gnd - - ground 110 pci_ad16 i/o pci - pci address/data
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 18 subject to change without notice pin # pin name type drive internal resistor description 111 pci_cbe2 i/o pci - pci command/byte enable 112 pci_frame_n i/o pci - pci frame 113 pci_irdy_n i/o pci - pci initiator ready 114 pci_perr_n i/o pci - pci parity error 115 pci_stop_n i/o pci - pci stop 116 pci_devsel_n i/o pci - pci device select 117 pci_trdy_n i/o pci - pci target ready 118 vddi pwr - - 1.8 volt core power 119 vss gnd - - ground 120 pci_serr_n od pci - pci system error 121 pci_par i/o pci - pci parity 122 pci_cbe1 i/o pci - pci command/byte enable 123 pci_ad15 i/o pci - pci address/data 124 pci_ad14 i/o pci - pci address/data 125 pci_ad13 i/o pci - pci address/data 126 pci_ad12 i/o pci - pci address/data 127 pci_ad11 i/o pci - pci address/data 128 vddo pwr - - 3.3 volt power 129 vss gnd - - ground 130 pci_ad10 i/o pci - pci address/data 131 pci_m66en i - - pci 66 mhz enable 132 pci_ad09 i/o pci - pci address/data 133 pci_ad08 i/o pci - pci address/data 134 pci_cbe0 i/o pci - pci command/byte enable 135 pci_ad07 i/o pci - pci address/data 136 pci_ad06 i/o pci - pci address/data 137 pci_ad05 i/o pci - pci address/data 138 pci_ad04 i/o pci - pci address/data 139 pci_ad03 i/o pci - pci address/data 140 pci_ad02 i/o pci - pci address/data 141 pci_ad01 i/o pci - pci address/data 142 pci_ad00 i/o pci - pci address/data 143 mem_cs_n o - memory chip select 144 vddo pwr - - 3.3 volt power table 3-1 sii3112a pin listing
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 19 subject to change without notice pin type pin description i input pin with lv ttl thresholds i-schmitt input pin with schmitt trigger o output pin t tri-state output pin i/o bi-directional pin od open drain output pin table 3-2 pin types pci pins are 5v tolerant.
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 20 subject to change without notice 3.2 sii3112a pin diagram figure 3-1. sii3112a pin diagram
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 21 subject to change without notice 3.3 sii3112a pin descriptions 3.3.1 pci 66mhz 32-bit pci address and data pin names: pci_ad[31..0] pin numbers: 89~96, 101~107, 110, 123~127,132, 133, 135~142 address and data buses are multiplexed on the same pci pins. a bus transaction consists of an address phase followed by one or more data phases. pci supports both read and write bursts. the address phase is the first clock cycle in which pci_frame_n signal is asserted. during the address phase, pci_ad[31:0] contain a physical address (32 bits). for i/o, this can be a byte address. for configuration and memory it is a dword address. during data phases, pci_ad[7:0] contain the least significant byte (lsb) and pci_ad[31:24] contain the most significant byte (msb). write data is stable and valid when pci_irdy_n is asserted; read data is stable and valid when pci_trdy_n is asserted. data is transferred during those clocks where both pci_irdy_n and pci_trdy_n are asserted. pci command and byte enables pin names: pci_cbe[3..0] pin numbers: 97, 111, 122, 134 command and byte enables are multiplexed on the same pci pins. during the address phase of a transaction, pci_cbe[3:0]_n define the bus command. during the data phase, pci_cbe[3:0]_n are used as byte enables. byte enables are valid for the entire data phase and determine which byte lanes carry meaningful data. pci id select pin name: pci_idsel pin number: 100 this signal is used as a chip select during configuration read and write transactions. pci frame cycle pin name: pci_frame_n pin number: 112 cycle frame is driven by the current master to indicate the beginning and duration of an access. pci_frame_n is asserted to indicate that a bus transaction is beginning. while pci_frame_n is asserted, data transfers continue. when pci_frame_n is de-asserted, the transaction is in the final data phase or has completed. pci initiator ready pin name: pci_irdy_n pin number: 113 initiator ready indicates the initializing agent?s (bus master?s) ability to complete the current data phase of the transaction . this signal is used with pci_trdy_n. a data phase is completed on any clock when both pci_irdy_n and pci_trdy_n are sampled as asserted. wait cycles are inserted until both pci_irdy_n and pci_trdy_n are asserted together. pci target ready pin name: pci_trdy_n pin number: 117 target ready indicates the target agent?s ability to complete the current data phase of the transaction. pci_trdy_n is used with pci_irdy_n. a data phase is completed on any clock when both pci_trdy_n and pci_irdy_n are sampled asserted. during a read, pci_trdy_n indicates that valid data is present on pci_ad[31:0]. during a write, it indicates the target is prepared to accept data. pci device select pin name: pci_devsel_n
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 22 subject to change without notice pin number: 116 device select, when actively driven, indicates the driving device has decoded its address as the target of the current access. as an input, pci_devsel_n indicates to a master whether any device on the bus has been selected. pci stop pin name: pci_stop_n pin number: 115 pci_stop_n indicates the current target is requesting that the master stop the current transaction. pci parity error pin name: pci_perr_n pin number: 114 pci_perr_n indicates a data parity error between the current master and target on pci. on a write transaction, the target always signals data parity errors back to the master on pci_perr_n. on a read transaction, the master asserts pci_perr_n to indicate to the system that an error was detected. pci system error pin name: pci_serr_n pin number: 120 system error is for reporting address parity errors, data parity errors on special cycle command, or any other system error where the result will be catastrophic. the pci_serr_n is a pure open drain and is actively driven for a single pci clock by the agent reporting the error. the assertion of pci_serr_n is synchronous to the clock and meets the setup and hold times of all bused signals. however, the restoring of pci_serr_n to the de-asserted state is accomplished by a weak pull-up. note that if an agent does not want a non-maskable interrupt (nmi) to be generated, a different reporting mechanism is required. pci parity pin name: pci_par pin number: 121 pci_par is even parity across pci_ad[31:0] and pci_cbe[3:0]_n. parity generation is required by all pci agents. pci_par is stable and valid one clock after the address phase. for data phases pci_par is stable and valid one clock after either pci_irdy_n is asserted on a write transaction or pci_trdy_n is asserted on a read transaction. once pci_par is valid, it remains valid until one clock after the completion of the current data phase. (pci_par has the same timing as pci_ad[31:0] but delayed by one clock.) pci request pin name: pci_req_n pin number: 86 this signal indicates to the arbiter that this agent desires use of the pci bus. pci grant pin name: pci_gnt_n pin number: 85 this signal indicates to the agent that access to the pci bus has been granted. in response to a pci request, this is a point- to-point signal. every master has its own pci_gnt_n, which must be ignored while pci_rst_n is asserted. pci interrupt a pin name: pci_inta_n pin number: 82 interrupt a is used to request an interrupt on the pci bus. pci_inta_n is open collector and is an open drain output.
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 23 subject to change without notice pci clock signal pin names: pci_clk pin number: 84 clock signal provides timing for all transactions on pci and is an input to every pci device. all other pci signals (except pci_rst_n, and pci_inta_n) are sampled on the rising edge of pci_clk. all other timing parameters are defined with respect to this edge. pci reset pin name: pci_rst_n pin number: 83 pci_rst_n is an active low input that is used to set the internal registers to their initial state. pci_rst_n is typically the system power-on reset signal as distributed on the pci bus. pci m66en pin name: pci_m66en pin number: 131 this pin configures the pci bus operating frequency. when low, the pci bus operates from 0 to 33 mhz. when high, the pci bus operates from 33mhz to 66mhz. 3.3.2 miscellaneous i/o ground pin name: vss pin number: 1, 38, 47, 57, 73, 78, 80, 88, 99, 109,119, 129 ground reference point to power supply. test pin name: test_mode pin number: 67 this pin is used, in conjunction with other pins, to enable various test functions within the device. power supply pin name(s): vddo pin number(s): 3, 37, 46, 72, 87, 108, 128, 144 power supply input (3.3 +/- 0.3 volt) pin name(s): vddi pin number(s): 39, 56, 79, 81, 98, 118 power supply input for internal core (1.8 +/- 0.09 volt) internal scan test pin name: scan_en pin number: 2 this pin, when active (high), will place all scan flip-flops into scan mode for chip testing. this pin must be left open or tie d to ground for normal operation.
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 24 subject to change without notice flash signals pin name: fl_addr[00] / ide_cfg pin number: 42 when pci_rst_n is deasserted, this pin is an output and represents flash memory address bit 0 during reset, it is sampled to configure mass storage class or raid mode in the pci class code register. a high on this pin sets mass storage class, a low sets raid mode. the configuration state is latched internally when pci_rst_n is deasserted. this pad is internally pulled high to enable mass storage class if left unconnected. pin name: fl_addr[01] / ba5_en pin number: 43 when pci_rst_n is deasserted, this pin is an output and represents flash memory address bit 1 during reset, it is sampled to configure base address register 5. a high on this pin enables base address register 5, a low disables base address register 5. the configuration state is latched internally when pci_rst_n is deasserted. this pin is internally pulled high to enable base address register 5 when left unconnected. pin name: fl_addr[02-18] pin numbers: 44, 49~55, 58~66 flash memory address bits; 19 total for 512k address space. flash address pins 15 to 18 are used to select internal test modes in conjunction with the test_mode pin; they have internal pull-downs and must be unconnected or pulled down. pin name: fl_data[00-07] pin numbers: 68~71, 74~77 8-bit flash memory data bus. pin name: fl_rd_n pin number: 48 flash read enable signal, active low pin name: fl_wr_n pin number: 45 flash write enable signal, active low memory chip select pin name: mem_cs_n pin number: 143 this pin is used to select and enable the external memory. it is active low. serial interface signals pin name: eeprom_sdat pin number: 40 serial interface data line pin name: eeprom_sclk pin number: 41 serial interface clock 3.3.3 serial ata signals power supply & ground pin name: vddd pin numbers: 6, 12, 19, 25, and 32 serdes 1.8 v power supply pins pin name: gndd pin numbers: 5, 7, 13, 18, 20, 26, and 31 serdes digital ground pin name: gnda pin numbers: 8, 11, 14, 17, 21, 24, 27, 30, and 34 serdes analog ground
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 25 subject to change without notice high speed serial signals pin name: rxn1 pin number: 28 channel 1 high-speed differential receive negative side. pin name: rxp1 pin number: 29 channel 1 high-speed differential receive positive side. loading an internal register through the flash or eeprom during the initialization sequence could reverse rxp1 and rxn1 pinouts. pin name: txn1 pin number: 23 channel 1 high speed differential transmit negative side pin name: txp1 pin number: 22 channel 1 high speed differential transmit positive side pin name: rxn2 pin number: 10 channel 2 high-speed differential receive negative side. pin name: rxp2 pin number: 9 channel 2 high-speed differential receive positive side. loading an internal register through the flash or eeprom during the initialization sequence could reverse rxp2 and rxn2 pinouts. pin name: txn2 pin number: 15 channel 2 high speed differential transmit negative side pin name: txp2 pin number: 16 channel 2 high speed differential transmit positive side other serdes signals pin name: xtalo pin number: 36 crystal oscillator pin for serdes reference clock. a 25mhz crystal must be used. pin name: xtali/clki pin number: 35 crystal oscillator pin for serdes reference clock. when external clock source is selected, the external clock (either 25mhz or 100 mhz) will come in through this pin. the clock precision requirement is 100ppm. pin name: rext pin number: 33 external reference resistor pin for termination calibration. this pin provides the addition function of selecting frequency of the clock source . for 25mhz crystal/external clock, a 1k, 1% resistor is connected to ground. to use 100mhz external clock, a 4.99k, 1% resistor is connected to ground.
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 26 subject to change without notice package drawing figure 3-2: package drawing ? 144 tqfp
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 27 subject to change without notice 4 block diagram the sii3112a contains the major logic modules shown below. pci interface serial ata channel #0 serial ata channel #1 pci dma engine arbiter data fifo data fifo flash & eeprom interface bus interface pci dma engine bus interface figure 4-1: sii3112a block diagram
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 28 subject to change without notice 5 auto-initialization the sii3112a supports an external flash and/or eeprom device for bios extensions and user-defined pci configuration header data. 5.1 auto-initialization from flash the sii3112a initiates the flash detection and configuration space loading sequence upon the release of pci_rst_n. it begins by reading the highest two addresses (7ffff h and 7fffe h ), checking for the correct data signature pattern ? aa h and 55 h , respectively. if the data signature pattern is correct, the sii3112a continues to sequence the address downward, reading a total of sixteen bytes. if the data signature is correct (55 h at 7fffc h ), the last twelve bytes are loaded into the pci configuration space registers. note: if both flash and eeprom are installed, the pci configuration space registers will be loaded with eeprom?s data. while the sequence is active, the sii3112a responds to all pci bus accesses with a target retry. d15 d14 d05 d04 d03 d02 d01 d00 mem_addr mem_addr mem_data mem_rd_n mem_wr_n mem_cs_n pci_rst_n t 1 t 2 7ffff 7fffe 7fffd 7fffc 7fffb 7fffa 7fff1 7fff0 figure 5-1 auto-initialization from flash timing parameter value description t 1 660 ns pci reset to flash auto-initialization cycle begin t 2 9600 ns flash auto-initialization cycle time table 5-1 auto-initialization from flash timing
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 29 subject to change without notice address data byte description 7ffff h d00 data signature = aa h 7fffe h d01 data signature = 55 h 7fffd h d02 aa = 120 ns flash device / else, 240 ns flash device 7fffc h d03 data signature = 55 h 7fffb h d04 pci device id [23:16] 7fffa h d05 pci device id [31:24] 7fff9 h d06 pci class code [15:08] 7fff8 h d07 pci class code [23:16] 7fff7 h d08 pci sub-system vendor id [07:00] 7fff6 h d09 pci sub-system vendor id [15:08] 7fff5 h d10 pci sub-system id [23:16] 7fff4 h d11 pci sub-system id [31:24] 7fff3 h d12 serialata phy config [07:00] (default: 0xf1) 7fff2 h d13 serialata phy config [15:08] (default: 0x80) 7fff1 h d14 serialata phy config [23:16] (default: 0x00) 7fff0 h d15 serialata phy config [31:24] (default: 0x00) table 5-2 flash data description 5.2 auto-initialization from eeprom the sii3112a initiates the eeprom detection and configuration space loading sequence after the flash read sequence. the sii3112a supports up to 256 byte eeprom with a 2-wire serial interface. the sequence of operations consists of the following. 1) start condition defined as a high-to-low transition on sdat while sclk is high. 2) control byte = 1010 (control code) + 000 (chip select) + 0 (write address) 3) acknowledge 4) starting address field = 00000000. 5) acknowledge 6) sequential data bytes separated by acknowledges. 7) stop condition. while the sequence is active, the sii3112a responds to all pci bus accesses with a target retry. mem_cs_n sclk sdat t 1 t 2 s1010000 w p an ddd t 3 figure 5-2: auto-initialization from eeprom timing
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 30 subject to change without notice parameter value description t 1 26.00 s end of auto-initialization from flash to start of auto-initialization from eeprom t 2 2.66 ms auto-initialization from eeprom cycle time t 3 19.26 s eeprom serial clock period table 5-3 auto-initialization from eeprom timing parameter description s start condition w r/w 0 = write command, 1 = read command a acknowledge d serial data n no-acknowledge p stop condition table 5-4 auto-initialization from eeprom timing symbols address data byte description 00 h d00 memory present pattern = aa h 01 h d01 memory present pattern = 55 h 02 h d02 data signature = aa h 03 h d03 data signature = 55 h 04 h d04 pci device id [23:16] 05 h d05 pci device id [31:24] 06 h d06 pci class code [15:08] 07 h d07 pci class code [23:16] 08 h d08 pci sub-system vendor id [07:00] 09 h d09 pci sub-system vendor id [15:08] 0a h d10 pci sub-system id [23:16] 0b h d11 pci sub-system id [31:24] 0c h d12 serialata phy config [07:00] (default: 0xf1) 0d h d13 serialata phy config [15:08] (default: 0x80) 0e h d14 serialata phy config [23:16] (default: 0x00) 0f h d15 serialata phy config [31:24] (default: 0x00) table 5-5 eeprom data description
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 31 subject to change without notice 6 ata command supported 6.1 data modes the sii3112a pci to serial ata controller has an internal datapath interface between the pci block and the serial ata controller block. the data modes (register mode, pio mode and dma mode) are of no significance inside the sii3112a. 6.2 ata commands the sii3112a pci to serial ata controller decodes ata commands in hardware. the commands supported include ata/atapi-5 and ata/atapi-6 commands, including the 48-bit lba extended commands. certain obsolesced commands are also supported. the supported commands are listed below: table 10-1 supported ata commands command command/ features codes comment cfa erase sectors c0h cfa request extended error code 03h cfa translate sector 87h cfa write multiple without erase cdh cfa write sectors without erase 38h check media card type d1h check power mode e5h configure stream 51h device configuration freeze lock b1h/c1h device configuration identify b1h/c2h device configuration restore b1h/c0h device configuration set b1h/c3h device reset 08h download microcode 92h execute device diagnostics 90h the two serial ata ports for sii3112a pci to serial ata controller are both "single masters". flush cache e7h flush cache ext eah 48-bit lba command format track 50h obsolesced vendor specific command, needs to be programmed as vendor specific commands get media status dah identify device ech
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 32 subject to change without notice command command/ features codes comment identify packet device a1h idle e3h idle immediate e1h initialize device parameters 91h obsolesced in ata/atapi-6. media eject edh media lock deh media unlock dfh nop 00h packet a0h read buffer e4h c8h read dma c9h obsolesced command code supported, decoded as command code c8h read dma ext 25h 48-bit lba command read dma queued c7h read dma queued ext 26h 48-bit lba command read log ext 2fh 22h read long 23h obsolesced command read multiple c4h read multiple ext 29h 48-bit lba command read native max address f8h read native max address ext 27h 48-bit lba command 20h read sector(s) 21h obsolesced command code supported, decoded as command code 20h read sector(s) ext 24h 48-bit lba command read stream dma 2a read stream pio 2b 40h read verify sector(s) 41h obsolesced command code supported, decoded as command code 40h read verify sector(s) ext 42h 48-bit lba command recalibrate 10h obsolesced command supported. security disable password f6h security erase prepare f3h security erase unit f4h security freeze lock f5h
sii3112a data sheet rev b2 6/30/03 copyright ? 2003 silicon image inc. 33 subject to change without notice command command/ features codes comment security set password f1h security unlock f2h seek 70h service a2h set features efh set max address f9h/00h set max address ext 37h 48-bit lba command set max freeze lock f9h/04h set max lock f9h/02h set max unlock f9h/03h obsolesced command supported. set max set password f9h/01h set multiple mode c6h the sii3112a pci to serial ata controller intercepts the command to set up the number of sectors for a drq block upon this command. sleep e6h smart disable operations b0h/d9h smart enable operations b0h/d8h smart enable/disable attributes autosave b0h/d2h smart execute off-line immediate b0h/d4h smart read attribute thresholds b0h/d1h obsolesced command supported. smart read data b0h/d0h smart read log b0h/d5h smart return status b0h/dah smart save attribute values b0h/d3h obsolesced command supported. smart write log b0h/d6h standby e2h standby immediate e0h write buffer e8h cah write dma cbh obsolesced command code supported, decoded as command code cah write dma ext 35h 48-bit lba command write dma queued cch write dma queued ext 36h 48-bit lba command write log ext 3fh 32h write long 33h obsolesced command supported write multiple c5h
copyright ? 2003 silicon image inc. sii3112a data sheet rev b2 34 subject to change without notice command command/ features codes comment write multiple ext 39h 48-bit lba command 30h write sector(s) 31h obsolesced command code supported, decoded as command code 30h write sector(s) ext 34h 48-bit lba command write stream dma 3ah write stream pio 3bh 7 power sequencing 1.8v and 3.3v supplies the sii3112a operates with 1.8v for the digital logic (vddi) and the analog circuitry (vddd), and 3.3v (vddo) supplies for the i/o?s. the voltage difference between the 1.8v supply and the 3.3v supplies must never be greater than 2.0v. it is possible for the 1.8v supply to rise faster than the 3.3v supply on power up without violating this rule, as long as the difference never exceeds 2.0v.

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