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fractional - n/integer - n pll synthesizer adf4150 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third p arties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their resp ective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 analog devices, inc. all ri ghts reserved. f eatures fractional - n synthesizer and integer - n synthesizer programmable divide - by - 1/ - 2/ - 4/ - 8/ - 16 output 5.0 ghz rf b andwidth 3.0 v to 3.6 v power supply 1.8 v logic compatibility separate charge pump supply (v p ) allows extended tuning voltage in 3 v systems programmable dual - modulus prescaler of 4/5 or 8/9 programmable output power level rf output mute function 3 - wire serial interface analog and digital lock detect switched bandwid th fast - lock mode cycle slip reduction a pplications wireless infrastructure (w - cdma, td - scdma, wimax, gsm, pcs, dcs, dect) t est equipment wireless lans, catv equipment clock g eneration g eneral d escription the adf4150 allows implementation of fractional - n or integer - n phase - locked loop (pll) frequency synthesizer s if used with an extern al voltage - controlled oscillator (vco), loop filter , an d external reference frequency. the adf4150 is for use with external vco parts and is softwar e compatible with the adf4350 . the vco frequency can be divide d by 1/ 2/4/ 8/ 16 to allow the user to generate rf output frequencies as low as 3 1 .2 5 mhz. for applications that require isolation the rf output stage can be muted . the mute function is both pin and software controllable. control of all the on - chip registers is through a simple 3 - wire interface. the device operates with a power supply ra nging from 3.0 v to 3.6 v and can be powered down when not in use. the adf4150 is available in a 4 mm 4 mm package. f unctional block d iagram muxout cp out ld sw ref in clk data le av dd sdv dd dv dd v p a gnd ce cp gnd sd gnd r set rf out + rf out ? rf in + rf in ? phase comparator fl o switch charge pump output stage rf input pdb rf multiplexer 10-bit r counter 2 divider 2 doubler function latch data register integer reg n counter fraction reg third-order fractional interpolator modulus reg multiplexer lock detect adf4150 08226-001 divide-by-1/ -2/-4/-8/-16 figure 1.
adf4150 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolu te maximum ratings ............................................................ 6 transistor count ........................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 9 circuit description ......................................................................... 11 reference input section ............................................................. 11 rf n divider ............................................................................... 11 int, frac, mod, and r counter relationship .................... 11 int n mode ................................................................................ 11 r counter .................................................................................... 11 phase frequency detector (pfd) and charge pump ............ 11 muxout and lock detect ...................................................... 12 input shift registers ................................................................... 12 program modes .......................................................................... 12 output stage ................................................................................ 12 register maps .................................................................................. 13 register 0 ..................................................................................... 18 register 1 ..................................................................................... 18 register 2 ..................................................................................... 18 register 3 ..................................................................................... 20 register 4 ..................................................................................... 20 register 5 ..................................................................................... 20 initialization sequence .............................................................. 20 rf s ynthesizer a worked example ...................................... 21 modulus ....................................................................................... 21 reference doubler and reference divider ............................. 21 12- bit programmable modulus ................................................ 21 cycle slip reduction for faster lock times ........................... 22 spurious optimization and fast lock ...................................... 22 fast lock timer and register sequences ................................ 22 fast lock an example ............................................................ 23 fast lock loop filter topology ............................................. 23 spur mechanisms ....................................................................... 23 spur consistency and fractional spur optimization ........... 24 phase resync ............................................................................... 24 applications inf ormation .............................................................. 25 direct conversion modulator .................................................. 25 interfacing ................................................................................... 26 pcb design guidelines for chip scale package .................... 26 output matching ........................................................................ 27 outline dimensions ....................................................................... 28 ordering guide .......................................................................... 28 revision history 7 / 11 revision 0: initial version
adf4150 rev. 0 | page 3 of 28 specifications av dd = dv dd = s d vdd = 3.3 v 10%; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. the o perating temperature range is ? 40c to +85 c . table 1 . parameter b version unit conditions/comments min typ max ref in characteristics input frequency 10 250 mhz for f < 10 mhz ensure slew rate > 21 v/s input sensitivity 0.7 av dd v p -p biased at av dd /2 1 input capacitance 5.0 pf input current 60 a rf input characteristics rf input frequency (rf in ), rf output buffer disabled 0.5 4. 0 ghz ?10 dbm rf i nput p ower +5 dbm rf input frequency (rf in ), rf output buffer disabled 0.5 5.0 ghz ?5 dbm rf i nput p ower +5 dbm rf input frequency (rf in ) rf output buffer enabled 0.5 3.5 ghz ?10 dbm rf i nput p ower +5 dbm rf input frequency (rf in ) rf output buffer and dividers enabled 0.5 3.0 ghz ?10 dbm rf i nput p ower +5 dbm prescaler output frequency 750 mhz maximum pfd frequency fractional - n (low spur mode) 26 mhz fractional - n mode (low noise mode) 32 mhz integer - n mode 32 mhz charge pump i cp sink/source r set = 5.1 k ? high value 4.65 ma low value 0. 29 ma r set range 2.7 10 k ? i cp leakage 1 na v cp = v p /2 sink and source current matching 2 % 0.5 v v cp v p ? 0.5 v i cp vs. v cp 1 % 0.5 v v cp v p ? 0.5 v i cp vs. temperature 2 % v cp = v p /2 logic inputs input high voltage, v inh 1.5 v input low voltage, v inl 0.6 v input current, i inh /i inl 1 a input capacitance, c in 3.0 pf logic outputs output high voltage, v oh dv dd ? 0.4 v cmos output chosen output high current, i oh 500 a output low voltage, v o 0.4 v i ol = 500 a power supplies av dd 3.0 3.6 v dv dd , sd vdd av dd v p av dd 5.5 v di dd + ai dd 2 5 0 60 ma output dividers 6 to 24 ma each output divide by two consumes 6 ma i rfout 2 24 32 ma rf output stage is programmable low power sleep mode 1 a
adf4150 rev. 0 | page 4 of 28 parameter b version unit conditions/comments min typ max rf output characteristics minimum output frequency using rf output dividers 31.25 mhz 500 mhz vco input and divide -by -1 6 selected maximum rf in frequency using rf output dividers 4400 mhz harmonic content (second) ? 19 dbc fundamental vco output harmonic content (third) ?13 dbc fundamental vco output harmonic content (second) ? 20 dbc divided vco output harmonic content (third) ?10 dbc divided vco output output power 3 ? 4 dbm maximum setting +5 dbm minimum setting output power variation 1 db level of signal with rf mute enabled ?40 dbm noise characteristics normalized phase noise floor (pn synth ) 4 ?223 dbc/hz pll loop bw = 500 khz (abp = 3 ns) normalized 1/f noise (pn 1_f ) 5 ?123 dbc/hz 10 khz offset. normalized to 1 ghz. (abp = 3 ns) normalized phase noise floor (pn synth ) 4 ?222 dbc/hz pll loop bw = 500 khz (abp = 6 ns) ; l ow noise mode selected normalized 1/f noise (pn 1_f ) 5 ?119 dbc/hz 10 khz offset ; n ormalized to 1 ghz; (abp = 6 ns) ; l ow noise mode selected spuriou s signals due to pfd frequency 6 ? 90 dbc vco output ? 7 5 dbc rf output buffers 1 ac coupling ensures av dd /2 bias. 2 t a = 25c; av dd = dv dd = 3.3 v; prescaler = 8/9; f refin = 100 mhz; f pfd = 26 mhz; f rf = 1.7422 ghz. 3 using a tuned load. 4 the synthesizer phase noise floor is estimated by measuring the in - band phase noise at the out put of the vco and subtracting 20 log n (where n is the n divider value) and 10 log f pfd . pn synth = pn tot ? 10logf pfd ? 20logn. 5 the pll phase noise is composed of 1/f (flicker) noise plus the normalized pll noise floor. the formula for calculating the 1 / f noise contribution at an rf frequency (f rf ) and at a frequency offset (f) is given by pn = p 1_f + 10log(10 khz/f) + 20log(f rf /1 ghz). both the normalized phase noise floor and flicker noise are modeled in adisimpll . 6 spurious measured on eval - adf4150eb 1z, using a rohde & schwarz fsup signal source analyzer.
adf4150 rev. 0 | page 5 of 28 timing characteristi cs av dd = dv dd = sd vdd = 3.3 v 10%; v p = av dd to 5.5 v; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. operating temperature range is ?40c to +85 c. table 2 . parameter limit (b version) unit test conditions/comments t 1 20 ns min le s etup t ime t 2 10 ns min data to clk s etup t ime t 3 10 ns min data to clk h old t ime t 4 25 ns min cl k h igh d uration t 5 25 ns min clk l ow d uration t 6 10 ns min cl k to le s etup t ime t 7 20 ns min le p ulse w idth clk dat a le le db31 (msb) db30 db1 (contro l bit c2) db2 (contro l bit c3) db0 (lsb) (contro l bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 08226-002 figure 2 . timing diagram
adf4150 rev. 0 | page 6 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating av dd to gnd 1 ? 0.3 v to +3.9 v av dd to dv dd ? 0.3 v to +0.3 v v p to av dd ? 0.3 v to +5.8 v digital i/o voltage to gnd 1 ? 0.3 v to v dd + 0.3 v analog i/o voltage to gnd 1 ? 0.3 v to v dd + 0.3 v ref in to gnd 1 ? 0.3 v to v dd + 0.3 v operating temperature range ?40 c to +85 c storage temperature range ?65 c to +125 c maximum junction temperature 150 c lfcsp ja thermal impedance (paddle - soldered) 27.3 c/w reflow soldering peak temperature 260 c time at peak temperature 40 sec 1 gnd = agnd = dgnd = 0 v . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. transistor count 23380 (cmos) and 809 ( b ipolar) esd caution
adf4150 rev. 0 | page 7 of 28 pin configuration and fu nction descriptions a gnd av dd 2 dv dd ref in sdv dd sd gnd muxout r set rf out + rf out ? pdb rf ld notes 1. the lfcsp has an exposed paddle that must be connected to gnd. pin 1 indic a t or 1 clk 2 dat a 3 le 4 ce 5 sw 6 v p 15 16 17 18 14 13 7 cp out 8 cp gnd 9 a v dd 1 1 1 rf in ? 12 a gnd 10 rf in + 21 22 23 24 20 19 adf4150 t op view (not to scale) 08226-003 figure 3 . pin configuration table 4 . pin function descriptions pin o. neonic description 1 clk serial clock input. data is clocked into the 32 - bit shift register on the clk rising edge. this input is a high impedance cmos input. 2 data serial data input. the serial data is loaded msb first with the three lsbs as the control bits. this input is a high impedance cmos input. 3 le load enable, cmos input. when le goes high, the data stored in the shift register is loaded into the register that is selected by the three lsbs. 4 ce chip enable. a logic low on this pin powers down the device and puts the charge pump into three - state mode. taking the pin high powers up the device depending on the status of the power - down bits. 5 sw fastlock switch. make a connection to this pin from the loop filter when using the fastlock mode. 6 v p charge pump power supply. this pin should be greater than or equal to av dd . in systems where av dd is 3 v, it can be set to 5.5 v and used to drive a vco with a tuning range of up to 5.5 v. 7 cp out charge pump output. when enabled, this provides i cp to the external loop filter. the output of the loop filter is connected to v tune to drive the external vco. 8 cp gnd charge pump ground. this is the ground return pin for cp out . 9 av dd 1 analog power supply. this pin ranges from 3.0 v to 3.6 v. decoupling capacitors to the an alog ground plane are to be placed as close as possible to this pin. av dd must have the same value as dv dd . 10 rf in + input to the rf input. this small signal input is ac - coupled to the external vco. 11 rf in ? complementary input to the rf input. this point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pf. 12, 13 a gnd analog ground. this is a ground return pin for av dd 1 and av dd 2. 14 rf out ? complementary rf output. the output level is programmable. the vco fundamental output or a divided down version is available. 15 rf out + rf output. the output level is programmable. the vco fundamental output or a divided down version is available. 16 av dd 2 analog power supply. this pin ranges from 3.0 v to 3.6 v. decoupling capacitors to the analog ground plane are to be placed as close as possible to this pin. av dd 2 must have the same value as dv dd . 17 pdb rf rf power - down. a logic low on this pin mutes the rf outputs. this function is also software controllable. 18 dv dd digital power supply. this pin s hould be the same voltage as av dd . place d ecoupling capacitors to the ground plane as close as possible to this pin. 19 ref in reference input. this is a cmos input with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k?. this input can be driven from a ttl or cmos crystal oscillator, or it can be ac - coupled. 20 ld lock detect output pin . this pin outputs a logic high to indicate pll lock ; a logic low output indicates loss of pll lock. 21 muxout multiplexer output. this multiplexer output allows either the lock detect, the scaled rf, or the scaled reference frequency to be accessed externally.
adf4150 rev. 0 | page 8 of 28 pin no. mnemonic description 22 sdv dd power supply pin for the digital sigma - delta ( -) modulator. this pin s hould be the same voltage as av dd . decoupling capacitors to the ground plane are to be placed as close as possible to this pin. 23 sd gnd digital - modulator ground. ground return path for the - m odulator. 24 r set connecting a resistor between this pin and gnd sets the charge pump output current. the nominal voltage bias at the r set pin is 0.48 v. the relationship between i cp and r set is set cp r i 23.9 = where: r set = 5.1 k?. i cp = 5 ma. 25 ep the exposed pad must be connected to gnd.
adf4150 rev. 0 | page 9 of 28 typical performance characteristics 0 ?50 0 5.0 power (dbm) frequency (ghz) 08226-042 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 +25c +85c ?40c figure 4. rf input sensitivity ; rf output enabled ; output divide - by - 1 selected 10 ?50 0 6 power (dbm) frequency (mhz) 08226-043 ?40 ?30 ?20 ?10 0 1 2 3 4 5 +25c +85c ?40c figure 5. rf input sensitivity ; rf output disabled 0 ?40 0 4.0 power (dbm) frequency (ghz) 08226-044 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0.5 1.0 1.5 2.0 3.0 2.5 3.5 +25c +85c ?40c figure 6. rf sensitivity ; rf output enable d (rf dividers - by - 2/ - 4/ - 8/ - 16 enabled ) ?180 ?160 ?140 ?120 ?100 ?80 ?60 power (dbc) 08226-045 1k 10k 100k 1m 10m frequenc y (hz) figure 7. integer - n phase noise and spur perform ance; low noise mode; vcoout = 175 0 mhz, ref in = 100 mhz, pfd = 25 mhz, loop filter bandwidth= 5 0 khz 1m 10m 100m 1g 10g frequenc y (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 power (dbc) 08226-046 figure 8. fractional - n phase noise and spur performance ; low noise mode; vcoout = 175 0 mhz, ref in = 10 0 mhz, pfd = 25 mhz, lo op filter bandwidth= 15 khz, channel spacing = 200 kh z. frac = 26, mod = 125 1k 10k 100k 1m 10m frequenc y (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 power (dbc) 08226-047 figure 9 . fractional - n phase noise and spur performance; low spur mode; vcoout = 1750 mhz, ref in = 100 mhz, pfd = 25 mhz, loop filter bandwidth= 5 0 khz, channel spacing = 200 khz. frac = 26, mod = 125
adf4150 rev. 0 | page 10 of 28 ?180 ?160 ?140 ?120 ?100 ?80 ?60 1k 10k 100k 1m 10m power (dbc) frequenc y (hz) 08226-038 figure 10 . rf output phase noise rf dividers used; integer - n; low noise mode; vcoout = 175 0 mhz, ref in = 100 mhz, pfd = 25 mhz, loop filter bandwidth = 5 0 khz 1k 10k 100k 1m 10m frequenc y (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 power (dbc) 08226-039 figure 11 . rf buffer output fractional - n phase noise and spur performance; low noise mode; vcoout = 175 0 mhz, ref in = 10 0 mhz, pfd = 25 mhz, loop filter bandwidth = 15 khz, channel spacing = 200 kh z ; frac = 1, mod = 5 ; output divider = 1 1k 10k 100k 1m 10m frequenc y (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 power (dbc) 08226-040 figure 12 . rf buffer output fractional - n phase noise and spur performance; low noise mode; vcoout = 175 0 mhz, ref in = 10 0 mhz, pfd = 25 mhz, loop filter bandwidth = 15 khz, channel spacing = 200 kh z; frac = 1, mod = 5; output divider = 2 1k 10k 100k 1m 10m frequenc y (hz) ?180 ?160 ?140 ?120 ?100 ?80 ?60 power (dbc) 08226-041 figure 13 . rf buffer output fractional - n phase noise and spur performance; low noise mode; vcoout = 175 0 mhz, ref in = 10 0 mhz, pfd = 25 mhz, loop filter bandwidth = 15 khz, channel spacing = 200 kh z. frac = 1, mod = 5. output divider = 4
adf4150 rev. 0 | page 11 of 28 circuit description reference input sect ion the reference input stage is shown in figure 14 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power - d own is initiated, sw3 is closed and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin on power - down. buffer t o r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down contro l 08226-010 figure 14 . reference input stage rf n divider the rf n divider allows a division ratio in the pll feedback path . division ratio is determined by in t, f rac , and mod values, which build up this divider . int, frac, mod , and r counter relationship the int, frac, and mod values, in conjunc tion with the r counter, make it possible to generate output frequencies that are spaced by f ractions of the pfd frequency . see the rf synthesizer a worked exam ple section for more informa - tion. the rf vco frequency (rf out ) equation is rf out = f pfd ( int + ( frac / mod )) (1) w here : rf out is the output frequency of external voltage controlled oscillator (vco). int is the preset divide ratio of the binary 16 C bit counter (23 to 65535 for 4/5 prescaler, 75 to 65535 for 8/9 prescaler). mod is the preset fractional modulus (2 to 4095). frac is the numerator of the fractional division (0 to mod ? 1). f pfd = ref in [(1 + d )/( r (1 + t ))] (2) where : ref in is the reference input frequency. d is the ref in doubler bit. t is the ref in divide - by - 2 bit (0 or 1). r is the preset divide ratio of the binary 10 - bit programmable reference counter (1 to 1023). third order fractional interpolator frac value mod reg int reg rf n divider n = int + frac/mod from vco output/ output dividers t o pfd n counter 08226-011 figure 15 . rf int divider int n m ode if the frac = 0 and db8 in register 2 (ldf) is set to 1 , the synthesizer operates in integer - n mode. the db8 in register 2 (ldf) shoul d be set to 1 to get integer - n digital lock detect. additionally, lower phase noise is possible if the anti - backlash pulse width is reduced to 3 ns. this mode is not valid for f ractional - n applications. r counter the 10 C bit r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 1023 are allowed. phase frequency dete ctor (pfd) and charge pump the p hase f requency d etector ( pfd ) takes inputs from the r counter and n c ounter and produces an output proportional to the phase and frequency difference between them. figure 16 is a simplified schematic of the phase frequency de tector. the pfd includes a programmable delay element that sets the width of the anti backlash pulse, which can be either 6 ns (default , for f ractional - n applications ) or 3 ns (for integer - n mode) . this pulse ensures there is no dead zone in the pfd transfer function, and gives a consistent reference spur level. u3 clr2 q2 d2 u2 down up high high cp ?in +in charge pump del a y clr1 q1 d1 u1 08226-012 figure 16 . pfd simplified schematic
adf4150 rev. 0 | page 12 of 28 muxout and lock detect the output multiplexer on the adf4150 allows the user to access various internal points on the chip. the state of muxout is controlled by m3, m2, and m1 (for details, see figure 22 ). figure 17 shows the muxout section in block diagram form. d gnd dv dd control mux muxout analog lock detect digi t al lock detect r counter output n counter output dgnd rese r ved three-s ta te-output dv dd r counter input 08226-013 figure 17 . muxout schematic input shift register s the adf4150 digital secti on includes a 10 - bit rf r counter, a 16 - bit rf n counter, a 12 - bit frac counter, and a 12 - bit modulus counter. data is clocked into the 32 - bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of six latches on the rising edge of le. the destination latch is determined by the state of the three control bits (c3, c2 , and c1) in the shift register. these are the 3 lsbs, db2, db1, and db0, as shown in figure 2 . the truth table for these bits is shown in table 5 . figure 19 shows a summary of how the latches are programmed. table 5 . c3, c2, and c1 truth table control bits c3 c2 c1 register 0 0 0 register 0 (r0) 0 0 1 register 1 (r1) 0 1 0 register 2 (r2) 0 1 1 register 3 (r3) 1 0 0 register 4 (r4) 1 0 1 register 5 (r5) program modes figure 20 through figure 25 show how the program modes are to be set up in th e adf4150 . a number of settings in the adf4150 are double buffered. these include the modulus value, phase value, r counter value, reference doubler, reference divide - by - 2, and current setting. this means that two events have to occur before the part uses a new value of any of the double - buffered settings. first, the new value is latched into the device by writing to the appropriate register. second, a new writ e must be performed on register r0. for example, any time the modulus value is updated, register r0 must be written to, t hus ensur ing the modulus value is loaded correctly. divider select in r egister 4 ( r4 ) is also double buffered, b ut only if db13 of regis ter 2 ( r2 ) is high. output stage the rf out + and rf out ? pins of the adf4150 are connected to the collectors of an npn differential pair driven by buffered outputs of the vco, as shown in figure 18 . to allow the user to optimize the power dissipation vs . the output power require - ments, the tail current of the differenti al pair is programmable by bit d2 and bit d1 in r egister 4 ( r4 ) . four current levels may be s et. these levels give ou tput power levels of ?4 dbm, ?1 db m, +2 dbm, and +5 dbm, respectively, using a 50 ? resistor to av dd and ac coupling into a 50 ? load. alternatively, both outputs can be combined in a 1 + 1:1 tra nsformer or a 180 microstrip coupler (see the output matching s ection) . if the outputs are used individually, the optimum output stage consists of a shunt inductor to av dd . another feature of the adf4150 is that the supply current to the rf output stage can be shut down until the part achieves lock as measured by the digital lock detect circuitry. this is enabled by the mute - till - lock detect (mtld) bit in register 4 (r4) . vco rf out + rf ou t ? buffer/ divide-by-1/ -2/-4/-8/-16 08226-014 figure 18 . output stage
adf4150 rev. 0 | page 13 of 28 register maps db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) 12-bit fractional value (frac) control bits n8 n7 n6 n5 n4 n3 n2 n1 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(0) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 pr1 p12 p11 p10 p9 12-bit phase value (phase) 12-bit modulus value (mod) control bits p8 p7 p6 p5 p4 p3 p2 p1 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(0) c1(1) db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 l2 l1 m3 m2 m1 rd2 rd1 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 d1 cp4 cp3 cp2 cp1 u6 u5 u4 u3 u2 u1 c3(0) c2(1) c1(0) csr rdiv2 reference doubler charge pump current setting 10-bit r counter control bits db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 f3 f2 0 0 f1 0 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(1) control bits 12-bit clock divider value ldp pd polarity power-down cp three- state counter reset output power clk div mode dbr 1 1 dbr = double buffered register?buffered by the write to register 0. 2 dbb = double buffered bits?buffered by the write to register 0, if and only if db13 of register 2 is high. reserved ldf reserved abp charge cancel reserved register 4 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d13 d12 d11 d10 bs8 bs7 bs6 bs5 bs4 bs3 bs2 bs1 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(1) c2(0) c1(0) control bits reserved reserved rf output enable ld pin mode mtld divider select feedback select register 0 register 1 register 2 register 3 register 5 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d15 d14 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3(1) c2(0) c1(1) control bits reserved reserved dbb 2 double buff reserved reserved db r 1 dbr 1 dbr 1 dbr 1 dbr 1 reserved reserved reserved prescaler low noise and low spur modes muxout 08226-015 figure 19 . register summary
adf4150 rev. 0 | page 14 of 28 n16 n15 ... n5 n4 n3 n2 n1 integer value (int) 0 0 ... 0 0 0 0 0 not allowed 0 0 ... 0 0 0 0 1 not allowed 0 0 ... 0 0 0 1 0 not allowed . . ... . . . . . ... 0 0 ... 1 0 1 1 0 not allowed 0 0 ... 1 0 1 1 1 23 0 0 ... 1 1 0 0 0 24 . . ... . . . . . ... 1 1 ... 1 1 1 0 1 65533 1 1 ... 1 1 1 1 0 65534 1 1 ... 1 1 1 1 1 65535 f12 f11 .......... f2 f1 fractional value (frac) 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 ......... 1 1 4095 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 n16 n15 n14 n13 n12 n11 n10 n9 reserved 16-bit integer value (int) 12-bit fractional value (frac) control bits n8 n7 n6 n5 n4 n3 n2 n1 f12 f11 f10 f9 f8 f7 f6 f5 f4 f3 f2 f1 c3(0) c2(0) c1(0) intmin = 75 with prescaler = 8/9 08226-016 figure 20 . register 0 (r0) p12 p11 .......... p2 p1 phase value (phase) 0 0 .......... 0 0 0 0 0 .......... 0 1 1 (recommended) 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 .......... 1 1 4095 db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 pr1 p12 p11 p10 p9 12-bit phase value (phase) 12-bit modulus value (mod) control bits p8 p7 p6 p5 p4 p3 p2 p1 m12 m11 m10 m9 m8 m7 m6 m5 m4 m3 m2 m1 c3(0) c2(0) c1(1) reserved m12 m11 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... m2 m1 interpolator modulus (mod) 0 0 1 0 2 0 0 1 1 3 . . . . . . . . . . . . . . . 1 1 0 0 4092 1 1 0 1 4093 1 1 1 0 4094 1 1 1 1 4095 prescaler p1 prescaler 0 4/5 1 8/9 db r db r 08226-017 figure 21 . register 1 (r1)
adf4150 rev. 0 | page 15 of 28 rd 2 r ef er enc e d o ub l er 0 d i sab l ed 1 enab l ed rd 1 r ef er enc e d i vi d e b y 2 0 d i sab l ed 1 enab l ed c p4 c p3 c p2 c p1 i c p (ma ) 4. 7k ? 0 0 0 0 0 . 31 0 0 0 1 0 . 63 0 0 1 0 0 . 94 0 0 1 1 1 . 25 0 1 0 0 1 . 56 0 1 0 1 1 . 88 0 1 1 0 2 . 19 0 1 1 1 2 .50 1 0 0 0 2 . 81 1 0 0 1 3 . 13 1 0 1 0 3 . 44 1 0 1 1 3 . 75 1 1 0 0 4 . 06 1 1 0 1 4 . 38 1 1 1 0 4 . 69 1 1 1 1 5 . 00 r1 0 r 9 .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. .... .. .. .. r 2 r 1 r d i vi d er ( r ) 0 0 0 1 1 0 0 1 0 2 . . . . . . . . . . . . . . . 1 1 0 0 102 0 1 1 0 1 102 1 1 1 1 0 102 2 1 1 1 1 102 3 db3 1 db3 0 db2 9 db2 8 db2 7 db2 6 db2 5 db2 4 db2 3 db2 2 db2 1 db2 0 db1 9 db1 8 db1 7 db1 6 db1 5 db1 4 db1 3 db1 2 db1 1 db1 0 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 0 l 2 l 1 m3 m2 m1 rd 2 rd 1 r1 0 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 d 1 c p4 c p3 c p2 c p1 u 6 u 5 u 4 u 3 u 2 u 1 c3 (0 ) c2 (1 ) c1 (0 ) rdiv2 db r reference doubler db r charge pump curr en t se tti n g 10 -b it r c o un t er db r c o n t r o l b it s ldp pd polarity power-down cp three- state counter reset ldf mu xo u t double buff u 5 l d p 0 10 n s 1 6 n s u 4 pd pol ar it y 0 n eg a ti ve 1 po s iti ve u 3 pow er -d ow n 0 d i sab l ed 1 enab l ed u 2 c p t hr ee-s t a t e 0 d i sab l ed 1 enab l ed u 1 c o un t er r eset 0 d i sab l ed 1 enab l ed d 1 d o ub l e bu ff er r4 db22 :db 2 0 0 d i sab l ed 1 enab l ed u 6 l d f 0 f rac -n 1 i n t -n reserved m3 m2 m1 o u t pu t 0 0 0 t hr ee-s t a t e o u t pu t 0 0 1 d v dd 0 1 0 d g n d 0 1 1 r d i vi d er o u t pu t 1 0 0 n d i vi d er o u t pu t 1 0 1 ana log lo ck d et ec t 1 1 0 d igit a l lo ck d et ec t 1 1 1 r ese r ved l 1 l 2 n oi se mo d e 0 0 low n oi se mo d e 0 1 r ese r ved 1 0 r ese r ved 1 1 low sp ur mo d e low noise and low spur modes 08226-018 figure 22 . register 2 (r2)
adf4150 rev. 0 | page 16 of 28 c 2 c 1 clock divider mode 0 0 clock divider off 0 1 fast lock enable 1 0 resync enable 1 1 reserved d12 d11 .......... d2 d1 clock divider value 0 0 .......... 0 0 0 0 0 .......... 0 1 1 0 0 .......... 1 0 2 0 0 .......... 1 1 3 . . .......... . . . . . .......... . . . . . .......... . . . 1 1 .......... 0 0 4092 1 1 .......... 0 1 4093 1 1 .......... 1 0 4094 1 1 .......... 1 1 4095 csr db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 0 f1 0 c2 c1 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(0) c2(1) c1(1) control bits 12-bit clock divider value clk div mode reserved f1 cycle slip reduction 0 disabled 1 enabled reserved 0 0 reserved 08226-019 f 3 f 2 f 2 char g e canc e ll a t io n 0 d i s ab l e d 1 e nab l e d f 3 an t i back l a s h p u l se w i d t h 0 6 n s ( f rac - n ) 1 3 n s ( i n t _ n ) charge cancel abp figure 23 . register 3 (r3) d3 rf out 0 disabled 1 enabled d 2 d 1 output power 0 0 ?4 0 1 ?1 1 0 +2 1 1 +5 d8 mute till lock detect 0 mute disabled 1 mute enabled d12 d11 rf divider select 0 0 1 0 0 2 0 1 4 0 1 8 d10 0 1 0 1 1 0 16 0 d13 feedback select 0 fundamental 1 divided 08226-020 output power db31 db30 db29 db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 0 0 d13 d12 d11 d10 bs8 bs7 bs6 bs5 bs4 bs3 bs2 bs1 d9 d8 d7 d6 d5 d4 d3 d2 d1 c3(1) c2(0) c1(0) control bits reserved reserved rf output enable mtld divider select feedback select reserved dbb 2 figure 24 . register 4 (r4)
adf4150 rev. 0 | page 17 of 28 l d pi n mo d e db3 1 db3 0 db2 9 db2 8 db2 7 db2 6 db2 5 db2 4 db2 3 db2 2 db2 1 db2 0 db1 9 db1 8 db1 7 db1 6 db1 5 db1 4 db1 3 db1 2 db1 1 db1 0 db 9 db 8 db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 0 0 0 0 0 0 0 0 d1 5 d1 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c3 (1 ) c2 (0 ) c1 (1 ) c o n t r o l b it s r ese r ved r ese r ved reserved d 1 5 d 1 4 lo ck d et ec t pi n o pe ra tio n 0 0 lo w 0 1 d igit a l lo ck d et ec t 1 0 lo w 1 1 h ig h r ese r ved 08226-021 figure 25 . register 5 (r5)
adf4150 rev. 0 | page 18 of 28 r egister 0 control b its with bits [c3:c1] set to 0, 0 , 0 , r egister 0 is programmed. figure 20 shows the input data format for programming this register. 16- bit integer value (int) these 16 bits set the int value, which determ ine s the integer part of the feedback division factor. they are used in equation 1 (see th e int, frac, mod, and r counter relationship sectio n). all inte ger values from 23 to 65 , 535 are allowed for 4/5 prescal er. for 8/9 prescaler , the minimum integer value is 75. 12- bit fractional value (frac) the 12 frac bits set the numerator of the fraction that is input to the - modulator. this, along with int, specifies the new frequency channel that the synthesizer locks to, as shown in the rf synthesizer a worked example section . frac values from 0 to mod ? 1 cover channe ls over a frequency range equal to the pfd reference frequency. r egister 1 control bits with bits [ c3 :c1] set to 0, 0 , 1, r egister 1 is programmed. figure 21 shows the input data format for programming this register. prescaler value the dual modulus prescaler (p/p + 1), along with the int, frac, and mod counters, determines the overall division ratio from the vco output to the pfd input. operating at cml le vels, it takes the clock from the vco output and divides it down for the counters. it is based on a synchronous 4/5 core. when set to 4/5, the maximum rf frequency allowed is 3 ghz. therefore, when operating the a df4150 above 3 ghz, this must be set to 8/9. the prescaler limits the int value , where : p = 4/5, n min = 23 p = 8/9, n min = 75 in the adf4150 , p1 in r egister 1 set s the prescaler values. 12- bit p hase value ( ph ase ) these bits control what is loaded as the phase word. the word must be less than t he mod value programmed in r egister 1 . the word is used to program the rf output phase from 0 to 360 with a resolution of 360 /mod. see the phase r esync section for more information. in most applications, the phase relationship between the rf signal and the reference is not important. in such applications, the phase value can be used to optimize the fractional and subfractional spur levels. see th e spur consistency and fractional spur optimization section for more information. if neither the phase resync nor the spurious optimization functions a re being used, it is recommended that the phase word be set to 1. 12- bit m odulus value (mod) this programmable register sets the fractional modulus. this is the ratio of the pfd frequency to the channel step resolution on the rf output. see the rf synthesizer a worked example section for more information. r egister 2 control b its with bits[c3: c1] set to 0 , 1, 0 , r egister 2 is programmed. figure 22 shows the input data format for programming this register. low noise and spur mode s the noise modes on the adf4150 are con trolled by db30 and db29 in r egister 2 ( s ee figure 22) . the noise modes allow the user to optimize a design either for improved spurious perfor - mance or for improved phase noise performance. when the lowest spur setting is chosen, dither is ena bled. this randomizes the fr actional quantization noise so it resembles white noise rather than spurious noise. as a result, the part is optimized for improved spurious performance. this operation would normally be used when the pll closed - loop bandwidth i s wide, for fast - locking applications. (wide loop bandwidth is seen as a loop bandwidth greater than 1/10 of the rf out channel step resolution (f res )). a wide loop filter does not attenuate the spurs to the same level as a narrow loop bandwidth. for best noise performance, use the lowest noise setting option. as well as disabling the dither, it also ensures that the charge pump is operating in an optimum region for noise performance . this setting is extremely useful where a narrow loop filter band - width is available. the synthesizer ensures extremely low noise and the filter attenuates the spurs. the typical performance characteristics give the user an idea of the trade - off in a typical w - cdma setup for the different noise and spur settings.
adf4150 rev. 0 | page 19 of 28 muxout the on - chip multiplexer is controlled by bits [db28: db26 ] ( s ee figure 22) . reference doubler setting db25 to 0 feeds the ref in signal directly to the 10 - bit r counter, disabl ing the doubler. setting this bit to 1 multiplies the ref in frequency by a factor of 2 before feeding into the 10- bit r counter. when the doubler is disabled, the ref in falling edge is the active edge at the pfd input to the fractional synthesizer. when the doubler is enabled, both the rising and falling edges of ref in become active edges at the pfd input. when the doubler is enabled and the lowest spur mode is chosen, t he in - band phase noise performance is sensitive to the ref in duty cycle. the phase noise degradation can be as much as 5 db for the ref in duty cycles outside a 45% to 55% range. the phase noise is insensitive to the ref in duty cycle in the lowest noise mod e. the phase noise is insensitive to the ref in duty cycle when the doubler is disabled. the maximum allowable ref in frequency when the doubler is enabled is 30 mhz. rdiv 2 setting the db24 bit to 1 inserts a divide - by - 2 toggle flip - flop between the r counte r and pfd, which extends the maximum ref in input rate. this function allows a 50% duty cycle signal to appear at the pfd input, which is necessary for cycle slip reduction. 10- bit r counter the 10 - bit r counter allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd . division ratios from 1 to 1023 are allowed. double b uffer db13 enables or disables double buffering of bit s[ db22 :db 20] in r egister 4 . the divider select s ectio n explains how double buffering works. current setting bits[ db12 :db 9 ] set the charge pump current setting. this should be set to the charge pump current that the loop filter is design ed with (see figure 22). ldf setting db 8 to 1 enables integer - n digital lock detect , when the frac part of the divider is zero; setting db8 to 0 enables fractional - n digital lock detect . lock detect precision (ldp) when db7 is set to 0, the fractional - n digital lock detect is activated. in this case after setting db7 to 0, 40 consecutive pfd cycles of 10 ns must occur before digital l ock detect is set. when db7 is programmed to 1, 40 consecutive reference cycle s of 6 ns must occur b efore digital lock detect goes high . setting db8 to 1 causes the activation of the integer - n digital lock detect . in this case , after setting db7 to 0 , 5 consecutive cycles of 1 0 ns must occur before digital lock detect is set. when db7 is set to 1, five consecutive cycles of 6 ns must occur. phase detector polarity db6 sets the phase detector polarity. when a passive loop filter , or non inverting active loop filter i s used, set this bit to 1. if an active filter with an inverting char acteristic is used, this bit should be set to 0. power - down (pd) db5 provides the programmable power - down mode. setting this bit to 1 performs a power - down. setting this bit to 0 returns the synthesizer to normal operation. wh en in software power - down mode , the part retains all information in its registers. on ly if the supply voltages are removed are the register contents lost. when a power - down is activated, the following events occur: ? the synthesizer counters are forced to their load state conditions. ? the charge pump is forced into three - state mode. ? the digital lock detect circuitry is reset. ? the rf out buffers are disabled . ? the input register remains active and capable of loading and latching data. charge pump (cp) three - state db4 puts the charge pump into three - state mode when programmed to 1. it should be set to 0 for normal operation. counter reset db3 is the r counter and n counter reset bit for the adf4150 . when this bit is 1, the rf synthesizer n counter a nd r counter ar e held in reset. for normal operation, this bit should be set to 0.
adf4150 rev. 0 | page 20 of 28 r egister 3 control b its with bits [c3: c1] set to 0 , 1, 1 , r egister 3 is programmed. figure 23 shows the input data format for programming this register. ant ib acklash pulse width setting db22 to 0 sets the pfd antibacklash pulse width to 6 ns. this is the recommen ded mode for fraction al - n use. by s ettin g this bit to 1, the 3 ns pulse width is used and result s in a phase noise and spur improvement in integer - n operation. for fractional - n mode it is not recommended to use this smaller setting. charge cancellation mode pulse width settin g db21 to 1 enables charge pump charge cancellation. this has the effect of reducing pfd spurs in integer - n mode. in fractional - n mode , this bit should not be used and the relevant result in a phase noise and spur improvement. for fractional - n mode , it is not recommended to use this smaller setting. cycle slip reduction ( csr ) enable setting db18 to 1 enables cycle slip reduction. this is a method for improving lock times. note that the signal at the phase fre - quency detector (pfd) must have a 50% duty cycle for cycle slip reduction to work. the charge pump current setting must also be set to a minimum. see the cycle slip reduction for faster lock times section for more information. clock divider mode b its [db16: db15 ] must be set to 1, 0 to activat e phase r esync or 0, 1 to activ ate fast lock. setting bits[db16:db15] to 0, 0 disables the clock divider. see figure 23. 12- bit clock divider value the 12 - bit clock divider value sets the timeout counter for activation of phase r esync. see th e phase r esync section for more information. it also sets the timeout counter for fast lock. see t he fast lock timer and register sequences section for more information. r egister 4 control b its with bits[c3: c1] set to 1, 0, 0 , r egister 4 is programmed. figure 24 shows the input data format for programming this register. feedback s elect db23 selects the fe edback from vco output to the n - counter. when this bit is set to 1, the signal is taken from the vco directly . w hen this bit is set to 0 , it is taken from the output of the o utput dividers. the dividers enable covering of the wide frequency band (13 7.5 mhz to 4.4 ghz). w hen the divider is enabled and the feedback signal is taken from the output, the rf output signals of two separately configured plls are in phase. th is is useful in some applica tions where the positive i nterference of signals is required to increase the power. divider select bits [ db22 :db 20] select the value of the output d i vider (s ee figure 24) . mute - till - l ock d etect if db10 is set to 1, the supply current to the rf output stage is shut down until the part achieves lock as measured by the digital lock detect circuitry. rf output enable db5 enables or disables primary rf output , depending on the chosen value. output power db4 and db3 set the value of the primary rf output power level (s ee figure 24 ) . r egister 5 control b its with bits[c3: c1] set to 1, 0, 1 , r egister 5 is programmed. figure 25 shows the input data form for programming this register. lock detect pin operation bits [db 2 3 : db22 ] set the o peration of the lock detect pin (s ee figure 25) . i nitialization s equence the following sequence of registers is the correct sequence for initial power up of the adf4150 after the correct application of voltages to the supply pins: ? register 5 ? register 4 ? register 3 ? register 2 ? register 1 ? register 0
adf4150 rev. 0 | page 21 of 28 rf synthesizer a worked example the following is an example how to program the adf4150 synthesizer: rf out = [ int + ( frac / mod )] [ f pfd ] / rf divider (3) where: rf out is the rf frequency output. int is the integer division factor. frac is the fractionality. mod is the modulus. rf divider is the output divider that divides down the vco frequency. f pfd = ref in [(1 + d) /( r (1 + t ))] (4) where: ref in is the reference frequency input. d is the rf ref in doubler bit. t is the reference divide - by - 2 bit (0 or 1). r is the rf reference division factor. for example, in a umts system, where 2112.6 mhz rf frequency output (rf out ) is required, a 10 mhz referen ce frequency input (ref in ) is available, and a 200 khz channel resolution (f resout ) is required, on the rf output. a 2.1 ghz vco would be suitable, but a 4.2 ghz vco would also be suitable . in the second case , the r f divider of 2 should be used ( vco freque ncy = 4225.2 mhz, rf out = vco frequency/rf d ivider = 4225.2 mhz/2 = 2112.6 mhz ) . it is also important where the loop is closed. in this example , the loop is closed as depicted in figure 26 (from the out divider ) . f pfd pfd vco n divider 2 rf out 08226-022 figure 26 . loop closed before output divider a channel resolution (f resout ) of 200 khz is required at the output of the rf divider. therefore , channel resolution at the output of the vco ( f res ) is to be twice the f resout , that is , 400 khz. mod = ref in / f res mod = 10 mhz /4 00 khz = 25 from equation 4 f pfd = [10 mhz (1 + 0)/1] = 10 mhz (5) 2112.6 mhz = 10 mhz ( int + frac /25)/2 (6) where: int = 422 frac = 13 modulus the choice of modulus (mod) depends on the reference signal (ref in ) available and the channel resolution (f res ) required at the rf output. for example, a gsm system with 13 mhz ref in sets the modulus to 65. this means the rf output resolution (f res ) is the 200 khz (13 mhz/65) necessary for gsm. with dither off, the fractional spur interval depend s on the modulus values chosen (s ee table 6 ). reference doubler an d reference divid er the reference doubler on - chip allows the input reference signal to be doubled. this is useful for increasing the pfd comparison frequency. making the pfd frequency higher improves the noise performance of the system. doubling the pfd frequency usually i mproves noise performance by 3 db. it is important to note that the pfd cannot operate above 32 mhz due to a limitation in the speed of the - circuit of the n - divider. the reference divide - by - 2 divides the reference signal by 2, resulting in a 50% duty cycle pfd frequency. this is necessary for the correct operation of the cycle slip reduction (csr) function. see the cycle slip reduction for faster lock times s ection for more information. 12- bit programmable mod ulus unlike most other fractional - n plls, the adf4150 allows the user to program the modulus over a 12 - bit range. this means the user can set up the part in many different configurations for the application, when combined with the reference doubler and the 10 - bit r counter. for example , consider an application that requires 1.75 ghz rf and 200 khz channel step resolution. the system has a 13 mhz reference signal. one possible setup is feeding the 13 mhz directly to the pfd and programming the modulus to divide by 65. this results in the required 200 khz resolution. another possible setup is using the reference doubler to create 26 mhz fr om the 13 mhz input signal. the 26 mhz is then fed into the pfd programming the modulus to divide by 130. this also results in 200 khz resolution and offers superior phase noise performance over the previous setup. the programmable modulus is also very useful for multi - standard appli cations. if a dual - mode phone requires pdc and gsm 1800 standards, the programmable modulus is a great benefit. pdc requires 25 khz channel step resolution, whereas gsm 1800 requires 200 khz channel step resolution.
adf4150 rev. 0 | page 22 of 28 a 13 mhz reference signal can be fed directly to the pfd , and the modulus can be programmed to 520 when in pdc mode (13 mhz/520 = 25 khz). the modulus needs to be reprogrammed to 65 for gsm 1800 operation (13 mhz/65 = 200 khz). it is important that the pfd frequency remain constant (13 mhz ) . this allows the user to de sign one loop filter for both setups without running into stability issues. it is important to remem - ber that the ratio of the rf frequency t o the pfd frequency principally affects the loop filter design , not the actual channel spacing . cycle slip reduction for faster lock time s as outlined in the low noise and spur mode section, the adf4150 contains a number of features that allow optimization for nois e performance. however, in fast l ocking applications, the loop bandwidth generally needs to be wide, and therefore, the filter does not provide much attenuation of the spurs. if the cycle slip reduction feature is enabled , the narrow loop ban dwidth is maintained for spur attenuation but fast er lock times are still possible . cycle slips cycle slips occur in integer - n/fractional - n synthesizers when the loop bandwidth is narrow compared to the pfd frequency. the phase error at the pfd inputs accumulates too fast for the pll to correct, and the charge pump temporarily pumps in the wrong direction. this slows down the lock time dramatically. the adf4150 co ntain s a cycle slip reduction feature that extend s the linear range of the pfd , allowing faster lock tim es without modifications to the loop filter circuitry . when the circuitry detects that a cycle slip is about to occur, it turns on an extra charge pum p current cell. this outputs a constant current to the loop filter, or removes a constant current from the loop filter (depending on whether the vco tuning voltage needs to increase or decrease to acquire the new frequency). the effect is that the linear range of the pfd is increased. loop s tability is maintained because the current is constant and is not a pulsed current. if the phase error increases again to a point where another cycle slip is likely, the adf4150 turns on another charge pump cell. this continues until the adf4150 detects the vco frequency has gone past the desired frequency. the extra charge pump cells are turned off one by one until all the extra charge pump cells have been disabled and the frequency is settled with the original loop filter bandwidth . up to seven extra charge pump cells can be turned on. in most applications, it is enough to eliminate cycle slips altogether, giving much faste r lock times. setting bit db18 in r egister 3 to 1 enables cycle slip reduction. note that the pfd requires a 45% to 55% dut y cycle f or csr to operate correctly. spurious optimizatio n and fast lock narrow loop bandwidths can filter unwanted s purious signals , but these usually have a long lock time. a wider loop bandwidth achieve s fast er lock times, but a wider loop bandwidth may lead to increased spurious signals inside the loop bandwidth . t he fast lock feature can achieve the same fast lock tim e as t he wider bandwidth , but with the advantage o f a narrow final loop bandwidth to keep spurs low . fast lock timer and regis ter sequences if the fast lock mode is used, a timer value is to be loaded into the pl l to determine the duration of the wide bandwidth mode. when bits [db16: db15 ] in r egister 3 are set to 0, 1 (fast lock enable), the timer value is loaded by the 12 - bit clock divider value. t he following sequence must be programmed to use fast lock : 1. initialization s equence ( s ee the initialization sequence section ); occurs only once after powering up the part. 2. load r egister 3 by setting bits [db16: db15 ] to 0, 1 and the cho sen fast lock timer value [db14:db3] . note that the duration the pll remains in wide bandwidth is equal to the fast lock timer/f pfd .
adf4150 rev. 0 | page 23 of 28 fast lock an example if a pll has a reference frequency of 13 mhz , f pfd of 13 mhz and a required lock time of 50 s, the pll is set to wide bandwidth for 40 s. this example assumes a modulus of 65 for channel spacing of 200 khz. if the time period set for the wide bandwidth is 40 s, then fast lock timer value = time in wide bandwidth f pfd / mod fast lock timer value = 40 s 13 mhz / 65 = 8 therefore, 8 must be loaded into the clock divider value in r egister 3 in step 1 of the seq uence described in the fast lock timer and register sequences section. fast lock loop filter topology t o use fast lock mode, t he damping resistor in the loop filter is reduced to ? of its value while in wide bandwidth mode. to achieve the wider loop filter bandwidth, the charge pump current increases by a factor of 16. t o maintain loop stability , the damping resistor must be reduced a factor of ? . to enable fast lock, the sw pin is shorted to the gnd pin by settings b its [db16: db15 ] in register 3 to 0, 1 . the following two t opologies are available : ? t he damping resistor (r1) is divided into two values (r1 and r1a) that have a ratio of 1:3 (see figure 27). ? a n extra resistor (r1a) is connected directly from sw, as shown in figure 28 . the extra resistor is calculated such that the parallel combination of an extra resistor and the damping resistor (r1) is reduced to ? of the original value of r1 (see figure 28). adf4150 cp sw c1 c2 r2 r1 r1 a c3 vco 08226-023 figure 27 . fast lock loop filter topology topology 1 adf4150 cp sw c1 c2 r2 r1 r1 a c3 vco 08226-024 figure 28 . fast lock loop filter topology topology 2 spur mechanisms this section describes the three different spur mechanisms that arise with a fractional - n synthesizer and how to minimize them in the adf4150 . fractional spurs the fractional interpolator in the adf4150 is a third - order - modulato r (sdm) with a modulus (mod) that is programmable to any integer value from 2 to 4095. in low spur mode (dither enabled) , the minimum allowable value of mod is 50. the sdm is clocked at th e pfd reference rate (f pfd ) that allows pll output frequencies to be synthesized at a channel step resolution of f pfd /mod . in low noise mode (dither off ), the quantization noise from the - modulator appears as fractional spurs. the interval between spur s is f pfd /l, where l is the repeat length of the code sequence in the digital - modulator. for the third - order modulator used in the adf4150 , the repeat length depends on the value of mod, as listed in table 6 . table 6 . fractional spurs with dither off condition (dither off) repeat length spur interval if mod is divisible by 2 but not 3 2 mod channel step/2 if mod is divisible by 3 but not 2 3 mod channel step/3 if mod is divisible by 6 6 mod channel step/6 otherwise mod channel step in low spur mode (dither on ), the repeat length is extended to 2 21 cycles, regardless of the value of mod, which makes the quantization error spectrum look like broadband noise. this may degrade the in - band phase noise at the pll output by as much as 10 db. f or lowest noise, dither off is a better choice, particularly wh en the final loop bandwidth is low enough to attenuate even the lowest frequency fractional spur. integer boundary spurs another mechanism for fractional spur creation is the inte - ractions between the rf vco frequency and the reference frequency. when these frequencies are not integer related (the point of a fractional - n synthesizer) spur sidebands appear on the vco output spectrum at an offset frequency that corres - ponds to the beat note or difference frequency between an integer multiple of the refere nce and the vco frequency. these spurs are attenuated by the loop filter and are more noticeable on channels close to integer multiples of the reference where the difference frequency can be inside the loop bandwidth, therefore the name integer boundary s purs.
adf4150 rev. 0 | page 24 of 28 reference spurs reference spurs are generally not a problem in fractional - n synthesizers because the reference offset is far outside the loop bandwidth. how ever, any reference feed through mechanism that bypasses the loop can cause a prob lem. f eed thr ough of low levels of on - ch ip reference switching noise, through the rf in pin back to the vco, can result in reference spur levels as high as ? 90 dbc. pcb layout needs to ensure adequate isolation between vco traces and the input ref erence to avoid a poss ible feed through path on the board. spur consistency and fractional spur optimization with dither off, the fractional spur pattern due to the quanti - zation noise of the sdm also depends on the particular phase word with which the modulator is seeded. the phase word can be varied to optimize the fractional and subfractional spur levels on any particular frequency. thus, a look - up table of phase values corresponding to each frequency can be constructed for use when programming the adf4150 . if a look - up table is not used, keep the phase word at a constant value to ensure consistent spur levels on any particular frequency . p hase r esync the output of a fractional - n pll can settle to any one of the mod phase offsets with respect to the input reference, where mod is the fractional modulus. the phase resync feature in the adf4150 produce s a consistent output phase offset with respect to the input reference. this is necessary in applications where the output phase and frequency are important, such a s digital beam forming. see the phase programmability section for how to program a specific rf output phase when using phase resync. phase resync is enabled by setting bit db16 , bit db15 i n register 3 to 1, 0 . when phase resync is enabled, an internal timer generates sync signals at intervals of t sync given by the following formula: t sync = clk_div_value mod t pfd w here : t pfd is the pfd reference period. clk_div_value is the decim al value programmed in bits [ db 14: db 3] of register 3 and can be any integer in the range of 1 to 4095. mod is the modulus value pr ogrammed in bit s [ db 14: db 3] of register 1 (r1). when a new frequency is programmed, the second sync pulse after the le rising edge is used to resynchronize the output phase to the reference. the t sync time is to be programmed to a v alue that is a t least as long as the worst - case lock time. this guarantees that the phase resync occurs after the last cycle slip in the pll settling transient. in the example shown in figure 29 , the pfd reference is 25 mhz and mod is 125 for a 200 khz channel spacing. t sync is set to 400 s by programming clk_div_value to 80. le phase frequency sync (internal) ?100 0 100 200 1000 300 400 500 600 700 800 900 time (s) pll settles to correct phase after resync t sync last cycle slip pll settles to incorrect phase 08226-025 figure 29 . phase resync exampl e p hase programmability the phase word in register 1 controls the rf output phase . as this word is swept from 0 to mod, the rf output phase sweeps over a 360 range in steps of 360 /mod.
adf4150 rev. 0 | page 25 of 28 applications information direct conversion mo dulator direct conversion architectures are increasingly being used to implement base station transmitters. figure 30 shows how a nalog devices, inc . , parts can be used to implement such a system . the circu it block diagram shows the ad9788 txdac? being used with the ad l5375 . the use of dual in tegrated dacs, such as the ad9788 with its specified 0.02 db and 0.004 db gain and offset matching characteristics, ensures minimum error contribution (over temperature) from this portion of the signal chain. the local oscillator (lo) is implemented using the adf4150 . the low - pass filter was designed using adisimpll ? for a channel spacing of 200 khz and a closed - loop bandwidth of 35 khz . the lo ports of the adl5375 can be driven differentially from the rf out + and r f out ? outputs of the adf4150 . this gives better performance than a single - ended lo driver and eliminates the use of a balun to convert from a single - ended lo input to the more desirable differential lo inputs for the adl5375 . the typic al rm s phase noise (100 hz to 5 mhz) of the lo in this configu ration is 0.61 rms . the adl5375 accepts lo drive levels from ?10 dbm to 0 dbm. the optimum lo power can be software programmed on the adf4150 , which allows levels from ?4 dbm to +5 dbm from each output. the rf output is designed to drive a 50 ? load but must be ac - coupled, as shown in figure 30 . if the i and q inputs are driven in quadrature by 2 v p - p signals, the resulting output power from the modulator is approximately 2 dbm. ad9788 txdac refio fsadj modulated digital data qoutb iouta ioutb qouta 2k ? low-pass filter low-pass filter 2700pf 1200pf 39nf 680 ? 360 ? ibbp ibbn qbbp qbbn loip loin spi-compatible serial bus adf4150 cp gnd a gnd a gnd sd gnd rf out ? rf out + 1nf 1nf 4.7k ? r set le data clk ref in fref in cp dv dd av dd ce muxout v cc vco out vco v tune 16 18 av dd 9 19 1 2 3 24 8 12 13 23 v dd lock detect 51 ? 51 ? 51 ? 51 ? 51 ? 15 14 20 21 ld 7 pdb rf 17 6 22 sdv dd vp 5 sw 4 adl5375 r fout quadrature phase splitter d so p rf in ? rf in + 11 10 v vco 3.9nh 3.9nh 1nf 1nf 100pf 100pf v vco 08226-026 figure 30 . direct conversion modulator
adf4150 rev. 0 | page 26 of 28 interfacing the adf4150 has a simple s pi - compatible serial interface for writing to the device. clk, data, and le control the data transfer. when le go es high, the 32 bits that have been clocked into the appropriate register on each rising edge of clk are transferred to the appropriate latch. see figure 2 for the timing diag ram and table 5 fo r the register address table. aduc812 interface figure 31 shows the interface between the adf4150 and the aduc812 microconverter?. because the aduc812 is based on an 8051 core, this interface can be used with any 8051 - based microcontroller. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4150 needs a 32- bit word, which is accomplished by writing four 8 - bit bytes from the microconverter to the device. when the fourth byte has been written, the le input should be brought high to complete the transfer. aduc812 adf4150 clk sdat a le ce muxout (lock detect) sclock mosi i/o ports 08226-027 figure 31 . aduc812 to adf4150 interface i/o port lines on the aduc812 are also used to control power - down (ce input) and detect lock (muxout configured as lock detect and polled by the port input). when operating in the described mode, the maximum sclock rate of the aduc8 12 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 125 khz. adsp - 21xx interface figure 32 shows the interface between the adf4150 and a adsp - 21xx digital signal processor. the adf4150 needs a 32- bit ser ial word for each latch write. the easiest way to accom plish this using the adsp - 21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. adsp-21xx adf4150 clk sdat a le ce muxout (lock detect) sclk mosi tfs i/o ports 08226-028 figure 32 . adsp - 21xx to adf4150 interface set up the word length for 8 bits and use four memory locations for each 32 - bit word. to program each 32 - bit latch, store the 8 - bit bytes , enable the autobuffered mode, and wr ite to the transmit register of the dsp. this last operation initiates the autobuffer transfer. pcb design guideline s for chip scale package the lands on the chip scale pa ckage (cp - 24- 7 ) are rectangu lar. the pcb pad for these is to be 0.1 mm longer than th e package land length and 0.05 mm wider than the package land width. the land is to be centered on the pad. this ensures t he solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the pcb is to be at least as large as the exposed pad. on the pcb, there is to be a minimum clearance of 0.25 mm between the thermal pad and the inner edges of the pad pattern. this ensures that shorting is avoided. thermal vias can be used on the pcb thermal pad to impro ve the thermal performance of the package. if vias are used, they are to be incorporated in the thermal pad at 1.2 mm pitch grid. the via diameter is to be between 0.3 mm and 0.33 mm, and the via barrel is to be plated with one ounce copper to plug the via .
adf4150 rev. 0 | page 27 of 28 output matching there are a number of ways to match the output of the adf4150 for optimum operation; the most basic is to use a 50 ? resistor to a v dd . a dc bypass capacitor of 100 pf is connected in series as shown in figure 33 . because the resistor is not frequency dependent, this provides a good broadband match. the output power in this circuit into a 50 ? load typically gives values chosen by bit s[db4 :d b3 ] in r egister 4 (r4). 08226-029 50 ? 100pf rf out a v dd 50? figure 33 . simple adf4150 output stage a better solution is to use a shunt inductor (acting as an rf choke) to a v dd . this gives a better match and, therefore, more output power. experiments indicate that the circuit shown in figure 34 provides an excellent match to 50 ? for the w - cdma umts band 1 (2110 mhz to 2170 mhz) . the maximum output power in that case is about 7 dbm. both single - ended architectures can be examined us ing the eval - adf4150 eb1z evaluation board. 3.9nh 1nf rf out av dd 50? 08226-030 figure 34 . optimum adf4150 output stage if differential outputs are not needed , the unused output can be terminated or combine d with both outputs using a balun.
adf4150 rev. 0 | page 28 of 28 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.18 compliant to jedec standards mo-220-wggd. 112108-a bot t om view top view exposed pa d pin 1 indic a t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 1 24 7 12 13 18 19 6 2.65 2.50 sq 2.45 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 35 . 24 - lead lead frame chip scale package [lfcsp_ w q ] 4 mm 4 mm body, very very thin quad (cp - 24 - 7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adf4150 bcpz ? 40c to +85c 2 4 - lead lead f rame chip scale package [lfcsp_w q] cp -24-7 ADF4150BCPZ - rl7 ?40c to +85c 24- lead lead f rame chip scale package [lfcsp_w q] cp -24-7 eval - adf4150eb1z evaluation board 1 z = rohs compliant part. ? 2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08226 - 0 - 7/11(0)

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