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2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 1 of 54 product description the kxti9 is a tri - axis +/ - 2g, +/ - 4g or +/ - 8g silicon micromachined accelerometer with integrated orientation, tap/double tap, and activity detecting algorithms. the sense element is fabricated using kionix?s proprietary plasma micro machining process technology. acceleration sensing is based on the principle of a differential capacitance arising from acceleration - induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from process varia tion, temperature, and environmental stress. the sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. a separate asic device packaged with the sense element provides signal condit ioning, and intelligent user - programmable application algorithms. the accelerometer is delivered in a 3 x 3 x 0.9 mm lga plastic package operating from a 1.8 C 3.6v dc supply. voltage regulators are used to maintain constant internal operating voltages o ver the range of input supply voltages. this results in stable operating characteristics over the range of input supply voltages and virtually undetectable ratiometric error. i 2 c digital protocol is used to communicate with the chip to configure and chec k for updates to the orientation, directional tap tm detection and activity monitoring algorithms.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 2 of 54 functional diagram x sensor vdd io vdd gnd y sensor z sensor 8 6 10 i 2 c digital engine charge amp 5 1 4 temp sensor a / d 9 7 digital filter
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 3 of 54 product specifications table 1. mechanical (specifications are for operation at 2.6v and t = 25c unless stated otherwise) parameters units min typical max operating temperature range o c - 40 - 85 zero - g offset mg - 25 125 zero - g offset variation from rt over temp. mg/ o c 0.7 (xy) 0.4 (z) sensitivity (12 - bit) 1 gsel1=0, gsel 0 =0 ( 2 g) counts/g 988 1024 1060 gsel1=0, gsel0=1 ( 4g) 494 512 530 gsel1=1, gsel0=0 ( 8g) 247 256 265 sensitivity (8 - bit) 1 gsel1=0, gsel0=0 ( 2g) counts/g 61 64 67 gsel1=0, gsel0=1 ( 4g) 30 32 34 gsel1=1, gsel0=0 ( 8g) 15 16 17 sensitivi ty variation from rt over temp. %/ o c 0.01 (xy) 0.03 (z) self test output change on activation g 0.7 (xy) 0.5 (z) mechanical resonance ( - 3db) 2 hz 3500 (xy) 1800 (z) non - linearity % of fs 0.6 cross axis sensitivity % 2 notes: 1. resolution and acceleration ranges are user selectable via i 2 c . 2. resonance as defined by the dampened mechanical sensor.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 4 of 54 table 2. electrical (specifications are for operation at 2.6v and t = 25c unless stated otherwise) parameters units min t ypical max supply voltage (v dd ) operating v 1.71 2.6 3.6 i/o pads supply voltage (v io ) v 1.7 v dd current consumption all on (res = 1) a 325 directional tap? (r es = 0 , odr = 400hz ) 165 low power (res = 0, odr 25hz) 100 s tandby 10 output low voltage (v io < 2v) 1 v - - 0. 2 * v io output low voltage (v io > 2v) 1 v - - 0.4 output high voltage v 0.8 * v io - - input low voltage v - - 0.2 * v io input high voltage v 0.8 * v io - - input pull - down current a 0 sta rt up time 2 res = 0 ms 0.050 res = 1, odr = 12.5hz 81 res = 1, odr = 25 hz 41 res = 1, odr = 50hz 21 res = 1, odr = 100hz 11 res = 1, odr = 200hz 6 res = 1, odr = 400hz 4 res = 1, odr = 800hz 2.5 power up tim e 3 ms 10 i 2 c communication rate khz 400 output data rate (odr) 4 hz 12.5 50 800 bandwidth ( - 3db) 5 res = 0 khz 1.59 res = 1 hz odr/2 notes: 1. for i 2 c communication, this assumes a minimum 1.5 k pull - up resistor on scl and sda pins. 2. start up time is from pc1 set to valid outputs. 3. power up time is from vdd valid to device boot completion. 4. user selectable through i 2 c . 5. user selectable and dependant on odr and res.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 5 of 54 table 3 . environmental pa rameters units min typical max supply voltage (v dd ) absolute limits v - 0.5 - 3.63 operating temperature range o c - 40 - 85 storage temperature range o c - 55 - 150 mech. shock (powered and unpowered) g - - 5000 for 0.5ms 10000 for 0.2ms esd hbm v - - 2000 caution: esd sensitive and mechanical shock sensitive component, improper handling can cause permanent damage to the device. this product conforms to directive 2002/95/ec of the european parliament and of the council of the european union (rohs). specifically, this product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (pbb), or polybrominated diphenyl ethers (pbde) above the maximum concentration values (mcv) by weight in any of its homogenous materials. homogenous materials are "of uniform composition throughout." this product is halogen - free per iec 61249 - 2 - 21. specifically, the materials used in this product contain a maximum total halogen content of 1500 ppm with less than 900 - ppm bromin e and less than 900 - ppm chlorine. soldering soldering recommendations are available upon request or from www.kionix.com . hf
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 6 of 54 application schematic table 4 . kxti9 pin descriptions pin name description 1 io vdd the power supply input for the digital communication bus . optionally d ecouple this pin to ground with a 0.1uf ceramic capacitor. 2 dnc reserved C do not connect 3 dnc reserved C do not connect 4 gnd ground 5 vdd the power supply input. decouple t his pin to ground with a 0.1uf ceramic capacitor. 6 d nc reserved C float or c onnect to io vdd 7 in t physical interrup t 8 d nc reserved C do not connect 9 scl i 2 c serial clock 10 sda i 2 c serial data 1 2 3 4 5 6 7 8 9 1 0 v d d c 1 s c l s d a k x t i 9 i n t i o v d d c 2
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 7 of 54 test specifications ! special characteristics : t hese characteristics have been identified as being critical to the customer. every part is tested to verify its conformance to specification prior to shipment. table 5 . test specifications parameter specification test conditions zero - g offset @ rt 0 +/ - 128 counts 25c, vdd = 2.6 v sensitivity @ rt 1024 +/ - 35.8 counts/g 25c, vdd = 2.6 v
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 8 of 54 package dimensions and orientation 3 x 3 x 0.9 mm lga all dimensions and tolerances conform to asme y14.5m - 1994
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 9 of 54 orientation when device is a ccelerated in +x, +y or +z direction, the corresponding output will increase. static x/y/z output response versus orientation to earths surface (1g): gsel1=0, gsel0=0 ( 2g) position 1 2 3 4 5 6 diagram top bottom botto m top resolution (bits) ddas((b (bits) 12 8 12 8 12 8 12 8 12 8 12 8 x (counts) 0 0 1024 64 0 0 - 1024 - 64 0 0 0 0 y (counts) 1024 64 0 0 - 1024 - 64 0 0 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 1024 64 - 1024 - 64 x - polar ity 0 + 0 - 0 0 y - polarity + 0 - 0 0 0 z - polarity 0 0 0 0 + - (1g) earth?s surface pin 1 +x +y +z
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 10 of 54 static x/y/z output response versus orientation to earths surface (1g): gsel1=0, gsel0=1 ( 4g) position 1 2 3 4 5 6 diagram t op bottom bottom top resolution (bits) 12 8 12 8 12 8 12 8 12 8 12 8 x (counts) 0 0 512 32 0 0 - 512 - 32 0 0 0 0 y (counts) 512 32 0 0 - 512 - 32 0 0 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 512 32 - 512 - 32 x - polarity 0 + 0 - 0 0 y - polarity + 0 - 0 0 0 z - polarity 0 0 0 0 + - (1g) earth?s surface static x/y/z output response versus orientation to earths surface (1g): gsel1=1, gsel0=0 ( 8g) position 1 2 3 4 5 6 diagram top bottom bottom top resolution (bits) 12 8 12 8 12 8 12 8 12 8 12 8 x (counts) 0 0 256 16 0 0 - 256 - 16 0 0 0 0 y (counts) 256 16 0 0 - 256 - 16 0 0 0 0 0 0 z (counts) 0 0 0 0 0 0 0 0 0 256 16 - 256 - 16 x - polarity 0 + 0 - 0 0 y - polarity + 0 - 0 0 0 z - polarity 0 0 0 0 + - (1g) earth?s surface
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 11 of 54 kxti9 digital interface the kionix kxti9 digital accelerometer has the ability to communicate on the i 2 c digital serial interface bus . this flexibil ity allows for easy system integration by eliminating analog - to - digital converter requirements and by providing direct communication with system micro - controllers. in doing so, all of the digital communication pins have shared responsibilities. the ser ial interface terms and desc riptions as indicated in table 6 below will be observed throughout this document. term description transmitter the device that transmits data to the bus. receiver the device that receives data from the bus. master the device that initiates a transfer, generates clock signals, and terminates a transfer. slave the device addressed by the master. table 6 . serial interface terminologies i 2 c serial interface as previously mentioned, the kxti9 has the ability to communicate o n an i 2 c bus. i 2 c is primarily used for synchronous serial communication between a master device and one or more slave devices. the master, typically a micro controller, provides the serial clock signal and addresses slave devices on the bus. the kxti9 always operates as a slave device during standard master - slave i 2 c operation. i 2 c is a two - wire serial interface that contains a serial clock (scl) line and a serial data (sda) line. scl is a serial clock that is provided by the master, but can be held l ow by any slave device, putting the master into a wait condition. sda is a bi - directional line used to transmit and receive data to and from the interface. data is transmitted msb (most significant bit) first in 8 - bit per byte format, and the number of b ytes transmitted per transfer is unlimited. the i 2 c bus is considered free when both lines are high. i 2 c operation transactions on the i 2 c bus begin after the master transmits a start condition (s), which is defined as a high - to - low transition on the data line while the scl line is held high. the bus is considered busy after this condition. the next byte of data transmitted after the start condition contains the slave address (sad) in the seven msbs (most significant bits), and the lsb (least signif icant bit) tells whether the master will be receiving data ?1? from the slave or transmitting data ?0? to the slave. when a slave address is sent, each device on the bus compares the seven msbs with its internally stored address. if they match, the devic e considers itself addressed by the master. the slave address asso ciated with the kxti9 is 0001111 .
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 12 of 54 it is mandatory that receiving devices acknowledge (ack) each transaction. therefore, the transmitter must release the sda line during this ack pulse. the receiver then pulls the data line low so that it remains stable low during the high period of the ack clock pulse. a receiver that has been addressed, whether it is master or slave, is obliged to generate an ack after each byte of data has been receiv ed. to conclude a transaction, the master must transmit a stop condition (p) by transitioning the sda line from low to high while scl is high. the i 2 c bus is now free. writing to a kxti9 8 - bit register upon power up, the master must write to the kxti9 ?s control registers to set its operational mode. therefore, when writing to a control register on the i 2 c bus, as shown sequence 1 on the following page, the following protocol must be observed: after a start condition, sad+w transmission, and the kxti9 ack has been returned, an 8 - bit register address (ra) command is transmitted by the master. this command is telling the kxti9 to which 8 - bit register the master will be writing the data. since this is i 2 c mode, the msb of the ra command should always be zero (0). the kxti9 acknowledges the ra and the master transmits the data to be stored in the 8 - bit register. the kxti9 acknowledges that it has received the data and the master transmits a stop condition (p) to end the data transfer. the data sent to the kxti9 is now stored in the appropriate register. the kxti9 automatically increments the received ra commands and, therefore, multiple bytes of data can be written to sequential registers after each slave ack as shown in sequence 2 on the following pag e. reading from a kxti9 8 - bit register when reading data from a kxti9 8 - bit register on the i 2 c bus, as shown in sequence 3 on the next page, the following protocol must be observed: the master first transmits a start condition (s) and the appropriate s lave address (sad) with the lsb set at ?0? to write. the kxti9 acknowledges and the master transmits the 8 - bit ra of the register it wants to read. the kxti9 again acknowledges, and the master transmits a repeated start condition (sr). after the repeate d start condition, the master addresses the kxti9 with a ?1? in the lsb (sad+r) to read from the previously selected register. the slave then acknowledges and transmits the data from the requested register. the master does not acknowledge (nack) it recei ved the transmitted data, but transmits a stop condition to end the data transfer. note that the kxti9 automatically increments through its sequential registers, allowing data to be read from multiple registers following a single sad+r command as shown be low in sequence 4 on the following page. if a receiver cannot transmit or receive another complete byte of data until it has performed some other function, it can hold scl low to force the transmitter into a wait state. data transfer only continues whe n the receiver is ready for another byte and releases scl.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 13 of 54 data transfer sequences the following information clearly illustrates the variety of data transfers that can occur on the i 2 c bus and how the master and slave interact during these transfer s. table 7 defines the i 2 c terms used during the data transfers. term definition s start condition sr repeated start condition sad slave address w write bit r read bit ack acknowledge nack not acknowledge ra register address data transmitted/ received data p stop condition table 7 . i 2 c terms sequence 1. the master is writing one byte to the slave. master s sad + w ra data p slave ack ack ack sequence 2. the master is writing multiple bytes to the slave. master s sad + w ra data data p slave ack ack ack ack sequence 3. the master is receiving one byte of data from the slave. master s sad + w ra sr sad + r nack p slave ack ack ack data sequence 4. the master is receivi ng multiple bytes of data from the slave. master s sad + w ra sr sad + r ack nack p slave ack ack ack data data
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 14 of 54 kxti9 embedded registers the kxti9 has 44 embedded 8 - bit registers that are accessible by the user. this secti on contains the addresses for all embedded registers and also describes bit functions of each register. table 8 below provides a listing of the accessible 8 - bit registers and their addresses. register name type i2c address read/write hex binary xout_hpf_l r 0x00 0000 0000 xout_hpf_h r 0x01 0000 0001 yout_hpf_l r 0x02 0000 0010 yout_hpf_h r 0x03 0000 0011 zout_hpf_l r 0x04 000 0 0100 zout_hpf_h r 0x05 0000 0101 xout_l r 0x06 0000 0110 xout_h r 0x07 0000 0111 yout_l r 0x08 0000 1000 yout_h r 0x09 0000 1001 zout_l r 0x0a 0000 1010 zout_h r 0x0b 0000 1011 dcst _resp r 0x0c 0000 1100 not used - 0x0d 0000 1101 not used - 0x0e 0000 1110 who_am_i r 0x0f 0000 1111 tilt_pos_cur r 0x10 0001 0000 tilt_pos_pre r 0x11 0001 0001 kio nix reserved - 0x12 0001 0010 kionix reserved - 0x13 0001 0011 kionix reserved - 0x14 0001 0100 int_src_reg1 r 0x15 0001 0101 int_src_reg2 r 0x16 0001 0110 not used - 0x17 0001 0111 status_reg r 0x18 0001 1000 not used - 0x19 0001 1001 int_rel r 0x 1a 0001 1010 ctrl_reg1 * r/w 0x1b 0001 1011 ctrl_reg2 * r/w 0x1c 0001 1100
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 15 of 54 ctrl_reg3 * r/w 0x1d 0001 1101 int_ctrl_reg1 * r/w 0x1e 0001 1110 int_ctrl_reg2 * r/w 0x1f 0001 1111 int_ctrl_reg3 * r/w 0x20 0010 0000 data_ctrl_reg * r/w 0x21 0010 0001 not used - 0x22 C 0x27 - tilt_timer * r/w 0x28 0010 1000 wuf_timer * r/w 0x29 0010 1001 not used - 0x2a 0010 1010 tdt_timer * r/w 0x2b 0010 1011 tdt_h_thresh * r/w 0x2c 0010 1100 tdt_l_thresh * r/w 0x2d 0010 1101 tdt_tap_timer * r/w 0x2e 0010 1110 tdt_total_timer * r/w 0x2f 0010 1111 tdt_latency_timer * r/w 0x30 0011 0000 tdt_window_timer * r/w 0x31 0011 0001 buf_ctrl1* r/w 0x32 0011 0010 buf_ctrl2* r/w 0x33 0011 0011 buf_status_reg1 r 0x34 0011 0100 buf_status_reg2 r 0x35 0011 0101 buf_clear w 0x36 0011 0110 reserved - 0x37 C 0x3 9 - self_test r/w 0x3a 0011 1010 reserved - 0x3b C 0x59 - wuf_thresh * r/w 0x5a 0101 1010 reserved - 0x5b 0101 1011 tilt_angle * r/w 0x5c 0101 1100 reserved - 0x5d C 0x5e - hyst_set * r/w 0x 5 f 0101 1111 buf_read r 0x7 f 01 11 1111 * note: when changing the contents of these registers, the pc1 bit in ctrl_reg1 must first be set to 0. table 8 . kxti9 register map
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 16 of 54 kxti9 register descriptions accelerometer outputs these registers contain up to 12 - bits of valid acceleration d ata for each axis depending on the setting of the res bit in ctrl_reg1, where the acceleration outputs are represented in 12 - bit valid data when res = ?1? and 8 - bit valid data when res = ?0?. the data is updated every user - defined odr period, is protected from overwrite during each read, and can be converted from digital counts to acceleration (g) per figure 1 below. the register acceleration output binary data is represented in n - bit 2?s complement format. for example, if n = 12 bits, then the counts ran ge is from - 2048 to 2047, and if n = 8 bits, then the counts range is from - 128 to 127. 12 - bit register data (2s complement) equivalent counts in d ecimal range = +/ - 2g range = +/ - 4g range = +/ - 8g 0111 1111 1111 2047 +1.999g +3.998g +7.996g 0111 1111 1110 2046 +1.998g +3.996g +7.992g 8 - bit register data (2s complement) equivalent counts in decimal range = +/ - 2g range = +/ - 4g range = +/ - 8g 0111 1111 127 +1.984g +3.968g +7.936g 0111 1110 126 +1.968g +3.936g +7.872g figure 1 . acceleration (g) calculation
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 17 of 54 note: the high pass filter outputs are only avai lable if the wake up function is enabled. xout_hpf_l x - axis high - pass filtered accelerometer output least significant byte r r r r r r r r xoutd3 xoutd2 xoutd1 xoutd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x00h xout _hpf_h x - axis high - pass filtered accelerometer output most significant byte r r r r r r r r xoutd11 xoutd10 xoutd9 xoutd8 xoutd7 xoutd6 xoutd5 xoutd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x01h yout_hpf_l y - axis high - pass fi ltered accelerometer output least significant byte r r r r r r r r youtd3 youtd2 youtd1 youtd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x02h yout_hpf_h y - axis high - pass filtered accelerometer output most significant byt e r r r r r r r r youtd11 youtd10 youtd9 youtd8 youtd7 youtd6 youtd5 youtd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x03h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 18 of 54 zout_hpf_l z - axis high - pass filtered accelerometer output least significant byte r r r r r r r r zout d3 zoutd2 zoutd1 zoutd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x04h zout_hpf_h z - axis high - pass filtered accelerometer output most significant byte r r r r r r r r zoutd11 zoutd10 zoutd9 zoutd8 zoutd7 zoutd6 zoutd5 zoutd 4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x05h xout_l x - axis accelerometer output least significant byte r r r r r r r r xoutd3 xoutd2 xoutd1 xoutd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x06h xout_h x - axis accelerometer output most significant byte r r r r r r r r xoutd11 xoutd10 xoutd9 xoutd8 xoutd7 xoutd6 xoutd5 xoutd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x07h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 19 of 54 yout_l y - axis accelerometer output least sign ificant byte r r r r r r r r youtd3 youtd2 youtd1 youtd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x08h yout_h y - axis accelerometer output most significant byte r r r r r r r r youtd11 youtd10 youtd9 youtd8 youtd7 yout d6 youtd5 youtd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x09h zout_l z - axis accelerometer output least significant byte r r r r r r r r zoutd3 zoutd2 zoutd1 zoutd0 x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c addres s: 0x0ah zout_h z - axis accelerometer output most significant byte r r r r r r r r zoutd11 zoutd10 zoutd9 zoutd8 zoutd7 zoutd6 zoutd5 zoutd4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x0bh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 20 of 54 dcst_resp this register can be us ed to verify proper integrated circuit functionality. it always has a byte value of 0x55h unless the dcst bit in ctrl_reg3 is set. at that point this value is set to 0xaah. the byte value is returned to 0x55h after reading this register. r r r r r r r r dcstr7 dcstr6 dcstr5 dcstr4 dcstr3 dcstr2 dcstr1 dcstr0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01010101 i 2 c address: 0x0ch who_am_i this register can be used for supplier recognition, as it can be factory written to a known b yte value. the default value is 0x 04 h. r r r r r r r r wia7 wia6 wia5 wia4 wia3 wia2 wia1 wia0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000100 i 2 c address: 0x0fh tilt position registers these two registers report previous an d current tilt position data that is updated at the user - defined odr frequency and is protected during register read. table 9 describes the reported position for each bit value. tilt_pos_cur current tilt position register r r r r r r r r 0 0 le ri d o up fd fu reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00100000 i 2 c address: 0x10h tilt_pos_pre previous tilt position register r r r r r r r r 0 0 le ri do up fd fu reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00100000 i 2 c address: 0x11h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 21 of 54 bit description le left state (x - ) ri right state (x+) do down state (y - ) up up state (y+) fd face - down state (z - ) fu face - up state (z+) table 9 . kxti9 tilt position interrupt source registers these two registers report function state changes. this data is updated when a new state change or event occurs and each application?s result is latched until the interrupt release register is read. the motion interrupt bit wufs can be configured to report data in an unlat ched manner via the interrupt control registers. int_src_reg1 this register reports which axis and direction detected a single or double tap event, per table 1 0 . r r r r r r r r 0 0 tle tri tdo tup tfd tfu bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x15h bit description tle x negative (x - ) reported tri x positive (x+) reported tdo y negative (y - ) reported tup y positive (y+) reported tfd z negative (z - ) reported tfu z positive (z+) reported table 1 0 . kxti9 directional t ap tm reporting
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 22 of 54 int_src_reg2 this register reports which function caused an interrupt. reading from the interrupt release register will clear the entire contents of this register. r r r r r r r r 0 0 wmi drdy tdts1 tdts0 wufs tps bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x16h drdy indicates that new acceleration data is available. this bit is cleared when acceleration data is read or the interrupt release register is read. drdy = 0 C new acceleration data not available drdy = 1 C new acceleration data available tdts1, tdts0 indicates whether a single or double - tap event was detected per table 1 1 . tdts1 tdts0 event 0 0 no tap 0 1 single tap 1 0 double tap 1 1 dne table 1 1 . directional tap tm event description tps refl ects the status of the tilt position function. tps = 0 C tilt position state has not changed tps = 1 C tilt position state has changed wmi indicates that the buffers sample threshold has been exceeded when in fifo, filo, or stream mode. not used in tr igger mode. wmi = 0 C sample threshold has not been exceeded wmi = 1 C sample threshold has been exceeded status_reg this register reports the status of the interrupt. r r r r r r r r 0 0 0 int 0 0 0 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x18h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 23 of 54 int reports the combined interrupt information of all enabled functions. this bit is released to 0 when the interrupt source latch register (1ah) is read. int = 0 C no interrupt event int = 1 C interrupt event has occurred int _rel latched interrupt source information (int_src_reg1 and int_src_reg2), the status register, and t he physical interrupt pin (7) are cleared when reading this register. r r r r r r r r x x x x x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c addr ess: 0x1ah ctrl_reg1 read/write control register that controls the main feature set. r/w r/w r/w r/w r/w r/w r/w r/w pc1 res drdye gsel1 gsel0 tdte wufe tpe reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x1bh pc1 controls the operating mode of the kxti9. pc1 = 0 - stand - by mode pc1 = 1 C operating mode res determines the performance mode of the kxti9. note that to change the value of this bit, the pc1 bit must first be set to 0. res = 0 C low current, 8 - bit valid res = 1 - high current, 12 - bit valid drdye enables the reporting of the availability of new acceleration data on the interrupt. note that to change the value of this bit, the pc1 bit must first be set to 0. drdye = 0 C availab ility of new acceleration data not reflected on interrupt pin (7) drdye = 1 - availability of new acceleration data reflected on interrupt pin (7) gsel1, gsel0 selects the acceleration range of the accelerometer outputs per table 1 2 . note that to change t he value of this bit, the pc1 bit must first be set to 0.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 24 of 54 gsel1 gsel0 range 0 0 +/ - 2g 0 1 +/ - 4g 1 0 +/ - 8g 1 1 na table 1 2 . selected acceleration range tdte enables the directional tap tm function that will detect single and double tap events. n ote that to change the value of this bit, the pc1 bit must first be set to 0. tdte = 0 C disable tdte = 1 - enable wufe enables the wake up (motion detect) function that will detect a general motion event. note that to change the value of this bit, th e pc1 bit must first be set to 0. wufe = 0 C disable wufe = 1 - enable tpe enables the tilt position function that will detect changes in device orientation. note that to change the value of this bit, the pc1 bit must first be set to 0. tpe = 0 C disable tpe = 1 - enable ctrl_reg2 read/write control register that primarily controls tilt position state enabling. per table 1 3 , if a state?s bit is set to one (1), a transition into the corresponding orientation state will generate an interrupt. if it is set to zero (0), a transition into the corresponding orientation state will not generate an interrupt. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w otd th 0 lem rim dom upm fdm fum reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00111111 i 2 c address: 0x1ch
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 25 of 54 otdth determines the range of the directional tap tm output data rate (odr). see table 1 5 for additional clarification. otdth = 0 C slower range of directional tap tm odrs are available. o t dth = 1 C faster range of directional tap tm odrs are available. bit description lem left state rim right state dom down state upm up state fdm face - down state fum face - up state ta ble 1 3 . tilt position state enabling ctrl_reg3 read/write control register that provides more feature set control. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w srst otpa otpb dcst otdta otdtb owufa owufb reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01001101 i 2 c address: 0x1dh srst initiates software reset, which performs the ram reboot routine. this bit will remain 1 until the ram rebo ot routine is finished. srst = 0 C no action srst = 1 C start ram reboot routine note for i2c communication: setting srst = 1 will not result in an ack, since the part immediately enters the ram reboot routine. nack may be used to confirm this command. otpa, otpb sets the output data rate for the tilt position function per table 1 4 . the default tilt position odr is 12.5hz.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 26 of 54 otpa otpb output data rate 0 0 1.6hz 0 1 6.3hz 1 0 12.5hz 1 1 50hz table 1 4 . tilt position function output data rate d cst initiates the digital communication self - test function. dcst = 0 C no action dcst = 1 C sets st_resp register to 0xaah and when st_resp is read, sets this bit to 0 and sets st_resp to 0x55h otdta, otdtb sets the output data rate for the directional tap tm function per table 1 5 . the default directional tap tm odr is 400hz. otdth otdta otdtb output data rate 0 0 0 50hz 0 0 1 100hz 0 1 0 200hz 0 1 1 400hz 1 0 0 12.5hz 1 0 1 25hz 1 1 0 800hz 1 1 1 1600hz table 1 5 . directional tap tm functio n output data rate owufa, owufb sets the output data rate for the general motion detection function and the high - pass filtered outputs per table 1 6 . the default motion wake up odr is 50hz.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 27 of 54 owufa owufb output data rate 0 0 25hz 0 1 50hz 1 0 100 hz 1 1 200hz table 1 6 . motion wake up function output data rate int_ctrl_reg1 this register controls the settings for the physical interrupt pin (7). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set t o 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 0 ien iea iel ieu 0 0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00010000 i 2 c address: 0x1eh ien enables/disables the physical interrupt pin (7) ien = 0 C physical interrupt pin (7) is disabled ien = 1 C physical interrupt pin (7) is enabled iea sets the polarity of the physical interrupt pin (7) iea = 0 C polarity of the physical interrupt pin (7) is active low iea = 1 C polarity of the physical interrupt pin (7) is active high iel sets the response of the physical interrupt pin (7) iel = 0 C the physical interrupt pin (7) latches until it is cleared by reading int_rel iel = 1 C the physical interrupt pin (7) will transmit one pulse with a period of approximately 0.03 - 0. 05ms ieu sets an alternate unlatched response for the physical interrupt pin (7) when the motion interrupt feature (wuf) only is enabled. ieu = 0 C the physical interrupt pin (7) latches or pulses per the iel bit until it is cleared by reading int_rel ieu = 1 C the physical interrupt pin (7) will follow an unlatched response if the motion interrupt feature is enabled
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 28 of 54 int_ctrl_reg2 this register controls motion detection axis enabling. per table 1 7 , if an axis? bit is set to one (1), a motion on th at axis will generate an interrupt. if it is set to zero (0), a motion on that axis will not generate an interrupt. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w xbw ybw zbw 0 0 0 0 0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 11100000 i 2 c address: 0x1fh bit description xbw x - axis motion ybw y - axis motion zbw z - axis motion table 1 7 . motion detection axis enabling int_ctrl_re g3 this register controls the tap detection direction axis enabling. per table 1 8 , if a direction?s bit is set to one (1), a single or double tap in that direction will generate an interrupt. if it is set to zero (0), a single or double tap in that dire ction will not generate an interrupt. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 tmen tlem trim tdom tupm tfdm tfum reset value bit7 bit6 bit5 bit4 bi t3 bit2 bit1 bit0 00111111 i 2 c address: 0x20h bit description tlem x negative (x - ) trim x positive (x+) tdom y negative (y - ) tupm y positive (y+) tfdm z negative (z - ) tfum z positive (z+) table 18 . directional tap tm axis mask
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 29 of 54 tmen enables/disables alternate tap masking scheme tmen = 0 C alternate tap masking scheme disabled tmen = 1 C alternate tap masking scheme enabled data_ctrl_reg read/write control register that configures the acceleration outputs. note that to pro perly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w 0 0 hpfroa hprob 0 osaa osab osac reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000010 i 2 c address: 0x21h hpfroa, hpfrob sets the roll - off frequency for the first - order high - pass filter in conjunction with the output data rate (owufa, owufb) that is chosen for the hpf acceleration outputs that are used in the motion wake up (wuf) application per table 19 . n ote that this roll - off frequency is also applied to the x, y and z high - pass filtered outputs. high - pass filter configuration hpfroa hpfrob beta hpf roll - off (hz) 0 0 7/8 odr / 50 0 1 15/16 odr / 100 1 0 31/32 odr / 200 1 1 63/64 odr / 400 table 1 9 . high - pass filter roll - off frequency osaa, osab, osac sets the output data rate (odr) for the low - pass filtered acceleration outputs per table 2 0 .
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 30 of 54 osaa osab osac output data rate lpf roll - off 0 0 0 12.5hz 6.25hz 0 0 1 25hz 12.5hz 0 1 0 50hz 25 hz 0 1 1 100hz 50hz 1 0 0 200hz 100hz 1 0 1 400hz 200hz 1 1 0 800hz 400hz 1 1 1 does not exist does not exist table 2 0 . lpf acceleration output data rate (odr) tilt_timer this register is the initial count register for the tilt position state time r (0 to 255 counts). every count is calculated as 1/odr delay period, where the tilt position odr is user - defined per table 1 4 . a new state must be valid as many measurement periods before the change is accepted. note that to properly change the value o f this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w tsc7 tsc6 tsc5 tsc4 tsc3 tsc2 tsc1 tsc0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x28h wuf_timer this reg ister is the initial count register for the motion detection timer (0 to 255 counts). every count is calculated as 1/odr delay period, where the motion wake up odr is user - defined per table 1 6 . a new state must be valid as many measurement periods before the change is accepted. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w wufc7 wufc6 wufc5 wufc4 wufc3 wufc2 wufc1 wufc0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x29h tdt_timer this register contains counter information for the detection of a double tap event. when the directional tap tm odr is 400hz or less, every count is calculated as 1/odr delay period. when t he directional tap tm odr is 800hz, every count is calculated as 2/odr delay period. when the directional tap tm odr is 1600hz, every count is calculated as 4/odr delay period. the directional tap tm odr is user -
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 31 of 54 defined per table 1 5 . tdt_timer represents t he minimum time separation between the first tap and the second tap in a double tap event. the kionix recommended default value is 0.3 seconds (0x78h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w tdtc7 tdtc6 tdtc5 tdtc4 tdtc3 tdtc2 tdtc1 tdtc0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01111000 i 2 c address: 0x2bh tdt_h_thresh this register represents the 8 - bit jerk high threshold to det ermine if a tap is detected. though this is an 8 - bit register, the kxti9 internally multiplies the register value by two in order to set the high threshold. this multiplication results in a range of 0d to 510d with a resolution of two counts. the perfor mance index (pi) is the jerk signal that is expected to be less than this threshold, but greater than the tdt_l_thresh threshold during single and double tap events. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must fi rst be set to 0. the kionix recommended default value is 203 (0xcbh) and the performance index is calculated as: x? = x(current) C x(previous) y? = y(current) C y(previous) z? = z(current) C z(previous) pi = |x?| + |y?| + |z?| equation 1. performance index r/w r/w r/w r/w r/w r/w r/w r/w tth7 tth6 tth5 tth4 tth3 tth2 tth1 tth0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 11001011 i 2 c address: 0x2ch
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 32 of 54 tdt_l_thresh this register represents the 8 - bit (0d C 255d) jerk low threshold t o determine if a tap is detected. the performance index (pi) is the jerk signal that is expected to be greater than this threshold and less than the tdt_h_thresh threshold during single and double tap events. this register also contains the lsb of the td t_h_thresh threshold. the kionix recommended default value is 26 (0x1ah). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w tth7 ttl6 ttl5 ttl4 ttl3 ttl2 ttl1 t tl0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00011010 i 2 c address: 0x2dh tdt_tap_timer this register contains counter information for the detection of any tap event. when the directional tap tm odr is 400hz or less, every count is calculated as 1/odr delay period. when the directional tap tm odr is 800hz, every count is calculated as 2/odr delay period. when the directional tap tm odr is 1600hz, every count is calculated as 4/odr delay period. the directional tap tm odr is user - defi ned per table 1 5 . in order to ensure that only tap events are detected, these time limits are used. a tap event must be above the performance index threshold (tdt_thresh) for at least the low limit (ftdl0 C ftdl2) and no more than the high limit (ftdh0 C ftdh4). the kionix recommended default value for the high limit is 0.05 seconds and for the low limit is 0.005 seconds (0xa2h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/ w r/w r/w r/w r/w ftdh4 ftdh3 ftdh2 ftdh1 ftdh0 ftdl2 ftdl1 ftdl0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10100010 i 2 c address: 0x2eh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 33 of 54 tdt_total_timer this register contains counter information for the detection of a double tap event. when the directional tap tm odr is 400hz or less, every count is calculated as 1/odr delay period. when the directional tap tm odr is 800hz, every count is calculated as 2/odr delay period. when the directional tap tm odr is 1600hz, every count is c alculated as 4/odr delay period. the directional tap tm odr is user - defined per table 1 5 . in order to ensure that only tap events are detected, this time limit is used. this register sets the total amount of time that the two taps in a double tap event c an be above the pi threshold (tdt_l_thresh). the kionix recommended default value for tdt_total_timer is 0.09 seconds (0x24h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w std7 std6 std5 std4 std3 std2 std1 std0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00100100 i 2 c address: 0x2fh tdt_latency_timer this register contains counter information for the detection of a tap event. when the directional tap tm odr is 400hz or less, every count is calculated as 1/odr delay period. when the directional tap tm odr is 800hz, every count is calculated as 2/odr delay period. when the directional tap tm odr is 1600hz, every count is calculated as 4/od r delay period. the directional tap tm odr is user - defined per table 1 5 . in order to ensure that only tap events are detected, this time limit is used. this register sets the total amount of time that the tap algorithm will count samples that are above t he pi threshold (tdt_l_thresh) during a potential tap event. it is used during both single and double tap events. however, reporting of single taps on the physical interrupt pin (7) will occur at the end of the tdt_window_timer. the kionix recommended d efault value for tdt_latency_timer is 0.1 seconds (0x28h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w tlt7 tlt6 tlt5 tlt4 tlt3 tlt2 tlt1 tlt0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00101000 i 2 c address: 0x30h tdt_window_timer this register contains counter information for the detection of single and double taps. when the directional tap tm odr is 400hz or less, every count is cal culated as 1/odr delay period. when the directional tap tm odr is 800hz, every count is calculated as 2/odr delay period. when the directional tap tm odr is 1600hz, every count is calculated as 4/odr delay period. the directional tap tm odr is user - defined per table 1 5 . it defines the time window for the entire tap event, single or double, to occur. reporting of single taps on the physical interrupt pin (7) will occur at the end of this tap window. the kionix recommended default value for tdt_window_time r is 0.4 seconds
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 34 of 54 (0xa0h). note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w tws7 tws6 tws5 tws4 tws3 tws2 tws1 tws0 reset value bit7 bit6 bit5 bit4 bit3 bit2 b it1 bit0 10100000 i 2 c address: 0x31h buf_ctrl1 read/write control register that controls the buffer sample threshold. r/w r/w r/w r/w r/w r/w r/w r/w - smp_th6 smp_th5 smp_th4 smp_th3 smp_th2 smp_th1 smp_th0 reset value bit7 bit6 bit5 bi t4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x32h smp_th[6:0] sample threshold ; determines the number of samples that will trigger a watermark interrupt or will be saved prior to a trigger event. when buf_res=1, the maximum number of sample s is 41; when buf_res=0, the maximum number of samples is 84. buffer model sample function bypass none fifo specifies how many buffer sample are needed to trigger a watermark interrupt. stream specifies how many buffer samples are needed to trigger a watermark interrupt. trigger specifies how many buffer samples before the trigger event are retained in the buffer. filo specifies how m any buffer samples are needed to trigger a watermark interrupt. table 2 1 . sample threshold operation by buffer mod e
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 35 of 54 buf_ctrl2 read/write control register that controls sample buffer operation. r/w r/w r/w r/w r/w r/w r/w r/w bufe buf_res 0 0 0 0 buf_m1 buf_m0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x33h bufe cont rols activation of the sample buffer. bufe = 0 C sample buffer inactive bufe = 1 C sample buffer active buf_res determines the resolution of the acceleration data samples collected by the sample buffer. buf_res = 0 C 8 - bit samples are accumulated in the buffer buf_res = 1 C 12 - bit samples are accumulated in the buffer buf_m1, buf_m0 selects the operating mode of the sample buffer per table 2 2 . buf_m1 buf_m0 mode description 0 0 fifo the buffer collects 84 sets of 8 - bit low resolution values or 41 set s of 12bit high resolution values and then stops collecting data, collecting new data only when the buffer is not full. 0 1 stream the buffer holds the last 84 sets of 8 - bit low resolution values or 41 sets of 12bit high resolution values. once the buffe r is full, the oldest data is discarded to make room for newer data . 1 0 trigger when a trigger event occurs , the buffer holds the last data set o f smp[6:0] samples before the trigger event and then continues to collect data until full. new data is colle cted only when the buffer is not full. 1 1 filo the buffer holds the last 84 sets of 8 - bit low resolution values or 41 sets of 12bit high resolution values. once the buffer is full, the oldest data is discarded to make room for newer data. r ead ing from the buffer in this mode will return the most recent data first . table 2 2 . selected buffer mode
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 36 of 54 buf_status_reg1 this register reports the status of the sample buffer. r/w r/w r/w r/w r/w r/w r/w r/w smp_lev7 smp_lev6 smp_lev5 smp_lev4 smp_lev3 smp_l ev2 smp_lev1 smp_lev0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x34h smp_lev[7:0] sample level ; reports the number of data bytes that have been stored in the sample buffer. when buf_res=1, this count will increase by 6 for each 3 - axis sample in the buffer; when buf_res=0, the count will increase by 3 for each 3 - axis sample. if this register reads 0, no data has been stored in the buffer. buf_status_reg2 this register reports the status of the sample buffer trigger function. r/w r/w r/w r/w r/w r/w r/w r/w buf_trig 0 0 0 0 0 0 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x35h buf_trig reports the status of the buffers trigger function if this mode has been selected. when using trigger mode, a buffer rea d should only be performed after a trigger event. buf_clear latched buffer status information and the entire sample buffer are cleared when any data is written to this register. r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x bit7 bit6 bit5 bit4 bit3 b it2 bit1 bit0 i 2 c address: 0x36h
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 37 of 54 self_test when 0xca is written to this register, the mems self - test function is enabled. electrostatic - actuation of the accelerometer, results in a dc shift of the x, y and z axis outputs. writing 0x00 to thi s register will return the accelerometer to normal operation. r/w r/w r/w r/w r/w r/w r/w r/w 1 1 0 0 1 0 1 0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00000000 i 2 c address: 0x3ah wuf_thresh this register sets the acceleration t hreshold, wuf threshold that is used to detect a general motion input. wuf_thresh scales with gsel1 - gsel0 in ctrl_reg1, and the kxti9 will ship from the factory with this value set to correspond to a change in acceleration of 0.5g when configured to + / - 8g. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w wufth7 wufth6 wufth5 wufth4 wufth3 wufth2 wufth1 wufth0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00001000 i 2 c address: 0x5ah tilt_angle this register sets the tilt angle that is used to detect the transition from face - up/face - down states to screen rotation states. the kxti9 ships from the factory with tilt angle set to a low thresh old of 26 from horizontal. a different default tilt angle can be requested from the factory. note that the minimum suggested tilt angle is 10. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w ta7 ta6 ta5 ta4 ta3 ta2 ta1 ta0 reset value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 0000110 0 i 2 c address: 0x5ch
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 38 of 54 hyst_set this register sets the hysteresis that is placed in between the screen rotation state s. the kxti9 ships from the factory with hyst_set set to +/ - 15 of hysteresis. a different default hysteresis can be requested from the factory. note that when writing a new value to this register the current values of res0, res1 and res2 must be preser ved. these values are set at the factory and must not change. note that to properly change the value of this register, the pc1 bit in ctrl_reg1 must first be set to 0. r/w r/w r/w r/w r/w r/w r/w r/w res 2 res 1 res0 hyst4 hyst3 hyst2 hyst1 hyst0 re set value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 --- 101 00 i 2 c address: 0x 5 fh buf_read data in the buffer can be read according to the buf_res and buf_m settings in buf_ctrl2 by executing this command. more samples can be retrieved by contin uing to toggle scl after the read command is executed. data should only be read by set (6 bytes for high - resolution samples and 3 bytes for low - resolution samples) and by using auto - increment. additional samples cannot be written to the buffer while data is being read from the buffer using auto - increment mode. output data is in 2?s complement format. r/w r/w r/w r/w r/w r/w r/w r/w x x x x x x x x bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 i 2 c address: 0x7fh
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 39 of 54 kxti9 embedded applications orien tation detection feature the orientation detection feature of the kxti9 will report changes in face up, face down, +/ - vertical and +/ - horizontal orientation. this intelligent embedded algorithm considers very important factors that provide accurate o rientation detection from low cost tri - axis accelerometers. factors such as: hysteresis, device orientation angle and delay time are described below as these techniques are utilized inside the kxti9 . hysteresis a 45 tilt angle threshold seems like a go od choice because it is halfway between 0 and 90. however, a problem arises when the user holds the device near 45. slight vibrations, noise and inherent sensor error will cause the acceleration to go above and below the threshold rapidly and randomly , so the screen will quickly flip back and forth between the 0 and the 90 orientations. this problem is avoided in the kxti9 by choosing a 30 threshold angle. with a 30 threshold, the screen will not rotate from 0 to 90 until the device is tilted t o 60 (30 from 90). to rotate back to 0, the user must tilt back to 30, thus avoiding the screen flipping problem. this example essentially applies +/ - 15 of hysteresis in between the four s creen rotation states. table 2 3 shows the acceleration lim its implemented for t =30. orientation x acceleration (g) y acceleration (g) 0/360 - 0.5 < a x < 0.5 a y > 0.866 90 a x > 0.866 - 0.5 < a y < 0.5 180 - 0.5 < a x < 0.5 a y < - 0.866 270 a x < - 0.866 - 0.5 < a y < 0.5 table 23 . accele ration at the four orientations with +/ - 15 of hysteresis the kxti9 allows the user to change the amount of hysteresis in between the four screen rotation states. by simply writing to the hyst_set register, the user can adjust the amo unt of hysteresis u p to +/ - 45 . the plot in figure 2 shows the typical amount of hysteresis applied for a given digital count value of hyst_set .
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 40 of 54 figure 2 . hyst_set vs hysteresis device orientation angle (aka tilt angle) to ensure that horizontal and vertical device orientation changes are detected, even when it isn?t in the ideal vertical orientation C where the angle in figure 3 is 90, the kxti9 considers device orientation angle in its algorithm. figure 3 . device orientation angle as the angle in figure 3 is decreased, the maximum gravitational acceleration on the x - axis or y - axis will also decrease. therefore, when the angle becomes small enough, the user will not be able to make angle hyst_set vs hysteresis 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 hyst_set value (counts) hysteresis (+/- degrees) hysteresis
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 41 of 54 the screen orientation change. when the device orientation angle approaches 0 (device is flat on a desk or table), a x = a y = 0g, a z = +1g, and there is no way to determine which way the screen should be oriented, the internal algorithm determines that the device is in either the face - up or face - down orientation, depending on the s ign of the z - axis. the kxti9 will only change the screen orientation when the orientation angle is above the factory - defaulted/user - defined threshold set in the tilt_angle register. equation 2 can be used to determine what value to write to the tilt_ang le register to set the device orientation angle. tilt_angle (counts) = sin * (32 (counts/g) ) equation 2. tilt angle threshold tilt timer the 8 - bit register, tilt_timer can be used to qualify changes in orientation. the kxti9 does this by incrementing a counter with a size that is specified by the value in tilt_timer for each set of acceleration samples to verify that a change to a new orientation state is maintained. a user defined output data rate (odr) determines the time period for each sample. equation 3 shows how to calculate the tilt_timer register value for a des ired delay time. tilt_timer (counts) = delay time (sec) x odr (hz) equation 3. tilt position delay time motion interrupt feature description the motion interrupt feature of the kxti9 reports qualified changes in the high - pass filtered acceleration bas ed on the wake up (wuf) threshold. if the high - pass filtered acceleration on any axis is greater than the user - defined wake up threshold (wuf_thresh), the device has transitioned from an inactive state to an active state. when configured in the unlatched mode, the kxti9 will report when the motion event finished and the device has returned to an inactive state. equation 4 shows how to calculate the wuf_thresh register value for a desired wake up threshold. note that this calculation varies based on the configured g - range of the part. wuf_thresh (counts) = wake up threshold (g) x sensitivity (counts/g) equation 4. wake up threshold
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 42 of 54 a wuf (wuf_timer) 8 - bit raw unsigned value represents a counter that permits the user to qualify each active/inactive sta te change. note that each wuf timer count qualifies 1 (one) user - defined odr period (owuf). equation 5 shows how to calculate the wuf_timer register value for a desired wake up delay time. wuf_timer (counts) = wake up delay time (sec) x owuf (hz) equat ion 5. wake up delay time figure 4 below shows the latched response of the motion detection algorithm with wuf timer = 10 counts. figure 4 . latched motion interrupt response 0g typical motion interrupt example hpf acceleration wuf threshold ex: delay counter = 10 motion 10 inactive wuf timer
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 43 of 54 figure 5 below shows the unlatched response of the motion detection algorithm with wuf timer = 10 counts. figure 5 . unlatched motion interrupt response 0g typical motion interrupt example hpf acceleration wuf threshold ex: delay counter = 10 motion 10 inactive wuf timer
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 44 of 54 directional tap detection feature description the directional tap detection feature of the kxti9 rec ognizes single and double tap inputs and reports the acceleration axis and direction that each tap occurred. eight performance parameters, as well as a user - selectable odr are used to configure the kxti9 for a desired tap detection response. performan ce index the directional tap tm detection algorithm uses low and high thresholds to help determine when a tap event has occurred. a tap event is detected when the previously described jerk summation exceeds the low threshold (tdt_l_thresh) for more than the tap detection low limit, but less than the tap detection high limit as contained in tdt_tap_timer. samples that exceed the high limit (tdt_h_thr esh) will be ignored. figure 6 shows an example of a single tap event meeting the performance index crite ria. figure 6 . jerk summation vs threshold tdt_l_thresh : sampled data 3.14 3.15 3.16 3.17 3.18 3.19 3.2 3.21 0 20 40 60 80 100 120 140 160 180 calculated performance index time(sec) jerk (counts) pi
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 45 of 54 single tap detection the latency timer (tdt_latency_timer) sets the time period that a tap event will only be characterized as a single tap. a second tap has to occur outside of the latency timer. if a sec ond tap occurs inside the latency time, it will be ignored as it occurred too quickly. the single tap will be reported at the end of the tdt_window_timer. figure 7 shows a single tap event meeting the pi, latency and window requirements. figur e 7 . si ngle directional tap tm timing tdt_window_timer tdt_la tency_timer tdt_l_thresh 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 0 20 40 60 80 100 120 140 160 calculated performance index time(sec) jerk (counts) pi
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 46 of 54 double tap detection an event can be characterized as a double tap only if the second tap crosses the performance index (tdt_l_thresh) outside the tdt_timer. this means that the tdt_timer determines the minimum time sep aration that must exist between the two taps of a double tap event. similar to the single tap, the second tap event must exceed the performance index for the time limit contained in tdt_tap_timer. the double tap will be reported at the end of the seco nd tdt_latency_timer. figure 8 shows a double tap event meeting the pi, latency and window requirements. figure 8 . double directional tap tm timing tdt_window_timer tdt_timer tdt_latency_timer tdt_latency_timer tdt_l_thresh 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 0 50 100 150 200 calculated performance index time(sec) jerk (counts) pi
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 47 of 54 sample buffer feature description the sample buffer feature of the kxt i9 accumulates and outputs accelera tion data based on how it is configured. there are 4 buffer modes available, and samples can be accumulated at either low (8 - bit) or high (12 - bit) resolution. acceleration data is collected at the odr specified by osaa:osad in the output data control reg ister. each buffer mode accumulates data, reports data, and interacts with status indicators in a slightly different way. fifo mode data accumulation sample collection stops when the buffer is full. data reporting data is reported with the ol dest byte of the oldest sample first (x_l or x based on resolution). status indicators a watermark interrupt occurs when the number of samples in the buffer reaches the sample threshold . the watermark interrupt stays active until the buffer co ntains less than this number of samples. this can be accomplished through clearing the buffer or explicitly reading greater than smpx samples (calculated with equation 6). buf_res =0 : smpx = smp_lev[7:0] / 3 C smp_th[6:0] buf_ res =1 : smpx = smp_lev[7:0] / 6 C smp_th[6:0] equation 6. samples above sample threshold stream mode data accumulation sample collection continues when the buffer is full; older data is discarded to make room for newer data. data reporting d ata is reported with the oldest sample first (uses fifo read pointer). status indicators a watermark interrupt occurs when the number of samples in the buffer reaches the sample threshold . the watermark interrupt stays active until the buffer contains less than this number of samples. this can be accomplished through clearing the buffer or explicitly reading greater than smpx samples (calculated with equation 1).
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 48 of 54 trigger mode data accumulation when a physical interrupt is caused by o ne of the digital engines, the trigger event is asserted and smp[6:0] samples prior to the event are retained. sample collection continues until the buffer is full. data reporting data is reported with the oldest sample first (uses fifo read pointer) . status indicators when a physical interrupt occurs and there are at least smp[6:0] samples in the buffer, buf_trig in buf_status_reg2 is asserted. filo mode data accumulation sample collection continues when the buffer is full; older data is dis carded to make room for newer data. data reporting data is reported with the newest byte of the newest sample first (z_h or z based on resolution). status indicators a watermark interrupt occurs when the number of samples in the buffer reach es the sample threshold . the watermark interrupt stays active until the buffer contains less than this number of samples. this can be accomplished through clearing the buffer or explicitly reading greater than smpx samples (calculated with equat ion 1). buffer operation the following diagrams illustrate the operation of the buffer conceptually. actual physical implementation has been abstracted to offer a simplified explanati on of how the different buffer modes operate. figure 9 represents a h igh - resolution 3 - axis samp le w ithin the buffer. figures 10 - 18 represent a 10 - sample version of the buffer (for simplicity), with sample threshold set to 8. regardless of the selected mode, the buffer fills sequentially, one byte at a time. fi gure 9 sh ows one 6 - byte data sample. note the location of the filo read pointer versus that of the fifo read pointer.
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 49 of 54 index byte 0 x_l < ---- fifo read pointer 1 x_h 2 y_l 3 y_h 4 z_l 5 z_h < ---- filo read pointer buffer write pointer ---- > 6 figure 9 . one buffer sample regardless of the selected mode, the buffer fills sequentially, one samp le at a time. note in figure 10 the location of the filo read pointer versus that of the fifo read pointer. the buffer write pointer shows w here the next sample will be written to the buffer. index sample 0 data0 1 data1 2 data2 buffer write pointer 4 5 6 7 8 9 figure 10 . buffer filling
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 50 of 54 the buffer continues to fill sequentially until the sample threshold is reached. note in figure 11 the location of the filo read pointer versus that of the fifo read pointer. index sample 0 data0 1 data1 2 data2 3 data3 4 data4 5 data5 6 data6 buffer write pointe r 8 9 figure 11 . buffer approaching sample threshold in fifo, stream, and filo modes, a watermark interrupt is issued when the number of samples in the buffer reaches the sample threshold . in trigger mode, this is th e point where the oldest data in the buffer is discarded to make room for newer data. index sample 0 data0 1 data1 2 data2 3 data3 4 data4 5 data5 6 data6 7 data7 buffer wr ite pointer 9 figure 12 . buffer at sample threshold
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 51 of 54 in trigger mode, data is accumulated in the buffer sequentially until the sample threshold is reached. once the sample threshold is reached, the oldest samples are discarded when new sampl es a re collected. note in figure 13 how data0 was thrown out to make room for data8. index sample 0 data1 1 data2 2 data3 3 data4 4 data5 5 data6 6 data7 trigger write pointer 8 9 figure 13 . additional data prior to trigger event after a trigger event occurs, the buffer no longer discards the oldest samples, and instead begins accumulating samples sequentially until full. the buffer then stops collecting samples, as seen in figure 14 . this results in the buffer holding smp_th[6:0] samples prior to the trigger event, and smpx samples after the trigger event. index sample 0 data1 1 data2 2 data3 3 data4 4 data5 5 data6 6 data7 7 data8 8 data9 9 data10 figure 14 . additional data after trigger event
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 52 of 54 in fifo, stream, filo, and trigger (after a trigger event has occurred) modes, the buffer continues filling sequentially after the sample threshold is reached. sample accumulation after the buffer is full depends on the selected operation mode. fifo and trigger modes stop accumulating samples when the buffer is full , and stream and filo modes begin discarding the oldest data when new samples are accumulated. index sample 0 data0 1 data1 2 data2 3 data3 4 data4 5 data5 6 data6 7 data7 8 data8 9 data9 figure 15 . buffer full after the buffer has been filled in filo or stream mode, the oldest samples are discarded when new samples a re collected. note in figure 16 how data0 was thrown out to make room for data10. index sample 0 data1 1 data2 2 data3 3 data4 4 data5 5 data6 6 data7 7 data8 8 data 9 9 data10 figure 16 . buffer full C additional sample accumulation in stream or filo mode
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 53 of 54 in fifo, stream, or trigger mode, reading one sample from the buffer will remove the oldest sample and effectively shift the entire buff er c ontents up, as seen in figure 17 . index sample 0 data1 1 data2 2 data3 3 data4 4 data5 5 data6 6 data7 7 data8 8 data9 buffer write pointer figure 17 . fif o read from full buffer in filo mode, reading one sample from the buffer will remove the newest sample and leave the older samples untouched, as seen in figure 18 . index sample 0 data0 1 data1 2 data2 3 data3 4 data4 5 data5 6 data6 7 data7 8 data8 buffer write pointer figure 18 . filo read from full buffer
2g / 4g / 8g tri - axis digital accelerometer specifications part number: kxti9 - 1001 rev. 2 jul - 2011 36 thornwood dr. C ithaca, ny 14850 ? 201 1 kionix C all rights reserved tel: 607 - 257 - 1080 C fax:607 - 257 - 1146 438 - 2322 - 1107191455 w ww.kionix.com - info@kionix.com page 54 of 54 revision history revision description date 1 initial product release 16 - jun - 2011 2 corrected register addresses for z output. added note about hpf requiring wuf to be enabled. updated table references 19 - jul - 2011 "kionix" is a registered trademark of kionix, inc. products described herein are protected by pa tents issued or pending. no license is granted by implication or otherwise under any patent or other rights of kionix. the information contained herein is believed to be accurate and reliable but is not guaranteed. kionix does not assume responsibility for its use or distribution. kionix also reserves the right to change product specifications or discontinue this product at any time without prior notice. this publication supersedes and replaces all information previously supplied.

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