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isplsi 1024/883 in-system programmable high density pld 1 1024mil_01 features high-density programmable logic ?high-speed global interconnect ?4000 pld gates ?48 i/o pins, six dedicated inputs ?144 registers ?wide input gating for fast counters, state machines, address decoders, etc. ?small logic block size for fast random logic ?security cell prevents unauthorized copying high performance e 2 cmos technology ? f max = 60 mhz maximum operating frequency ? t pd = 20 ns propagation delay ?ttl compatible inputs and outputs ?electrically erasable and reprogrammable ?non-volatile e 2 cmos technology ?100% tested in-system programmable ?in-system programmable (isp) 5-volt only ?increased manufacturing yields, reduced time-to- market, and improved product quality ?reprogram soldered devices for faster debugging combines ease of use and the fast system speed of plds with the density and flex- ibility of field programmable gate arrays ?complete programmable device can combine glue logic and structured designs ?four dedicated clock input pins ?synchronous and asynchronous clocks ?flexible pin placement ?optimized global routing pool provides global interconnectivity ispdesignexpert ?logic compiler and com- plete isp device design systems from hdl synthesis through in-system programming superior quality of results tightly integrated with leading cae vendor tools productivity enhancing timing analyzer, explore tools, timing simulator and ispanalyzer pc and unix platforms unctional block diagram output routing pool clk b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 c7 c6 c5 c4 c3 c2 c1 c0 output routing pool output routing pool global routing pool (grp) logic array dq dq dq dq glb 0139-a-isp description the isplsi 1024/883 is a high-density programmable logic device processed in full compliance to mil-std- 883. this military grade device contains 144 registers, 48 universal i/o pins, six dedicated input pins, four dedicated clock input pins and a global routing pool (grp). the grp provides complete interconnectivity between all of these elements. the isplsi 1024/883 features 5-volt in-system programmability and in-system diagnostic capabilities. it is the first device which offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. the basic unit of logic on the isplsi 1024/883 device is the generic logic block (glb). the glbs are labeled a0, a1 .. c7 (see figure 1). there are a total of 24 glbs in the isplsi 1024/883 device. each glb has 18 inputs, a programmable and/or/xor array, and four outputs which can be configured to be either combinatorial or registered. inputs to the glb come from the grp and dedicated inputs. all of the glb outputs are brought back into the grp so that they can be connected to the inputs of any other glb on the device. copyright ?2000 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. september 2000 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com functional block diagram http://
specifications isplsi 1024/883 2 the device also has 48 i/o cells, each of which is directly connected to an i/o pin. each i/o cell can be individually programmed to be a combinatorial input, registered in- put, latched input, output or bi-directional i/o pin with 3-state control. additionally, all outputs are polarity selectable, active high or active low. the signal levels are ttl compatible voltages and the output drivers can source 4 ma or sink 8 ma. eight glbs, 16 i/o cells, two dedicated inputs and one orp are connected together to make a megablock (see figure 1). the outputs of the eight glbs are connected to a set of 16 universal i/o cells by the orp. the i/o cells within the megablock also share a common output enable (oe) signal. the isplsi 1024/883 device con- tains three of these megablocks. functional block diagram figure 1.isplsi 1024/883 functional block diagram y 0 y 1 y 2 y 3 i/o 0 i/o 1 i/o 2 i/o 3 in 5 in 4 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 47 i/o 46 i/o 45 i/o 44 i/o 43 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 i/o 35 i/o 34 i/o 33 i/o 32 i/o 17 i/o 16 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 4 i/o 5 reset global routing pool (grp) output routing pool (orp) clk 0 clk 1 clk 2 ioclk 0 ioclk 1 clock distribution network b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 c7 c6 c5 c4 c3 c2 c1 c0 output routing pool (orp) generic logic blocks (glbs) megablock output routing pool (orp) lnput bus input bus ispen input bus 0139d_1024.eps sdi/in 0 sdo/in 1 sclk/in 2 mode/in 3 the grp has as its inputs the outputs from all of the glbs and all of the inputs from the bi-directional i/o cells. all of these signals are made available to the inputs of the glbs. delays through the grp have been equalized to minimize timing skew. clocks in the isplsi 1024/883 device are selected using the clock distribution network. four dedicated clock pins (y0, y1, y2 and y3) are brought into the distribution network, and five clock outputs (clk 0, clk 1, clk 2, ioclk 0 and ioclk 1) are provided to route clocks to the glbs and i/o cells. the clock distribution network can also be driven from a special clock glb (b4 on the isplsi 1024/883 device). the logic of this glb allows the user to create an internal clock from a combination of internal signals within the device. http://
specifications isplsi 1024/883 3 absolute maximum ratings 1 supply voltage v cc ...................................-0.5 to +7.0v input voltage applied ........................ -2.5 to v cc +1.0v off-state output voltage applied ..... -2.5 to v cc +1.0v storage temperature ................................ -65 to 150 c case temp. with power applied .............. -55 to 125 c max. junction temp. (t j ) with power applied ... 150 c 1. stresses above those listed under the ?bsolute maximum ratings?may cause permanent damage to the device. functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications). dc recommended operating conditions v v parameter symbol min. max. units 5.5 0.8 v cc + 1 supply voltage v cc v il v ih 0005a mil.eps 4.5 0 2.0 military/883 t c = -55 c to +125 c input low voltage input high voltage v capacitance (t a =25 o c, f=1.0 mhz) symbol parameter maximum 1 units test conditions c 1 10 pf v cc =5.0v, v in =2.0v c 2 i/o and clock capacitance 10 pf v cc =5.0v, v i/o , v y =2.0v 1. characterized but not 100% tested. table 2- 0006mil dedicated input capacitance data retention specifications table 2- 0008b parameter data retention minimum maximum units erase/reprogram cycles 20 10000 years cycles http://
specifications isplsi 1024/883 4 switching test conditions input pulse levels gnd to 3.0v input rise and fall time 3ns 10% to 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure 2 3-state levels are measured 0.5v from steady-state active level. table 2- 0003 dc electrical characteristics over recommended operating conditions 0.4 -10 10 -150 -150 -200 215 v ol v oh i il i ih i il-isp i il-pu i os 1 i cc 2,4 i ol =8 ma i oh =-4 ma 0v v in v il (max.) 3.5v v in v cc 0v v in v il (max.) 0v v in v il v cc = 5v, v out = 0.5v v il = 0.5v, v ih = 3.0v f toggle = 1 mhz 135 2.4 condition parameter symbol min. max. output low voltage output high voltage input or i/o low leakage current input or i/o high leakage current isp input low leakage current i/o active pull-up current output short circuit current operating power supply current units typ. 3 v v a a a a ma ma 1. one output at a time for a maximum duration of one second. v out = 0.5v was selected to avoid test problems by tester ground degradation. characterized but not 100% tested. 2. measured using six 16-bit counters. 3. typical values are at v cc = 5v and t a = 25 o c. 4. maximum i cc varies widely with specific device configuration and operating frequency. refer to the power consumption sec - tion of this datasheet and thermal management section of the lattice semiconductor data book or cd-rom to estimate maximum i cc . 0007a-24 mil figure 2. test load + 5v r 1 r 2 c l * device output test point * c l includes test fixture and probe capacitance. output load conditions (see figure 2) test condition r1 r2 cl a 470 ? 390 ? 35pf b active high 390 ? 35pf active low 470 ? 390 ? 35pf active high to z 390 ? 5pf cat v oh - 0.5v active low to z 470 ? 390 ? 5pf at v ol + 0.5v table 2- 0004a http://
specifications isplsi 1024/883 5 external timing parameters over recommended operating conditions min. max. data propagation delay, 4pt bypass, orp bypass data propagation delay, worst case path clock frequency with internal feedback 3 clock frequency with external feedback clock frequency, max toggle 4 glb reg. setup time before clock, 4pt bypass glb reg. clock to output delay, orp bypass glb reg. hold time after clock, 4 pt bypass glb reg. setup time before clock glb reg. clock to output delay glb reg. hold time after clock ext. reset pin to output delay ext. reset pulse duration input to output enable input to output disable ext. sync. clock pulse duration, high ext. sync. clock pulse duration, low i/o reg. setup time before ext. sync. clock (y2, y3) i/o reg. hold time after ext. sync. clock (y2, y3) ns ns mhz mhz mhz ns ns ns ns ns ns ns ns ns ns ns ns ns ns t pd1 t pd2 f max (int.) f max (ext.) f max (tog.) t su1 t co1 t h1 t su2 t co2 t h2 t r1 t rw1 t en t dis t wh t wl t su5 t h5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 a a a a a b c description 1 parameter # 2 units test 5 cond. 1 tsu2 + tco1 ( ) 60 38 83 9 0 13 0 13 6 6 2.5 8.5 20 25 13 16 22.5 24 24 -60 table 2-0030-24 mil 1. unless noted otherwise, all parameters use a grp load of 4 glbs, 20 ptxor path, orp and y0 clock. 2. refer to timing model in this data sheet for further details. 3. standard 16-bit loadable counter using grp feedback. 4. f max (toggle) may be less than 1/( t wh + t wl). this is to allow for a clock duty cycle of other than 50%. 5. reference switching test conditions section. http://
specifications isplsi 1024/883 6 internal timing parameters 1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7.3 1.3 1.3 6.0 4.6 2.7 4.0 4.0 3.3 5.3 2.0 2.7 4.0 5.0 6.0 8.3 8.6 9.3 10.6 12.7 1.3 2.7 3.3 13.3 12.0 9.9 3.3 0.7 min. max. description parameter units -60 inputs t iobp t iolat t iosu t ioh t ioco t ior t din grp t grp1 t grp4 t grp8 t grp12 t grp16 t grp24 glb t 4ptbp t 1ptxor t 20ptxor t xoradj t gbp t gsu t gh t gco t gr t ptre t ptoe t ptck orp t orp t orpbp # 2 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 i/o register bypass i/o latch delay i/o register setup time before clock i/o register hold time after clock i/o register clock to out delay i/o register reset to out delay dedicated input delay grp delay, 1 glb load grp delay, 4 glb loads grp delay, 8 glb loads grp delay, 12 glb loads grp delay, 16 glb loads grp delay, 24 glb loads 4 product term bypass path delay 1 product term/xor path delay 20 product term/xor path delay xor adjacent path delay 3 glb register bypass delay glb register setup time before clock glb register hold time after clock glb register clock to output delay glb register reset to output delay glb product term reset to register delay glb product term output enable to i/o cell delay glb product term clock delay orp delay orp bypass delay 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. 3. the xor adjacent path can only be used by lattice hard macros. http://
specifications isplsi 1024/883 7 internal timing parameters 1 ns ns ns ns ns ns ns ns ns 6.0 4.6 1.3 4.6 1.3 4.0 6.7 6.7 6.0 7.3 6.6 7.3 6.6 12.0 outputs t ob t oen t odis clocks t gy0 t gy1/2 t gcp t ioy2/3 t iocp global reset t gr 47 48 49 50 51 52 53 54 55 output buffer delay i/o cell oe to output enabled i/o cell oe to output disabled clock delay, y0 to global glb clock line (ref. clock) clock delay, y1 or y2 to global glb clock line clock delay, clock glb to global glb clock line clock delay, y2 or y3 to i/o cell global clock line clock delay, clock glb to i/o cell global clock line global reset to glb and i/o registers min. max. description parameter units -60 # 2 1. internal timing parameters are not tested and are for reference only. 2. refer to timing model in this data sheet for further details. http://
specifications isplsi 1024/883 8 isplsi timing model glb reg delay i/o pin (output) orp delay feedback 4 pt bypass 20 pt xor delays control pts grp loading delay input register clock distribution i/o pin (input) y0 y1,2,3 d q grp 4 glb reg bypass orp bypass dq rst re oe ck i/o reg bypass i/o cell orp glb grp i/o cell #21 - 25 #27, 29, 30, 31, 32 #28 #33 #34, 35, 36 #51, 52, 53, 54 #42, 43, 44 #50 #45 #46 reset ded. in #26 #20 rst #55 #55 #37 #38, 39, 40, 41 #48, 49 #47 1. calculations are based upon timing specifications for the isplsi 1024-60. derivations of t su, t h and t co from the product term clock 1 t su = logic + reg su - clock (min) = ( t iobp + t grp4 + t 20ptxor ) + ( t gsu ) - ( t iobp + t grp4 + t ptck(min) ) = ( #20 + #28 + #35 ) + ( #38 ) - ( #20 + #28 + #44 ) 7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (2.7 + 2.7 + 4.6) t h = clock (max) + reg h - logic = ( t iobp + t grp4 + t ptck(max) ) + ( t gh ) - ( t iobp + t grp4 + t 20ptxor ) = ( #20 + #28 + #44 ) + ( #39 ) - ( #20 + #28 + #35 ) 5.3 ns = (2.7 + 2.7 + 9.9) + (6.0) - (2.7 + 2.7 + 10.6) t co = clock (max) + reg co + output = ( t iobp + t grp4 + t ptck(max) ) + ( t gco ) + ( t orp + t ob ) = ( #20 + #28 + #44 ) + ( #40 ) + ( #45 + #47 ) 25.3 ns = (2.7+ 2.7 +9.9) + (2.7) + (3.3 + 4.0) derivations of t su, t h and t co from the clock glb 1 t su = logic + reg su - clock (min) = ( t iobp + t grp4 + t 20ptxor ) + ( t gsu ) - ( t gy0(min) + t gco + t gcp(min) ) = ( #20 + #28 + #35 ) + ( #38 ) - ( #50 + #40 + #52 ) 7.3 ns = (2.7 + 2.7 + 10.6) + (1.3) - (6.0 + 2.7 + 1.3) t h = clock (max) + reg h - logic = ( t gy0(max) + t gco + t gcp(max) ) + ( t gh ) - ( t iobp + t grp4 + t 20ptxor ) = ( #50 + #40 + #52 ) + ( #39 ) - ( #20 + #28 + #35 ) 5.3 ns = (6.0 + 2.7 + 6.6) + (6.0) - (2.7 + 2.7 + 10.6) t co = clock (max) + reg co + output = ( t gy0(max) + t gco + t gcp(max) ) + ( t gco ) + ( t orp + t ob ) = ( #50 + #40 + #52 ) + ( #40 ) + ( #45 + #47 ) 25.3 ns = (6.0 + 2.7 + 6.6) + (2.7) + (3.3 + 4.0) http://
specifications isplsi 1024/883 9 maximum grp delay vs glb loads isplsi 1024-60 1 2 3 4 8 12 16 glb loads grp delay (ns) 4 5 6 0 0126a-80-24-mil.eps power consumption figure 3. typical device power consumption vs fmax i cc can be estimated for the isplsi 1024 using the following equation: i cc = 42 + (# of pts * 0.45) + (# of nets * max. freq * 0.008) where: # of pts = number of product terms used in design # of nets = number of signals used in device max. freq = highest clock frequency to the device the i cc estimate is based on typical conditions (v cc = 5.0v, room temperature) and an assumption of 2 glb loads on average exists. these values are for estimates only. since the value of i cc is sensitive to operating conditions and the program in the device, the actual i cc should be verified. 50 100 150 0 10203040506070 f max (mhz) i cc (ma) 80 200 notes: configuration of six 16-bit counters typical current at 5v, 25 ? c isplsi 1024 0127a-24-80-isp power consumption in the isplsi 1024/883 device de- pends on two primary factors: the speed at which the device is operating, and the number of product terms used. figure 3 shows the relationship between power and operating speed. http://
specifications isplsi 1024/883 10 dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb on the device. dedicated clock input. this clock input is connected to one of the clock inputs of all of the glbs on the device. input/output pins - these are the general purpose i/o pins used by the logic array. name table 2 - 0002c-24 mil jlcc pin numbers description 22, 26, 30, 37, 41, 45, 56, 60, 64, 3, 7, 11, 23, 27, 31, 38, 42, 46, 57, 61, 65, 4, 8, 12, 24, 28, 32, 39, 43, 47, 58, 62, 66, 5, 9, 13, i/o 0 - i/o 3 i/o 4 - i/o 7 i/o 8 - i/o 11 i/o 12 - i/o 15 i/o 16 - i/o 19 i/o 20 - i/o 23 i/o 24 - i/o 27 i/o 28 - i/o 31 i/o 32 - i/o 35 i/o 36 - i/o 39 i/o 40 - i/o 43 i/o 44 - i/o 47 25, 29, 33, 40, 44, 48, 59, 63, 67, 6, 10, 14 54 y1 16 y0 55 mode/in 3 1 input - this pin performs two functions. when ispen is logic low, it functions as pin to control the operation of the isp state machine. it is a dedicated input pin when ispen is logic high. ground (gnd) gnd v vcc cc in 4 - in 5 2, 15 input - these pins are dedicated input pins to the device. input - dedicated in-system programming enable input pin. this pin is brought low to enable the programming mode. the mode, sdi, sdo and sclk options become active. 19 ispen input - this pin performs two functions. when ispen is logic low, it functions as an input pin to load programming data into the device. sdi/in 0 is also used as one of the two control pins for the isp state machine. it is a dedicated input pin when ispen is logic high. 21 sdi/in 0 1 34 sdo/in 1 1 output/input - this pin performs two functions. when ispen is logic low, it functions as an output pin to read serial shift register data. it is a dedicated input pin when ispen is logic high. 49 sclk/in 2 1 input - this pin performs two functions. when ispen is logic low, it functions as a clock pin for the serial shift register. it is a dedicated input pin when ispen is logic high. active low (0) reset pin which resets all of the glb and i/o registers in the device. 20 reset dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any glb and/or any i/o cell on the device. 51 y2 dedicated clock input. this clock input is brought into the clock distribution network, and can optionally be routed to any i/o cell on the device. 50 y3 1, 18, 35, 52 17, 36, 53, 68 1. pins have dual function capability. 2. nc pins are not to be connected to any active signals, vcc or gnd. no connect nc 2 pin description http://
specifications isplsi 1024/883 11 pin configuration isplsi 1024/883 68-pin jlcc pinout diagram i/o 28 i/o 27 i/o 26 i/o 25 i/o 24 in 3/mode 1 y1 vcc gnd y2 y3 in 2/sclk 1 i/o 23 i/o 22 i/o 21 i/o 20 i/o 19 i/o 43 i/o 44 i/o 45 i/o 46 i/o 47 in 5 y0 vcc gnd ispen 1 sdi/in 0 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 42 i/o 41 i/o 40 i/o 39 i/o 38 i/o 37 i/o 36 in 4 gnd vcc i/o 35 i/o 34 i/o 33 i/o 32 i/o 31 i/o 30 i/o 29 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 1 sdo/in 1 gnd vcc i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 10 60 61 43 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 62 42 63 41 64 40 65 39 66 38 67 37 68 36 1 35 2 34 3 33 4 32 5 31 6 30 7 29 8 28 9 27 reset isplsi 1024/883 top view 0123-24-isp/jlcc 1. pins have dual function capability. http://
specifications isplsi 1024/883 12 part number description table 2-0041a-24-mil military/883 note: lattice semiconductor recognizes the trend in military device procurement towards using smd compliant devices, as such, ordering by this number is recommended. t pd (ns) f max (mhz) ordering number package 60 20 isplsi 1024-60lh/883 68-pin jlcc isplsi family smd # 5962-9476101mxc ordering information device number grade /883 = 883 military process 1024 xx x x x speed 60 = 60 mhz f max power l = low package h = jlcc device family isplsi 00212-80b-isp1024 mil isplsi http://

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