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2001 microchip technology inc. ds35007b pic16f84a data sheet 18-pin enhanced flash/eeprom 8-bit microcontroller m http://
ds35007b - page ii 2001 microchip technology inc. i nform at ion cont ai ned in this pub l ication r egarding dev i c e applic at ions and the like i s int ended t hr ough sug gest ion only and may be supers eded by updates. i t i s your res ponsibili ty to ensure t hat your appli c a t ion m eet s wit h your s pecif ic at ions. no repr esent at ion or warranty is gi v en and no l iabilit y is assum ed by microc hip t e chnology i n c o rporated wit h r e spect t o t he accurac y or use of s uch inform ation, or infringement of p a t e nt s or ot h e r intell ec t ual property right s ar i s ing from suc h use or otherwise . use of m i c rochip s produc t s as cr i t ical com - ponent s in li fe support s ystems is not authorized except with expres s writ ten approval by micr ochip. no licenses ar e c on- veyed , implicit ly or otherwise, under any int ellectual pr operty right s . t rademarks th e mi cro ch i p na me a n d l o go , th e mi cr oc hi p l o go , pi c, picm ic ro , pi c mas ter , pi c s t a r t , p r o ma te, k ee l oq , se ev al , m p l a b a n d t he e m b e dde d c ont r o l s o l u t i on s c o m p a n y ar e r eg- is t e re d t r ade m a r k s of mi cr oc hip t e ch no logy i n co rp ora t ed in t h e u. s . a . a nd o t her co unt r i es . t o t al e ndurance, icsp , in-circuit s e rial pro gramm ing, f ilter- lab, mx dev , mic r oi d, flex ro m, fu zzy l ab, mp as m, mp li nk , m p lib, picc, picdem , p i cd em . net, icep i c, migrat able me mory , fansen se, e conomonit or, select mode and micr oport ar e tradem arks of m i crochip t e c hnology i nc orporated in t he u.s.a. ser i alized quick t e rm p r ogram ming (s qt p ) is a serv ice mar k of mic rochip t echnology incorpora t ed i n the u.s.a. all other tradem arks m ent ioned h e rein are property of their respe ct i ve com p anies. ? 2001, micr ochip t e chnology incorpora t ed, p rint ed in the u. s . a . , a ll right s r e serve d. p r inte d o n r e cycle d pap er .
? 2001 micro chip technology inc. ds 35007b- page 1 m pic16f84a hi gh per f orm anc e ri sc cpu fea ture s: ? o nl y 3 5 s i n g le word ins t ru cti ons to le arn ? al l i nst ruc t io ns si ngl e-c y c l e exc ep t fo r pro gram b ranc he s w h ic h are tw o- cy cl e ? o pe rati ng spe ed: d c - 2 0 mh z cl ock i npu t d c - 2 0 0 ns in str u cti on cy cl e ? 1 024 word s o f pro g ra m m e m o ry ? 6 8 by te s o f dat a r am ? 6 4 by te s o f dat a eeprom ? 1 4-bit w i d e i n s t ruc t io n w o rd s ? 8 -bit wide da t a b y te s ? 1 5 sp eci a l fun c ti on h a rdw a re re gis t ers ? ei ght -lev el dee p h a rd w a re s t a c k ? d i rect , in dir ect an d rel ati ve ad dres si ng mo des ? f ou r in t e rru pt s o u rce s: - ex t ern a l r b0/in t pin - t mr 0 t i me r ov er f l ow - po r tb <7:4> i n terr upt-o n-c han ge - d at a eeprom write c o m p let e per i pher al feat ures: ? 1 3 i/o p i ns wi t h i ndi vi dua l d i rec t io n c on t rol ? h i gh c u rre nt sin k / s ou rce for dire ct led d riv e - 2 5 ma si nk m ax. pe r pi n - 2 5 m a so urc e m a x . p e r p i n ? t m r 0: 8-bi t ti me r/c oun ter wi th 8 -bi t p rogra m m ab l e pres ca le r speci al mic r ocont rol l er feat ure s : ? 1 0,00 0 e ras e/w ri t e c y c l e s en ha nce d f l ash pro gram m e m o ry ty pic a l ? 1 0,00 0,0 00 typ i c a l eras e/wri t e c y c le s eepro m da t a me mo ry t y p i ca l ? eeprom dat a rete nti on > 40 y e ars ? i n -circ uit seri al progra m m i n g ? (i csp?) - v i a tw o pi ns ? po w er-on res e t (por), powe r-up t i m e r (pwr t ), os c i l l a t or s t a rt-up t i m e r (ost) ? w a t ch dog t i m e r (wd t ) w i th i t s ow n on -c hip rc os ci ll at o r f o r r e li ab l e o p e ra t i o n ? c od e p rote c ti on ? p o w er s a v i ng sleep m o de ? sel e c ta bl e o s c il l at o r op t io n s pi n di agrams cmos enhanced flash/eeprom t echnol ogy: ? lo w po w er , h i g h s pee d te ch nol ogy ? f u lly s t at ic des ig n ? w i de ope rati ng vo lt ag e ra ng e: - c o mme rc i a l: 2 . 0v t o 5 . 5v - i n dus tri a l: 2.0 v to 5.5 v ? l o w po w e r c ons um pti o n : - < 2 m a ty pic a l @ 5v , 4 m h z -1 5 m a t y p i c a l @ 2v , 3 2 k h z - < 0.5 m a typ ic a l st a ndb y cur rent @ 2v ra 1 ra 0 o s c1/cl k in o s c2/cl k out v dd rb 7 rb 6 rb 5 rb 4 ra2 ra3 ra4/t0cki mclr v ss rb0 / i n t rb1 rb2 rb3 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 pdip, soic pic16f84a ra 1 ra 0 o s c1/cl k in o s c2/cl k out v dd rb 7 rb 6 rb 5 rb 4 ra2 ra3 ra4 / t 0 cki mc l r v ss rb0 / i n t rb1 rb2 rb3 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 sso p pic16 f 84a 10 11 v ss v dd 18-pin enhan c e d flash/eeprom 8-bit microcontroller
pic16f84a ds35007b-page 2 ? 2001 microchip technology inc. t a ble of content s 1. 0 dev ic e ov er view .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .... .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 3 2. 0 mem ory organization .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 5 3. 0 dat a e e pr om mem o ry .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. . . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 13 4. 0 i /o por t s . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. . . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 15 5. 0 t im er0 module . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. . . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 19 6. 0 speci al feat ur es of the c pu . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 21 7. 0 i ns t ruc t ion set s u mm ary . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 35 8. 0 developm ent suppor t . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. . .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 43 9. 0 electrical characteristics . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 49 10. 0 dc/ac characteristic grap hs . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 61 11. 0 pac kaging information . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 71 appendix a : revision hi s t or y . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. . . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 75 appendix b : convers i on cons i der at ions . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 76 appendix c: m igrat ion f ro m baseline t o mid-range dev i c es . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. . . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 78 i ndex . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 79 on-line s upport . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 83 reader respons e . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. . . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 84 pic16f84a produc t i den t i f i ca t ion s ys t em . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. . . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 85 t o our v a lued cust o mers i t i s our intent ion to pr ovide our valued customer s wi th t he bes t docum ent ation possible t o ensu r e s u cce ssful us e of your m i c r o chip product s . t o t his end, we wi ll conti n ue to i m prov e our pu bl ica t ions to bett e r s uit your needs . our publicat ions w i ll be r efined and enhanced as new volumes and updates ar e introduced. i f y ou have any questi on s o r c omm ent s r egarding this publicat ion, p l eas e c ont ac t t h e m arketing co mm unic ations dep ar t m ent via e-m ail at docerro rs@m a i l . m icroch ip. com or f ax t he r ead er r esp onse fo rm i n t he bac k of t h i s dat a sheet t o ( 480) 792-415 0. w e welcom e y our f eedbac k. most cur r ent da t a s h ee t t o obt ain t he mos t up-to-dat e ver sion of this dat a sheet, please register at our w orldwide w eb site at: ht tp: / / w ww .micro chip. c o m y ou can det erm ine the v ersion of a dat a s heet by examining i t s li terature nu mber f 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? 2001 microchip technology inc. ds35007b-page 3 pic16f84a 1 .0 d ev ice o vervi ew t h i s do cu me n t co nta i ns d e v i c e sp ec if i c in f o r m at i o n f o r th e op era t io n of t he pi c 16f8 4 a d e v i ce . add i ti ona l i n for m a t ion m a y be fo und in th e pic m ic ro? mi d- r a nge r e fere nc e m anu al, ( d s 330 23), w h ic h m ay b e d ow nl oad ed f rom the m i c roc hi p w eb s i t e. t he r ef er- e n ce ma nua l sh oul d be c o n s i dere d a c o m p le me nt a ry d ocu me nt t o thi s d at a sh eet , and is hig hl y re com - m e n ded rea d i ng for a bett e r u n d e rst and ing o f th e d evi ce a rchi t ec tur e a nd ope rati on of the p erip hera l mo du l e s . th e pic 1 6 f 84 a be lo ngs to t he mi d-range fa mi ly o f th e picm ic ro ? m i c roc on troller dev ic es . a b l o c k di agram of th e d e v i ce is s how n in fig u re 1-1. th e pro g ram me mo ry c ont ain s 1k w o rd s, w h i c h trans - la t e s t o 1 0 24 i ns t ruc t i o ns , si nc e e a c h 14 -b it p rog ra m me mo ry w o rd is t h e sa me w idt h a s ea ch d e v i c e i n st ru c- ti on. th e dat a m e m o ry (r am ) co nt ai ns 6 8 byt e s . d a t a eeprom is 64 bytes. th ere ar e a l s o 13 i/o pin s th at are us er-c on fig u red o n a pin -to-p in bas is . so me pin s a re m ul t ip lex ed w i th oth er de vi ce fun c ti on s. t hes e func ti ons in cl ude : ? ex t ern a l inte rrupt ? c ha nge on po r tb i n te rrup t ? t i m er 0 cloc k inp u t t abl e 1 -1 de t a i l s th e pi nou t of the dev ic e w i th d e s c ri p- ti ons an d d et a ils fo r ea ch pin . figure 1-1: pi c16f84 a block di agram f l as h progr am m e mory p r ogram counter 13 p r ogram bus i n s t ruc t ion regist e r 8 level stack (13-bit) direct addr 8 inst ruct ion decode & cont ro l t i ming generat ion o s c2/clkout o s c1/clkin powe r-up ti m e r o s cill ator s t ar t -up t i me r power -on res et w atc hdog ti m e r mclr v dd , v ss w reg al u mux i /o por t s tmr0 st a t us reg fs r r e g indirect add r ra3:ra0 rb7:rb 1 ra 4/ t0ck i ee adr e epr om dat a mem o ry 64 x 8 ee da t a a ddr m u x ra m addr ra m file registers ee pro m data m e mor y dat a bus 5 7 7 rb0/int 14 8 8 1k x 14 68 x 8
pic16f84a ds35007b-page 4 ? 2001 microchip technology inc. t a ble 1 - 1 : pi c16f84 a p i nout de scri ption pin name pdip no. soic no. ssop no. i/ o / p ty p e buffe r ty p e de scrip tion o sc1 /clkin 1 6 16 18 i st/cm o s (3 ) os ci ll a t or cr y s ta l i n p u t /e xt e rna l cl oc k so u rce in p u t . os c 2 / c lk o u t 1 5 1 5 1 9 o o sc il lato r c rys t a l ou tput . c o n nec t s to cry s t a l o r res o n a to r in crys t a l o s c ill ato r m ode . in rc m ode , o s c 2 p i n o u tp ut s c l ko u t , wh i c h has 1/ 4 th e fre que nc y o f o sc 1 a nd d e n o tes th e i n st ruc t io n c ycl e r a t e . mc lr 4 4 4 i/p st m a st er c l ear ( r e s e t ) i npu t/pro gram m i ng v o lt a g e in put . thi s p i n i s a n ac tiv e l o w reset t o the de v i c e . po r t a is a bi-d ire c ti ona l i/ o port. r a 0 1 7 1 7 1 9 i/o t tl r a 1 1 8 1 8 2 0 i/o t tl r a 2 1 1 1 i/o t tl r a 3 2 2 2 i/o t tl r a 4/t0cki 3 3 3 i/o st can a l s o be se lec t ed to be the clo c k in put t o the tm r0 ti me r/coun ter . o u tpu t i s o pen dra i n typ e . po r t b i s a bi -di rec tional i/o po rt. po r t b ca n b e s of t w a r e p rog ram m e d f o r i n t er n al we ak pu ll -u p o n al l i npu t s . r b 0/int 6 6 7 i/o tt l/st (1 ) r b0 / in t ca n al so be se l ec t ed as an ext er n al in terru pt p i n. r b 1 7 7 8 i/o t tl r b 2 8 8 9 i/o t tl r b 3 9 9 1 0 i/o t tl r b 4 1 0 1 0 1 1 i/o t t l i nt errup t -on -ch ang e p i n. r b 5 1 1 1 1 1 2 i/o t t l i nt errup t -on -ch ang e p i n. r b 6 1 2 1 2 1 3 i/o tt l/st (2 ) int errup t -on -ch ang e p i n. seri al program m i ng cl oc k. r b 7 1 3 1 3 1 4 i/o tt l/st (2 ) int errup t -on -ch ang e p i n. serial prog ramm i n g dat a. v ss 5 5 5, 6 p g round re ferenc e fo r lo gic an d i / o pin s . v dd 1 4 14 15, 16 p pos i ti ve su pp ly for l ogi c and i/o pi ns . leg end : i = i npu t o = o u tpu t i/o = in put /o utput p = po w e r = n o t us ed ttl = ttl in put s t = sc hm itt t rig ger inp u t note 1 : t h is bu ffe r is a s c hm it t t rig ge r i np ut wh en co n f i g ur e d a s t h e e x t e rna l in t er ru pt . 2: t h is bu ffe r is a s c hm it t t rig ge r i np ut wh en u s e d i n s e ria l pro g ram mi ng mo de . 3: t h is bu ffe r is a s c hm it t t rig ge r i np ut wh en co n f i g ur e d i n rc osci ll a t o r mo de a nd a c m os in p ut o t h e rw is e.
? 2001 microchip technology inc. ds35007b-page 5 pic16f84a 2 . 0 m emory organization t he r e a r e t w o m em or y b l oc ks i n t h e p i c 16 f 84 a . th es e are th e prog ram m e m o ry and t he da t a me mo ry . each bloc k ha s i t s o w n b u s, so tha t ac ce ss to eac h b l oc k can oc cu r du rin g th e s am e o s c ill ato r cy c l e. th e dat a m e m o ry c a n fu rther b e b rok en do w n into th e g ene ral pu rpos e r am and th e spec ia l f unc tio n r e gis t ers (sf r s ). the op erat ion of the sfr s th at c ont rol th e c ore a re de sc ribed he re. th e sfr s use d to c ont rol the pe riph eral m od ule s a re des cri be d i n th e s ec t io n di sc us si ng eac h i nd i vi du al p eri phe ral mo dul e. th e da t a m e m o ry area als o c ont ain s th e da t a eeprom m e m o ry . th is m e m o ry is no t di rectly m a ppe d i n to th e dat a m e m o ry , b u t is i ndi rec t ly m a p ped . t hat is , a n in dir e ct add res s p o in ter s p e c i f ies th e ad dre s s of th e d a t a eeprom m e m o ry to rea d /writ e . the 64 by tes of d a t a eepro m m e m o ry have th e ad dre s s rang e 0 h -3f h . m o re de t a i l s on th e eeprom m e m o ry c a n b e fo und in sec t io n 3 .0. ad dit i on al i nfo rma t io n on de vi ce mem ory m ay be foun d i n the pic m ic ro? m i d-r a nge r e ferenc e ma nua l, (d s3 302 3). 2. 1 p r ogram memory organi zat i on th e pic16 fxx has a 1 3 -b it pro g ram c o u n te r c a p abl e of ad d res si ng a n 8 k x 14 p ro g ra m me mo ry s pac e. fo r th e pic 1 6 f 84 a, t he firs t 1k x 14 (0 000 h-0 3 ffh ) a re p hys ic al ly im ple m e nte d (fi gur e 2-1 ). ac ce ss in g a l oc a- ti on a bov e the phy si ca lly im ple m e nte d add res s w i l l c aus e a w rap aro und . f or ex am ple , for lo cat i on s 20 h, 4 20h , 8 20h , c 2 0h, 10 20h , 1 420 h, 182 0h, an d 1c 20 h, t h e in st ru ct i o n wi ll be t h e sa me . th e reset v e c t or is a t 0 000 h a n d th e i n te rrupt v e c t or i s a t 00 04h . figure 2-1: pr o g ram m e m o ry m a p and s t a ck - pic1 6f84a pc<12:0> stack level 1 stack level 8 re se t v e ctor peripheral interrupt vector us er m e mor y sp ac e call, return retfie, retlw 13 0000h 0004h 1fffh 3ffh
pic16f84a ds35007b-page 6 ? 2001 microchip technology inc. 2. 2 d at a mem o r y or ganiz a ti on th e dat a m e m o ry i s p a r t iti one d into tw o ar eas . t he firs t i s the sp eci a l fu nc tion r e gis t er s (sfr ) a rea , w h ile th e s e c ond i s th e ge ne ral pur pos e r e g i st ers (g pr ) are a . th e sf r s c o n t rol the ope ration of t he d e v i c e . po rtio ns o f dat a m emo ry a re ba nk ed. t his is f or bo th th e sf r area and the g pr are a . th e g pr are a i s b ank ed to a llo w grea ter t han 1 16 b y te s o f ge nera l p u rpo s e r am . the ba nk ed are a s o f t he sfr are fo r th e re gis t er s that c ont rol the p erip he ral fun c ti on s. ban k in g re qui res the us e of c o n t rol bit s fo r ba nk sel e c t io n. th es e c ont rol b i t s are loc a t ed i n th e st a t u s r egi ste r . fi gu re 2 -2 s how s th e da t a me mor y m ap org ani za tion . in str u ct ion s movwf a nd mo vf can mo ve v a l ues fr o m th e w re gi ste r to a n y l o c a ti on i n th e reg i s t er fi le (f), an d vice -ve rsa . th e ent ire dat a mem or y can b e a c c es s e d e i th er d i rec t ly us in g th e ab so lute ad dres s o f ea ch regi ste r fil e o r ind i re c t l y th rou gh t he f ile sele c t regi s t e r (fsr) (se c t io n 2 . 5 ). i n di re ct a d d re ssi n g us es t h e p res en t v a l ue of t he r p0 b i t fo r a c c e s s i n to th e ba nk ed ar eas of d a t a me mo ry . d a t a m em ory i s p arti t io ned in to t w o b ank s w hic h c ont ain th e gen eral p u rpo s e re gis t ers a nd the s p e c ia l fu nc tio n reg i s t ers . ba nk 0 is s e le ct ed b y c l e a rin g th e r p0 b i t ( st a t u s< 5 > ). s e t t i n g t h e r p0 b i t s el e cts b a nk 1 . ea ch ba nk ex ten d s u p t o 7 f h (12 8 by tes ). t he firs t t w el ve l o ca ti o ns o f ea ch b a nk a re res er v ed f o r t he sp e c i a l f u n c t i on r e g i st e rs. t h e r e ma in de r ar e g e n - e ral purpo s e regi st ers , impl em ente d a s s t a t ic ram. 2 . 2. 1 g e n er al pu r p ose re gi ste r file ea ch ge neral pu rpos e r e gis t er (g pr ) i s 8 -bit s w i d e a nd i s a c c e s s ed ei ther dire ctl y o r ind i re ctl y th rou gh th e fs r (sec tio n 2 . 5 ). th e gp r ad dre s s es i n ba nk 1 a re ma ppe d to a ddres s e s in b ank 0. as an ex am ple , add res s i ng l o c a - ti on 0c h o r 8c h wi l l ac c ess th e s am e g pr . figure 2-2: reg i s t er file map - pi c16f8 4 a fi le addr ess 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0ah 0bh 0ch 7fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8a h 8b h 8ch ff h b ank 0 b ank 1 i ndirec t addr . (1 ) indi r e ct addr . (1) tm r0 op ti on _reg pc l st a t u s fs r po r t a po r t b eed a t a e ead r p cla t h i n tc on 68 gener al purpo se registers (s r am ) pcl st a t u s fs r tris a tris b eec on1 ee con2 (1 ) p cla th i n tcon mapped in b ank 0 unimplemented data memory location, read as '0'. file address note 1: not a physical register. cfh d0h 4fh 50h (acc esses )
? 2001 microchip technology inc. ds35007b-page 7 pic16f84a 2. 3 s peci al funct io n regi ster s th e spe c i al f unc tio n r eg i st ers ( f ig ure 2 -2 an d table 2 -1) are us ed by th e c p u an d p e rip hera l fu nc tio ns to co ntro l the de vi ce op erat ion . t hes e re gis t er s a re st at ic r am. th e sp ec ial fu nc tio n regi ste rs c an be c l as s i fie d int o tw o s e t s , c o re an d p e rip heral . tho s e as so ci ated w i t h th e c ore f unc tio ns are d esc rib ed i n th is s ec t io n. th os e re lated t o th e o per ation o f th e p e ri phe ral fea t ures a re de sc rib ed in the se cti on for th at spe c i f ic fe ature . t able 2 - 1 : sp ec ial function r e gis t e r file s u mma ry a d dr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v a lu e on po wer- on re set det ail s on p a ge bank 0 00 h i ndf uses content s of fs r to addr ess dat a m emory (no t a phy sical r egis t er ) ---- ---- 11 01 h t mr 0 8 -bit real-t i me clock / counter xxxx xxxx 20 02 h p cl low order 8 bi t s of the p r ogram counter (pc) 0000 0000 11 03 h st a t u s (2) irp rp 1 r p 0 to pd zd cc 0001 1xxx 8 04 h f sr i ndirect dat a mem o ry add r ess pointer 0 xxxx xxxx 11 05 h p o r t a (4) r a4/t 0c ki ra 3 r a 2 ra1 r a0 ---x xxxx 16 06 h p o r tb (5 ) rb7 rb 6 rb 5 rb4 rb 3 rb 2 rb1 rb0/i nt xxxx xxxx 18 07h unim plemented l oc at ion, re ad as '0' 08 h e eda t a eep rom dat a register xxxx xxxx 13, 14 09 h e ea dr eep rom addr ess register xxxx xxxx 13, 14 0a h pclath w ri te buf f er f o r upper 5 bit s of t he pc (1 ) ---0 0000 11 0 b h i n t c on g ie e e i e t0 ie i n te r b ie t 0 i f int f r bi f 0000 000x 10 ba n k 1 80 h i ndf uses content s of fsr t o addres s dat a mem o ry (not a phys i c al regis t e r) ---- ---- 11 81 h op tio n_ reg rbp u i ntedg t 0cs t 0s e p sa ps 2 ps1 p s0 1111 1111 9 82 h p cl low ord e r 8 bit s of p rogram counter (pc) 0000 0000 11 83 h st a t u s (2 ) ir p r p 1 r p 0 to pd zd cc 0001 1xxx 8 84 h f sr i ndirect dat a mem o ry addres s p o inter 0 xxxx xxxx 11 85h trisa p or t a dat a direc t ion r egi s t er ---1 1111 16 86 h t risb por t b da t a directi o n register 1111 1111 18 87h uni m plemented l o c a t ion, read as '0' 88h eecon1 e e i f w re rr w re n w r rd ---0 x000 13 89 h e econ2 eep rom control register 2 (n ot a phy sical r egi s t er ) ---- ---- 14 0a h p cla th w ri te buf fer for upper 5 bit s of the pc (1 ) ---0 0000 11 0 b h i n t c o n g ie e e i e t0 ie i n te r b ie t 0 i f in t f r b i f 0000 000x 10 le gend: x = unk nown, u = unch anged. - = unimplem ent ed, re ad as '0', q = value depen ds on cond i t ion no t e 1: the u pper byte of the program co unt er i s not directl y acc essible. pcla th is a slave reg i s t er f o r pc<12:8>. the c ont ent s o f pcla t h can be t rans f err ed to the upper by t e of t h e progr am counter , but the content s of p c<12: 8> are never t ran s- fer re d to pcla th. 2: the t o and pd status bits in the status register are not affected by a mclr reset. 3: other (non power-up) resets include: external reset through mclr and t he w atchdog t im er res et . 4: on any device res e t , t hes e pins are configured as input s. 5: this is the value that will be i n the port out put latch.
pic16f84a ds35007b-page 8 ? 2001 microchip technology inc. 2 . 3. 1 s t a tu s r e gi s t er th e st a t u s r egi ste r co nt ai ns the a rith m e t ic st a t us of th e alu , the r es et s t a t us a nd th e ban k s ele ct bi t for d a t a me mo ry . as w i th an y reg i s t er , th e st a t u s reg i s t er c an be th e d e st ina t io n fo r a n y ins t ru cti on. if the st a t u s regist er i s th e de sti nat ion for an i n s t ruc t io n tha t af fec t s t he z, d c o r c b i t s , th en the w rit e to th es e th ree bi t s is di sa ble d. th es e b i t s ar e s et o r c l ea red ac co rdin g t o d evi ce lo gic . fu rthe rm o re, the t o and pd bi t s are no t w r it abl e. th ere f ore , the res u l t of an ins t ruc t i on w i th t he st a t u s re gis t er a s de st ina t io n ma y b e dif f e r ent t han i nte nde d. fo r ex am ple , clrf status w i l l cl ea r the u ppe r thre e bit s a nd s e t the z bi t. thi s le av es th e st a t us reg i s t er as 000u u1uu (whe re u = un ch ang ed). only t he b cf , bsf , sw ap f and mo vw f inst r u cti ons should be used to alte r the st a t u s reg i ster ( t a ble 7- 2) , because these instr uction s do n ot a f f ect any st at us bit . regis t er 2-1: s t a t us r e gis t e r (addr es s 0 3 h, 8 3 h) note 1 : th e ir p and r p 1 b i t s (st a t u s <7:6 >) are not used by the pic 1 6 f 84 a an d s hou ld be pro gra mm ed as c l e ared . u s e of th es e bi t s a s ge ner al p urpo s e r / w bit s i s no t r eco mm en ded , s i n c e th is m ay af fec t up w a rd co mp ati b il ity wi th fut u re produc t s . 2: th e c an d d c bit s op erat e as a bo rrow an d dig i t borro w ou t b i t, res pec tiv e l y , i n s ubt rac t ion . see th e sublw an d subwf i ns t r u ct i o ns f o r ex am pl e s . 3: wh en the st a t u s re gis t er is th e d es t i n at i on fo r an i n st r uc t io n t h at aff ec t s th e z, dc or c b i t s , the n th e writ e to th es e th ree bi t s is d i s abl ed. th e spe c i f ie d b i t(s ) w i l l b e u pda ted ac co rdin g to de vi ce log i c r/w -0 r / w -0 r /w -0 r-1 r -1 r/w -x r / w-x r /w -x irp r p1 r p0 t o pd zd c c bi t 7 bit 0 bi t 7- 6 unimp lem ente d: ma i nta in as 0 bi t 5 rp0 : r e gis t er bank se lec t b i t s (us e d for d i re ct add res s in g) 01 = bank 1 (80h - ff h) 00 = bank 0 (00h - 7 f h) bi t 4 to : t i me -out bit 1 = after pow e r-up, clrwdt in st r u ct i o n , or sleep in st r u ct i o n 0 = a wdt t i m e -ou t oc c u rred bi t 3 pd : pow e r-dow n bi t 1 = after pow e r-up or b y th e clr wdt in str u ct ion 0 = b y ex ec ut i o n o f t h e sleep in st r u ct i o n bi t 2 z : ze ro b i t 1 = t he res u lt of an a r ith m e t ic or log i c ope rati on is ze ro 0 = t he res u lt of an a r ith m e t ic or log i c ope rati on is not ze ro bit 1 dc : digit carry/borrow bit ( addwf , addlw,sublw ,subwf i nst ruc t io ns) (for borr ow , th e p o l a rit y is rev e rs ed) 1 = a ca rry-o ut from the 4t h lo w ord e r b i t o f th e re sul t o c c u rred 0 = n o c a rry -out from th e 4 t h l o w or der b i t of th e re su lt bi t 0 c : carry / b o rrow bit ( addwf , addlw,sublw,subwf instructions) (for borrow , th e p o la rity i s rev e rs ed) 1 = a ca rry-o ut from the m o s t sig n if ica n t bit of t he re su lt o c c u rre d 0 = n o c a rry -out from th e m o s t si gni fic ant bit of the res u lt oc cu rred note: a su btra ct ion is e x ec ut ed by add in g th e t w o s c om pl em ent of the seco nd ope ran d. for rot a te ( rrf , rlf ) i nst ruc t io ns, thi s bi t is l oad ed w i th ei the r th e h i gh or lo w ord er bit of t he s ou rce reg i s t er . l ege nd: r = read ab le b i t w = w ri t ab le bit u = u n imp l e m e nted bi t, re ad as 0 - n = v alue at por 1 = bit is set 0 = bit is cleared x = b it is unk nown
? 2001 microchip technology inc. ds35007b-page 9 pic16f84a 2.3 . 2 o p t ion reg i s t er th e o p tio n regi st er is a re ada ble a nd w r it abl e re gis t er w h i c h c o n t ain s v a rio u s c ont rol bi t s to c onf igu r e th e tmr0 /wdt pre s c a le r , the ex tern al int int e rrup t, t m r 0 , a n d t h e w e ak pu l l- u p s on p o r t b . register 2-2: option re gis t e r (addr es s 8 1 h) note : wh en th e pre s c a l e r is a s s i g ned to th e w dt (psa = ' 1 ' ) , tm r0 h a s a 1 : 1 p r e s ca le r as si gn m en t . r / w - 1 r /w- 1 r / w - 1 r / w-1 r / w - 1 r / w - 1 r /w- 1 r / w - 1 rbpu intedg t 0 cs t0 se psa ps2 ps1 ps0 bi t 7 bit 0 bit 7 rb p u : po r tb pu ll-u p en abl e b i t 1 = por t b pu ll -up s ar e di sa ble d 0 = por t b pu ll -up s ar e en abl ed by in div i d ual po rt la tch v alu es bi t 6 intedg : in terru pt ed ge sele c t bit 1 = inte rrup t on ris i ng ed ge of rb0 /int p i n 0 = interrupt on fal lin g e dge of rb0/int pin bi t 5 t0cs : tmr0 cloc k sou rce select bit 1 = t rans iti o n on r a4/t0c ki pi n 0 = internal in str u ct ion cy c l e c l o c k (clko u t) bi t 4 t0se : tmr0 sou rce edg e se lec t b i t 1 = i nc rement on hig h -to -lo w transit i on on ra4/t 0 c ki p i n 0 = i nc rement on low -t o -hi gh transit i on on ra4/t 0 c ki p i n bi t 3 psa : pres c a le r as s i g n m ent bit 1 = pres c a l er i s ass i g ned to the wdt 0 = pres c a l er i s ass i g ned to the t i m e r0 mo dul e bi t 2- 0 ps2:ps0 : pres c a l e r rate sel e ct bi t s l ege nd: r = r ead ab le b i t w = w ri t ab le bit u = uni m pl em en t e d b it , r ea d a s 0 - n = v a l u e at por 1 = bi t i s s e t 0 = bi t i s c l e a red x = bit is un k n own 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 12 8 bi t v a lu e t mr0 rate wdt ra te
pic16f84a ds35007b-page 10 ? 2001 microchip technology inc. 2.3 . 3 i ntcon re giste r th e in tc o n reg i st er is a rea dab le a nd w rit abl e re gis t er th at co nt a i ns t he va rio us en ab le bi t s for al l i nter rupt so urc es. regis t er 2-3: intcon re giste r (addre s s 0 b h, 8bh) note : interru pt fl ag bit s ar e se t w h e n an in terru pt c ond iti on occ u rs , re gar dle s s of the st a t e of i t s co rres pon din g ena ble b i t or the gl oba l e n a b l e b i t, g i e (intcon<7 > ). r/w - 0 r /w -0 r/w - 0 r /w -0 r/w - 0 r /w -0 r/w - 0 r /w -x gie eeie t 0ie i nte r bie t 0 i f i nt f r bif bi t 7 bit 0 bi t 7 g i e: g l ob al inte rrupt ena b le bi t 1 = en abl es al l u nma sk ed in terru pt s 0 = d is a bl es al l i n t er r u pts bi t 6 eeie : ee writ e co mp lete in terru pt en abl e b i t 1 = en abl es the ee w r ite com p l e te int e rrup t s 0 = d i sab l e s th e ee w r i t e c o mp let e in terr upt bi t 5 t0ie : t m r 0 ov er f l ow i n te rru pt e n ab le b it 1 = en abl es the tm r0 i n te rrupt 0 = di s a bl es t h e tm r 0 i n te rru pt bi t 4 inte : rb0 /int ex te rnal int e rrup t ena b l e bi t 1 = en abl es the rb0/i n t ex ternal int e rrupt 0 = di sab l e s th e rb0 /int e x te rna l i n terr upt bi t 3 rb i e : rb po rt cha nge int e rrup t en abl e b i t 1 = en abl es the rb po rt c han ge int e rrupt 0 = d i sab l e s th e r b port ch ang e i n terr upt bi t 2 t0if : tm r0 o v erfl ow in terru pt fl ag bit 1 = tmr 0 re g is t er h as o v er f l ow e d (m us t be cl ea re d i n sof t w a re) 0 = tmr 0 re g is t er d id no t over f l ow bi t 1 intf : r b 0/int exte rnal in terru pt f l ag bi t 1 = th e rb0/ i n t ex te rn al in t e rr u p t o c c u rr e d (m us t be cl ea re d i n s o f t w a re) 0 = t he r b0 /in t e x t e rna l i n ter rupt did no t oc cu r bi t 0 rb i f : rb po rt cha n g e in terru pt f l ag bi t 1 = at lea s t one of the rb7:r b4 pin s cha n g ed s t a t e (m us t b e c l ea red in sof t w a re ) 0 = n o ne o f th e r b7 : r b4 p i ns ha ve ch ang ed st ate l ege nd: r = r ead ab le b i t w = w ri t ab le bit u = uni m pl em en t e d b it , r ea d a s 0 - n = v a l u e at por 1 = bi t i s s e t 0 = bi t i s c l e a red x = bit is un k n own
? 2001 microchip technology inc. ds35007b-page 11 pic16f84a 2. 4 pcl and pcla th th e p r ogra m c o u n ter (pc ) sp eci f ie s th e a ddre s s of th e i n s t ruc t io n t o fetc h for ex ec uti on. th e pc is 1 3 bit s w i d e . t h e l o w by te i s c a ll ed t h e pc l r e g i s t er . t h i s r e g - i s te r i s r ead abl e a nd w rit a bl e. t he hi gh by te i s ca lle d th e pc h reg i s t er . thi s re gis t er c o n t ai ns the pc < 12: 8> b i t s and is no t di rect ly read abl e o r w rit a ble . if t he p ro- g ram c oun ter (pc ) i s mo dif i ed o r a c ond iti ona l t e s t i s tru e , th e in structi o n re qu ires two cy c l es . the se con d c y c l e is ex ecu t ed as a nop . al l u pda tes to t he pc h re g- i s te r go thro ugh th e pcla th re giste r . 2.4 . 1 s t a ck t he s t ac k al l ow s a c o mb in at i o n of up to 8 pr o g r a m c al ls a nd int e rrupt s to oc cu r . th e st a c k c ont ain s the retu rn ad d res s f rom th i s b ran ch in p r o g ram exec ut i on . m i d -rang e d ev i c es hav e an 8 l ev el dee p x 1 3-bi t w i d e ha rd w ar e s t ac k. t h e sta c k spa c e i s no t par t of ei t he r p rogra m or d at a s p ac e and the s t ac k poi nte r is n ot re ada ble or w ri t abl e. t he pc i s pu sh ed on to th e st ac k w h en a call i n s t ruc t io n is ex ec ute d or an in terru pt c aus es a bran ch . the s t ac k i s po ped in t he ev en t of a retur n, retl w or a re tfie i ns t ruc t io n e x ec ut i on . pc la t h i s n o t mo di f i e d w h en t h e s t ac k i s pu sh ed o r poped . aft er the s t ac k ha s bee n pu sh ed ei ght ti me s, th e nin t h p ush ov erw rit es th e v alu e tha t w as s t or ed fro m th e firs t p ush . th e te nth p us h ov erw ri t es the se co nd p us h (an d so on ). 2. 5 i ndir ect addres sing; i ndf and fsr r e gist ers th e in d f registe r is no t a p h y s i c a l reg i s t er . addr ess i n g in d f ac tu all y ad dres se s th e regi st er w hos e ad dres s i s c ont ain ed in t he fsr reg i st er (fsr is a po in ter ). th is i s i ndi rec t ad dres s i ng . ex amp l e 2-1: indir e ct ad dres s ing r e a d i ng i n d f it s e l f i ndi rec t ly (fsr = 0) w i ll produc e 00 h. w rit ing to th e in d f reg i s t er i ndi rec t ly res ult s in a no -op e rat i on (al t ho ugh st a t u s bit s m a y be af fec t ed ). a si mp le p rogra m to c l ea r r am lo cat i on s 20 h-2f h us in g i ndi rec t ad dre s s i ng is s how n in exa m p l e 2 -2. ex amp l e 2-2: how to c l e ar r a m us ing indir e ct addre s s ing an ef f ect iv e 9-b i t a ddre s s is obt ain ed b y c on c a t ena tin g th e 8-b i t fsr reg i s ter a nd th e irp bi t (st a tus<7 >), a s s how n in f i gu re 2 - 3. h o w e ve r , ir p is no t us ed i n th e pic1 6f8 4 a. ? r eg is ter f ile 05 co nt a i ns th e v al ue 1 0h ? r eg is ter f ile 06 co nt a i ns th e v al ue 0 ah ? l oad the va lue 05 in to t he f sr reg i st er ? a re ad of th e in d f r egi ste r w ill ret u rn t he v a l ue of 1 0h ? i n c re me nt t he va lue of the fsr re gis t e r by on e (fs r = 06 ) ? a re ad of t he i ndf reg i s ter n o w wil l re turn the v a lu e o f 0ah . movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue
pic16f84a ds35007b-page 12 ? 2001 microchip technology inc. figure 2-3: dire ct/indi rect a ddre ss ing direct addressing rp1 rp0 6 from opcode 0irp7 (fsr) 0 ind irect ad dressin g b ank s elect loc ation select bank selec t loc at ion select 00 01 80h ff h 00h 0b h 0ch 7fh ba nk 0 b ank 1 no t e 1: for me mory m ap det ail, see f igure 2 -2. 2: m aint a i n as clear f or upward com p ati bilit y with fut ure produc t s . 3: no t i m plemented. 4fh 50h da t a me mo r y (1 ) (3) (3) (2) (2) add r es s e s ma p b ac k to ban k 0
? 2001 microchip technology inc. ds35007b-page 13 pic16f84a 3.0 dat a eeprom m e mory th e eeprom d a t a m e m o ry is read ab le a nd writ abl e du r i ng no r m a l o pe r a t i o n ( f ul l v dd rang e). thi s me mo ry is no t di r e ct ly ma p p e d i n t h e r e g i s t er f i le spac e. i n st e a d i t i s i nd i rec t ly a ddre s s ed th roug h t he spec ia l f unc tio n regist ers . ther e a r e four sfr s u s ed to re ad and w r i t e th is me mo ry . t hes e re gis t e r s a r e: ? eecon1 ? eec o n 2 (n ot a ph ys ic al ly im ple m e n te d re gis t er) ? eeda t a ? eeadr eeda t a ho lds th e 8 -bi t da t a for re ad /write , an d eeadr h o l d s the ad dres s of t he eepro m l o c a tio n b ein g a c c es s e d. pic 16f 84a dev ic es h ave 6 4 b y te s of d a t a eepro m wi th a n a ddre s s ran ge from 0h to 3fh . th e eeprom dat a m e m o ry a llo ws b y te rea d an d writ e. a by te w ri t e a uto ma tic all y e ras es t he l oca tio n an d writ es the n e w da t a (e ras e be fore write ). the eepro m d ata m em o ry is r at e d f o r hi gh e ras e/ w ri t e c ycl e s . t he w rit e tim e is co ntrol l e d by a n on-c hi p tim er . t he w rit e- ti me w ill v ary w i th vo lt ag e a nd tem pera t ure as w el l a s f rom ch ip t o c hi p. p l ea se r e fe r t o a c s pe c i f ic at i o ns fo r ex ac t l i m i t s . wh en th e dev ic e is cod e pro t ec ted , t he c pu ma y c ont inu e to rea d and wr ite th e dat a eepro m m e m o ry . th e d e vi ce pro g ramm e r c an n o l ong er a c c e s s th is me mo ry . ad dition al in form ati on on t he d a t a ee pr o m i s av ai l- ab le in th e pic m ic ro? m i d -r ang e r ef eren c e ma nua l (ds3 302 3). reg is t er 3-1: ee co n1 r e g is t er (add res s 8 8 h) u-0 u -0 u-0 r /w -0 r/w -x r /w -0 r/s-0 r/ s-0 eeif w rerr wren wr rd bi t 7 bit 0 bi t 7- 5 unimp lem ente d: r e ad as '0 ' bi t 4 eeif: eeprom write opera tion in terru pt f l ag bit 1 = t he w r i t e o p e rati on c o m p l e te d (m us t be cl ea red i n s o ft w a re) 0 = t he w ri t e o pe rati on i s not com pl ete or h as no t be en st a rted bi t 3 wrerr: eeprom error f l ag bi t 1 = a w ri t e ope ration is prem at urely t e rm ina t ed (an y m c lr r e set or a n y wd t r e se t du rin g no rma l o pera t io n) 0 = t he w r i t e o p e r ati on c o m p l e te d bi t 2 wren: eeprom w r i t e en ab le b i t 1 = al l o ws wri t e cy cl e s 0 = in hi bit s wri te to th e eeprom bi t 1 wr: w r ite c ont rol bit 1 = in iti ate s a w r ite c y c l e. the bi t is c l ea red by hard w are onc e w r i t e is co mp lete . th e w r bit ca n o n ly be se t (n ot c l e a red ) in so ftware . 0 = w r it e c y c l e to t he ee pr o m is c o m p le te bi t 0 rd : read con t rol bit 1 = in iti a te s a n eeprom rea d rd i s c l e a red in har dware . th e rd bi t c an onl y b e s e t (not c l eare d ) i n s o ft ware. 0 = do es not ini tia te a n eeprom rea d l ege nd: r = read ab le b i t w = w ri t ab le bit u = u n imp l e m e nted bi t, re ad as 0 - n = v a l u e at por 1 = bi t i s s e t 0 = bi t i s c l e a red x = bit is un k n own
pic16f84a ds35007b-page 14 ? 2001 microchip technology inc. 3. 1 r eadi ng the eepr om d a t a memory t o rea d a d at a m em ory lo ca tion , the us er m ust w ri t e th e a ddres s to th e eead r reg i s t er an d th en s e t con t rol b i t rd (eeco n 1 < 0> ). th e dat a i s av ai lab l e, in th e v e ry ne x t cycl e, in t h e e ed a t a r eg i st er ; th e ref o re, it c a n be re ad i n the n ex t ins t ru cti on. e ed a t a w ill hol d thi s v alu e u ntil an oth er rea d o r unt il i t is w ritt en t o by the us er (d uring a write op erat ion ). ex amp l e 3-1: dat a ee p r om re ad 3. 2 w r i t i ng t o t he eeprom dat a memory t o writ e an eepro m da t a lo c a tio n , th e us er m u s t firs t w ri t e th e a ddres s to the eead r reg i s t er and the da t a to the eed a t a regi ste r . th en th e us er m u st f o ll ow a s pec if ic se que nc e to in itia te the w rite for e ac h b y te . ex amp l e 3-2: dat a ee p r om w r ite th e w ri t e w i l l n ot in iti ate if th e ab ov e s equ enc e i s n ot e x ac tl y fo ll ow ed (w rite 55 h to eec on 2 , w rit e aah to eec o n 2, the n se t w r bi t) f o r eac h by te. w e s t ro ngl y re co mm end tha t in terru pt s be dis ab l ed du ring thi s c ode s egm en t. addition ally , the wr en bit in eec o n 1 m u st b e se t to enab le w r ite. this m echan ism prev ent s acc ident al w r ites to dat a eepr o m due t o errant (unex pected) code exe- cu t i on (i.e., l o st programs ). the us er should k eep the wr en bit c lear at all time s, excep t w hen up dating eepr o m . the wren bit is not cleared by hardw are. aft er a w rit e se qu enc e ha s b een ini t ia ted, cle ari ng th e wr en b i t w i l l no t af fec t thi s w rit e cy c l e. t he wr b i t w i l l be inh i b i ted from bei ng s et u nle ss the w r en b i t is se t. at the c om pl etio n of the w rit e cy cl e, the wr bit i s c l ea red in ha rdw a r e a nd the ee w ri t e c o mp le te in terru pt f l ag bi t (eeif ) is s e t. t he u s e r c an e i th er en ab le thi s in terru pt or po ll th is b i t. eeif m u s t b e c l ea red by so ftw are . 3 . 3 w ri te v e ri fy d ep end in g o n th e a ppl ic atio n, goo d p rogra m m i n g pr act i c e m ay dic t at e th at th e v alu e w ri tten to th e d at a eeprom s h oul d be v e rifi ed (ex a m p l e 3 -3) to th e de si red va lue to be w r itte n. t his s hou ld be use d i n ap pl ic atio ns whe re a n eeprom bit wil l b e s tres s e d ne ar t he spe c i f ic ati on lim it . gen e ral l y , th e eepro m write fa ilu re wil l be a bi t w h ic h w as w ri tten as a ' 0 ' , but read s bac k as a ' 1' (d ue to l eak age of f th e b i t). ex amp l e 3- 3: w r it e v e r i f y t a ble 3 - 1 : regis t er s/bi t s as sociate d w i th dat a e e p r om bcf status, rp0 ; bank 0 movlw config_addr ; movwf eeadr ; addre ss to read bsf status, rp0 ; bank 1 bsf eecon1, rd ; ee re ad bcf status, rp0 ; bank 0 movf eedata, w ; w = e edata bsf status, rp0 ; bank 1 bcf intcon, gie ; disable ints. bsf eecon1, wren ; enable write movlw 55h ; movwf eecon2 ; write 55h movlw aah ; movwf eecon2 ; write aah bsf eecon1,wr ; set wr bit ; begin write bsf intcon, gie ; enable ints. r e qu i r ed s equence bcf status,rp0 ; bank 0 : ; any code : ; can go here movf eedata,w ; must be in bank 0 bsf status,rp0 ; bank 1 read bsf eecon1, rd ; yes, read the ; value written bcf status, rp0 ; bank 0 ; ; is the value written ; (in w reg) and ; read (in eedata) ; the same? ; subwf eedata, w ; btfss status, z ; is difference 0? goto write_err ; no, write error add ress nam e bi t 7 b it 6 bit 5 bi t 4 bi t 3 bi t 2 bit 1 bit 0 v a lu e on po wer- on re set v a lu e on al l ot her re se ts 08h e eda t a ee prom dat a reg i s t er xxxx xxxx uuuu uuuu 09h e ea d r ee prom add ress register xxxx xxxx uuuu uuuu 88h e econ1 e e i f w re rr w re n w r rd ---0 x000 ---0 q000 89h e e con2 ee prom control regis t e r 2 ---- ---- ---- ---- legend: x = unknown, u = unc hanged, - = unimp l em ent e d, read a s '0', q = value depends upon c ondit ion. shaded cells are not used by dat a ee prom .
? 2001 microchip technology inc. ds35007b-page 15 pic16f84a 4. 0 i /o p o rt s s o m e pi n s f o r t h es e i/ o po r t s ar e mu l t ip le x e d w i t h an a l ter nate fu nc tion fo r th e p e rip hera l feat ures o n th e d evi ce . in ge ner al, w he n a pe rip hera l is ena ble d, th at pin ma y n o t b e us ed as a gen eral pu rpos e i/o pi n. ad dit i on al inf orm atio n o n i / o por t s ma y b e f oun d i n th e pic m ic ro? m i d -r a ng e r e fer enc e m anu al (d s33 0 2 3 ). 4. 1 p ort a and trisa regist ers po r t a is a 5-bi t w i de , bi -dire c ti on al po rt. th e co rre- s pon di ng da t a dire cti o n reg i s t er is t r i sa. se tti ng a tri sa b i t (= 1 ) wi ll m a k e th e c o rres pon din g po r t a pi n a n i npu t (i .e., pu t th e cor resp o n d in g o u tp ut driv er in a h i -impeda nc e mo de ). c l ea ring a tr isa bi t (= 0) w i l l m a k e the corr esp o n d in g por t a p i n a n out put (i .e., p u t th e c o n t ent s o f th e o u tpu t l a tc h on th e s e le cte d p i n) . r e adi ng the po r t a reg i st er reads the s t at us o f th e p i ns , w herea s wri t in g to i t wi ll w ri t e to th e po rt lat c h. al l w ri t e o perat io ns are rea d -m odi fy- w r i te ope rations . th ere f ore , a w ri t e to a por t im pl ies th at t he p o rt pin s a re re ad. th is v a lu e is m odi fie d a n d th en w ritt en to the p o rt da ta l a tc h. pi n r a4 is m ult ipl ex ed w i th the t i m er0 m odu le cl oc k i npu t to be co me t he r a4/ t0c ki pi n. th e r a4/t 0c ki p i n is a sc hm itt t rig ger inp ut and an ope n d rai n o utpu t . al l o t he r r a port pi ns ha ve tt l i npu t l e v e ls a nd ful l c m os out put driv ers . ex amp l e 4-1: initializi ng po rt a figure 4-1: block dia g r am of pi ns r a 3:ra0 figure 4-2: block dia g r am of p i n ra4 note : on a p o w e r - o n r e se t , t h es e pi ns a r e c o n - fi gured as inputs and read a s '0 '. bcf status, rp0 ; clrf porta ; initialize porta by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0x0f ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as input s ; ra4 as output ; trisa<7:5> are alway s ; read as '0'. data bus q d q ck q d q ck qd en p n wr po r t wr tris da t a lat c h t r is l a t ch rd tris rd po r t ttl input bu f f e r v ss v dd i/ o p i n no te: i /o pins have protection di o des t o v dd and v ss . dat a bus wr por t wr tri s rd port dat a lat c h t r is latc h rd tri s schm i tt t r igger i nput buf f er n v ss ra4 pin tmr0 clock input q d q ck q d q ck en qd en no t e: i / o pins have protection diodes to v dd and v ss .
pic16f84a ds35007b-page 16 ? 2001 microchip technology inc. t a ble 4 - 1 : p o rt a fun ctions t a ble 4 - 2 : sum m ar y of re giste r s ass o ciated with p o rt a name bit0 buffe r t y pe fun ction ra0 b i t 0 t tl i npu t/out pu t ra1 b i t 1 t tl i npu t/out pu t ra2 b i t 2 t tl i npu t/out pu t ra3 b i t 3 t tl i npu t/out pu t ra4 /t0cki b i t4 s t i npu t/ou tpu t or ex tern al c l o c k in put for tmr0 . o u tput is op en drain ty pe . l ege nd: tt l = ttl inp u t, st = schm it t t rig ge r inp u t address name bi t 7 bi t 6 b i t 5 b i t 4 bit 3 bi t 2 bit 1 bi t 0 v a lu e on p o w er- o n reset v a lu e on al l ot her re se t s 05h p o r t a r a 4 / t 0cki ra3 ra2 ra1 ra0 ---x xxxx ---u uuuu 85h trisa t ri s a 4 t ri s a 3 t risa 2 t ri s a 1 t risa 0 ---1 1111 ---1 1111 legend: x = unknown, u = unc hanged, - = unimp l em ent ed, read as '0'. shaded cells are unimplemented, read as '0'.
? 2001 microchip technology inc. ds35007b-page 17 pic16f84a 4. 2 po rtb and trisb reg i st ers po r t b i s an 8 - bit w i de, bi -di r ec tion al p o rt. th e co rre- s pon di ng da t a dire cti o n reg i s t er is t r i sb. se tti ng a tri sb bi t (= 1 ) will m a k e th e c o rres p o ndi ng po r tb pi n a n i npu t (i .e., pu t th e cor r esp o n d in g o u tp ut driv er in a h i -impeda nc e mo de ). c l ea ring a tr isb bi t (= 0) w i l l m a k e the co rres p o ndi ng po r t b pin an o u tp ut ( i .e. , p u t th e c on t ent s o f th e o utpu t l atc h on th e s ele cte d p i n) . ex amp l e 4-2: initializi ng po rtb ea ch o f th e po r t b pi ns has a w e ak i n te rnal pul l-u p . a si ng l e co nt ro l bi t ca n tu rn o n a l l t h e pu l l- u p s . t hi s i s pe r- fo rme d by c l e a ri ng bi t r bpu (o p t io n < 7>). t he w e a k p ull -up is aut om atic al ly turn ed of f w hen the po rt pi n i s c onf igu r ed as an ou tpu t. t he pu ll- up s a re di sab l e d o n a po wer-on res e t. fo ur of po r t b s pi ns , r b7 : r b4, hav e an in terru pt-o n- c han ge fe atu re. o nl y pi ns c onf igu red a s in put s ca n ca u s e t h is i n te rru pt t o oc cu r (i . e ., an y r b7 : r b4 p i n c onf igu red as a n o u tp ut is ex c l ud ed from t he in terru pt- o n -c han ge c o m p a ris on) . the in put pin s (of r b7 : r b4) ar e c om p a red w i t h th e ol d va l ue l at c he d on t h e l a st re ad of po r t b. th e m isma t c h o u tpu t s o f r b7 : r b4 a re o r e d to gethe r t o ge ner ate the r b port c h ang e in terru pt wi th f l ag bi t rbif (intcon<0>). th is i n ter rupt ca n w a k e t he dev ic e from sl eep . th e u s er , in t he in terru pt se rvi c e r o uti ne, c a n cl ear th e i nter rupt in the fol l ow i ng m an ne r: a ) an y read o r w rit e o f po r t b. t h is w i ll end th e m i s m a t ch c ond iti on. b ) c l ear fl ag bi t r bif . a m i s m a t c h c ond itio n w i ll c on t in ue to se t fl ag b i t r bif . r e adi ng por t b w i ll end th e m i s m atc h c on dit ion an d a llo w fla g b i t rbif to be c l e a re d. th e i n te rrupt -on-ch a nge fea t ure is rec o m m end ed for w a ke-u p on k e y d epre s s i o n ope rati on an d op erat ion s w h ere po r t b i s o n ly us ed f o r the int e rrup t -on - ch ang e fe atu r e. po ll ing of por t b is n o t re co mm en ded w h il e us in g th e in t er ru pt -o n- c h an ge f ea t ur e . figure 4-3: block dia g r am of pi ns r b 7:rb4 figure 4-4: block dia g r am of pi ns r b 3:rb0 bcf status, rp0 ; clrf portb ; initialize portb by ; clearing output ; data latches bsf status, rp0 ; select bank 1 movlw 0xcf ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as input s ; rb<5:4> as outputs ; rb<7:6> as inputs rbpu (1) d a t a la tch f r om o t her p v dd q d ck q d ck qd en qd en data bu s wr po r t w r t r is s e t rb if t r is la tch rd t r is rd po r t rb7 : rb 4 p i n s w eak pu ll- u p rd po r t lat ch tt l in put b u ffer no t e 1 : tr is b = ' 1' ena bl es wea k pu l l - up ( i f rbpu = '0' i n th e o p tio n _r e g r e g i ster ). 2: i/o pi ns ha ve d i ode pr ote cti on to v dd an d v ss . i/o pin (2) rbpu (1) i/o pin (2) data latch p v dd q d ck q d ck q d en da t a b u s wr po r t w r t r is rd t r is rd po r t we a k pu ll- u p rd port rb0/int ttl input buffer sc hm i tt t r i g ger bu f f e r t r is la tch not e 1 : t r is b = ' 1 ' en ab l e s w e a k p ul l -u p ( i f rbpu = ' 0 ' in the opt ion_ r e g r egist er) . 2: i/o pins hav e dio d e pr otec tion to v dd and v ss .
pic16f84a ds35007b-page 18 ? 2001 microchip technology inc. t a ble 4 - 3 : portb fun c tions t a bl e 4 - 4 : sum m ar y o f re g ist e r s ass o ciat ed wit h p o rt b name bi t b uffe r t y pe i/o con s is tenc y fu nctio n rb0 /int b i t 0 t t l /st (1 ) inp u t/o utp u t p i n or e x te rnal in terru pt i npu t. interna l s o ftw a re p rogram m a b l e w eak pu ll- up. r b1 b it 1 t t l i n pu t / ou t pu t pi n . i n t er n al so f t w ar e pr o g ram ma bl e w e a k p ul l- u p . r b2 b it 2 t t l i n pu t / ou t pu t pi n . i n t er n al so f t w ar e pr o g ram ma bl e w e a k p ul l- u p . r b3 b it 3 t t l i n pu t / ou t pu t pi n . i n t er n al so f t w ar e pr o g ram ma bl e w e a k p ul l- u p . r b4 b it 4 t t l i n pu t / ou t pu t pi n (w i t h i n te rru pt -o n- c ha n ge ). interna l s o ftw a re p rogram m a b l e w eak pu ll- up. r b5 b it 5 t t l i n pu t / ou t pu t pi n (w i t h i n te rru pt -o n- c ha n ge ). interna l s o ftw a re p rogram m a b l e w eak pu ll- up. rb6 b i t 6 t t l /st (2 ) inp u t/o utp u t p i n (w ith int e rrupt -on -ch ang e). interna l s o ftw a re p rogram m a b l e w eak pu ll- up. seria l p rogr am min g c l o c k . rb7 b i t 7 t t l /st (2 ) inp u t/o utp u t p i n (w ith int e rrupt -on -ch ang e). interna l s o ftw a re p rogram m a b l e w eak pu ll- up. seria l p rogr am min g d a t a . l ege nd: t t l = ttl in put, st = sch m i tt t ri gge r. note 1 : th is bu f f e r is a sch m it t t rig ge r in put w h en co nfi gured a s th e e x te rna l i n terr upt. 2: th is bu f f e r is a sch m it t t rig ge r in put w h en us ed in se ria l pro gram m i ng m ode . address name b i t 7 bit 6 bit 5 bit 4 bit 3 bi t 2 bi t 1 bit 0 v a lu e on p ower - o n reset value on all ot her res e ts 06 h p o r tb rb7 r b6 r b 5 r b4 rb3 r b2 rb 1 r b0/i nt xxxx xxxx uuuu uuuu 86 h tris b tri s b7 t r is b6 t r is b5 tri s b4 tri s b3 tri s b2 tris b1 t r is b0 1111 1111 1111 1111 81 h o p tio n_ reg r b pu intedg t0cs t0se psa ps2 ps 1 ps0 1111 1111 1111 1111 0bh,8bh intcon gie eeie t0ie inte rbie t0if intf rbif 0000 000x 0000 000u legend: x = unknown, u = unchanged. shaded cells are not used by portb.
? 2001 microchip technology inc. ds35007b-page 19 pic16f84a 5. 0 t i me r 0 m o du le th e t i m e r0 m o d u le t i m e r/c oun ter ha s the foll ow in g fe atu r es : ? 8 -bit tim e r/c o u n te r ? r ea da ble an d w rit abl e ? i n t ern al or e x te rnal c l oc k sel ec t ? ed ge sel ec t fo r ex tern al cl ock ? 8 -bit so ftw are pro g ramm abl e p res cal e r ? in terru pt-o n-ov erf l ow f r om ffh to 00h fi gu re 5- 1 is a si mp li fied blo c k di agra m o f the t i me r0 mo du l e . ad dit i on al i nfo rma t io n o n ti me r mo dul es is av ail ab l e i n th e pic m ic ro? m i d -r ang e r e f e ren c e ma nua l (d s3 302 3). 5. 1 t imer 0 opera t i on t i me r0 c an ope rate as a t i m e r o r as a co u n te r . t i m e r mo d e is s e l e ct ed by c l e a r i n g bi t t 0 c s (o p t io n _ reg <5>). in t i me r m o d e , the t i me r0 mo d- u l e w i ll i n c rem en t ev ery ins t ru cti on c y c le (w ith o u t pre s - c a l e r). if the t m r 0 re gis t er is w ritten, the i n c rem ent i s i nhi bit ed for t he f oll ow in g tw o in stru ct ion cy c l es . th e u s er c an w o rk aro u n d t h is b y w riti ng an ad jus t ed v a lu e to the tm r0 re giste r . c o unte r mod e is sel ec t ed b y se tti ng bi t t0c s (o p t io n _ r eg <5>). in c o unt er m o d e , t i me r0 w i l l i nc rem ent, e i th er on e v e ry ri si ng or fa ll ing e dg e of pi n r a4 /t0c ki. the i nc rem ent ing edg e is de term in ed b y th e t i m e r0 sou rc e edge sele c t b i t, t 0 se (op t ion _ reg<4>). clea rin g bi t t0 se s e le c t s th e ri s - i ng ed ge. r e stri cti on s on th e ex tern al c l oc k in pu t a re di sc u sse d be l o w . wh en an ex tern al cl oc k i npu t i s u s e d f or t i me r0, it m us t m eet ce rt ai n re qui reme n t s. the req u ire m e n t s en su re th e ex tern al cl oc k ca n be s y n c h roni ze d w i th th e int erna l ph as e cl oc k (t os c ). a l s o, t h er e i s a de l ay i n th e a c t u al i n cre m e n ti ng of t i me r0 a fter sy nc hroniz ati on. ad dition al i n fo rma t io n on ex ternal clo c k req u i rem ent s i s av ail a b l e in t he pic m ic ro? m i d-r a nge r e ferenc e m anu al , (d s33 023 ). 5. 2 p rescaler an 8- bi t c o u n t e r i s av ai la bl e as a pre s c a le r fo r th e t i m e r 0 mo du le , or a s a p os t sc al er f o r th e w at c h do g t i me r , re s p ec ti v e l y (f ig ure 5 - 2 ). f o r s i m p li c i ty , t h i s c o u n te r is b e i n g r e fe rre d to as p res c a l e r t h ro ug ho ut t h i s d a t a s h e e t . n o te tha t th ere is on ly o n e pre s c a le r a v ai la bl e w h ic h i s m utu al ly ex c lu s i v e ly sh ar ed b etw e en the t im er 0 mo du le an d th e w a tc hd og t i m er . th us , a p r e s c al er a s s i g n m e nt f o r t h e t i m e r0 m o dul e m e an s t h a t th ere is n o pr e sca le r f o r t h e w a t c hd og t ime r , an d v ice - v e r s a . th e p res cal er i s not read abl e o r writ abl e. th e psa an d ps2: ps0 bi t s (op t ion_reg<3:0 > ) de term in e the pres ca ler a s s i gn me nt an d pre s c ale rati o. cle a ri ng b i t psa wil l as s i gn t he p res c a l e r to the t i m e r0 m odu le . whe n th e p r es cal e r i s a s s i g ned to t he t i me r0 m odu le , pre s c ale v alu es of 1 : 2, 1:4, ..., 1:25 6 a re s e le ct abl e. set t ing bit p s a w ill assign the pr escaler t o t he w atch dog t i me r ( w d t ). w hen t he pr escaler is assigned to t he wd t , pr escale values of 1: 1, 1:2, .. ., 1:128 are selectable. wh en as si gne d to the t i m er0 mo dul e, all in stru cti on s writ ing to the tm r0 re gi ste r (e. g ., clrf 1, movwf 1, bsf 1, etc . ) w ill cle ar the pres ca ler . whe n ass i g ned to wdt , a clrwdt i n st ruc t io n w i l l c l ea r th e pre s c a l e r al on g w i t h th e wd t . figure 5-1: t i m e r0 block dia g r a m note : w r i t in g t o tm r 0 w h e n t h e p r es ca le r is a ssi g n e d t o t i me r 0 w i ll c l ea r t h e p r es ca le r c oun t, b u t w ill no t c han ge the pre s c a l e r as s ign me nt. note 1: t0cs, t0se, psa, ps2:ps0 (option_reg<5:0>). 2: the presca l e r is share d wit h w a t c hd og t i mer ( r ef er t o figure 5 -2 f o r det ailed block diagram) . ra4/t0cki t0se 0 1 1 0 pin t0cs f osc /4 programmable prescaler sync with internal clocks tmr0 ps ou t (2 cyc l e delay) ps ou t dat a b us 8 ps a ps 2 , ps 1 , ps 0 set interrupt flag bit t0if on overflow 3
pic16f84a ds35007b-page 20 ? 2001 microchip technology inc. 5.2 . 1 s w i tchin g pre s ca le r as si gn men t th e pres ca ler as si gnm en t i s full y und er sof t w are co n- tro l (i. e ., it c a n b e ch ang ed o n the f l y d u ri ng pro g ra m e x ec ut ion ). 5. 3 t imer0 i n ter r upt th e t m r 0 in terru pt is ge nerat ed w h e n t he tm r 0 re g- i s te r ov erflows from ffh to 0 0h. thi s o v er flow s e t s b i t t 0 i f ( i n t c o n < 2> ). t h e in t e rr u p t ca n b e ma sk ed by c l ea rin g b i t t 0 ie (intco n<5>) . bit t0 if m u s t b e c l ea red in s o ftware by th e t i m e r0 m o d u l e in terru pt ser- vi ce r o ut i ne be f or e r e- e n ab l in g t h is in t er ru pt . t he tm r 0 int e rrupt c a n not aw ak en th e p roc es sor from sl eep s i nc e th e ti m e r is s hut -of f du ring sleep . figure 5-2: block diagra m of the t i m e r0 /wd t pre s c aler t a ble 5 - 1 : regis t er s as s o ci ated w ith t ime r0 note : to avoid an unintended dev i c e reset , a s pec if ic i ns t ruc t io n s equ enc e (s how n in th e picmic ro? m i d -rang e re feren c e m a n- u al, d s330 23 ) mu st be ex ec ute d w he n c han gi ng t he pres ca ler as si gnm en t fro m t i me r0 to the wd t . thi s s equ enc e m us t b e fo llo w ed eve n i f th e wd t is di sa ble d. ra4/t0cki t0se pin m u x clkout (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1 m u x m u x m u x wa tchdog t i mer ps a 0 1 0 1 wd t t i m e -out ps 2:p s0 8 no te: t 0cs , t0se , ps a, ps 2:ps0 are (op t i o n_re g<5: 0>). ps a w d t enable bi t m u x 0 1 0 1 dat a bus s e t f lag bit t 0 i f on ov erf low 8 psa t0cs addres s name bi t 7 b it 6 b it 5 b i t 4 b i t 3 b it 2 b it 1 b it 0 v a lue on po r, bor v a lu e on al l ot her re se ts 01 h t m r 0 t imer0 module register xxxx xxxx uuuu uuuu 0b h,8bh i ntcon gie ee ie t0ie inte r bie t0if intf rbif 0000 000x 0000 000u 81 h o pt ion_reg rbpu in te d g t0 c s t 0 se ps a p s 2 ps 1 p s 0 1111 1111 1111 1111 85 h t risa p or t a dat a direction r egi s t er ---1 1111 ---1 1111 le gend: x = unk nown, u = unch anged, - = unimplem ent ed locat ions read as '0' . shaded cells are not u s ed by t i m e r0.
? 2001 microchip technology inc. ds35007b-page 21 pic16f84a 6.0 s pecial fe a t ures of the cpu w hat se t s a m i c r oc on trol ler ap a r t f r om oth e r p r oc ess ors are sp ec ial ci rcu i t s to d eal w i th the nee ds of re al ti me a ppl ic atio ns . the pic 1 6f8 4 a has a hos t of s uc h fe atu r es inte nd ed t o m axi mi ze sy st em reli ab ili ty , m i n i m i ze cos t thro ug h eli m i nat ion o f ext erna l c o m pon en t s , prov id e p o w e r s a v i n g op era t ing m ode s a nd o f f e r c ode pro t ec tio n . t hes e f eat ures are : ? o sc sel e c tio n ? r eset - pow e r-o n r e se t (p o r ) - po w er-up t i m e r ( pwr t) - o s c il la tor s t a rt-up t i m e r (ost) ? in terru pt s ? w a tc h dog t i m e r (wdt) ? sl eep ? c od e pro tec t io n ? i d l o c a ti ons ? i n -circ uit seri al progra m m i n g ? (i csp?) t he pi c 1 6f 8 4a ha s a w at c hd o g t im er w hi c h c a n be s hut -of f o nly t hrou gh co nfi gur atio n bit s . it runs o f f it s o w n r c osc i l l a t or for add ed rel i ab ili ty . the re a re tw o ti me rs th at o f fe r n e c e s s a ry de lay s o n po w e r-u p. o ne i s th e o s c i l l at or s t art-u p t i m e r (o st), i n te nde d to kee p th e c hip in r es et un til the c ry s t a l os c ill ato r is st a bl e. th e oth e r is t he pow e r-up t i m e r (pw r t), w h i c h p ro- v i de s a fix ed del ay o f 72 m s (no m i nal ) on p o w e r-u p on ly . th is d e s i gn k e e p s th e dev ic e in reset whi l e th e po w er s up ply s t abi li ze s. w i th the s e tw o ti me rs o n-c hi p, m o s t ap pli c a t io ns nee d n o e x te rnal reset c i rc ui try . sl eep m ode o f fe rs a v e ry l o w c u rrent po wer-do w n m ode . the u s e r c a n wa k e - up fro m sleep th roug h ex te rnal reset , w a tc hdo g t i m e r t i m e -ou t o r th roug h an i n ter r upt. sev e ra l o s c i l l at or o p ti ons a r e p r ov ide d to al lo w the p art t o fit the app lic ati on . the r c osc i l l at or o p t i on sa ve s sys t e m co st wh i l e t h e l p cr ystal o p t i on s av es po w e r . a se t o f c onf igu rati on bit s a re use d to s e le ct the va riou s opti o n s . ad dition al in form ati on on s p e c i a l fe ature s is av ail abl e i n t he pic m i c ro ? m i d -r ang e r e fer enc e ma nua l (d s3 302 3). 6. 1 c onf igur ati on b i t s th e c onfig u rati on b i t s ca n be prog ramm e d (re ad a s ' 0 ' ), or left unp rogra m m ed (rea d as '1 ') , to s ele ct v ari ou s de vi ce co nfi gura t io ns. the s e bit s ar e m app ed i n pr ogram m e m o ry l o ca tio n 2 007 h. ad dres s 2 007 h is bey on d the u s e r prog ram mem or y s p ac e an d i t b el ong s to the s pec ia l t es t/co nfi gura t io n m e m o ry sp ac e (20 00h - 3ff f h). t h is s p ac e c an o n l y be ac ce ss ed du ring pro gram m i ng . regis t er 6-1: pi c16f84 a configuration w o r d r/p-u r / p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/p-u r/ p-u cp cp cp c p cp cp cp cp cp cp pwr t e w d te f0sc1 f 0 s c0 bi t 1 3 bi t 0 bi t 13 - 4 cp: cod e pro tec tio n b i t 1 = c ode pro t ec tio n di sa ble d 0 = all prog ram m e mo ry is co de prote c t e d bi t 3 pwrte : powe r-up t i m e r ena b l e bi t 1 = power-u p t i m e r is di s a ble d 0 = pow e r-u p t i me r is en abl ed bi t 2 wdte : w a tc hd og t i m e r en abl e bi t 1 = wdt e nab led 0 = wd t d i s abl ed bi t 1- 0 fosc1:f o sc0 : o s c ill ato r sel ec t io n bi t s 11 = rc o s c i l l a to r 10 = hs os ci lla tor 01 = xt os c ill ato r 00 = lp o s c ill ato r
pic16f84a ds35007b-page 22 ? 2001 microchip technology inc. 6. 2 o sci ll ator conf ig urat ions 6.2 . 1 o s ci lla tor t y pe s th e pi c 16f84 a c a n be ope rated i n fo ur d i f f ere n t o s c ill ato r mo des . th e us er c a n prog ram tw o c onf igu rati on b i t s (fo sc 1 a nd f o sc 0 ) to s ele ct one of th es e fo ur m o d e s : ? l p l ow powe r cry s t a l ? xt c ry st al/r e s o nat or ? h s h i gh sp ee d c ry s t a l/r e son a to r ? r c r e s i s t or / c a pac it o r 6.2 .2 cry st al osci lla to r /cer a mi c res o na t o rs in x t , lp , o r hs m ode s, a c rys t al or cer a mi c reso na tor i s co nne cte d to the o sc 1/c l kin a nd osc 2 /c lko u t p i ns to es t a b lis h o s c i l l at ion (fig ure 6 -1 ). figure 6-1: cry st al/ce ramic res o nator op erati o n ( h s, xt o r l p o s c configuration) th e pic 1 6f8 4 a os ci ll ator d e s i gn req u ire s th e us e o f a p a ra ll el c u t cr ys tal . use o f a se ri es cu t c rysta l ma y g i ve a fre que nc y out o f th e cry s t al ma nu fac t ure rs s pec if ic ations . whe n in xt , l p , or h s m ode s, th e d evi ce ca n hav e a n ex tern al c l oc k s ou rce t o dri v e th e osc1/cl kin pi n (f igu re 6 -2). figure 6-2: ex ter nal clock inpu t ope ration ( hs , x t or lp osc configuration) t able 6 - 1: cap a c ito r se lec t i o n for ce ramic res o nators note 1 : se e t a b l e 6 -1 f o r re co mm en ded v a lu es o f c1 a n d c2 . 2: a s e rie s res i s t or (r s ) m a y be re qui red fo r a t st r ip cu t cr ys t a l s . c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic16fxx r s (2) internal ranges tested: mode fr eq o s c 1 /c 1 o sc 2 / c 2 xt 45 5 kh z 2.0 mh z 4.0 mh z 47 - 100 pf 15 - 33 pf 15 - 33 pf 47 - 100 pf 15 - 33 pf 15 - 33 pf h s 8.0 mh z 1 0 .0 mhz 15 - 33 pf 15 - 33 pf 15 - 33 pf 15 - 33 pf note : r ec om m end ed va lue s of c 1 an d c 2 a re i den tic al to th e ra nge s tes t ed in thi s t abl e. h ig her c a p a c it a nce inc rea se s th e st abi lit y of th e o s c i l l at or , but al so i ncr eas es th e s t art- up ti me . th ese va lue s a re fo r des ig n gu id anc e on ly . sin c e e ach reso na tor ha s i t s o w n c ha rac teri sti c s , th e u s er sh oul d c ons ul t the res o n a tor m a nufa c t u rer f o r th e ap pro pria t e va lue s of ex tern al co mp o- ne nt s . note : wh en us ing res o n a tors w i th fre q u enc ie s ab ov e 3 . 5 m h z, the us e of h s mo de rath er th an xt m o d e , is re com m end ed. h s m o d e may be used at any v dd for which the controller is rated. osc1 osc2 open clock from ext. system pic16fxx
? 2001 microchip technology inc. ds35007b-page 23 pic16f84a t able 6 - 2 : cap ac ito r se lec t i o n fo r cry st al osci l l ator 6.2 . 3 rc os cill ator fo r tim i n g i ns ens iti v e app li cat i on s, the r c dev ic e op tio n o f fe rs add iti ona l cos t sav i n gs . th e r c osc i l l at or frequency is a fun c ti on of the s upp ly v olt age , th e re s i s t o r (r ext ) v a lue s , c a p a c i tor (c ext ) v a l ues , an d th e ope rating tem p e ratu re. in ad dition to th is , t he os ci l- l a tor frequ enc y w i ll va ry fro m u n it to un it d ue t o no rma l pr oce s s p a r a m e ter v a ri ati on. fu rthermo re, th e di f f eren c e in le ad fram e c ap ac i t an c e be tw ee n p ack ag e ty pe s als o af f ec t s the os ci ll ati on freq uen cy , es pec ia ll y fo r l o w c ext va lue s . th e us er ne eds t o t ak e in to ac c oun t v a ri ation, due to to leranc e o f th e e x t e rna l r a nd c c o m pon ent s. fig u re 6-3 s how s h o w an r / c c om bin ati on is co nne cte d to the pic 1 6f84 a. figure 6-3: rc o s cillator m o de m ode f r eq o sc1 /c1 o sc2/c2 lp 32 kh z 20 0 k h z 68 - 10 0 pf 15 - 33 pf 6 8 - 100 pf 15 - 33 pf xt 10 0 k h z 2 mh z 4 mh z 100 - 15 0 p f 15 - 33 pf 15 - 33 pf 1 00 - 150 pf 15 - 33 pf 15 - 33 pf hs 4 mhz 20 mh z 15 - 33 pf 15 - 33 pf 15 - 33 pf 15 - 33 pf note : h i ghe r c ap ac i t a nc e inc rea se s th e st abi lit y o f th e osc i l l at or , bu t a l so i nc reas es th e s t art -up t i m e. th es e va lu es a re fo r de sig n g uid anc e on ly . r s ma y be requ ired in h s mo de , as w e l l as xt mo de , to av oi d o v e r- d riv ing c ry s t a ls w i th lo w d riv e lev el s pe c i f i- c ati on. s i nc e ea ch cry s t al h as i t s ow n c har act eris t i c s , th e u s er sh oul d c on s ul t th e cr y s tal ma nu f a c t ur e r f o r a p p rop ri at e v a lu es of ex ternal c o m p o nen t s . fo r v dd > 4 .5v , c 1 = c2 ? 3 0 pf is r ec om - m en ded . osc2/clkout c ext r ext pic16fxx osc1 f osc /4 internal clock v dd v ss recom mended values : 5 k w r ext 100 k w c ext > 20pf
pic16f84a ds35007b-page 24 ? 2001 microchip technology inc. 6. 3 reset th e pic 1 6 f 84 a d i f f e ren t ia tes b e tw ee n va rious k i nd s o f reset: ? pow e r-o n r e se t (p o r ) ?m c l r during normal operation ?mclr d u rin g sl eep ? w d t r e s e t (d uri ng n o rm al op erati o n ) ? w d t w a k e -u p (d urin g sl eep) f i g u r e 6- 4 s h o w s a s i m p l i f ie d bl oc k d i ag r a m o f t h e on-ch i p reset circ uit. the mclr r es et p a t h ha s a n ois e fil t er to ign ore sm al l p ul s es . the el ec tric al sp ec i- fi ca tio n s state th e p uls e w i d t h requ irem en t s for th e mcl r pi n . so m e re gi st ers a r e n o t af fe ct ed in an y r e set c o nd iti o n ; th ei r s t a t u s i s un kn ow n on a po r an d un ch an ge d i n a ny o t he r reset . m o s t ot he r reg i s t e r s a r e re s e t to a res et stat e on po r , mc lr or wdt reset during normal oper- ation and on mclr d u ri ng sle e p . th ey are no t a f f e c te d b y a wd t r e se t du rin g sleep, si nc e th is r e set is vi ew e d as t h e r es ump t i o n of no r m al o p er at i on . t abl e 6 -3 gi v e s a de s c rip t ion of reset c o nd itio ns f o r th e prog ram c o u n te r (pc ) an d the st a tu s r egi ste r . t abl e 6 -4 gi v e s a f u ll des c ription of reset s t at es f o r al l re gisters . th e t o and pd bi ts a r e s et o r c le a r ed di f f e rent l y in d if - fe rent reset s i tua tio ns (sec ti o n 6 .7). th es e b i t s a r e us ed in s o ftwa r e to de term in e th e n a tu re o f th e reset. figure 6-4: si mplifi ed b l ock diagram o f o n -chi p re s e t cir cuit t a ble 6 - 3 : res e t condition for p r og r a m counte r and the s t a t us r e gis t er s r q external reset mclr v dd osc1/ wd t mod u l e v dd rise detect os t /pw rt on- chi p rc osc (1 ) wd t t i m e -out p ower-on rese t os t 10-bit ripple c ount er pw r t chip_res et 10-bit ripple count e r reset enable o s t ena ble pwrt s leep clkin no t e 1: t his is a s e pa rate os cill ator f r om t he rc oscillat or of the clkin pi n. 2: see t able 6- 5. see t a b l e 6 -5 co nditio n p rogram coun ter s t a t u s regis ter power-o n re s e t 0 0 0 h 0001 1xxx mclr duri ng norm a l op erat ion 0 0 0 h 000u uuuu mc lr duri ng sleep 00 0h 0001 0uuu wd t r e s e t (du r ing no rma l op era t io n) 00 0h 0000 1uuu wdt w a ke -up p c + 1 uuu0 0uuu inte rrupt wak e -up fro m sl eep pc + 1 (1 ) uuu1 0uuu leg end : u = u nch an ged , x = unk no w n note 1 : w h en t h e w ak e- u p is du e t o an in te r r up t a nd th e gi e bi t i s se t, th e p c is lo ad ed w i t h t he i nt e r r u pt ve ct or ( 00 04 h) .
? 2001 microchip technology inc. ds35007b-page 25 pic16f84a t able 6 - 4 : res e t conditions fo r all regis t er s re gis te r a d d re s s powe r-on re s e t mclr d u ring: C no r m al opera tion C sleep wdt res e t d u ring norma l ope ratio n w ake -up fr o m sl eep: C th r o ugh interrup t C th r o ugh wdt t ime -out w xxxx xxxx uuuu u uuu uuuu uuuu indf 0 0 h ---- ---- ---- - --- ---- ---- tm r0 01 h xxxx xxxx uuuu u uuu uuuu uuuu pcl 0 2 h 0000 0000 0000 0 000 pc + 1 (2 ) st a t us 03 h 0001 1xxx 000q q uuu (3 ) uuuq quuu (3 ) fs r 0 4 h xxxx xxxx uuuu u uuu uuuu uuuu por t a (4) 05 h ---x xxxx ---u u uuu ---u uuuu por t b (5) 06 h xxxx xxxx uuuu u uuu uuuu uuuu eeda t a 0 8 h xxxx xxxx uuuu u uuu uuuu uuuu eeadr 0 9 h xxxx xxxx uuuu u uuu uuuu uuuu pc la t h 0a h ---0 0000 ---0 0 000 ---u uuuu int c o n 0 bh 0000 000x 0000 0 00u uuuu uuuu (1 ) indf 8 0 h ---- ---- ---- - --- ---- ---- op t i o n _ r eg 81 h 1111 1111 1111 1 111 uuuu uuuu pcl 8 2 h 0000 0000 0000 0 000 pc + 1 (2 ) st a t us 83 h 0001 1xxx 000q q uuu (3 ) uuuq quuu (3 ) fs r 8 4 h xxxx xxxx uuuu u uuu uuuu uuuu tri sa 8 5 h ---1 1111 ---1 1 111 ---u uuuu tri sb 8 6 h 1111 1111 1111 1 111 uuuu uuuu eecon1 8 8 h ---0 x000 ---0 q 000 ---0 uuuu eecon2 8 9 h ---- ---- ---- - --- ---- ---- pc la t h 8a h ---0 0000 ---0 0 000 ---u uuuu int c o n 8 bh 0000 000x 0000 0 00u uuuu uuuu (1 ) l ege nd: u = un ch ang ed, x = un kn o w n, - = uni mp leme n t ed bi t, rea d a s ' 0 ' , q = v a l ue d epe nd s o n c ond iti o n note 1 : o n e or m o re bi t s in in tc o n w ill be af fec t ed (to cau s e wa k e -u p). 2: w hen the wak e -up is du e to an in terru pt a nd the g i e bi t is s e t, t he pc is loa d e d wit h th e i n terr upt ve cto r (0 004 h). 3: t abl e 6 -3 l i s t s the reset v a lu e fo r ea c h s p ec ifi c c o n d it ion . 4: on a n y de v i c e reset , th es e p i ns are c onfig u red as inp u t s . 5: th is is th e v a lu e th at w i ll be in the port out put lat c h.
pic16f84a ds35007b-page 26 ? 2001 microchip technology inc. 6. 4 p ower- on reset (por) a po w e r-on r e se t pul se is g ene rated on -ch i p w h e n v dd ri se is detec t ed (in th e r ang e o f 1.2v - 1.7v) . t o t a ke ad va nt ag e o f th e po r , j us t tie th e m c lr pi n d i rec t ly (or t h rou g h a res i s tor) t o v dd . t h is w i ll e lim in ate ex tern al r c c om pon en t s u s u all y n eed ed to c r ea te po w e r-on res e t. a m i nim u m ris e t i m e for v dd m u s t b e m e t for this to op era t e p rop erly . see ele c tr ica l sp ec ific at ion s f o r de t a i l s . w hen the dev ic e s t art s n o rm al o perat io n (e xit s th e reset c ond iti on), d e v i c e o pera tin g p a r a m e ters (v o l t- a ge, frequen cy , temper ature , e t c.) mu st b e m e t to e nsu re ope rati on. if t hes e c on dit ion s a re not me t, th e d e v i c e m u s t b e h e ld in reset unti l th e op era t ing c o n- d i ti ons are m et. fo r add iti ona l in form ati o n , refe r t o app lic ati on n o te an 6 07, " po w e r- up t ro u b l e s h oo t i n g ." th e p o r c i rc ui t d oes n o t p rod uc e an i n tern al reset w h en v dd de cl ine s . 6. 5 power- up t i mer ( p w r t) th e power- up t i m e r (pwr t ) p rov ide s a fix e d 72 m s n o m i na l ti me -out (t pw rt ) from por (fi gure s 6 -6 th rou g h 6 -9). the power-u p t i m e r op erat es on a n i n ter nal rc o s c ill ato r . t he c h i p is k e pt in reset a s l ong as the pwr t is a c ti ve . the pwr t de lay a llo ws th e v dd to rise to an a c c ep t ab le le ve l (po s s i bl e ex ce p- ti on sh ow n i n f i gu re 6 -9). a c onfig u ration bi t, pwr t e , c a n en ab l e/ d is a bl e the pw r t . see r e gis t er 6-1 f o r th e op erat ion of th e pw r t e bi t fo r a pa rt i c u l ar d e v i c e . th e pow e r-up tim e de lay t pw rt w i l l va r y f r om c h ip t o c h i p du e to v dd , tem pera t ure , an d p r oce s s v a ria t io n. se e dc p a ram e t e rs for d e t a ils . 6. 6 o s cil l at or s t a r t- up t i m e r ( o st) th e os ci ll ator s t art- up t i m er (os t ) p r ov ide s a 102 4 os c ill ato r cy cl e d ela y ( f rom o s c 1 in pu t) aft er th e p w r t de l a y en d s ( f ig ur e 6 -6 , fi g u re 6- 7 , fi g u re 6- 8 an d fig ure 6-9 ). t his ens ure s the c rys t a l osc i l l at or or re son ato r ha s s t a rted and st abi li zed . th e o st ti me -ou t (t ost ) i s in v o k e d o n ly for xt , lp an d h s mo des a nd on ly on po w e r-on r e se t o r w a k e -u p fro m sleep . wh en v dd r i se s ve ry s low l y , it is p o s s i b le t hat th e t pw r t t i m e -o u t an d t ost t i me -o u t w i l l ex pi re be f o re v dd h as rea c h ed it s f i na l va lue . in th is c as e (fi g u re 6 - 9 ), a n ex te rnal powe r-on re s e t c i rc uit m a y be ne ce ss ary (fi gure 6 -5 ). figure 6-5: ex ter nal p o w e r - o n re se t circui t ( f or slo w v dd po w e r - up ) note 1: ex t e rn al p ower-on reset circuit is requ i r ed only if v dd po wer-up r at e is too slow . the diode d help s dis charge t h e c a p a cit o r quickly when v dd powers down. 2: r < 40 k w i s recom m ended t o m a ke sur e t h at volt age drop acros s r does not exce ed 0.2v (max leak age current spec on mclr pin i s 5 m a ) . a larger voltage drop will degrade v ih level on the mclr pi n. 3: r1 = 100 w to 1 k w will l imit any current flow- ing into mclr from external capacitor c, in the event of a mclr pin breakdow n due to es d o r e o s. c r1 r d v dd mclr pic16fxx v dd
? 2001 microchip technology inc. ds35007b-page 27 pic16f84a figure 6-6: time-out sequence on power-up (mclr n o t t i e d to v dd ): case 1 figure 6-7: time-out sequence on power-up (mclr no t t i e d t o v dd ): case 2 figure 6-8: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time t pw r t t ost v dd mclr int e rnal por pwrt time-out ost time-out internal reset v dd m clr interna l p o r pwrt time-out ost time-out internal reset t pw r t t ost v dd mclr internal por t pw r t t ost pwrt time-out ost time-out internal reset
pic16f84a ds35007b-page 28 ? 2001 microchip technology inc. figure 6-9: t i m e -out s e que nce o n pow e r-up (mclr ti ed t o v dd ): sl o w v dd ris e t ime 6.7 t ime- out sequence and power- down s t at us bi t s ( t o /pd ) o n p o w e r-u p (fig ure s 6 - 6 thr oug h 6 - 9 ), th e tim e -o ut s equ en ce is as fol l ow s : 1. p w r t ti me -o ut is in vo ke d a f t er a p o r h as ex p ir e d. 2 . th en , the o s t i s a c ti va ted . th e tot a l t i me -ou t wi l l vary b as ed on os ci lla tor con f ig u- ra tio n and pw r t e co nfigura t io n b i t s t atu s . fo r e x am - p l e, i n r c mo de w i t h the pwr t d i s abl ed, t here w i ll b e no t im e- o u t a t al l. t a b l e 6-5: t i me - o u t i n v a r i ou s si t u atio ns si nce the tim e -o ut s oc cu r from the po r pul se , if m c lr is ke pt l ow l o ng en o ug h , th e t i me - ou t s w i ll ex pi r e . t h en br ing i ng m c lr hi gh, e x ec ut ion w i ll be gi n im me dia t el y (fi g u r e 6 - 6 ). th is is us efu l fo r tes t in g pu rpo s es or to s y n c h r oni ze m ore th an on e pic 16f 84a de vi ce w he n op era t in g in p a ral lel . t abl e 6 -6 s ho w s the si gni fic an c e of the t o and pd bi ts. t abl e 6 -3 li s t s the reset c o n d it ion s fo r s o me special registers, while table 6-4 lists the reset conditions for all the registers. table 6-6: status bits and their significance v dd m clr v1 w hen v dd r i s es ver y slowly , it is possible that the t pw rt t i m e -out a nd t os t t i me -out w i ll expire b e f o re v dd has reached it s final value. in this example, the chip will res et properly if , a nd only if, v 1 3 v dd m in. interna l p o r t pw rt t os t pw rt time -o ut os t t i m e-out i n tern al res e t o scil l ator configuration power-up wake-up from sleep pwrt en able d pwrt disa ble d xt , hs, l p 72 ms + 102 4t os c 1 024 t os c 10 24t osc r c 72 ms to pd co nditi o n 11 power-on res e t 0x i lle gal , t o is set on por x0 illegal, pd i s s e t on p o r 01 w d t r e s e t (duri ng norm a l op erat ion ) 00 wdt wake-up 11 mclr during normal operation 10 mclr d u rin g sl eep or int e rrup t wa k e -up f r om sleep
? 2001 microchip technology inc. ds35007b-page 29 pic16f84a 6. 8 i nter rupt s t h e p i c 1 6 f 84 a ha s 4 so ur c e s of i n t e r r u p t : ? e x t ern a l int e rrup t r b 0/ in t pi n ? t m r 0 ove r flo w in terru pt ? p o r t b ch ang e i nter r upt s (p ins r b 7: r b 4) ? d at a eeprom write c o m p le te i n ter r upt th e i n terr upt c o n t rol regi s t e r (intcon) rec o rd s i ndi vi dua l int errup t requ es t s in f l ag b i t s . it als o c ont ain s th e i ndi vi dua l a nd glo bal in terru pt e nab le bit s . th e glo bal in terru pt ena bl e b i t, gi e (in t c o n <7 >), e nab les (if se t) al l un ma sk ed int errup t s or d i sa bl es (if cl ea re d) al l i n te rru pts. i nd iv i du al in t er ru p t s c an be d i s abl ed thr oug h thei r c orr esp ond in g ena ble b i t s i n int c on re gis te r . bit gie is c l ea red on r e set . th e retu rn f rom in terru pt in s tru c ti o n , retfie , e x i t s in t e rr u p t ro ut i n e a s w el l a s s ets t h e gi e bi t , w h i c h re -enable s inte rrupt s . th e r b0/i n t p i n in terru pt, th e r b p o rt ch an ge in terru pt a nd the tm r 0 o v e rflo w in terru pt f l ag s are co nt a i ne d i n th e int c o n re gi ste r . w hen a n in terru pt is res pon ded to, th e g i e bit i s c l e a red to di sa ble any fu rther inte rrupt, the retu rn a ddre s s is pu sh ed onto th e s t ac k a nd the pc is lo ade d w i th 000 4h . f o r ex ternal in terru pt ev en t s , s u c h as th e r b0 /in t pi n or po r t b ch an ge in terru pt, th e in terru pt l a ten c y will b e thr ee to fo ur in struct ion c y c l e s . th e e x ac t la ten c y d epe nds w hen t he in terru pt ev en t occ u rs . th e la ten c y i s th e sa me f or bo th on e and tw o cy cl e i n s t ruc t io ns. on ce in th e in terru pt serv ic e r o utine, th e s our ce( s ) of the in terru pt can b e d e te rmi ned b y pol lin g th e in terru pt fla g bit s . th e in terru pt fla g bit (s) m u s t b e c l e a red in s o ftware be fore re-en abl in g in terru pt s to a v oi d i n fi nit e in terru pt reques t s . figure 6-10: inte rrup t l ogic 6.8 . 1 i nt in t e rrup t ex ternal int e rrupt o n r b0/ in t p i n is edg e t rigg e re d: ei the r ris i ng i f intedg b i t (o p t io n_ reg < 6>) is se t, or fal lin g i f in t ed g bit is cl ea r . wh en a v al i d edg e ap pe ars on th e r b0/in t pi n, the in tf b i t (in t c o n <1 >) i s se t. t h is i n te rrupt ca n be dis a b l ed b y c l ea rin g c o n trol b i t inte (intco n<4>). fl ag bi t i n tf m u s t be cl eared i n s o ftw a re v i a the interrupt serv ic e r o u t in e b e fore re-e na bli ng t h is in terru pt. the in t i n terr upt ca n w a ke th e p roc es sor fro m sleep (se cti o n 6 .1 1) o n ly if th e inte bi t wa s s e t pri o r to g o in g i n to sl eep . t he s t atu s o f the g i e bi t dec id es w h eth e r th e pro c e s s o r b ranc he s to the int e rrupt v e ct or fo l l o wi n g wa ke -u p . 6.8 .2 t mr0 inter rupt an ov erfl ow (f fh ? 00 h) i n tm r0 will s e t fl ag bi t t0 if (in t c o n <2 >). t he inte rrup t c an b e e nab led / di sa ble d by s e tti ng /cl eari n g ena bl e bi t t0 ie (in t c o n <5 >) (se c t i o n 5 .0) . 6.8 . 3 p or tb i n te rru p t an in put ch ang e o n po r t b< 7:4 > s e t s fl ag bit r b if (in t c o n <0 >). t he inte rrup t c an b e e nab led / di sa ble d by set t in g/c l ea rin g e nab le bi t r bi e (in t c o n < 3 > ) (se cti o n 4 .2) . 6.8 . 4 da t a e e p rom inte rrup t at th e c o m p l e ti on of a d a t a eeprom writ e c y c l e, fla g bi t eeif (eecon1<4 > ) wil l b e s e t. t he inte rrup t c a n b e en ab led / di sab l e d by s ett ing / cl eari ng e nab le bi t eeie (int c o n<6 > ) (se c t i o n 3 .0 ). note : in div i d ual in terru pt fl ag bit s a r e s e t re gard l es s o f t he st atu s of the i r c o rre spo nding mask bit or the gie bit. rbif rbie t0if t0ie intf inte gie eeie wake-up (if in sl e ep m o d e ) int e rr up t to cp u eeif note : f or a ch an g e on th e i / o p i n t o be r ec o gn iz e d, t h e pu lse wid t h m u s t be a t le as t t cy wi d e .
pic16f84a ds35007b-page 30 ? 2001 microchip technology inc. 6. 9 c ont ext savi ng dur i ng int err upt s du ring a n in terru pt, o n ly the r e turn pc v a l ue i s s a v e d on t h e sta ck. t y p i c a l l y , u s e rs wi sh to sa ve ke y r e gi st e r v a l ues d u ri ng an i n te rrupt (e .g., w re gis t er an d st a t u s r e gi st e r). t h is is i m p l em en t e d i n sof t w a re. th e cod e in exa m p l e 6 -1 sto res an d re st ores th e st a t u s an d w reg i s t er s v a lu es . th e u s e r de fined re gister s, w_ tem p and st a tu s _ tem p a r e th e tem - po ra ry st o ra g e lo c a t i on s f o r t h e w an d s t a t u s re gis t er s v al ues . ex am ple 6 -1 do es the fol l ow i ng: a) s t ore s t he w reg i s t er . b) s tore s t he st a tu s re giste r in st a tu s _ tem p . c ) ex ec ute s th e i n terr upt serv ic e r o u t in e c ode . d) r es t o res the st a t u s ( and ban k sel ec t bi t) re gis t er . e) r e s t o res the w re gis t er . ex amp l e 6-1: sav ing s t a t u s an d w regis t ers in ram 6. 10 w at chdog t i mer (wdt) th e w a tc hdo g t i mer is a f ree runn ing o n-c hi p r c o s cil l a t or w hic h do es n ot req uir e any ext erna l c o m pon en t s . thi s rc os ci lla tor is se p a r a te from th e r c osc i l l at or of the o sc 1 /c lki n pi n. tha t m e a n s th at th e wdt wi ll run even if th e cl o c k on th e o s c1 /clkin a nd o sc 2/c lko u t pi ns of th e dev ic e ha s bee n s t op ped , for e x am pl e, b y ex ec uti on o f a sleep i n s t ruc t io n. d u ring no rma l o perat io n, a wd t time -o ut g ene rate s a d e v i c e reset . i f th e d e v i c e i s in sleep m o d e , a wd t w a ke -up c aus es the d e v i c e to w a k e -u p a nd c ont inu e w i th norm a l o p e rati on. th e wd t c a n b e p erm ane ntl y di sa ble d by prog ram m i ng c onf igu rati on b i t w d t e as a '0 ' ( sect ion 6.1 ). 6.1 0.1 wd t pe rio d th e wd t ha s a no mi na l tim e -o ut pe riod o f 18 m s , (w i t h no pre s c a l e r). t he t i m e -ou t pe rio d s var y w i th te mp erat ure, v dd an d pr o c e s s v ar i a t i o ns f rom par t t o p a rt (s ee d c sp ec s). if lo ng er ti me -out per iod s a re de si red , a p res ca ler w i th a d i vi si on rati o o f up to 1 : 12 8 c an b e as si gne d to the w d t und er s oftw a re c ontr ol b y writ ing to the o p tio n_reg reg i s ter . thu s , tim e -o ut pe rio ds up to 2 . 3 s ec on ds ca n be rea l i z ed . th e clr wdt an d sle ep in s tru c t ion s c l e a r t he wdt an d the po st s c a l e r (if as si gn ed to the wd t) and p re- v ent it from tim i n g o ut a nd gen era t ing a dev ic e reset c o nd itio n. th e t o b i t in t h e s t a t u s r e g i s t er w i l l be c l ea r e d u p o n a wdt ti me -ou t . push movwf w_temp ; copy w to temp register, swapf status, w ; swap status to be saved into w movwf status_temp ; save status to status_temp register isr : : : ; interrupt service routine : ; should configure bank as required :; pop swapf status_temp,w ; swap nibbles in status_temp registe r ; and place result into w movwf status ; move w into status register ; (sets bank to original state) swapf w_temp, f ; swap nibbles in w_temp and place re sult in w_temp swapf w_temp, w ; swap nibbles in w_temp and place re sult into w
? 2001 microchip technology inc. ds35007b-page 31 pic16f84a 6.1 0.2 wd t pro g r a mmi ng consi dera t ions it s hou ld al so be t a ke n into a c c ou nt that un de r w ors t c a s e c ond iti ons (v dd = mi n., t e mpe ratu re = ma x., m ax . wd t p re sca l e r), it ma y ta ke s e v e ra l se co nd s b e f o re a wd t t i me -ou t o c cu rs . figure 6-1 1 : w atc hdog t i me r block diagram t able 6 - 7 : sum m ar y of re giste r s ass o ciated with the w a tch d og t i me r from tmr0 clock source (figure 5-2) t o tm r0 ( f i g u r e 5 -2) postscaler wdt timer m u x psa 8 - to -1 mu x psa wd t time-out 1 0 0 1 wdt enable bit p s2:ps 0 ? ? 8 mu x no t e : ps a and p s2:ps 0 are bit s in t he op t ion_re g register . addr n ame bi t 7 b it 6 b it 5 b i t 4 b it 3 b i t 2 bit 1 b it 0 v a lu e on po wer- on res et v a lue on all o t her resets 2007h config. bits (2) (2) (2) (2) pwrte (1) wdte fosc1 fosc0 (2) 81h option_reg rbpu intedg t0cs t0s e psa ps 2 p s1 p s0 1111 1111 1111 1111 le gend: x = unk nown. s haded c el ls are not used by t h e w d t. no t e 1: s ee regist er 6-1 f or oper at ion of t he pw r t e bit. 2: s ee regist er 6-1 and section 6.12 f or operation of the c ode and dat a pr ot ection bit s.
pic16f84a ds35007b-page 32 ? 2001 microchip technology inc. 6. 1 1 power- down mode (sleep) a d e v i c e m a y be powe red d o wn (sl eep) an d la ter p o were d u p (wak e-u p fro m sleep). 6.1 1 .1 sl ee p th e pow e r-d ow n m ode is e n te red by e x e c u t ing th e sleep ins t ru cti on. if ena ble d, th e w at c hd og t i me r is cl eare d (bu t ke ep s ru nni ng) , th e pd bit (status<3>) is cleared, the to bi t (st a t u s <4 >) is se t, an d th e o s c ill ato r dri v er is t u rne d o f f. the i/ o por t s ma int ain th e s t a t us th ey ha d b efo re th e sleep instructi on w a s ex ec ute d (driv i n g hi gh, l ow , o r hi -im ped anc e). fo r t he lo wes t c u rre nt c o ns um pti on in sl eep m o d e , p l ac e al l i/o pin s a t e i th er v dd or v ss , wi th no ext e rna l c i rc uit ry draw i ng cu rren t fro m the i/ o pin s , an d d i s abl e e x te rnal c l o c k s . i/o p i ns t hat are hi -imp e dan ce in put s s hou ld b e pu ll ed h i gh or lo w e x te rna lly to a v o i d s w itc h- i ng c u rre nt s c a u s e d by flo a tin g in put s. th e t0 c k i inp u t s hou ld al so be at v dd or v ss . the co ntribut ion fro m o n-c hip pu ll-u p s on por t b s hou ld be co nsi de red. th e m c lr pi n m u s t be at a l o gi c h i g h le ve l ( v ih mc ). it s h o u ld b e no ted t hat a reset g ene rate d by a wdt time-out does not drive the mclr pin lo w . 6 . 1 1 . 2 w ake -u p fr o m sl e e p th e de v i c e c an wak e -u p from sleep th roug h one of th e fo llo wing events: 1. external reset input on mclr pin . 2. wd t w ak e -up (if wd t w a s e nab led ) . 3. in terru pt from r b0 /in t p i n , r b p o rt ch ang e, or da t a eepro m wri te c o m p le te. pe ripherals ca nno t ge nerat e inte rrupt s duri ng sleep , s i nc e no o n-c hip q cl oc ks are pre s e nt. th e firs t eve n t (m c l r r e se t) w i ll ca us e a dev ic e reset. th e t w o l a tter events are considered a contin- uation of program execution. the to and pd bi ts c an be us e d to de term in e the c a u s e of a d e v i c e reset . th e pd b i t, w h ic h i s se t o n p o w er - u p, i s cl ea r ed when sleep is invoked. the to b i t is cl ea red if a wd t ti me -out oc cu rred (and ca us ed w ake -up ) . wh il e th e sleep in st r u ct i on is be i ng ex ec u t e d , t h e n e x t i n st ruc t ion (pc + 1) i s p re-fetch ed. for th e de vi ce to w a k e -u p through a n int e rrup t eve n t, th e co rres pon din g i n terr upt en abl e b i t mu st be s e t (enabl ed). w a k e -u p oc c u rs rega rdless of th e s t ate of th e gi e bi t. if th e gi e b it i s cl ea r (d i s a bl e d) , t h e de v ic e co nt i nu e s ex ec ut i on a t th e i n s t ruc t io n a fter the sleep in s t ru ct i o n . i f t h e gi e bi t i s s et (ena bl ed), the de vi ce ex ec utes th e i ns t ruc t io n af ter the s leep i ns t ruc t io n and t hen b ran che s to th e in t e rr u p t ad dr e s s ( 0 00 4h ). i n c as es w h er e t he ex ec uti o n of th e ins t ru cti on fol l o w i n g sleep is n o t de si rab l e, the u s e r s hou ld ha ve a nop afte r th e sleep ins t ru cti on. figure 6-12: w a k e -up from s l ee p thr o ugh interr upt q 1 q 2 q 3 q4 q1 q2 q3 q 4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q 4 q1 q2 q3 q4 os c 1 cl kout (4 ) int p i n int f f l a g ( i nt con<1 >) gie b i t ( i nt con<7 >) instruction flow pc instruction fetched instruction executed pc pc+1 p c +2 i n st ( p c) = sl eep inst( p c - 1 ) in st ( p c + 1 ) sl eep pr oce ssor in sl eep in ter r up t la ten c y (n o t e 2) i n st( p c + 2 ) i n st( p c + 1 ) inst (00 04h ) in st(0 005 h) i n st( 000 4h ) du mm y cycle pc + 2 00 04 h 0 0 05 h dum m y cycle t ost (2 ) pc+2 not e 1 : xt , hs, o r l p o scilla to r m o d e a s su m e d . 2: t ost = 102 4t os c ( d r a win g n o t to sca le ) . t h is d e l a y will n o t b e th e r e fo r rc o sc m o d e . 3: g i e = ' 1 ' a ssu m e d . i n th is ca se a fte r wa k e - u p , t h e p r o ce ss o r ju m p s to th e in t e r r u p t r o u t in e . i f gie = ' 0 ' , e xe cu t io n will co n t i n u e in - line . 4: c l k o u t i s no t av ai l a b l e i n the se o sc m ode s, b u t sh ow n he re for ti mi n g r e fe ren ce.
? 2001 microchip technology inc. ds35007b-page 33 pic16f84a 6.1 1 .3 w a ke -up usin g interr upt s w hen g l ob al in terru pt s a r e dis a b l ed (g ie c l ea red) an d an y i nt e r r up t s o ur c e ha s b ot h its i nt e r r up t e n ab l e bi t and interrupt flag bi t s e t, o n e of th e fo ll ow in g w i l l oc c u r: ? if the in terru pt o c c u rs bef o re th e e x e c ut ion of a sleep in st r u ct ion , t he sleep ins t ru cti on w il l com - p l ete as a nop . the refo re, the wd t a nd w d t po s t s c a le r wi ll no t be cl ea re d, t he t o bit will not be set and pd bit s w i ll not be cl eare d. ? if the in terru pt o c c u rs during or after the exec u - ti on of a sleep i ns t ruc t io n, t he dev ic e w i ll i m m e- d i ate l y wak e -u p fro m s l eep . th e sleep i nst ruc t io n w i ll be c om pl etel y ex ec ute d befo r e the w a k e -u p. ther efore , th e w d t an d wd t po s t s c a le r w i ll be cl ea r e d, t he t o bit will be set and the pd bit w ill be cl ea red. ev en i f the f l ag b i t s w e re c hec ked before executing a sleep in st r u ct i o n , i t ma y be p o s s i b le f o r fl a g bi ts t o b eco me s et b efo re t he sleep in s t ru ct i o n co mp l e t e s. t o d e ter m i ne w hethe r a sl eep i nst ruc t ion e x ec ut ed, tes t th e pd bit. if the pd bi t is se t, th e sleep in st r u ct i o n w a s e x ec ut ed a s a nop . t o e nsu re t hat the wd t is c l ea red, a clrwd t ins t ru c- ti on sh oul d b e ex ec ute d b e fo re a sleep in s t ru ct i o n . 6. 12 pro gram v eri f i cat io n/code pro t ect ion if the co de prot ect i on bi t(s) hav e not bee n p ro- gr am med , th e on -ch i p p rogram m e m o ry c an b e rea d ou t fo r v e rifica tio n p u rpo s e s . 6. 13 i d locat io ns fo ur me mo ry lo ca tio ns (2 000 h - 2 00 4h) are d es i gn ate d as id lo ca tion s to sto re c hec k s um or o t her c od e i den tifi ca tion num be rs. t hes e l oca tio ns are n ot ac c es s ib le du ring n orm al ex ec uti on bu t a re r ead abl e an d w rit a ble o nly duri ng pro gram / v eri fy . on ly th e fo ur l eas t si gni fic a n t bi t s of id loc a ti on are us abl e. 6. 14 i n -ci r cui t seri al progr am mi ng pic 1 6f8 4 a m i c roc ont rollers ca n b e s e ria l l y pr ogra m m ed w hi l e in t he end a ppl ic ati on ci rcu i t. th is i s s i m ply don e w i th tw o l i ne s for c l oc k a nd da t a, an d thre e ot her lin es fo r po w e r , g rou nd, and th e p rogram m i n g v olt age . c u sto m e rs ca n man ufa ctu re boa rds w i th un pro g ramm ed dev ic es , an d t hen pro g ram th e m i c roc ont roller ju st be fore s h i ppi ng th e prod uc t, al lo wing the m o s t re c e n t fi rm w a re or c u s tom fi rm wa re to be pro g ramm ed. fo r com p l e te d e t a ils of seri al pro gra m m i ng , ple a s e re fer to the in -circ u i t se rial pr ogra m m i n g ? (icsp?) g u i de, (d s30277) .
pic16f84a ds35007b-page 34 ? 2001 microchip technology inc. notes :
? 2000 microchip technology inc. ds35007b-page 35 pic16f84a 7.0 i nstr uction set su mmary ea c h pic16 c xx in s tru c ti o n is a 1 4 -b it wo rd, d i v i de d int o a n o p c o d e w h ic h s pe c i f ie s t h e i ns t r uc t io n t y pe an d on e or mo re op e ran ds w h ic h f u rt he r sp ec i f y t he op e rat i on o f t he i ns t ru ct i o n. t h e p i c 1 6c xx in st ru ct i on s e t su mm ar y i n t a b le 7 -2 lis t s by te-orie n ted , b i t-ori- e nted , an d litera l a nd cont r o l o pera t io ns . t abl e 7 -1 s how s th e o pco de fie l d des cri pti ons . fo r byte -orien ted i nst ruc t io ns, ' f ' rep res ent s a fi le re g- i s te r de si gna tor a nd ' d ' re pre s en t s a d est ina t io n de si g- na t o r . t h e f i le r e gi st e r de si g na t or s pe c if i es w hi c h f i le re gis t er is to be u s e d b y th e i n s t ruc t io n. th e de sti nat ion d es i gn ato r s pe c i f ies w here t he res ul t of th e ope ration is to be pl ac ed. if ' d ' is z e ro, th e res u lt i s p l ac ed i n the w reg i st er . if ' d' is one , the re su lt is pl ace d i n th e fi le regist er s pec ifi e d in the ins t ru cti on. fo r bit- o riente d i nst ruc t io ns, ' b ' repre s e nt s a b i t fiel d d esi gn ator w hic h sel ec t s the nu mb er o f th e bi t a f fe cte d b y the o per ation, w h i l e ' f ' re pres en t s th e add res s of th e fi le in w hic h t he b i t i s loc ate d. fo r li teral and co ntrol ope rati ons , ' k ' rep r es ent s a n e i gh t or ele v e n bi t c ons t a nt o r li tera l v a lu e. t able 7 - 1 : opcode fie l d des crip t ions th e ins t ruc t i on se t i s hig hly o rtho go nal an d is gro upe d i nto thre e b asi c cat ego ries : ? byt e -orie n ted ope rations ? bit-o riente d o pera t io ns ? li teral and cont r o l op erat ion s al l in stru cti o n s are ex ec uted w i th in o ne s i n g le ins t ruc - t i o n cy cl e , un l e s s a co nd i t io n a l t e st i s t rue o r t h e pr o - gr am c ou nte r i s c han ged as a res ult o f an i nst ruc t io n. i n t hi s c as e, t he ex ec u t i o n tak es tw o in s t ru ct i o n cy cl es w i t h the s eco nd c y c l e ex ec ute d as a nop . o n e i n st ru c- ti on c y c l e c ons is t s of fo ur os ci lla tor pe riod s. th us , f or an o s c i l l at or freq uen cy o f 4 m h z, th e norm al i ns t ruc t io n ex ec uti on ti me is 1 m s. if a c on dit ion al tes t is tru e o r th e pr ogram c oun ter i s c han ged as a res u lt of an ins t ruc - ti on, the in stru cti on ex ec utio n ti me is 2 m s. t abl e 7 -2 li st s the i nst ruc t io ns re cog ni z ed by th e m p asm ? as s e m b le r . fi gur e 7 -1 sh ow s th e ge neral form at s th at the ins t ruc - ti ons c an hav e. al l ex am pl es use the fol l o w i n g form at t o rep res ent a he xa dec im al nu mb er: 0x hh w h e re h si gn ifie s a he xa dec im al di git. figure 7-1: gene ral forma t fo r ins t ructions a de sc ri p t io n o f ea ch in st ru ct i o n is av ai l a b l e in t h e pic m ic ro? m i d-r a nge r e ferenc e ma nu al (d s33 023 ). fie ld des c riptio n f r e g i st er f i le ad d res s ( 0 x0 0 t o 0 x 7f ) w w o rk in g re gis t e r (ac c u m u l at or) b bi t a ddres s wi th in an 8-bit fi le registe r k l i te ral fie l d, co nst ant dat a o r la bel x do n' t c a re loc a ti on (= 0 or 1 ) t he ass em bl er w i ll gen erat e c ode wi th x = 0 . i t i s the rec o m m e nde d form o f u s e for co mp at- i bi lity wi t h a ll m i c roc hi p s oft w a re t ool s. d d es t in at i o n se l ec t ; d = 0 : st o re r e su l t i n w , d = 1 : s t ore res u lt in fil e re gis t er f. d ef a ul t is d = 1 pc pr ogram co unt er to t i m e -ou t bi t pd po wer-d own b i t note : t o ma int ain u pw ard com p a t ib ili ty w i th fu ture pi c 16c xx products, do n o t us e the option and tris instructions. b y te-oriented fi le register o perat ions 13 8 7 6 0 d = 0 f o r destinat ion w op code d f ( file #) d = 1 f o r destinat ion f f = 7-bit fi le register a ddress b it - or i ented f ile reg i s t er operations 13 10 9 7 6 0 op c o d e b (b it # ) f (f il e #) b = 3-bit bit address f = 7-bit fi le register a ddress literal and control o perat ions 13 8 7 0 op c o d e k (l i t e ra l ) k = 8-bit immediat e value 13 1 1 10 0 opcode k (l iter al) k = 1 1 -bit imm ediat e value general call and goto instructions only
pic16f84a ds35007b-page 36 ? 2000 microchip technology inc. t a ble 7 - 2 : pi c16cx x x in struction s e t mnemon i c, operan ds des cr ipti o n cycles 14- b i t op code st atu s a ffected no tes ms b l sb byt e -o rie n te d fi le re gis te r op era t i o ns addw f andw f clrf clrw comf decf decfs z inc f inc fs z io rw f mo v f mo v w f nop rlf rrf sub w f sw ap f xo r w f f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d a dd w and f a nd w wit h f clear f clear w com plement f dec reme nt f dec reme nt f , s kip if 0 i n crem ent f increm ent f, skip if 0 inclusive or w wit h f m o ve f mov e w to f no operati o n rot ate left f t hr ough car ry rot ate right f through carry s ubt r act w from f s wap nibbles in f e xclusiv e or w wit h f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 df ff df ff lf ff 0x xx df ff df ff df ff df ff df ff df ff df ff lf ff 0x x0 df ff df ff df ff df ff df ff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c, dc,z z z z z z z z z c c c, dc,z z 1, 2 1, 2 2 1, 2 1, 2 1, 2,3 1, 2 1, 2,3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 bit -orie nte d fi le re gis te r op era t i o ns bcf bs f btfs c btfs s f, b f, b f, b f, b b i t cl ea r f bi t s e t f b i t t e st f, sk i p if clear bit t e st f, s k i p if s e t 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bf ff bf ff bf ff bf ff ffff ffff ffff ffff 1, 2 1, 2 3 3 litera l a nd control o p era t i o ns addl w andl w call clrw dt g oto io r l w mo v l w re tfi e retl w return sle ep sub l w xo rl w k k k - k k k - k - - k k a dd lit er al and w a nd literal with w call subroutine clear watchdog t im er go t o address inclusive or literal with w mov e li ter al to w return f ro m interrupt return wit h li teral in w return f ro m subroutine go i n t o st andby mode s ubt r a ct w from lit era l e xclusiv e or l iteral with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kk kk kk kk kk kk 01 10 kk kk kk kk kk kk 00 00 kk kk 00 00 01 10 kk kk kk kk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c, dc,z z to ,p d z to ,p d c, dc,z z note 1: w hen an i /o register is m odi fied as a function of it self ( e.g. , movf portb, 1 ), the v al ue used wil l be that value pr esent on the pi ns thems elves. for exam ple, if the dat a lat c h is ' 1 ' f or a pi n configured as i nput and is driven low by an external device, the dat a wil l be w ritten bac k w i th a ' 0' . 2: i f this i ns t ruc t ion is ex ecuted on t he tmr0 register (and, where applicable, d = 1), the pr escaler will be cleared i f assigned t o the t im er0 module. 3: i f p rogram co unt er (p c) is mo di fied or a condit ional t e s t i s true, the instruction r equires t wo cyc les. the s e cond cyc l e is exec uted as a nop . note : ad dit i on al i n for m a t ion on th e m i d-ra ng e in stru cti on s e t i s av ai lab l e i n th e pic m ic ro ? m i d - r ang e m c u fa mi ly reference manual (ds33023).
? 2000 microchip technology inc. ds35007b-page 37 pic16f84a 7. 1 i nstr ucti on descri p ti ons addl w a dd lite r a l a nd w sy nt a x : [ lab e l ] addl w k op er a n d s : 0 k 255 o p e r ati on: (w ) + k ? (w ) s t at us af fe ct ed: c , d c , z d e sc ript ion : t he c on t en t s of th e w reg i s t er a r e ad de d to the e i g h t-bi t li tera l ' k ' a nd the res ult is pl ace d i n th e w re gis te r . addwf add w a nd f sy nt a x : [ lab e l ] addwf f, d op er a n d s : 0 f 12 7 d ? [0 , 1 ] ope rati on: (w ) + (f ) ? (d est i na tio n ) s t at us af fe ct ed: c , d c , z d e sc ript ion : ad d the con t en t s o f t he w re gis t er w i t h re g i s t e r 'f '. i f 'd ' i s 0 , t h e re s u l t i s s t o red in t he w reg i s t er . if ' d ' i s 1, t he r es u lt is st o red ba ck in re gi s te r ' f' . andl w and l i te ra l w i th w sy nt a x : [ lab e l ] andl w k op er a n d s : 0 k 255 ope rati on: (w ) .and. (k ) ? (w ) s t at us af fe ct ed: z d e sc ript ion : t he c on t en t s of w reg i st er a re and ed wi th t he eig h t-b i t l i te ral ' k '. the res ult is pl ac ed i n t he w re gis te r . andwf and w with f sy nt a x : [ lab e l ] andwf f, d op er a n d s : 0 f 12 7 d ? [0 , 1 ] ope rati on: (w ) .and. (f) ? (d est i na tio n ) s t at us af fe ct ed: z d e sc ript ion : an d t he w reg i s t er w i th r egi ste r ' f ' . if ' d' is 0, the res ult is st ored in t he w regi st er . i f ' d' is 1, th e re su lt i s s t o red bac k in re gi ste r ' f '. bcf bit c l e a r f sy nt a x : [ la be l ] bcf f,b op er a n d s : 0 f 12 7 0 b 7 o pe r ati on: 0 ? (f< b >) s t at us af fe cte d : n o n e de scri p t i o n : bit 'b ' i n re gist e r 'f ' i s cl e a re d. bsf b it set f sy nt a x : [ la be l ] bsf f,b op er a n d s : 0 f 12 7 0 b 7 o pe rati on: 1 ? (f< b >) s t at us af fe cte d : n o n e de scri p t i o n : bit 'b ' i n re gist e r 'f ' i s se t . btf ss b it t e s t f, sk ip if set sy nt a x : [ la bel ] btf ss f, b o p e rand s: 0 f 127 0 b < 7 o p e rati on: sk ip if (f ) = 1 s t at us af fe cte d : n one d es c ripti on : if bi t ' b' in regi st er ' f ' is '0 ', the nex t ins t ru cti on is ex ecu t ed . if b i t ' b ' is ' 1 ' , th en the ne xt ins t ruc - t i on is di sc ar d e d a nd a nop is ex e- cu ted ins t ea d, ma kin g t his a 2t cy ins t ru cti on.
pic16f84a ds35007b-page 38 ? 2000 microchip technology inc. btf s c b it t e st, sk ip i f clea r sy nt a x : [ l abe l ] b tfsc f , b o p e rand s: 0 f 12 7 0 b 7 op er a t io n : sk ip if ( f < b > ) = 0 s t at us af fe ct ed: n o n e d e s c ri p t i o n : i f b i t 'b ' i n r e g i s t e r 'f ' i s '1 ', t h e n e x t in st ruc t ion is ex ec ute d. i f b i t 'b ' i n r e g i s t e r 'f ' i s '0 ', t h e n e x t in st ruc t ion i s di sc arde d, an d a no p is ex ec ute d ins t e ad, m ak i n g thi s a 2t cy in str u ct ion . call c al l sub r o u tine sy nt a x : [ lab e l ] call k op er a n d s : 0 k 204 7 ope rati on: (pc)+ 1 ? to s, k ? pc<1 0:0 > , (pcl a th< 4 :3> ) ? pc<1 2:1 1 > s t at us af fe ct ed: n o n e de sc ript ion : cal l su bro u tin e . firs t, re turn a ddre s s (pc +1 ) is pu sh ed o n to th e s t ac k. the el ev en-b i t i m m ed i - a t e a ddre s s is lo ade d i nto p c bit s <1 0:0 >. t he u p p e r bi t s of t he pc a re l oad ed from pc la th . call is a t w o -cy cl e i n s t ru c t io n . clrf cl e a r f sy nt a x : [ lab e l ] cl rf f op er a n d s : 0 f 12 7 o pe rati on: 0 0h ? (f) 1 ? z s t at us af fe ct ed: z d e sc ript ion : t he con t en t s of re gi ste r ' f ' are c l e ared an d th e z bit is se t. clr w cl e a r w sy nt a x : [ la bel ] cl r w o p e rand s: n o ne op er a t io n : 00 h ? (w) 1 ? z s t at us af fe ct ed: z de s c ript ion : w reg i s ter i s c l e a re d. ze ro b i t (z) is s e t. clr w dt cle a r w a tc hd og t i m e r sy nt a x : [ l a be l ] cl r w dt o p e r and s: n o ne o p e r ati on: 0 0h ? wdt 0 ? wdt pre s c aler, 1 ? to 1 ? pd status affected: to , pd de scr i p t i o n : clr wdt in str u cti on r es et s th e watchd o g t i me r . it als o res et s the p r es ca ler of th e w d t . s t a t us bi t s to and pd a r e s e t. c o mf c o mpl eme nt f sy nt a x : [ la bel ] co m f f,d o p e r ands: 0 f 127 d ? [0, 1 ] o p e r ati on: (f ) ? (d es tin a tio n ) s t at us af fe cte d : z d e s c r ipti on : t he co nte n t s of regi ste r ' f ' are com p l e m ent ed. if ' d ' i s 0 , th e res u lt i s s t ored in w . if ' d ' i s 1, t he res ult is sto r ed bac k in regi st er ' f ' . d e c f d ecr e men t f sy nt a x : [ la bel ] d e c f f,d o p e r and s: 0 f 12 7 d ? [0 ,1] o p e r ati on: (f) - 1 ? (d es tin a tio n ) s t at us af fe cte d : z d e s c ription : d ec rem ent reg i st er ' f ' . if ' d ' is 0, the res u l t is s t ore d in th e w regis- ter . if ' d ' i s 1 , th e re su lt i s s t or ed ba ck in r e g ist er ' f ' .
? 2000 microchip technology inc. ds35007b-page 39 pic16f84a decfsz de crem ent f, ski p if 0 sy nt a x : [ la bel ] d e c f sz f ,d op er a n d s : 0 f 127 d ? [0, 1 ] o p e r ati on: ( f) - 1 ? (de s ti na tion); s k i p if re su lt = 0 s t at us af fe ct ed: n o ne d e sc ript ion : t he co nten t s of r egi ste r ' f ' are d e c rem ent ed. if ' d ' i s 0 , th e re sul t is p l ac ed i n t h e w re g i s t er . if ' d ' i s 1, t he r es ul t is pl ac e d b ac k i n r e g i s t e r 'f '. i f th e re sul t i s 1 , th e ne xt ins t ru c- t i on is ex ec ute d . i f th e res u l t is 0 , t hen a no p is ex ec ute d i nst ead , ma ki ng it a 2 t cy in st ru ct i o n . g o t o u n c ond ition al bran c h sy nt a x : [ la bel ] g o t o k op er a n d s : 0 k 20 47 o pe rati on: k ? p c < 10: 0> p c l a t h <4:3> ? pc < 12: 1 1 > s t at us af fe ct ed: n o ne de s c ri p t i o n : g oto is an un co ndi tio nal bra nch . t he e l e v en -bi t im me dia t e v al ue i s l o a ded in to pc b i t s <1 0:0 >. th e u p p e r b i t s of pc are loa ded fro m p c l a t h <4:3>. got o is a t w o - c y c l e in st ru ct ion . incf inc re m e n t f sy nt a x : [ la bel ] incf f,d o p e rand s: 0 f 127 d ? [0, 1 ] o p e rati on: (f) + 1 ? (d es tin a tio n ) s t at us af fe ct ed: z d e sc ript ion : the co nte nt s of regi ste r ' f ' are inc rem en ted . if ' d ' i s 0 , th e re su lt is pl ac ed in the w reg i s t er . if ' d ' is 1, t he re su lt i s pla c e d ba ck in regi st er ' f ' . incfsz inc r e me nt f, sk ip i f 0 sy nt a x : [ la be l ] incfsz f,d o p e r and s: 0 f 127 d ? [0 ,1] o p e r ati on: (f) + 1 ? ( des tin a ti on), sk ip if res ult = 0 s t at us af fe cte d : n one d es c ripti on : t he co nte nt s of regi st er ' f ' are inc rem en ted . if ' d' is 0 , th e resu lt is p l ac ed in t he w r e gi st e r . i f ' d ' is 1, the res ul t is pl ac ed bac k in re g i s t e r 'f '. if th e re su lt i s 1, th e n e x t in struc- tio n i s e x e c ut ed. if th e re su lt i s 0 , a nop i s ex ec ut e d in st e a d, m ak in g it a 2t cy in str u cti on . io rl w i nclu sive o r lite r a l w ith w sy nt a x : [ l a be l ] io rl w k op er a n d s : 0 k 255 o p e rati on: (w ) .o r . k ? (w) s t at us af fe cte d : z d e s c r ipti on : t he c o n t en t s of t he w reg i s t er a r e o r e d wi th th e e i gh t-bi t li tera l ' k ' . t he r esu lt is pla c e d i n th e w re gis te r . io r w f in c lus ive o r w w ith f sy nt a x : [ lab e l ] io r w f f,d op er a n d s : 0 f 12 7 d ? [0,1 ] ope rati on: (w ) .or. (f) ? ( d es t in a t i o n) s t at us af fe cte d : z des c ription : i n c l u s i v e o r the w r egi ste r with re g i st er ' f ' . i f 'd ' is 0, t h e r e su lt i s p l ac ed in the w re gis t er . if ' d ' i s 1 , t he r es ul t is p l ac ed b ac k i n re gis t e r 'f '.
pic16f84a ds35007b-page 40 ? 2000 microchip technology inc. mov f mo v e f sy nt a x : [ l abe l ] mo vf f, d o p e rand s: 0 f 12 7 d ? [0 ,1] o p e rati on: (f) ? (des ti natio n ) s t at us af fe ct ed: z d e sc ript ion : th e c onten t s o f reg i s t er f are m ove d t o a de sti nat ion de pen dan t up on the st a t us of d. i f d = 0, des - tin a ti on is w re gis t er . if d = 1 , th e de sti nat ion is fi le r egi ste r f i t se lf. d = 1 is u s efu l to t est a f ile r egist er , sin c e s t at us f lag z is af f ecte d. m o vl w m ov e lit eral t o w sy nt a x : [ lab e l ] mo vl w k op er a n d s : 0 k 255 o pe rati on: k ? (w ) s t at us af fe ct ed: n o ne d e sc ript ion : t he e i g ht-bi t l i te ral ' k ' is loa ded i n to w re gis t er . th e do n t ca res w i l l a s se mb le as 0s. m o vwf m ov e w to f sy nt a x : [ lab e l ] mo vwf f op er a n d s : 0 f 12 7 o p e rati on: (w ) ? (f) s t at us af fe ct ed: n o ne d e sc ript ion : m o v e d a t a from w regi st er to re gis t e r 'f '. n o p n o op er ati o n sy nt a x : [ l a be l ] no p o p e rand s: n o ne o pe rati on: n o op erat ion s t at us af fe ct ed: n o ne d e sc ript ion : n o op erat ion . retf ie re turn from inte r r u pt sy nt a x : [ lab e l ] r e tfie o p e r and s: n o ne o p e rati on: t o s ? pc, 1 ? gi e s t at us af fe cte d : n o n e retl w r e turn wi th litera l in w sy nt a x : [ lab e l ] r e tl w k op er a n d s : 0 k 255 o pe rati on: k ? (w ); to s ? pc s t at us af fe cte d : n o n e d e s c ription : t he w reg i s t er i s l o a ded wi th the e i gh t-bit li teral ' k ' . the pro g ram c ou nter is lo ade d fro m the top of th e s t a c k (the ret u rn a d d res s ). t h is is a tw o-c y c l e ins t ru cti on. return r e turn fro m sub r outin e sy nt a x : [ la bel ] return o p e rand s: n o ne o p e rati on: t o s ? pc s t at us af fe cte d : n o n e d e s c ription : r e t urn fr om s ubrou ti ne. th e s t ac k is po ped an d t he top of th e s t a c k (t o s) i s l oad ed int o th e p rogram cou n te r . t h is is a two-c y c l e i n st ru ct io n .
? 2000 microchip technology inc. ds35007b-page 41 pic16f84a rlf r ot ate left f throug h carry sy nt a x : [ lab e l ] r lf f,d op er a n d s : 0 f 12 7 d ? [0,1 ] o pe rati on: se e d esc rip t io n b elo w s t at us af fe ct ed: c d e sc ript ion : t he c on t en t s of re gis t er ' f ' a re ro t a te d o ne bit to t he l e ft thro ugh th e ca rry fl ag . if ' d ' is 0, t he res ul t is pl ac e d i n t h e w r eg is t er . i f ' d ' is 1, t h e r e su l t i s st or e d ba ck i n re gis ter ' f ' . rrf ro t a te right f throug h carry sy nt a x : [ l a be l ] rr f f, d op er a n d s : 0 f 12 7 d ? [0,1 ] o p e r ati on: se e d e s c ri ptio n b e lo w s t at us af fe ct ed: c d e sc ript ion : t he con t en t s of re gis t e r ' f ' are ro t a t ed o ne bit to t he r i gh t th rough t he c a rry fl ag. if ' d ' is 0 , t he res u l t i s pla c e d in th e w regi st er . i f ' d' is 1, t he r es u lt is pl a c e d b ac k i n re gi s te r ' f' . sl eep sy nt a x : [ la bel ]s l e ep o p e rand s: n o ne op er a t io n : 00 h ? wdt , 0 ? wd t p res ca l e r , 1 ? to , 0 ? pd s t atus affected: to , pd d e sc ript ion : t he po w er-do w n st a t us b i t, pd is c l e a re d. t i me -out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c register f c sublw subtract w from literal syntax: [ label ] sublw k op er a n d s : 0 k 25 5 ope r ati on: k - (w ) ? ( w) s t at us af fe cte d : c , dc , z de scr i p t i o n : th e w r e gi st e r is s u bt ra ct ed ( 2 s co mp le me n t m e t h od ) f rom t h e e i gh t-bit l i ter a l ' k ' . the res u l t is p l ac ed in the w re gi ste r . subwf subtra c t w fr o m f sy nt a x : [ la bel ] su b wf f,d o p e rand s: 0 f 12 7 d ? [0 ,1] ope rati on: (f) - (w ) ? ( d es t in atio n) s t at us af fe cte d : c , dc, z d es c ripti on : subt rac t (2 s co mp lem en t m eth od) w regi st er from r egi ste r ' f ' . if ' d ' i s 0, the res ult is st ored in the w re gi s- ter . if ' d ' i s 1 , th e re sul t i s s tore d bac k in regi ste r ' f ' . sw apf sw a p ni bble s in f sy nt a x : [ lab e l ] sw apf f,d o p e rand s: 0 f 12 7 d ? [0 ,1] o p e r ati on: (f<3 :0> ) ? (de s t i na tio n <7 :4>), (f<7 :4> ) ? (de s t i na tio n <3 :0>) s t at us af fe cte d : n on e d es c ripti on : t he up per and lo w er n i bb les of reg i s t er ' f ' ar e ex c han ged . if 'd ' i s 0 , t h e r e su l t i s p la c ed in w r e gi s - ter . if ' d' i s 1, the re su lt is pl ac ed in re gist e r 'f '.
pic16f84a ds35007b-page 42 ? 2000 microchip technology inc. xo rl w e x c lus ive o r litera l w i th w sy nt a x : [ l abe l ] xo r l w k op er a n d s : 0 k 255 o p e rati on: (w ) .xo r . k ? ( w) s t at us af fe ct ed: z d e sc ript ion : th e c on t ent s o f th e w regi st er a re xo re d wit h th e e i gh t-bit li t- e ral 'k '. the res u l t is pl ac ed in th e w regi st er . xo r wf e xc lusi ve o r w wi th f sy nt a x : [ la bel ] x o r wf f,d o p e rand s: 0 f 12 7 d ? [0 ,1] ope rati on: (w) . xo r . (f) ? ( des tin ati on) s t at us af fe cte d : z d e s c ripti on : exc lu si ve or the co nten t s of t he w re gis t e r with reg i st er ' f ' . if ' d ' is 0, the res ult is st ored in the w reg i s t er . if ' d ' is 1 , the res u l t is st ored ba ck in reg i st er ' f ' .
? 2001 microchip technology inc. ds35007b-page 43 pic16f84a 8 .0 d ev elop me nt suppo rt th e pi c m ic ro ? m i c r oc ont roll ers are su ppo rted w i th a fu ll ran ge of ha rdw ar e a nd s oftw a r e d ev elo pm ent to ols : ? i n t eg rate d d e v e l opm en t env i ro nm en t - m plab ? ide softwa re ? ass em bl e rs/ c o mp il er s / li n k e rs - m p asm tm a s se mb ler - m plab c 1 7 a nd mpl ab c 18 c co m p il ers - m plink tm o b j e c t li nk er/ mp l i b tm o b jec t li bra rian ? sim ul a t o rs - m plab s im s o ftwa re si m u lato r ?e m u l a t o r s - m plab i c e 20 00 i n -circ u i t emula tor - i cepi c? in-ci rc u it em ul ato r ? i n -c i rc uit debu gg er - m plab i cd ? d ev ic e progra m m e rs -p r o m a t e ? ii u n i v e rsa l d e vi ce p ro gr a m m e r - picst ar t ? pl u s e nt ry -le ve l d ev el o pm en t pro gram m e r ? l ow co s t de mon s t rati on bo ard s - picdem tm 1 d e mo nst rati on board - pic d em 2 d e m ons trat ion boa rd - picdem 3 d e mo ns trati on boar d - picdem 17 de m ons tra t io n boa rd -k ee l oq ? de mo ns trati on board 8. 1 m plab i nteg r at ed devel opment envi ronment sof t ware th e m plab id e s o ftw a re b ring s an eas e o f s o ftw a re d eve lo pm ent p revi ou s ly uns ee n in th e 8-b i t mi cro c o n- tro l l e r m a rk et. the m pl ab ide i s a wi nd ows ? -b as e d a ppl ic atio n t hat co nt ai ns : ? an i nt e rf ac e t o de bu g gi n g t o ol s - s im ula t or - p rogra m m e r (s o l d s e p a ra tely ) - em ul a t or ( s o l d separ a t el y ) - i n-c i rc uit deb ugg er (s ol d s e p a rately ) ? a f u ll -featured e d ito r ? a p roj ect ma na ger ? c us to mi zab l e tool ba r and k ey ma pp ing ? a s t a t us ba r ? o n-l i ne he lp th e m plab id e al low s y ou t o : ? ed i t y o u r so urc e fi les (e ith e r as s e m b ly or c ) ? o ne tou c h as se mb le (o r c om pil e) a nd dow n l oa d to pic m ic ro em ul ato r an d s i m u la tor tools (aut o- m ati ca lly up dat es all pro j e c t i nfo rma t io n) ? d eb ug us ing : - s ourc e file s - a bs ol u t e li s t i n g f i le - m ac hin e c od e th e ab ili ty t o us e m plab id e w i t h m u lti p l e de bug gin g to ols a llo w s us ers to ea si ly s w itc h f rom th e c os t - ef fe cti v e s i m u l a to r to a fu ll -feat ured em ula t or w i th m i ni ma l re trai nin g. 8. 2 m p a sm assem b l er th e m p asm a s s e m b l e r is a f u ll -fea ture d uni v e rs a l m a c ro a s s e m b le r fo r all picm ic ro mcu s . th e m p asm as se mb ler h as a co mm an d li ne i nte rfac e an d a w i nd ow s s hel l. it c an be u s ed a s a s t an d-a l on e ap pl ic atio n on a win dow s 3 . x or gre ate r s y s t em , or it c an b e us ed thro ugh mpl ab id e. the mp asm ass e m - bl er g e n e rat e s reloca t a b l e obj ec t fi les fo r the m plin k ob je ct li nk er , int el ? s t a nda rd hex fi le s , m a p fi les to de t ai l me mo ry us ag e and s y m bo l refe renc e, an a bs o- l ute lst f ile t hat c ont ain s s ourc e li nes and g ene rate d m a c h in e c o d e , a nd a co d fil e fo r de bug gi ng. th e mp a sm a s s em ble r fe atu res inc l u de: ? i n t eg ration i n to mp lab id e p roj ec t s . ? u s er-de f in ed ma cro s to s t ream li ne as se mbl y c ode . ? c on dit i on al as sem bl y for m ul t i-p urpo s e so urc e fi les . ? d ire c t i ve s that al low c om pl ete co ntro l ov er the a sse mb l y p roc es s. 8. 3 m plab c17 and m p lab c18 c c o m pi l ers th e mpl ab c 1 7 a nd m plab c 18 c ode de vel o p m e n t sy ste m s a re c om ple te a n si c co mp ile rs f or m i c roc hip s pic1 7cxxx an d pic1 8cxxx fa m i ly of m i c roc ont roll ers , re sp ec tiv ely . th es e com pi l e rs prov id e p ow e rf ul in t e gr a t io n c a p a bi l it i es an d ea se of u s e no t fo und wi th oth e r c o m p i l ers . fo r eas ie r s ou rce l ev el de bu ggi ng, th e co mp il ers p ro- vi d e sy mb ol in f o rm at i o n t ha t i s c om p a t ib l e w i t h t he m plab i d e m e m o ry d i s p la y .
pic16f84a ds35007b-page 44 ? 2001 microchip technology inc. 8. 4 m plink object l i nker / mplib object libr ari an th e mpl i n k o bje ct li nk er c om bi nes re lo cat abl e o bje ct s c reate d by th e mp asm as se mbl er a nd th e m plab c 1 7 an d m plab c 1 8 c c o m p il ers . it c an als o li n k r e lo c ata bl e ob j ec t s f rom p re- c om pi le d l ib rar i e s, us in g di rec t iv es f r o m a li n k e r scr i p t. th e m pl i b ob jec t lib raria n is a l i b rarian f o r p re- c om pil ed c od e to be u s e d w i th t he m plin k ob jec t l i nk er . w hen a rou t in e from a li bra ry is ca lle d fro m a noth er sou rce fi le, onl y the mo dul es tha t c on t ain th at ro uti ne w i l l be l i nk ed i n w i th t he ap pli c a t io n. th is a llo w s la rg e l i br a ri es t o be u s e d eff ic ie n t l y in m an y di f f e ren t a ppl ic ati ons . the m pli b o bje ct l i bra ria n ma nag es th e c rea tion an d m o d i fic a t i on of lib rary fil e s . th e mpli n k obj ec t li nk er fe atu res in cl ude : ? i n t e g r a ti on w it h mp a s m as semb le r a nd mp la b c 1 7 a nd mp l a b c 18 c comp il er s. ? a ll ow s a ll m emo ry are as t o be d efin ed as se ctio ns to prov ide l ink -time flex ibi lity . th e m pli b obj ec t li bra rian fea t ure s inc l u de: ? ea s i er l i nk in g be ca us e s i ng le lib rari es ca n be i nc l ud ed i ns t ea d o f m any s m al le r fil es . ? h e l p s k eep co de ma int ain abl e b y g roup in g re lat ed m od ule s toge the r . ? al l ow s li bra ries to be cre ate d an d mod ule s t o b e a dde d, l i s t ed , rep l ac ed , de let ed or ex tra c te d. 8. 5 m plab si m sof t ware simul ator th e mp l ab si m sof t w a re si mu la tor all o w s c ode de ve l- o pm ent in a pc -h ost ed en vi ronm en t b y si mu lat i ng th e picm ic ro s e rie s m i c roc ont rollers o n an i n s t ruc t io n l ev el. on an y g i v en ins t ruc t io n, the dat a ar eas c an b e e x am in ed o r mo difi ed a nd s t im ul i c an be app lie d fro m a fi le , o r u s e r-de f in ed ke y pre s s , to an y of th e pin s . th e ex e c u t i o n ca n b e p e rf o rme d in si ng l e st e p , ex ec ut e u n til bre a k , or trac e m o d e . the mp la b si m simulat or f ully sup ports symbolic de bug- ging using t he mp lab c 1 7 and t he mpl a b c 18 c com- pile r s a nd t he mp a s m a ssemble r . t he so ft war e simula tor of fe rs the fl exibil ity to devel op and debu g cod e o ut s id e of the labo rat ory envir onmen t, mak i ng it an e xcelle nt mu lti- pr oject sof t w are develo pment to ol. 8. 6 m plab i ce hi gh per f orm ance uni versal i n - c irc u it emulat or wit h mplab i de the mplab ic e u niversal in-circui t emula t o r is i n tended to pro v i de the pro duc t d e v e lo pm ent eng in eer w i th a c o m p le te m i c roc ont roller de si gn to ol s e t f o r pic m ic ro m i c roc ont rollers ( m c u s ). softw a re co ntrol of th e m plab ic e in -ci rcu it em ula t or is pro v i ded by th e m p lab in teg r ate d d e v e l opm en t env i ro nm ent (id e), w hi c h a llo w s ed iti ng, b uil din g, do w nlo adi ng an d so urc e de bu ggi ng from a s i n gle en vi ronm en t. th e m plab ic e 20 00 is a ful l -fe a tured e m u l a t or s y s - te m w i th enh anc ed tra c e, trig ge r an d d at a mo nit orin g fe atu res . inte rch ang ea ble proc es so r mo du les al low th e sy st e m t o be e as il y r ec on f ig u red f or em ul at i o n o f di ffe r- en t p roc es sor s . the uni ve rsa l a rch ite c tu re o f th e mp l ab i c e in -c i rcu i t em ul at o r a l l o w s e x pan si o n t o s upp ort new pi c m ic ro mi cro c on trolle rs. th e mp lab ic e in-c irc u i t em ula t or s y s t em has bee n de si gne d as a re al- t im e em ula t io n sy ste m , w i th ad va nc ed fe atur es th at are g ene rall y fo und o n mo re ex pe ns iv e d eve lo pm ent too l s. the pc p l at form an d m i c ros oft ? w i nd ow s ? env iro nm ent w ere ch os en to bes t m a k e th es e fe atu res av ail abl e t o y ou, the end us er . 8. 7 i cep i c i n - c i r cu it emulat or th e ic epic low c o st , i n -c irc u it e m u l at or is a s o lu tio n fo r the mi cro c hi p t e c hno log y pi c 16c 5x , pic 1 6 c 6 x, pic1 6c7x and pic16 c xxx fam i l i e s o f 8-b i t o n e- t im e -p ro g ram ma bl e (o tp ) m ic roc on t rol l er s . t h e m od - ul ar s y s te m c an su ppo rt d i f f eren t s ubs et s o f pic 16 c 5x or pi c16cxxx pr odu c t s thro ugh the u s e o f int e r- c han gea bl e pe rso nal ity mo du les , or d au ghte r bo ards . t he em ul at o r is c apa bl e o f e m u l at i ng w it h ou t ta rge t ap pl ic atio n c i rc ui try bei ng pres en t.
? 2001 microchip technology inc. ds35007b-page 45 pic16f84a 8. 8 m plab i cd i n-ci r cui t debugger m i c r oc hip ' s in-c i r cu it d eb ugg er , m p lab ic d , is a p ow - erful , low co st , run-t i m e dev el opm en t too l . thi s to ol i s b ase d o n t he f lash pi c m ic ro mc u s an d c an be use d to de vel o p for th is and oth e r pi c m ic ro m i c roc on trollers . th e m plab ic d u t ili ze s th e in -ci rcu it d ebu ggi ng c ap a- b ili ty b uil t int o the flash de vi ce s. th is f eat ure, a l on g w it h m ic roc hi p ' s in -c i rcu it ser i al p ro gr a m m in g tm pro t o- c o l , of fe rs co st-ef f e c ti ve i n -c irc u it fla sh de bug gin g fro m the g raph ic al us er inte rfac e of the m plab in teg rate d d e v e l opmen t env i ron m e n t. thi s en abl es a d esi gn er to d ev elo p a nd d ebu g s ourc e c ode by watc h- i ng va riab le s, si ngl e-s t ep pin g a nd se tti ng break poi nt s . r u nni ng at ful l sp eed e nab les t es t ing h ardw a re in rea l - ti me . 8. 9 pro ma te i i univ ersal devi ce programm er th e pr o ma te ii u niv ers al de vi ce pro gram m er i s a f ul l- f e a t u re d p ro gr a mm er , c apab l e of o pe ra t i n g in s t an d-al one mo de, as w ell as pc - ho s t ed m ode . the pr o ma te i i de vi c e p rog ra m m e r is ce c o m p li an t . the pr o ma te ii d evice pro gra mmer has pr ogr am- ma ble v dd an d v pp sup plie s, w hich al low i t to ve rif y pr ogr ammed memor y at v dd min a nd v dd ma x for max- imum rel iabi lit y . it has an lc d d ispl ay f or inst r uc tio ns and er ror me ssage s, ke ys to en ter comma nds and a modu lar detachab le soc k et as sembly t o sup por t var io us p acka ge type s. in st an d-a lone mod e, the pr o ma te ii devi c e pr ogr ammer can rea d, ve rif y , or pro gr am pi c m icr o de vices. it can al so set code p r ot ect ion i n th is mode . 8. 10 pi cst art plus entr y l evel devel opment progr am mer t he p i c st ar t p l us d ev el o pm en t p rog ram m e r i s an ea s y -t o- u s e , l o w co st , p rot o t yp e pr o g ra mm er . i t c o n - n e ct s t o th e pc v i a a c o m ( r s- 232 ) po rt. m plab i n t e gr a t ed d e v e l o pm en t e n vi ro n m e n t so f t w ar e m a k e s u s i ng t he p rog ram m e r si mp le and ef fic i e nt. th e pic st ar t plu s d e v e lo pm ent programm e r su p- p o rt s all pic m i c ro dev ic es w i th u p to 4 0 pi ns . larg e r pi n c oun t de vi ce s, s uc h as the pic 16c 9 2x an d pic 1 7c 76 x, m a y be s u p por ted w i th a n a dap ter s o c k e t . th e pi c s t ar t plu s d e v e lo pm ent pro g ramm e r is c e co mp l i a n t . 8. 1 1 pi cd em 1 low cost picmicr o demonstr a ti on board th e pic d em 1 de mo ns trati on b oar d is a si m p le boa rd w hi c h d em ons trat es the c ap abi lit ies o f s ev era l of m i c roc hip s m i c roc on trol lers . t he mi cro c o ntro lle rs su p- po rted are: p i c 16c 5 x ( pic 16c 5 4 to pi c 1 6c 58 a), pic1 6c61 , pic16 c 6 2 x, pic1 6c71 , pic16 c 8 x, pic 1 7c 42 , pi c 1 7c 43 a nd pic 1 7 c 44. all n e c e s s ar y ha rdw a re a nd sof t w are is in cl ude d to run ba si c d em o p r o g ram s. t h e us er ca n pr o g ram t h e s a mp le m i c roc on - tro lle rs pro v i ded w i t h t he pic d em 1 dem on stra tio n bo ard o n a pr o m a te i i d e v i c e prog ram m e r , or a pic s t a r t pl us d e v e lo pm en t p r og ram m e r , and eas il y te st fir m w ar e. the us er ca n als o co nn ect th e pic d em 1 dem on str a tio n b o a rd to th e m plab ic e i n - c i rc uit e m ul ato r a nd do w n lo ad th e firm w a re to th e em u- l a tor fo r tes t in g. a prot oty pe ar ea is av ail abl e for th e us er to bui ld s om e ad di tion al h ardw a re an d c onn ect it t o t h e m i c roc on t rol l e r so ck et (s ). s o m e o f t h e f e at u res i n cl ud e an r s-2 32 i n te rfac e, a pote n ti om ete r for s i m u - l ated an al og inp ut, pus h but ton sw i t ch es an d e i g ht le d s c onn ec ted to p o r t b. 8. 12 pi cd em 2 low cost pic16cxx demonstr a ti on board th e pi c d e m 2 d emo ns trat ion bo ard is a si mp le dem - on st rati on boa rd t hat su pp ort s th e pi c 16c 6 2, pic 1 6c 64 , pic 1 6 c 65, pic 1 6 c 73 a nd pic 16c 7 4 m i c roc ont rollers . all th e ne ces s a ry h a rdw a re an d so ft- w are is in cl ude d to run t he b as i c dem on str atio n p ro- gr am s. t he u s e r ca n p rogra m t he s am pl e m i c roc ont roll ers pro v id ed w i th the pic d em 2 de mo n- s t ration boa rd o n a pr o ma te i i de vi ce programm e r , or a pic st ar t pl us d e v e lo pm ent prog ramm e r , an d ea si ly te st fi rmw a r e . the m plab ic e i n -c irc u it em ul a- to r ma y a l s o be us ed w i th t he pi c d e m 2 dem on stratio n bo ard to te st firm w a re . a pro toty p e are a has b een p r o- v i de d to the us er f o r a ddi ng a d d i tio n a l ha rdw a r e an d c onn ec tin g it to t he m i c roc on troller soc k e t(s ). som e of th e f eat ures i n c l ud e a r s-2 32 in terfa c e , p u sh b u tto n s w itc hes , a po ten t iome t e r for s i m u la ted a nal og i npu t, a s e ria l ee pr o m to dem on st rate us age of the i2c t m bu s a nd s ep arat e he ade rs f or co nn ect i on to a n lc d m odu le and a key p a d.
pic16f84a ds35007b-page 46 ? 2001 microchip technology inc. 8. 13 pi cd em 3 low cost pic16cxxx demonst rat i on board th e pic d em 3 d em ons trat ion bo ard is a si mp le dem - o n st ration b oard tha t su ppo rt s t he pi c 1 6c 92 3 an d pic 1 6c 92 4 i n th e plc c p ac k a ge. it w i l l a l so su pp ort fu ture 4 4 -p in plcc m i c ro c o n tro lle rs with an lcd m o d- u l e. all the ne ces s a ry har dw are and s o ftw a r e i s i n c l ud ed to r un the bas ic d e m ons trat ion pro g ra ms . th e u s er c an p rogra m th e sa mp le m i c roc ontr oll ers p ro- v i d ed w i th th e p i c d em 3 dem on stra tio n boa rd on a pr o m a te ii de vi ce prog ramm e r , o r a pic st ar t plu s d e ve lo pm ent programm e r w i th an ad apt er s o c k e t, an d e a s i ly te s t fi rm wa re. the m p lab ice i n -c ircu it em ul a- to r ma y a l s o b e us ed w i th the pic d em 3 dem on str atio n b oard to te st firm w a re . a pro t oty p e ar ea has b e e n p ro- v i d ed t o th e u s e r for ad din g h ardw a re a nd con ne c ti ng it t o th e m ic roc on t rol l er so ck et (s ). s om e of t he f e at u res in cl u de a r s-2 32 i nt e rf ac e, p us h bu t t on s w it c he s , a p o ten t io me ter fo r s i m u l a te d ana log i n p u t, a th ermi s t or a nd s ep arat e he ade rs fo r co nne cti on t o an ext erna l l c d mo du le and a k eyp ad . al so pro v i ded on th e pi c d em 3 d em o ns tr a t io n bo ar d is a l c d p a ne l , w i t h 4 c o m m o n s a nd 1 2 se gm ent s , tha t is c a p abl e of d isp la y- i ng time , temp e ratu re a nd day o f th e w e ek . th e pic d em 3 d em ons trat ion boa rd pr ovi de s an add iti ona l r s-2 32 i n te rfac e a nd win dow s s o ftw a re fo r sh ow in g t h e d e m u lt i p l e xe d lc d si gn a l s o n a pc . a s i m p l e se ri al in t e rf a c e al l o w s t h e us er t o c o ns tr u c t a ha rd w a re de mu l t ip le x e r f o r t h e l c d si gn a l s . 8. 14 pi cd em 17 demonst rat i on board t h e p i c d em 17 d e m o n s t ra t i on bo a rd is an ev al u a t i on bo ard that dem on strates the cap a b ili tie s of s e v e ra l m i c roc hip m i c roc ont roll ers , i ncl ud ing pic 1 7c 75 2, pic 1 7c 75 6a, pi c 17c 7 62 a nd pic 1 7 c 7 6 6 . all ne ces - s a ry hard w are is inc l u ded to ru n b a si c d e m o p rogram s , w hi c h a re s upp lie d on a 3.5- inc h di sk . a prog ram m e d s am ple is inc l u ded an d the us er m ay eras e i t an d pr ogram it w i t h the ot her s a m p le p rogram s usi n g th e pr o ma t e ii devi c e p r og ra mmer , or t he p i c st a r t pl us de velop ment pro gr ammer , and easi ly deb ug an d te st t he samp le cod e. i n ad dit ion, th e pi c d em 1 7 dem- onst r a t io n boa rd s uppor t s do w n load ing o f pr ogr ams t o and exe c uti ng out of ext ern al fla s h me mor y on boa rd. th e pi c d e m 17 d emon s tr ati on boar d is a lso usabl e w i th the mpl a b ic e in-ci rcu i t e m ulat or , or th e pi c m as t e r emulat or and al l o f the samp le pro gr ams can b e r un an d modi fie d usin g ei the r emu lat or . ad dit ion- all y , a gene rous pr oto t ype ar ea is avail able f or user har dw ar e. 8. 15 k ee l oq eval uati on and pro gramm i ng t ool s k ee l oq e v a l ua tio n an d pr ogra m m i n g to ols su ppo rt mi cr o c h i ps h c s se cu re d a ta pro du cts . t h e h c s ev al - ua tio n k it in cl ude s a lc d dis p l a y t o sh ow c han gin g c ode s, a d ec ode r to de co de tra ns m i s s i on s a nd a p ro- gr am mi ng i nte rfac e t o pro gra m t est tran sm itt ers .
? 2001 microchip technology inc. ds35007b-page 47 pic16f84a table 8-1: development tools from microchip pi c1 2 c xx x p i c 140 00 p i c 16c 5 x p i c 16c 6 x pi c1 6 c xx x p i c 16f 62 x p i c 16c 7 x p i c 1 6c 7x x p i c 16c 8 x p i c 1 6f 8x x p i c 1 6c 9x x p i c 17c 4 x p i c 1 7c 7x x pi c1 8 c xx2 pi c1 8 f x x x 24 c x x / 25 c x x / 93 c x x hcsxxx m crf xxx mc p 2 5 1 0 so ft w a r e to ol s mplab ? integrated development environment 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 mp l a b ? c1 7 c co m p ile r 9 9 mpl a b ? c1 8 c co m p ile r 9 9 mpa s m tm ass e m b le r / mpl i n k tm ob je ct l i n k e r 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 emula t o r s mp l a b ? ice in -ci r c u it e m u lat o r 9 9 9 9 9 9 ** 9 9 9 9 9 9 9 9 9 i c epi c tm in -ci r c u it e m u la t o r 9 9 9 9 9 9 9 9 d e b ugg er mp l a b ? icd in -cir cu it d e bu gge r 9 * 9 * 9 9 pr ogr am mer s picst art ? pl u s en t r y lev e l d e ve l op m en t pr og ra mme r 9 9 9 9 9 9 ** 9 9 9 9 9 9 9 9 9 pro m a t e ? ii u n i versa l d e vic e p r og r am m e r 9 9 9 9 9 9 ** 9 9 9 9 9 9 9 9 9 9 9 de m o bo a r d s a n d ev a l ki t s picdem tm 1 dem o n s tr at io n bo a r d 9 9 9 ? 9 9 picdem tm 2 dem o n s tr at io n bo a r d 9 ? 9 ? 9 9 picdem tm 3 demo n s tr at io n bo a r d 9 picdem tm 1 4 a de m o n s t r a t io n bo a r d 9 picdem tm 17 de mo ns tr at i o n bo a r d 9 k ee l oq ? ev a l ua t i o n ki t 9 k ee l oq ? tr an sp on d e r k i t 9 mi c r o i d tm pr ogra mme r ?s kit 9 12 5 k h z m i cr o i d tm de v e lo p e r ? s kit 9 12 5 kh z a n tic o l lisi o n m i c r oid tm de v e lo p e r ? s kit 9 13 .56 mh z a n tic o lli sion mi c r oi d tm d e v e l oper? s k i t 9 m c p2 5 1 0 can de v e lo p e r ? s kit 9 * c ontact the mi cr och i p t e chn o l o g y in c. w e b si t e a t w w w .m i c roc h i p .c om for i n fo rm ati o n o n h o w t o u s e t he mp la b ? ic d in -c i r cui t d e bu gge r ( d v 164 00 1) w i t h p i c 1 6c 6 2 , 63, 64, 65 , 7 2 , 7 3 , 74, 76 , 77 . * * co n t a ct m i cr o ch i p t e c h n o lo g y in c. fo r a va ila b ility d a t e . ? d e vel o pm ent too l i s av ai l a b l e on se l e ct d e vi ce s.
pic16f84a ds35007b-page 48 ? 2001 microchip technology inc. notes :
? 2001 microchip technology inc. ds35007b-page 49 pic16f84a 9.0 e l e ctr i c a l charac teristics abs olute m axim um rating s ? am bi ent tem p e r atur e un de r bia s .. ...... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ..... .-5 5 c to +12 5 c s tora g e tem p e r atu r e ... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... .... .. ..... ...... ..... -6 5 c to +15 0 c v o lt a ge on a ny pi n w i t h re sp ect to v ss (ex c e p t v dd , m c lr , a nd ra4) .... ..... ...... ...... ..... ...... ..... .... -0. 3 v to (v dd + 0. 3v) v o lt a ge on v dd wit h re sp ect to v ss . ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... -0. 3 to +7. 5 v v o lt age on mclr with res pec t to v ss (1 ) ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ..-0 .3 t o +1 4v v o lt a ge on ra4 with res p e c t to v ss . ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... -0. 3 to +8. 5 v t o tal po w e r di ss ipa ti o n (2 ) .. ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... .. .... .. 80 0 m w ma xi mu m c u rre nt o u t o f v ss pi n . . ...... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ... 15 0 m a ma xi mu m c u rre nt i n t o v dd pi n ..... ...... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ... 1 0 0 m a in put cl am p c u rre nt, i ik (v i < 0 o r v i > v dd ) .. .... ... .... ... .... .... ... .... .... ... .... .... ... .... ... .... .... ... .... .... ... .... ... .... .... ... .... .... ... .... .... .. 20 m a ou t p u t c l am p cu rre nt , i ok (v o < 0 o r v o > v dd ) . .... ... .... .... ... .... .... ... .... .... ... .... ... .... .... ... .... .... ... .... ... .... .... ... .... .... ... .... .... .. 20 m a m a x i m u m ou tput cu rrent su nk by an y i / o pin..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... . ..... ..... ...... ..... 25 m a m a x i m u m ou tput cu rren t so urce d by any i/ o p i n ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... .... .. ..... ...... ..... 2 5 m a ma xi mu m c u rre nt su n k b y po r t a ..... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... 80 m a m a x i m u m cu rren t s ourc e d by po r t a ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... 50 m a m a x i m u m cu rren t s unk by po r t b ..... ..... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... .... .. ...... ..... ...... ... 1 5 0 m a m a x i m u m cu rren t s ourc e d by po r t b .... ...... ..... ...... ...... ..... ...... ...... ..... ...... ..... ...... ...... ..... ...... ..... ...... . ..... ..... ...... ... 1 0 0 m a note 1 : v o l t ag e sp ik es be l o w v ss at th e m c lr pi n, i ndu ci ng c u rre nt s gre a te r tha n 80 ma, ma y c aus e l a tc h-u p . th us , a se rie s re si sto r of 50 -100 w s ho uld be us ed w hen ap ply i n g a lo w le vel to the m c l r pi n ra the r tha n pu l li n g t h is p i n d ir e ct l y t o v ss . 2: po w er di ss ip a t io n is ca lc ula t ed as f ollows: pdis = v dd x { i dd - ? i oh } + ? {(v dd -v oh ) x i oh } + ? (v o l x i ol ). ? n o t i c e : s t r e ss es abo ve tho s e li ste d u nde r a b s o l u te ma xi mu m r a tin g s ma y c a u s e per man e n t da ma ge t o th e d evi ce . t his is a stre ss rat i ng on ly and fu nct i on al ope rati on of th e d ev i ce at tho s e or a ny oth er c ond iti ons a bov e th os e i nd i ca ted i n t he ope rati on li sti ng s of this s pe c i f ic ati on is n ot im pli ed. e x po su re to ma xim um r atin g co ndi tio ns for e x te nde d p erio d s ma y af f ec t de vi ce reli abi li ty .
pic16f84a ds35007b-page 50 ? 2001 microchip technology inc. figure 9-1: pi c16f84 a-20 v o lt age - fre q uen c y grap h fig ure 9- 2: pi c16lf84 a - 04 v o lt ag e- freque ncy graph fig ure 9- 3: pi c16f8 4 a- 04 v o lt ag e - freque ncy grap h frequen c y voltage 6.0v 5.5v 4.5v 4.0v 2.0v 20 mhz 5.0v 3.5v 3.0v 2.5v fr e q uency voltage 6.0v 5.5v 4.5v 4.0v 2.0v 5.0v 3.5v 3.0v 2.5v f max = (6.0 mhz/v) (v ddappmin - 2.0v) + 4 mhz 4 mh z 10 mhz note 1: v dd ap pm i n is t he minimum v ol t age of the pi c mi cr o ? dev i c e in t he appli c at ion. 2: f max has a m a xim u m f r eque ncy of 10 m h z. frequen c y vo l t age 6. 0v 5.5v 4. 5v 4. 0v 2.0v 5. 0v 3. 5v 3.0v 2.5v 4 m h z
? 2001 microchip technology inc. ds35007b-page 51 pic16f84a 9. 1 dc c h aract eri s ti cs pic16l f84 a -04 (c o m m e rc ia l, in dus tri a l) s t a ndard o p eratin g cond ition s (un les s oth e rw ise st a ted) o pe rat i n g t em p er a t ur e 0 c t a +7 0 c (c om m e rc i a l) -4 0 c t a +8 5 c (i ndu s t ri al ) -4 0 c t a +1 25 c (ext end ed) pic16f84a-04 (c o m m e rc ia l, in dus tri a l, ext end ed) pic 16f 84a -2 0 (c o m m e rc ia l, in dus tri a l, ext end ed) s t a ndard o p eratin g cond ition s (un les s oth e rw ise st a t ed) o pe r atin g t em p er a t ur e 0 c t a +7 0 c (c om m e rc i a l) -4 0 c t a +8 5 c (i ndu strial ) -4 0 c t a +1 25 c (ext end ed) pa r am no. s y mb o l c h a r ac te r i st i c mi n t y p? m a x u ni t s condi tions v dd su pp l y v o lt a g e d 0 01 16 lf8 4 a 2 .0 5 .5 v xt , rc , an d l p os c co nfig ura t ion d001 d001a 16f 84 a 4.0 4.5 5. 5 5. 5 v v xt, rc and l p os c c on f ig urat ion h s os c co nfi gura t io n d0 0 2 v dr ram dat a reten t ion v olt a ge (n ot e 1) 1.5 v dev i c e i n sl eep m o de d0 0 3 v por v dd s t a r t v o lt ag e to en sure i n tern al power- on re s e t s i gn al vss v se e se ct io n on po w e r- on r e se t for de t a il s d0 0 4 s vd d v dd ris e ra te to e n s u re i n tern al power- on re s e t s i gn al 0.05 v/ms i dd sup ply current (note 2 ) d 0 10 16 lf8 4a 1 4 m a r c an d xt os c c on f ig urati on (note 4) f osc = 2. 0 mh z, v dd = 5.5 v d010 d010a d013 16f84a 1.8 3 10 4. 5 10 20 ma ma ma r c an d xt os c c o nfiguration (n ote 4) f osc = 4. 0 mh z, v dd = 5.5 v r c an d xt os c c on f ig urati on (note 4) f osc = 4. 0 mh z, v dd = 5.5 v (d uri ng flash p r og ram m i ng) h s os c co nfi gurat io n (pic 1 6f8 4 a-20) f osc = 20 mhz , v dd = 5 . 5v d 0 14 16 lf8 4a 1 5 45 m a l p osc c onf igu rati o n f os c = 32 khz, v dd = 2. 0v , wd t disabl ed leg end : r o w s w i th s t a nda rd v ol t ag e de vi ce dat a o nly are s had ed for i m p rov ed r ead abi lit y . ? d a t a in " t y p" co lum n is at 5 . 0v , 25c u nle ss ot herw i se st ated . t hes e p ara me ters are for des ig n gu id anc e onl y a nd are not test ed . n r n o t ra ted for o p e ration. note 1 : t h is is th e li mi t to wh ic h v dd ca n be lo w ered wi th out lo sin g r am da t a. 2: the su ppl y c urre nt i s ma inl y a fun c t i on of the ope rati ng vol t ag e a nd frequ en cy . ot her fac t ors , s uc h a s i/ o pin lo adi ng and sw i t ch ing rat e, o s c ill ato r ty pe, int erna l c od e e x ec ut ion p a ttern , an d te mp era t ure als o h av e an i m p a c t on th e c u rrent c o n s um pt ion . the tes t c ond iti ons fo r al l i dd m eas ure m e n t s in ac tiv e o perat io n m o d e a re: o sc1 = e x te rnal s qua re wav e , from ra il-to -rail ; a l l i/o pi ns tri -st a t ed , pu lle d t o v dd , t0cki = v dd , m c lr = v dd ; wd t ena bl ed/d i s abl ed as sp ec ifie d. 3: the powe r-down c u rren t in sleep m o de doe s n o t d epe nd on the os c i l l a t or t y pe . po w e r-do w n c u rre nt i s m e as u r ed with the p a r t in sleep m o de, with all i/o p i ns in hi -im ped anc e s t a t e a nd tie d to v dd an d v ss . 4: for r c o s c c onfi g u r ati on, cu rrent thro ugh r ext i s not inc l u ded . th e c u rre nt t h rou gh the res i s t or c a n be est i m a te d by th e fo rmu l a i r = v dd /2r ext (m a) wit h r ext in ko hm . 5: the d c u rren t is th e a ddi tio nal cu rren t c ons um ed w hen thi s p e ri phe ral is ena bl ed. thi s c u rre nt s h o u ld be add ed to th e b a s e i dd m eas ure m e n t.
pic16f84a ds3500 7b-page 52 ? 2001 mic r ochip t e c hnology i n c. i pd powe r - d o wn curre n t (note 3) d 0 20 16 lf8 4a d020 16f 84a-2 0 16f 84a-0 4 d 0 21 a 1 6 l f8 4a 0 . 4 1 . 0 m av dd = 2. 0v , w d t di sa ble d, i ndu st rial d02 1 a 16f 84a-2 0 16f 84a-0 4 1.5 1.0 3. 5 3. 0 m a m a v dd = 4. 5v , w d t di sa ble d, i ndu st rial v dd = 4. 0v , w d t di sa ble d, i ndu st rial d02 1 b 16f 84a-2 0 16f 84a-0 4 1.5 1.0 5. 5 5. 0 m a m a v dd = 4. 5v , w d t di sa ble d, e x te nd ed v dd = 4. 0v , w d t di sa ble d, e x te nd ed d0 2 2 d i wd t m odul e diffe rentia l curren t (note 5) w a tch dog t i m er .20 3.5 3.5 4.8 4.8 16 20 28 25 30 m a m a m a m a m a v dd = 2. 0v , i ndu str i al , c om m e rci al v dd = 4. 0v , c o mm erc i a l v dd = 4. 0v , in du strial, ext end ed v dd = 4. 5v , c o mm erc i a l v dd = 4. 5v , in du strial, ext end e d 9. 1 dc c h aract eri s ti cs ( c onti nued) pic16l f84 a -04 (co m m e rc ia l, in du s tri al) s t a ndard o p eratin g cond ition s (un les s oth e rw ise st a ted) op era t ing te mp eratu re 0 c t a +7 0 c (c om m e rc i a l) -4 0 c t a +8 5 c (i ndu s t ri al ) -4 0 c t a +1 25 c (ex t end ed) pic16f84a-0 4 (c o m m e rc ia l, in du strial, ext end ed) pic 16f 84a -2 0 (c o m m e rc ia l, in du strial, ext end ed) s t a ndard o p eratin g cond ition s (un les s oth e rw ise st a t ed) op era t ing te mp eratu r e 0 c t a +7 0 c (c om m e rc i a l) -4 0 c t a +8 5 c (i ndu stri al ) -4 0 c t a +1 25 c (ex t end ed) pa r am no. s y mb o l c h a r ac te r i st i c mi n t y p? m a x u ni t s condi tions leg end : r o w s w i th s t a nda rd v ol t ag e de vi ce dat a o nly are s had ed for i m p rov ed r ead abi lit y . ? d a t a in " t y p" co lum n is at 5 . 0v , 25c u nle ss ot herw i se st ated . t hes e p ara me ters are for des ig n gu id anc e onl y a nd are not test ed . n r n o t ra ted for o p e ration. note 1 : t h is is th e li mi t to wh ic h v dd ca n be lo w ered wi th out lo sin g r am da t a. 2: the su ppl y c urre nt i s ma inl y a fun c t i on of the ope rati ng vol t ag e a nd frequ en cy . ot her fac t ors , s uc h a s i/ o pin lo adi ng and sw i t ch ing rat e, o s c ill ato r ty pe, in terna l c od e e x ec ut ion p a ttern , an d te mp era t ure als o h av e an i m p a c t on th e c u rrent c o n s um pt ion . the tes t c ond iti ons fo r al l i dd m eas ure m e n t s in ac tiv e o perat io n m o d e a re: o sc1 = e x te rnal s qua re wav e , from ra il-t o -rail ; a l l i/o pi ns tri -st a t ed , pu lle d t o v dd , t0cki = v dd , m c lr = v dd ; wd t ena bl ed/d i s abl ed as sp ec ifie d. 3: the powe r-do w n c u rren t in sleep m o de doe s n o t d epe nd on the os c i lla tor t y pe . po w e r-do w n c u rre nt i s m e as u r ed with the p a r t in sleep m o de, with all i/o p i ns in hi -im ped anc e s t a t e a nd tie d to v dd an d v ss . 4: for r c o s c c onfi g u r ati on, cu rrent thro ugh r ext i s not inc l u ded . th e c u rre nt t h rou gh the res i s t or c a n be est i m a te d by th e fo rmu l a i r = v dd /2r ext (m a) wit h r ext in ko hm . 5: the d c u rren t is th e a ddi tio nal cu rren t c ons um ed w hen thi s p e ri phe ral is ena bl ed. thi s c u rre nt s h o u ld be add ed to th e b a s e i dd m eas ure m e n t.
? 2001 microchip technology inc. ds35007b-page 53 pic16f84a 9. 2 dc c h aract eri s ti cs: pic16 f84a-04 (commerci a l, i ndust ri al) pic16 f84a-20 (commerci a l, i ndust ri al) pic16 lf84a-04 ( c ommerci a l, indust ri al) d c c h ar ac ter i st ics a l l pins exc e pt pow e r sup ply p ins s t and a rd o pe r a t ing condi tions (unle ss othe r w is e s t ate d) o p e r ati ng tem per ature 0 c t a +70 c (c o m m e rc ia l) -40 c t a +85 c (in dus tria l) o pe r ati ng vo lt ag e v dd ran ge as de sc ribe d i n d c s pe c if ic atio ns (se c t ion 9 .1 ) pa ram no. s ymb ol c h a r acter istic m in t y p ? m a x u nit s c ond itions v il i nput low v o lt ag e i / o port s : d 0 30 w i th ttl buf fer v ss 0 . 8 v 4 . 5 v v dd 5. 5v (note 4) d0 3 0 a v ss 0 . 1 6 v dd v ent ire rang e (n o te 4) d 0 31 w i th schm it t t rig ge r buf fe r v ss 0 . 2 v dd v ent ire rang e d 0 32 m c lr , r a 4/t0 cki v ss 0 . 2 v dd v d 0 33 o s c 1 (xt , h s and lp mo des ) v ss 0 . 3 v dd v (note 1) d 0 3 4 osc1 (rc m o d e ) v ss 0 . 1 v dd v v ih i nput h i gh v olt a ge i / o port s : d0 4 0 d0 4 0 a w i th ttl buf fer 2 .0 0.25 v dd +0 . 8 v dd v dd v v 4. 5v v dd 5. 5v (n ot e 4) ent i re rang e (n o te 4) d 0 41 w i th schm it t t rig ge r buf fe r 0 .8 v dd v dd ent i re rang e d 0 42 m c lr , 0 .8 v dd v dd v d 0 42 a r a4 /t0cki 0 .8 v dd 8 . 5 v d 0 43 o s c 1 (xt , h s and lp mo des ) 0 .8 v dd v dd v (note 1) d 0 43 a o sc 1 (r c mo de) 0 . 9 v dd v dd v d0 5 0 v hy s hy stere s is of sc hmit t t r igg er i nput s 0 . 1 v d0 7 0 i pur b portb w e a k pu ll-up curre nt 50 25 0 40 0 m av dd = 5 . 0v , v pi n = v ss i il i nput leak age current (n o t es 2, 3 ) d 0 60 i / o port s 1 m av s s v pi n v dd , pin at hi- i m ped anc e d 0 61 m c lr , r a 4/t0 cki 5 m av s s v pi n v dd d0 6 3 o s c 1 5 m av s s v pi n v dd , xt , hs an d l p os c con f ig urat ion ? d a t a in t yp c olu mn is at 5.0 v , 25 c unl es s o t he rw is e s t ate d. the s e p ar ame ters a re fo r de si gn g uid an ce onl y a nd are not test ed . note 1 : i n r c osci ll a t or c on f i gu rat i o n, t h e os c 1 p in i s a sc hm it t t ri g ge r i np u t . do no t d riv e th e pi c 16 f 84 a w i t h an e x te rn al cl oc k w h il e th e de vi ce is in rc mo de , or c h i p d a m a g e ma y r e su lt . 2: the leak a ge cur rent on the mc l r pin is s t rong ly de pen den t on th e ap pl ied vo lt a ge lev el . th e s pec if ied lev e l s re pres en t no rma l o per atin g c o n d iti o n s . h i gh er l eak ag e c u rre nt m a y be me as ured at dif f e r ent inp u t vol t ag es . 3: n e ga tiv e c u rre nt i s d e fi ned as c o mi ng out of the pin . 4: the us er m ay ch oos e the bet ter o f th e tw o sp ec s.
pic16f84a ds35007b-page 54 ? 2001 microchip technology inc. v ol o utp ut lo w v ol t age d 0 80 i / o port s 0 . 6 v i ol = 8.5 m a, v dd = 4 . 5v d 0 83 o sc 2 / c lko u t 0 .6 v i ol = 1.6 m a, v dd = 4 . 5v , (r c m o de on l y ) v oh o utp ut high v o lt ag e d 0 90 i / o port s (no te 3 ) v dd -0.7 v i oh = - 3 .0 ma , v dd = 4 . 5v d 0 92 o sc 2 / c lko u t (note 3) v dd -0.7 v i oh = - 1 .3 ma , v dd = 4 . 5v (r c m o de on l y ) v od o p e n drain high v o l t age d 1 50 r a4 pi n 8 .5 v ca p a c itiv e lo adin g spe cs o n outp ut pin s d1 0 0 c os c2 o sc 2 pin 1 5 pf i n xt , hs an d l p mo des w h en e x t e rn a l cl oc k is us e d to dri v e osc 1 d1 0 1 c io al l i/ o p i ns an d o sc 2 (rc mo d e ) 5 0 p f d a t a e ep ro m m e m o ry d1 2 0 e d en du ranc e 1 m 1 0m e/w 25 c at 5v d1 2 1 v dr w v dd fo r rea d /wri te v mi n 5 . 5 v v min = m ini mu m o per atin g v olt age d1 2 2 t dew er ase / w rite cycl e ti me 4 8 m s pro g ram flash m e m o ry d1 3 0 e p en du ranc e 100 0 1 0k e/w d1 3 1 v pr v dd fo r rea d v mi n 5 . 5 v v min = m ini mu m o per atin g v olt age d1 3 2 v pew v dd fo r era s e /write 4 .5 5 .5 v d1 3 3 t pew er ase / w rite cycl e ti me 4 8 m s 9. 2 dc c h aract eri s ti cs: pic16 f84a-04 (commerci a l, i ndust ri al) pic16 f84a-20 (commerci a l, i ndust ri al) pic16 lf84a-04 ( c ommerci a l, indust ri al) ( c o n ti nued) d c c h ar ac ter i st ics a l l pins exc e pt pow e r sup ply p ins s t and a rd o pe r a ting condi tions (unle ss othe r w is e s t ate d) o p e r ati ng tem per ature 0 c t a +70 c (c o m m e rc ia l) -40 c t a +85 c (in dus tria l) o pe rati ng vo lt ag e v dd ran ge as de sc ribe d i n d c s pe c if ic atio ns (se c t ion 9 .1 ) pa ram no. symb ol c ha r acte r istic m in t y p ? m a x u nit s c ond itions ? d a t a in t yp c olu mn is at 5.0 v , 25 c unl es s o t he rw is e s t ate d. the s e p ar ame ters a re fo r de si gn g uid an ce onl y a nd are not test ed . note 1 : i n r c osci ll a t or c on f i gu rat i o n, t h e os c 1 p in i s a sc hm it t t ri g ge r i np u t . do no t d riv e th e pi c 16 f 84 a w i t h an ext erna l c l o c k whi l e t he dev ic e i s i n r c m od e, o r ch ip dam ag e may res ul t . 2: the leak a ge cur rent on the mc l r pin is s t rong ly de pen den t on th e ap pl ied vo lt a ge lev el . th e s pe c if ied lev e l s re pres en t no rma l o per atin g c o n d iti o n s . h i gh er l eak ag e c u rre nt m a y be me as ured at dif f e r ent inp u t vol t ag es . 3: n e ga tiv e c u rre nt i s d e fi ned as c o mi ng out of the pin . 4: the us er m ay ch oos e the bet ter o f th e tw o sp ec s.
? 2001 microchip technology inc. ds35007b-page 55 pic16f84a 9. 3 ac (t imin g) charact eri s ti cs 9 . 3. 1 t i m i n g pa r a me ter s y m b ol ogy th e t i m i ng p a r am ete r sy mb ol s h av e be en cre ate d fo l- l o win g on e o f th e fo llo wing fo rma t s: 1. tp ps2p ps 2 . tp ps t f f requ enc y t t i me l o w e rc as e l e tte rs ( pp) and the i r m e a n in gs : pp 2 to o s , osc o sc1 ck c lk o u t os t os c i l la t or s t a rt -up t im er cy cycl e t i me pwr t po we r -u p t i m e r i o i/ o port rb t r bx pi ns in p i n t p in t 0 t 0c ki mp mcl r w d t w at ch dog tim er u p p e r ca se le t t e r s an d t h ei r me an i n g s : s f f all p pe riod hh i g h rr i s e i i n v a lid (hi gh im ped anc e) v v al id l l ow z h ig h i m p eda nce
pic16f84a ds35007b-page 56 ? 2001 microchip technology inc. 9.3 . 2 t iming c o nd itio ns th e t em pera t ure an d v olt age s spe c i f ie d i n t abl e 9 -1 a ppl y to all ti mi ng sp ec ifi c at ion s unl es s oth erw is e no t e d. a l l t i mi ng s ar e me as u r e d be t w e e n h i g h an d l o w m ea s ur eme nt poi nt s as in dic at ed i n f i gu re 9 -4. f i g u re 9- 5 sp ec i f i e s th e l o ad co nd i t i o ns f o r t h e t i mi ng s pec if ic atio ns . t a ble 9 - 1 : t e mp e rature and v o lt age sp ec ifications - ac figure 9-4: par a me ter m e a s ure me nt inform ation figure 9-5: lo a d conditions a c characteris tics s t anda rd o pera ting c o nditi ons (unle ss otherw is e st ated ) o p e r ati ng t e m pera t ure 0 c t a +70 c for c o m m e rc ial -40 c t a + 8 5 c f o r i n du st ri al o pe rati ng v ol t ag e v dd ran ge as des c ribe d i n dc s pec ifi c a t io ns (sec t io n 9 .1) 0.9 v dd (high) 0.1 v dd (low) 0. 8 v dd rc 0. 3 v dd xt a l osc1 meas urement point s i /o po rt meas urement points 0. 1 5 v dd rc 0.7 v dd xt a l (high) (l ow) load condition 1 load c o nd i t i o n 2 pin r l c l v ss v dd /2 v ss c l pi n r l = 4 6 4 w c l = 50 p f fo r all pi ns ex ce p t os c 2 1 5 pf f o r o s c2 o u tp ut
? 2001 microchip technology inc. ds35007b-page 57 pic16f84a 9.3 . 3 t iming d i ag ra ms an d sp ec if icat i o ns figure 9-6: ex ter nal clock t i ming osc1 clkout q4 q1 q2 q 3 q4 q1 13 3 4 4 2 t able 9 - 2 : ex tern al clock t i ming re quire m e n t s pa ra m no. sy m cha r a c te ris tic m i n t y p ? m a x u nit s c ondi tions f os c ex te rna l clkin f r e que nc y (1 ) dc 2 m h z xt , r c o s c (-0 4, lf) dc 4 mhz xt , rc o s c (-0 4 ) dc 2 0 m hz hs o s c (-2 0 ) d c 2 0 0 kh z l p os c (-0 4, lf) o s c illa tor freq uen c y (1 ) dc 2 mhz rc o s c (-0 4 , l f ) dc 4 mhz rc o s c (-0 4 ) 0 .1 2 m h z xt os c (-0 4, lf) 0 . 1 4 m hz xt os c (-0 4) 1 .0 20 m h z h s o s c (-2 0) d c 2 0 0 kh z l p os c (-0 4, lf) 1t osc ex te rna l clkin pe riod (1 ) 500 ns xt , r c o s c (-0 4, lf) 250 ns xt , r c o s c (-0 4) 50 ns h s o s c (-2 0) 5. 0 m s l p os c (-0 4, lf) o s c illa tor perio d (1 ) 500 ns r c o s c (-0 4, lf) 250 ns r c o s c (-0 4) 500 1 0 , 00 0 n s xt os c (-0 4, lf) 250 1 0 , 00 0 n s xt os c (-0 4) 50 1 ,000 ns h s o s c (-2 0) 5. 0 m s l p os c (-0 4, lf) 2t cy in struc tion cy cle t i m e (1 ) 0. 2 4 / f os c dc m s 3 t os l, to s h clo ck in (osc1) hi gh or low ti m e 60 ns xt os c (-0 4, lf) 50 ns xt os c (-0 4) 2. 0 m s l p os c (-0 4, lf) 17 .5 ns h s o s c (-2 0) 4t o s r , to s f c lo ck in (o sc1) r i se o r fal l ti m e 25 ns xt os c (-0 4) 50 ns l p os c (-0 4, lf) 7 . 5 n s h s o s c (-2 0) ? d a t a in " t y p" co lum n is at 5 . 0v , 25 c u nle ss ot herw i se st ated . t hes e p ara me ters are for des ig n gu id anc e onl y a nd are not test ed . note 1 : i n st ru ct i o n cy cl e p e r i o d ( t cy ) e qu als fou r ti me s t he i npu t o s c ill ato r tim e-b as e p erio d. all sp eci f ie d v al ues are b as ed on cha rac teri za tio n da t a for t hat p art ic ula r os ci lla tor typ e u nde r st and ard ope rati ng con di t ion s w i th the d ev i c e exe c u t in g cod e. exc eed ing t hes e sp ec ifi ed li mi t s m ay res ul t i n an un st abl e osc i l l a t or ope ra- tion an d/o r hi ghe r tha n e x p ect ed curr ent co nsu m p t io n. all dev ic es are tes t ed to ope rate at "m in." v alu es w i th an e x t e rna l c l oc k app li ed t o th e osc 1 p i n . whe n an ex ternal cl oc k i npu t is u s ed , th e " m a x ." cy c l e time l i m i t i s " dc" (n o c l oc k ) for all de vic e s .
pic16f84a ds35007b-page 58 ? 2001 microchip technology inc. figure 9-7: clkout and i/o t i m i ng t a ble 9 - 3 : clkout and i/o t i m i ng re q u irem ent s osc1 cl k o u t i /o pi n (i n put ) i/o pin (output) q4 q1 q2 q 3 10 13 14 17 20, 21 22 23 19 18 15 11 12 16 old value new v al ue no te: all tests must be done with specified capacitive loads (figure 9-5) 50 pf on i/o pins and clkout. p aram no . sym c haracteristic m i n t y p? max u n i t s co ndi t ion s 10 t o sh2ck l osc1 - to clk out s t and ard ?1 5 3 0 n s (note 1) 10 a extended (lf) ? 15 120 ns (note 1) 1 1 t o sh2ck h osc1 - to clk out - s t and ard ? 15 30 ns (note 1) 1 1a extended (lf) ? 15 120 ns (note 1) 12 t c kr clkout rise t i me s t and ard ? 15 30 ns (note 1) 12 a extended (lf) ? 15 100 ns (note 1) 13 t c kf clkout f all time s t and ard ? 15 30 ns (note 1) 13 a extended (lf) ? 15 100 ns (note 1) 14 t c kl2iov clkout to p o rt out v ali d ? ? 0.5t cy +20 n s (note 1) 15 t iov 2ckh por t in valid bef ore clk out - s t and ard 0.30t cy + 30 ? ? ns (note 1) extended (lf) 0.30t cy + 80 ? ? ns (note 1) 16 t c kh2ioi por t in hold after clk out - 0? ? n s (note 1) 17 t o sh2iov osc1 - ( q 1 cy cle) to por t out valid s t and ard ? ? 125 ns extended (lf) ? ? 250 ns 18 t o sh2ioi osc1 - ( q 2 cy cle) to port input inv al id (i /o in hold time) s t and ard 1 0 ? ? n s extended (lf) 10 ? ? ns 19 t iov 2osh por t inp ut valid to os c1 - (i /o in set up t i me) s t and ard - 75 ? ? ns extended (lf) -175 ? ? ns 20 t ior por t out put r i s e time s t and ard ? 10 35 ns 20 a extended (lf) ? 10 70 ns 21 t iof por t out put fall ti m e s t and ard ? 10 35 ns 21 a extended (lf) ? 10 70 ns 22 t inp i n t pin high or lo w time s t and ard 2 0 ? ? n s 22 a extended (lf) 55 ? ? ns 23 t rb p rb7:rb 4 ch ange int high or low t i me s t and ard t os c ? ? n s 23 a extended (lf) t os c ? ? n s ? d a t a in "t y p " co lu m n is a t 5 . 0 v , 2 5 c un l e ss o t he rw i se st a t ed . th ese para m e t er s ar e fo r d e si g n gu i d a n ce onl y and ar e n o t t e ste d . b y desi g n. no t e 1 : m e a sur em ents ar e take n i n r c mo de wh e r e c l k o u t ou tpu t is 4 x t os c .
? 2001 microchip technology inc. ds35007b-page 59 pic16f84a figure 9-8: res e t , w a tc hdog t i me r , osci l l ator st art-up t i m e r and p o we r-up ti m e r ti m i n g t able 9 - 4 : res e t , w atc hdog t i me r , osci l l ator st art-up t i m e r and pow e r-up t i me r re q u i r em ent s v dd mclr i nternal po r pw r t t i me-out os c t i m e -out i nternal reset w atchdog t i mer reset 33 32 30 31 34 i /o pi ns 34 par a me ter no . sym c ha racte r istic m in t y p ? ma x u nit s c on dition s 30 t m cl m c lr pul s e wid t h (l ow ) 2 m sv dd = 5. 0v 31 t wd t w a tc hd og t i m e r t i m e - out peri od ( n o pres c a le r) 71 8 3 3 m s v dd = 5. 0v 32 t ost o s c ill ati on s t a rt-up t i m e r peri od 102 4t os c ms t os c = o sc 1 perio d 33 t pw rt pow er -up t i me r per i od 28 7 2 1 32 m s v dd = 5. 0v 34 t io z i/o hi -imp e dan ce from m c lr low or reset 1 0 0 n s ? d a t a in "t y p " co lu mn is at 5 v , 2 5 c , unl es s o t he rw is e s t ate d. the s e p ar ame ters a r e fo r de si gn g ui dan ce onl y a nd are not tes t ed .
pic16f84a ds35007b-page 60 ? 2001 microchip technology inc. figure 9-9: t i m e r0 clock t i mings t a ble 9 - 5 : t i m e r0 clock re quire m e nt s r a 4/t 0ck i 40 41 42 pa r a me ter no . sy m c harac t eris tic m in t y p? m a x u n i t s con ditio ns 40 tt0h t 0c ki h i gh puls e width n o pres c a le r 0 .5t cy + 2 0 ?? n s w i t h p re sc al er 50 30 ? ? ? ? ns ns 2. 0v v dd 3. 0v 3. 0v v dd 6. 0v 41 tt0l t 0c ki l o w pu ls e wid t h n o pres c a le r 0 .5t cy + 2 0 ? ? ns w i t h p re sc al er 50 20 ? ? ? ? ns ns 2. 0v v dd 3. 0v 3. 0v v dd 6. 0v 42 tt0p t0cki pe rio d t cy + 40 n ? ? ns n = pres ca le va lue (2, 4, ..., 2 5 6 ) ? d a t a in " t y p" co lum n is at 5 . 0v , 25 c , unl es s o t he rw ise s t ate d . thes e p a ra me ters are fo r des ig n g u id anc e on ly and are no t tes t e d .
? 2001 microchip technology inc. ds35007b-page 61 pic16f84a 10 .0 dc/ac cha racteristic graphs th e g r aph s prov id ed in t his s ec t ion are for des ign g uida nce an d are no t tes t ed . in s o m e grap hs , th e dat a p r es ent ed are out side s pec ified op eratin g ran ge (i.e ., out sid e sp eci f ie d v dd ran ge) . th is i s fo r info r mati on on ly a nd dev ic es are en su red t o o pera t e p rop erly on ly wi th in the sp eci f ie d ra nge . t he da ta p res en t e d i n t h is s ec t io n i s a s t atistical su mma r y o f da t a c o l l ec te d on un it s fro m d i f f ere n t l o t s ov er a p e rio d o f tim e a nd m atri x s am pl es. t y pi c al re pres en t s t he m ean of th e di st ribu tio n at 2 5 c . m a x o r m in rep res ent s (m ea n + 3 s ) or (m e a n - 3 s ), re sp ec tiv e ly , whe re s is a st and ard dev ia tion ov er t he w h ol e te mp erat ure rang e.
pic16f84a ds35007b-page 62 ? 2001 microchip technology inc. figure 10-1: t y p i cal i dd vs. f os c ov er v dd ( h s mo de , 25 c) fig ure 10- 2: max imu m i dd vs. f os c ov er v dd ( h s mo de , - 40 to +1 25 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4 6 8 10 12 14 16 18 20 f os c (m h z) i dd (m a ) 2.5 v 3.0 v 3.5 v 4.0 v 4.5 v 5.0 v 5.5 v 2.0 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 4 6 8 10 12 14 16 18 20 f os c (m h z) i dd (m a ) 2.5 v 3.0 v 3.5 v 4.0 v 4.5 v 5.0 v 5.5 v 2.0 v
? 2001 microchip technology inc. ds35007b-page 63 pic16f84a figure 10-3: t y p i cal i dd vs. f os c ov er v dd (xt m o de, 25 c) fig ure 10- 4: maximum i dd vs. f osc over v dd (xt mode, -40 to +125c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0 .5 1.0 1 .5 2.0 2 .5 3.0 3 .5 4.0 f os c (m h z) i dd (m a ) 2.0 v 2.5 v 3.0 v 3.5 v 4.0 v 4.5 v 5.0 v 5.5 v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.0 0 .5 1.0 1 .5 2.0 2 .5 3.0 3 .5 4.0 f os c (m h z) i dd (m a ) 2. 0 v 2. 5 v 3. 0 v 3. 5 v 4. 0 v 4. 5 v 5. 0 v 5. 5 v
pic16f84a ds35007b-page 64 ? 2001 microchip technology inc. figure 10-5: t y p i cal i dd vs. f os c over v dd (lp m o de, 25 c) fig ure 10- 6: max imu m i dd vs. f os c over v dd ( l p m o de, - 40 t o + 12 5c) 0 10 20 30 40 50 60 70 80 25 50 75 100 125 150 175 200 f os c (k h z) i dd ( a ) 5.0 v 5. 5 v 4. 0 v 3. 5 v 4. 5 v 3. 0 v 2. 5 v 2. 0 v 0 50 100 150 200 250 25 50 75 100 125 150 175 200 f os c (kh z ) i dd ( a ) 5.0 v 5.5 v 4.0 v 3.5 v 4.5 v 3.0 v 2.5 v 2.0 v
? 2001 microchip technology inc. ds35007b-page 65 pic16f84a figure 10-7: a v e rage f os c v s . v dd for r (rc m o de, c = 22 pf , 2 5 c) figure 10-8: average f osc vs. v dd for r (rc mode, c = 100 pf, 25 c) 0.0 2. 0 4. 0 6. 0 8. 0 10 . 0 12 . 0 14 . 0 16 . 0 2. 0 2. 5 3 . 0 3. 5 4. 0 4 . 5 5. 0 5. 5 v dd (v ) fre q ( m hz ) 5.1 k w 3.3 k w 10 k w 100 k w 0 20 0 40 0 60 0 80 0 10 00 12 00 14 00 16 00 18 00 20 00 2 . 02 . 5 3 . 03 . 5 4 . 0 4 . 55 . 05 . 5 v dd (v ) freq (khz) 100 k w 10 k w 5.1 k w 3. 3 k w
pic16f84a ds35007b-page 66 ? 2001 microchip technology inc. figure 10-9: a v e rage f os c vs . v dd for r (rc m o de, c = 300 pf , 25 c) fig ure 10- 10 : i pd v s . v dd (sle ep m o d e , a l l p e r iph e rals dis able d ) 0 10 0 20 0 30 0 40 0 50 0 60 0 70 0 80 0 90 0 2 . 0 2 . 5 3 . 03 . 54 . 04 . 55 . 05 . 5 v dd (v ) fr eq ( khz ) 3.3 k w 5. 1 k w 10 k w 10 0 k w 0.0 0.1 1.0 10 . 0 2 . 02 . 53 . 03 . 5 4 . 04 . 55 . 05 . 5 v dd (v ) i pd ( a ) max typ typ i c a l : sta t istica l m e a n @ 2 5 c m a x i mum: m ean + 3 s (- 40 c to + 125 c ) m i n i mum: m ean C 3 s ( - 40 c to +12 5 c)
? 2001 microchip technology inc. ds35007b-page 67 pic16f84a figure 10-1 1 : i pd v s . v dd (w dt mode ) fig ure 10- 12 : typical, minimum, and maximum wdt period vs. v dd over temp 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2.0 2 .5 3.0 3 .5 4.0 4 .5 5.0 5 .5 v dd (v ) i pd ( a ) max typ ty p i c a l : sta t istica l m e a n @ 2 5 c m a x i mum: mean + 3 s (-40c to +125c) m i n i mum: m ean C 3 s ( - 40 c to +12 5 c) 0 10 20 30 40 50 60 2. 0 2. 5 3. 0 3. 5 4. 0 4. 5 5. 0 5. 5 v dd (v) w d t p e r i od (m s) ma x min typ typ i c a l : sta t istica l m e a n @ 2 5 c m a x i mum: m ean + 3 s (- 40 c to + 125 c ) m i n i mum: m ean C 3 s ( - 40 c to +12 5 c)
pic16f84a ds35007b-page 68 ? 2001 microchip technology inc. fig ure 10- 13 : t yp ical, m inimu m and max imum v oh vs . i oh (v dd = 5v , - 4 0 c t o +12 5 c) fig ure 10- 14 : t yp ical, m inimu m and max imum v oh vs . i oh (v dd = 3v , - 4 0 c t o +12 5 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 2 .5 5.0 7 .5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 i oh (m a ) v oh (v ) ma typ mi n ty p i c a l : sta t istica l m e a n @ 2 5 c m a x i mum: m ean + 3 s (-40c to +125c) mini mum: m ean C 3 s ( - 40 c to +12 5 c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 i oh (m a ) v oh (v ) max typ min ty p i c a l : sta t istica l m e a n @ 2 5 c m a x i mum: m ean + 3 s (- 40 c to + 125 c ) m i n i mum: m ean C 3 s (-40c to +125c)
? 2001 microchip technology inc. ds35007b-page 69 pic16f84a fig ure 10- 15 : t yp ical, m inimu m and max imum v ol vs . i ol (v dd = 5 v , -40 c to + 1 25 c) figure 10- 16 : t yp ical, m inimu m and max imum v ol vs . i ol (v dd = 3 v , -40 c to + 1 25 c) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 20 25 i ol (m a ) v ol (v ) max ty p min typ i c a l : sta t istica l m e a n @ 2 5 c m a x i mum: m ean + 3 s (- 40 c to + 125 c ) m i n i mum: m ean C 3 s ( - 40 c to +12 5 c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0.0 2 .5 5.0 7 .5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 i ol (m a ) v ol (v ) max typ min ty pic a l : sta t istica l m e a n @ 2 5 c m a x i mum: m ean + 3 s (- 40 c to + 125 c ) m i n i mum: m ean C 3 s ( - 40 c to +12 5 c)
pic16f84a ds35007b-page 70 ? 2001 microchip technology inc. figure 10-17 : m ini m um and m a xim u m v in vs . v dd , (ttl input, -40 c to + 125 c) figure 10-18 : m ini m um and m a xim u m v in vs . v dd ( s t i n pu t, -4 0 c t o + 1 2 5 c) 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.0 2 .5 3.0 3 .5 4.0 4 .5 5.0 5 .5 v dd (v) v in (v ) v th v th v th ty p i c a l : sta t istica l m e a n @ 2 5 c maximum: mean + 3 s (-40c to +125c) minimum: mean C 3 s (-40c to +125c) 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 2.0 2 .5 3.0 3 .5 4.0 4 .5 5.0 5 .5 v dd (v ) v in (v ) v ih max v ih typ v ih min v il max v il typ v il min ty p i c a l : sta t istica l m e a n @ 2 5 c m a x i mum: m ean + 3 s (- 40 c to + 125 c ) m i n i mum: m ean C 3 s ( - 40 c to +12 5 c)
? 2001 microchip technology inc. ds35007b-page 71 pic16f84a 1 1 .0 p a ckaging informatio n 1 1 . 1 packa ge mark ing inf o rmat ion 1 8- lead p d ip x xxx xx xx xx xxx xx xx x xxx xx xx xx xxx xx xx yywwnnn yywwnnn xx xxx xx xx xx x xx xxx xx xx xx x 1 8- lead s o ic e x amp le xx xxx xx xx xx x e x amp le yy wwnnn xx x xxx xx xx x xx xx xxx xx xx 2 0 - lead s s o p e x amp le leg e nd: xx. ..x cus t om er sp eci f ic in form at ion * y y ea r c ode (la s t d i g i t o f c a le nda r ye ar) yy y e a r c ode (la s t 2 di git s o f c a le nda r y ear) ww w eek c ode (w ee k o f j anu ary 1 i s w e ek 0 1) n n n alp ha num eri c t r ac eab ili ty co de note : i n th e ev ent th e ful l mi cro c h i p p art nu mb er ca nno t be m ark ed on o ne l i ne , i t w ill be c arri ed o v er to the n ext l i ne thus lim it ing t he nu mb er of a v ai la ble c ha r ac ters f o r c us t om er s pe c i f ic in f or m at i on . * s t and ard pic m i c ro de vi ce ma rki ng c on s i s t s o f mi cro c h i p p art num be r , y ea r co de, w eek c ode , an d trac ea bil i ty c o d e . f o r pic m i c ro d e v i c e m a rki ng be yon d thi s , c e rt a i n pri c e a dde rs ap ply . pl eas e ch ec k w i th y ou r mi cro c hi p s ale s of fi ce. f or q t p dev ic es , an y sp ec ial ma rki ng a dde rs are inc l u ded in q t p pri c e. pi c16f8 4a- 04 i/p 01 10 017 01 1 001 7 /so pi c 1 6 f 84 a- 04 0 1 100 17 20/ss pic1 6f84 a-
pic16f84a ds35007b-page 72 ? 2001 microchip technology inc. 18- lea d pla s t ic d u a l in- line ( p ) C 30 0 mil ( p dip ) 15 10 5 15 10 5 b m o ld dra ft a n gle b o ttom 15 10 5 15 10 5 a m o ld dr a ft an g l e t o p 10 . 92 9. 40 7. 8 7 .43 0 .3 70 .31 0 eb o v e r a ll ro w sp a cin g 0.5 6 0. 46 0. 3 6 .0 22 .0 18 .01 4 b lo w er le a d w i d t h 1.7 8 1. 46 1. 1 4 .07 0 .0 58 .0 45 b1 u ppe r l ead w i d t h 0.3 8 0. 29 0. 2 0 . 015 .01 2 .00 8 c le ad th i c kn e ss 3.4 3 3. 30 3. 1 8 . 135 .1 30 .1 25 l t i p t o s ea t i ng p l ane 22 .99 22 . 80 22 . 61 . 905 .8 98 .89 0 d o ver al l l eng th 6.6 0 6.3 5 6. 1 0 .26 0 .2 50 .24 0 e1 m o l d ed p a ckag e w i dth 8.2 6 7. 94 7.6 2 . 325 .3 13 .30 0 e s h oul d er to s h ou l d er w i d t h 0. 3 8 .0 15 a1 ba se t o se a t in g pla n e 3.6 8 3. 30 2.9 2 . 145 .1 30 .1 1 5 a2 m o l d ed p a ckag e t h i ck ness 4. 32 3. 94 3. 5 6 .17 0 .15 5 .14 0 a t op to s e ati n g p l an e 2. 54 .1 00 p pit c h 18 18 n n umb er of p i n s ma x nom mi n max nom min d i m en si on li mi t s mi ll i m e t e r s inches* un it s 1 2 d n e1 c eb b e a p a2 l b1 b a a1 * co n t r o llin g pa r a m e te r no te s: d i m en si ons d an d e1 do not in cl u de mol d fl as h o r pr otr u si o n s. mol d fl as h or pr otr u si o n s sh al l n o t e xcee d . 010 ( 0.2 54m m) pe r si d e. je d e c e q ui va l e nt: ms - 001 dr a win g no . c0 4 - 0 0 7 s i gni f i cant ch a r act e ri s t i c
? 2001 microchip technology inc. ds35007b-page 73 pic16f84a 18-lead plastic small outline (so) C wide, 300 mil (soic) fo ot a n gl e f 04 80 48 15 12 0 15 12 0 b m o ld dra ft a n gle b o ttom 15 12 0 15 12 0 a m o ld dr a ft an g l e t o p 0. 51 0. 4 2 0. 3 6 .02 0 .0 17 .01 4 b le ad w i d t h 0.3 0 0. 27 0. 2 3 .0 12 .01 1 .00 9 c le ad th i c k n e s s 1.2 7 0. 84 0.4 1 .05 0 .0 33 .01 6 l fo ot le n g t h 0.7 4 0. 50 0. 25 .02 9 .0 20 .01 0 h c ham fer d i s t a nce 11 . 7 3 11 . 5 3 11 . 3 3 .4 62 .4 54 .44 6 d o v er al l l eng th 7.5 9 7. 49 7. 3 9 .29 9 .29 5 .29 1 e1 m o l d ed p a ckag e w i dth 10 .67 10 . 34 10 . 01 .42 0 .4 07 .39 4 e o v er al l w i dth 0.3 0 0. 20 0. 1 0 .0 12 .0 08 .00 4 a1 s t an doff 2.3 9 2. 3 1 2. 2 4 .09 4 .091 .08 8 a2 m o l d ed p a ckag e t h i c k ness 2.6 4 2. 50 2. 3 6 .10 4 .0 99 .09 3 a o v e r a ll he i g h t 1. 27 .0 50 p pit c h 18 18 n n umb er of p i n s ma x nom mi n ma x nom min d i m en s i on li mi t s mi ll i m e t e r s inches* un it s l b c f h 45 1 2 d p n b e1 e a a2 a1 a * con t r o llin g pa r a m e te r no te s : d i m en si ons d an d e1 do no t i n cl u de mol d fl as h o r p r otr u si o n s. mol d fl as h o r p r otr u si o n s s hal l n o t e xcee d . 010 ( 0.2 54m m) pe r s i d e. j e dec e q u i va l e n t : m s - 0 1 3 dr a win g no . c0 4 - 0 5 1 s i gn i f i cant cha r ac ter i s t i c
pic16f84a ds35007b-page 74 ? 2001 microchip technology inc. 20- lea d pla s t ic s h rink sma ll o u t line ( s s ) C 209 mil, 5 .30 mm ( s s o p ) 10 5 0 10 5 0 b m o l d d r aft a ngl e b o tt om 10 5 0 10 5 0 a m o l d d r aft a ngl e t o p 0. 3 8 0. 32 0.2 5 .0 15 .01 3 .0 10 b le ad w i d t h 2 03. 20 101 .60 0. 00 8 4 0 f f oot a ngl e 0.2 5 0.1 8 0. 10 . 010 .00 7 .0 04 c le ad th i ckne ss 0. 9 4 0. 7 5 0. 56 . 037 .03 0 .022 l f oot le ngt h 7. 3 4 7.2 0 7. 06 . 289 .28 4 .2 78 d ov era l l len gth 5. 3 8 5. 2 5 5. 1 1 .21 2 .20 7 .201 e1 m o l d e d p a c kage w i dth 8. 1 8 7. 8 5 7. 59 .32 2 .30 9 .2 99 e ov e r a ll wid t h 0.2 5 0. 1 5 0.0 5 . 010 .00 6 .002 a1 s t an do f f 1. 8 3 1.7 3 1. 63 .07 2 .06 8 .0 64 a2 m o l d e d p a c kage t h i ckn ess 1. 9 8 1. 8 5 1. 73 . 078 .07 3 .0 68 a ov e r a ll he ig h t 0.6 5 .02 6 p pit c h 20 20 n n um b er of p i n s max nom mi n ma x no m mi n d i me ns i o n l i mi t s m i l l i m eters inches* un its 2 1 d p n b e e1 l c b f a a2 a a1 * co n t r o llin g pa r a m e te r no t e s: d i m e n si o n s d an d e1 do no t i n cl u de mo l d fl a sh o r p r ot rusi o n s. mo l d fl a sh o r p r ot rusi o n s s hal l n o t exce ed . 010 ( 0.2 54 mm ) p er s i de. j e d e c e q ui va l ent : m o -1 50 d r a win g no . c0 4 - 0 7 2 sig n ifica n t ch a r a cte r i stic
? 2001 microchip technology inc. ds35007b-page 75 pic16f84a appendix a: revisio n history v e rsio n d a t e r evi sion desc riptio n a 9/ 98 t h i s is a new d at a sh eet . h ow e ve r , th e d evi ce s d es c ri bed in thi s dat a s hee t are th e u pgra des to the de vi ces fo und in the pic 1 6 f8x d a t a shee t , d s 3 043 0. b 8/01 ad ded d c an d ac c h arac teri st ics g r ap hs and t abl es to s ect ion 10 .
pic16f84a ds35007b-page 76 ? 2001 microchip technology inc. appendix b : conversion co n s iderations c o nsi d e r atio ns fo r c onv erti ng from o n e pic 1 6 x 8x de v ic e t o a n ot h er a re l is t ed in t a b le 1. t a ble 1 : conve r s i on cons ider ations - p i c16 c 84, pic 16f83 /f84, pic 16cr8 3/cr 84, pi c16f84 a difference pic16c84 p i c16f83/f84 p i c 16cr83/ cr8 4 pic16f84a p rogram m e mo ry size 1k x 14 512 x 14 / 1k x 14 512 x 14 / 1k x 14 1k x 14 d a t a mem o ry size 36 x 8 36 x 8 / 6 8 x 8 36 x 8 / 68 x 8 68 x 8 v olt age ran ge 2.0v - 6.0v (-40 c t o +85 c) 2.0v - 6. 0v (- 4 0 c to +85 c) 2. 0v - 6.0v (-40 c t o +85 c) 2.0v - 5. 5v (- 4 0 c to +125 c) m a xim u m operat ing fre- qu ency 10 m hz 10 m hz 10 m hz 20 mh z s upply current ( i dd ). s ee p a ram e ter # d014 in the el ec t ric al spec s f o r m ore det ail. i dd (ty p ) = 60 m a i dd (ma x) = 400 m a (lp osc , f os c = 32 k h z, v dd = 2.0v , w d t disabled) i dd (t yp ) = 1 5 m a i dd (m a x) = 4 5 m a ( l p osc, f os c = 32 kh z, v dd = 2. 0v , w d t di s abled) i dd (t yp) = 15 m a i dd (m ax) = 45 m a (l p o sc, f os c = 32 khz, v dd = 2.0v , w dt disabled) i dd (t yp ) = 1 5 m a i dd (m a x) = 4 5 m a ( l p osc, f os c = 3 2 khz , v dd = 2. 0v , w d t di s abled) p ower-d own cur rent (i pd ). s ee parameters # d 020, d021, and d021a in the electrical s pecs for m ore det ail. i pd (t yp) = 26 m a i pd (m ax) = 100 m a (v dd = 2.0v , w dt disabled, industrial) i pd (t yp ) = 0 . 4 m a i pd ( max ) = 9 m a (v dd = 2.0v , w dt disabled, industrial ) i pd (t yp) = 0. 4 m a i pd (m ax) = 6 m a (v dd = 2.0v , w dt di s abled, industrial) i pd ( t yp ) = 0.4 m a i pd (m a x) = 1 m a (v dd = 2 .0 v , w dt disabled, i n dust r i al) input low v olt age (v il ). s ee p a rameters # d032 an d d034 in the electrical s pecs for m o re det ail. v il (m ax) = 0. 2v dd (osc1, r c m ode) v il (max ) = 0. 1v dd ( o s c1, rc mode) v il (m ax) = 0. 1v dd (osc1, rc m ode) v il (max ) = 0. 1v dd ( o s c1, rc mode) input high v o l t age (v ih ). s ee p a ram e ter # d040 in the el ec t ric al spec s f o r m ore det ail. v ih (m i n) = 0. 36v dd (i /o por t s w i th ttl, 4.5v v dd 5. 5 v ) v ih ( m in) = 2.4v (i /o p o rt s w i t h ttl , 4.5v v dd 5.5v) v ih (m i n) = 2. 4v (i /o p o rts wi t h tt l, 4.5v v dd 5. 5v ) v ih ( m in) = 2.4v (i /o p o rt s w i t h tt l, 4.5v v dd 5.5v) d a t a ee pro m m e mory e rase/w rite cyc le ti m e (t dew ). s ee p a r a met e r # d 122 in t he elect r i c al s pecs for m o re det ail. t de w (t yp ) = 1 0 ms t de w (m a x) = 2 0 ms t de w (t yp) = 10 ms t de w (m ax) = 20 ms t de w ( t yp ) = 10 m s t de w ( max ) = 20 m s t de w (t yp) = 4 ms t de w (m ax) = 8 ms p o rt output rise/f all time (t ior, t i of). s ee parameters #20, 20a , 21 , and 21a in the elec - trical specs for m o re de t ail. t ior, t iof ( m ax) = 25 ns (c84) t ior, t iof ( max) = 60 ns (lc84) t i or , t i o f (max ) = 35 ns ( c84) t i or , t i o f (max ) = 70 ns ( lc84) t ior, t iof (m ax) = 35 ns (c84) t ior, t iof (m ax) = 70 ns (lc84) t i or , t i of ( max ) = 35 ns ( c84) t i or , t i of ( max ) = 70 ns ( lc84) m clr on-chip f ilt er . see parameter #30 in t he elec t r ica l spec s for more de t ail. no y es y es y es por t a and cr yst al os cil - lator values l es s t han 50 0 kh z fo r c rystal os cillat or con- f igurations operati ng below 500 k hz, the device may gener at e a s purious int ernal q-clock when por t a<0> swit c hes st at e. n/ a n / a n / a r b0/i n t pin t t l ttl/ s t* ( * schm i tt t r i g g e r) t t l/ st * (*sc hmitt t rigger) t t l /s t* ( * s chm it t t r i gger )
? 2001 microchip technology inc. ds35007b-page 77 pic16f84a e e a dr<7: 6 > and i dd i t is rec o mm ended that t he ee adr<7:6> bit s be cleared. w hen either of t hes e bit s i s se t , the m a xi- mum i dd for t he device is higher than when bot h are cleared. n/a n/a n/a the polarit y of the pwr t e bit pwrte pwrte pwrte pwrte r e comm ended value of r ex t f or rc oscillat or c i rcuit s r ex t = 3k w - 100k w r ex t = 5k w - 100k w r ex t = 5k w - 100 k w r ex t = 3k w - 100k w gie bit unint entional en abl e i f an int er rupt occ u rs whil e t he global int err upt enable (gi e ) bit is being cleared, the gie bit may unint entionall y be re- enabled by the us er s i nterrupt s ervic e routine (th e retfie ins t ruc t ion). n/ a n / a n / a p a ck ages pdip , soic p d i p , s o i c pdip , soic p d i p , s o i c , s sop open drain high v olt age ( v od ) 14v 12 v 12v 8.5v t able 1 : conve r s i on cons ider ations - p i c16 c 84, pic 16f83 /f84, pic 16cr8 3/cr 84, pi c16f84 a (continue d) difference pic16c84 p i c16f83/f84 p i c 16cr83/ cr 84 pic16f84a
pic16f84a ds35007b-page 78 ? 2001 microchip technology inc. appendix c : migration f r o m basel i n e to mid-ra nge devices th is s ec t io n d i s c u s s es ho w to m i gra t e from a ba se lin e d e v i c e (i .e., pic1 6c5x) to a m i d -ran ge de v i c e (i.e ., pic1 6cxxx). th e fol l ow i ng is t he li st of fe atu re i m p rov em ent s ov er th e pi c 1 6c 5x mi cro c o n trolle r fam i l y : 1 . in str uct ion w ord l eng th is in cre as ed to 14-b i t s . th is al low s l arge r p a ge si ze s, both in pro gra m m e m o ry (2k n o w as op pos ed to 5 12k b e fo re) a nd t he regi ste r fi le ( 128 by tes no w ve rsu s 3 2 by te s b e fo re). 2 . a pc latc h regi ste r (pc la th ) i s a dde d t o ha n- d l e pr ogra m m e m o ry p a g i ng . p a 2 , p a 1 a nd p a 0 b i t s are r e m o ve d fro m th e st a t u s reg i s t er an d p l ac ed in the op tio n re gis t er . 3 . d a t a m e m o ry p agi ng is red e fi ned s lig htl y . th e st a t u s reg i s t er i s mo dified . 4 . fo ur ne w in st ruc t ion s ha ve b een a dde d: retur n , retfie , addlw , an d sublw . t w o in st ru ct i on s , tris an d option, are b ein g p has ed o u t, a l th oug h th ey a re k ept for co mpat i b il it y wi t h p i c 1 6 c 5x . 5 . o p t i on a nd tr is re gis t er s are m ad e ad d res sa bl e . 6. i nt e rrup t c apa bi li t y i s ad d ed . i nt e rrup t v ec t or is a t 00 04h . 7 . s t ac k si ze is in cre ase d t o ei ght -dee p. 8 . reset v e c t o r is c han ged to 000 0h. 9 . reset o f al l reg i s ters is rev i s i ted . fi v e d i f fere n t reset (an d wa k e -up) ty pes a r e re c o gni z e d. r e gis t ers ar e res e t dif f e rently . 1 0 . w a k e - up from sleep thro ugh in terru pt i s a dde d. 1 1 . t w o s epar a t e t i me rs , t h e os ci ll a t or s t a rt -up t i m e r (o st ) and power-u p t i m e r (pw r t ), a re i n c l ud ed fo r mo re rel i ab le p o w e r- up. t hes e ti me rs ar e in vo ked s e l e ct iv ely to a v oi d u nne ce ss ary de lay s on p ow er- up a nd w ake -up . 1 2 . po r t b has w e ak pul l-u p s and in terru pt-on- c han ge fea t ure s . 1 3 . t 0 c ki pi n i s als o a po rt pi n (r a4 /t0c ki ). 1 4 . f s r is a fu ll 8-bi t re gis t er . 1 5. " in sy st em pr ogra m m i n g" is m ad e pos si bl e. th e u s er c an p rogr am pic 1 6c xx de vi ces us ing onl y fi ve pi ns : v dd , v ss , v pp , r b6 ( c lo ck ) a nd r b7 (d at a in/ out ). t o c onv ert co de w ritten fo r pic 1 6 c 5x t o pic 1 6f84a, th e u s er sh oul d t a ke the fo llo w i ng st ep s : 1. r em ov e a ny prog ram me mo ry p age se lec t op era tio ns (p a2, p a 1, p a0 b i t s ) f o r call , goto . 2. r ev i s i t any c omp ute d j um p op era t ion s ( w r i te to pc or add to pc, e tc .) to m a k e s u re p a g e bit s ar e s et p rope rly un der the new sc hem e. 3. el im ina t e any dat a me mo ry p a ge sw i t ch in g. r e d e fi ne dat a v a ria b le s for re all o c a ti on. 4. v e rify al l write s to st a tus, o p tio n, an d fsr re gis t ers s i nc e thes e h a v e c h a nge d. 5. cha nge reset v e c tor to 0 0 0 0h.
? 2001 microchip technology inc. ds35007b-page 79 pic16f84a index a abs o l u te maxim u m rat ings .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 49 ac (timing) characteristics . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 55 arc hit ecture, b lock diagram . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 3 as sembler mp as m ass embler . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 43 b b anki n g , dat a m e mor y . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 6 block diagram s crys t al/ceram i c res onat or operation . . . . . . . . . ... .. .. .. .. .. .. 22 ex t e rnal clock i nput o per at ion .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 22 ex t e rnal power -on re set circuit .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 26 i n ter r upt lo gi c . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 29 on-chip re set . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 24 pic16f84a .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 3 po rt a ra 3:ra 0 p ins . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 15 ra 4 p ins .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 15 po rt b rb 3:rb 0 p ins . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 17 rb 7:rb 4 p ins . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 17 rc o s c ill ator m ode . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 23 t i mer 0 .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 19 t i m e r0/w dt pre scaler . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 20 w a t c hdog timer (w dt) . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 31 c c ( carry) bit .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 clk in p i n .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 4 clkout pin ..... . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 4 code exam ples clearing ra m using i ndirec t addr essing . . . . . ... .. .. .. .. .. .. 11 dat a e e po m wr ite ver i f y . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 14 i ndirec t addr essing . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 11 i niti a l i zing porta . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 15 i niti a l i zing portb . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 17 reading d a t a ee prom . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 14 sav i ng sta t us and w r egi s t er s in ram . . ... .. .. .. .. .. .. 30 w rit ing t o dat a ee prom .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 14 code protecti o n . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. . 2 1 , 33 confi gur at ion bit s . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 21 confi gur at ion w o rd .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 21 conver sion cons iderat ions . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 76 d dat a e e pr om mem o ry .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 13 as sociated regis t e rs .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 14 ee adr register ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 7 , 13 , 25 ee con1 reg i s t e r . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 7 , 13 , 25 ee con2 reg i s t e r . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 7 , 13 , 25 ee data register . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 7 , 13 , 25 w r it e complete e nable ( eeie bit) . . . . . . . . . . . . . . . ... .. .. .. .. .. .. 29 w rit e complete flag (ee i f b i t ) .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 29 dat a ee prom w rite com plet e . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 29 dat a mem o ry . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 6 bank sel e ct ( r p0 bit) . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 6 banki n g .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 6 dc b i t .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 8 dc characteristi c s . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. . 5 1 , 53 developm ent suppor t ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 43 dev ic e ov er vi ew .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 3 e ee con1 re gi s t er ee i f b i t . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 29 electrical characteristics . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 49 load condit ions .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 56 pa ram e ter meas urem ent inf o rm ati o n . . ... .. .. .. .. .. .. .. .. .. .. 56 pic16f84a-0 4 v o l t age-frequenc y g r aph . . . . . . . . . . . . . . . . . 5 0 pic16f84a-2 0 v o l t age-frequenc y g r aph . . . . . . . . . . . . . . . . . 5 0 pic16LF84A- 04 v ol t age-frequenc y g r aph . . . . . . . . . . . . . . . 50 temperature and v olt age spec ifications - a c . . . . . . . . . . . 56 endur ance . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 1 err at a . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 2 ex t e rnal clock i n p u t (ra4/t0cki). see t i mer0 ex t ernal i nterrupt input (rb 0/i nt). se e int e rr upt sour ces ex t e rnal power -on r e set circuit.. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 26 f fi r mware inst r u ct ions . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 35 i i /o por t s .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 15 i c ep ic i n -cir cuit e m ul ator . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 44 i d locations . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 21 , 33 i n - circuit ser i al progr amm ing (icsp ) .. .. .. .. .. ... .. .. .. .. .. .. .. 21 , 33 i n d f register .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 7 i ndire ct addr essing . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 11 fsr regist e r . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 6 , 7 , 11 , 25 i n df register . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. . 7 , 11 , 25 i n s t ru ct ion f o rmat . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 35 i n s t ru ct ion set . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 35 ad d l w .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 37 ad d w f . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 37 an d l w .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 37 an d w f . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 37 bc f . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 37 bs f .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 37 btfs c . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 38 btfs s . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 37 ca ll .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 38 clrf . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 38 clrw .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 38 clrw dt . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 38 com f .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 38 de c f . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 38 de c f sz .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 39 got o .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 39 i n cf .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 39 i n cf sz .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 39 i orlw . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 39 i orwf . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 39 movf .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 40 movlw . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 40 movwf . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 40 nop . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 40 re tfi e .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 40 re tlw .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 40 re turn .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 40 rlf .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 41 rrf . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 41 sl ee p . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 41 su blw .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 41 su bwf .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 41 sw ap f .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 41 xorlw . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 42
pic16f84a ds35007b-page 80 ? 2001 microchip technology inc. x orwf . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 42 sum m ar y table .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 36 i n t i n ter r upt ( r b 0 /i nt) .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 29 i n tcon register . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... 7 , 10 , 20 , 25 , 29 ee i e bi t . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 29 gi e bi t . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 10 , 29 i n te bi t . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 10 , 29 i n tf bit . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 10 , 29 pe i e bi t . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 10 rb ie b i t ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 10 , 29 rb if bi t . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 10 , 17 , 29 t 0 i e b i t . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 10 , 29 t 0 i f bit . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 10 , 20 , 29 i n ter rupt sour ce s.. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 21 , 29 block diagram .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 29 dat a ee prom w rite com plet e . . . . . . ... .. .. .. .. .. .. .. .. .. 29 , 32 i n terrupt-on-ch ange (r b7:rb4) . .. .. ... .. .. .. . 4 , 17 , 29 , 32 rb 0/i n t p in, ex t e rnal ... .. .. .. .. .. .. .. .. .. ... .. .. .. . 4 , 18 , 29 , 32 t m r0 ov er fl ow .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 20 , 29 i n terrupts, context s a ving during . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 30 i n terrupts, e nable b i ts dat a ee prom w r ite com plet e ena bl e (ee i e bit ) . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 29 gl ob al i n terrupt enable ( g i e bit) .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 10 i n terrupt-on-ch ange (r b7:rb4) enable (r bi e b i t) . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 10 peripher al i n t erru pt enable (pe i e b i t) . . . . . . . . . . . . . . . . . ... .... 10 rb0/i n t enable (i n t e b i t) . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 10 t m r0 overfl ow e nabl e (t0i e b i t ) . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 10 i n terrupts, flag b i t s .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 29 dat a ee prom w rite com plet e fl a g (ee i f b i t ) . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 29 i n terrupt-on-ch ange (r b7:rb4) fl ag (r bi f bit ) . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 10 rb0/i n t f lag (int f bit ) .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 10 t m r0 overfl ow flag (t0if bit) . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 10 i r p bit . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 8 k k ee l oq ev al ua t ion a nd p rogram ming t ools . . . . . . . . . . . . . . . ... .. .. 46 m mas t er clear (mclr ) mclr pi n . .. .. .. .. .. .. .. .. .. ... .. .. .. .. ........................................ 4 mclr reset , norm al operat ion . . . . . ... .. .. .. .. .. .. .. .. .. ....... 24 mclr reset , sle e p . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. 24 , 32 mem o ry organization . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 5 dat a e e p r om mem o ry .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 13 dat a mem o r y . .. .. .. .. .. .. ... .. .. .. .. .. .. ............... .. .. .. .. .. .. ... .. .. .. 6 p r o g r am m e mor y . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 5 migration from b aseline to m id-range devices . . . . . . . . . . . ... .... 78 mp lab c17 and mp lab c18 c co mpilers . .. .. .. .. .. .. .. .. ... .. .. 43 mp lab icd in-circ u i t debugger . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 45 mp lab ice high p e rformanc e unive rsal in-circ u i t em ulat or wit h mp lab ide . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 44 mp lab int egr ated developm ent env i r onment so ft ware ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. 43 mp link object l i nk er/ m plib object librarian . . . . . . . . . . . ... .... 44 o opcode fiel d desc ript ions . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. 35 opti on register . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 9 i n tedg b i t .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 9 ps 2: ps 0 b i t s . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 9 ps a b i t .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 9 rbp u bit . . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 9 t0cs b i t .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 9 t0se bit .......... .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 9 opti on_re g regis t e r . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. . 7 , 18 , 20 , 25 i n tedg bi t .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 29 ps 2: ps 0 b i ts . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 19 ps a b i t .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 19 os c1 p i n . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 4 os c2 p i n . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 4 oscillat or configurat ion .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 21 , 22 block diagra m . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 22 , 23 capacitor selecti o n for ce ramic resona t o rs .. .. .. .. .. .. .. 22 capacitor selecti o n for cr ystal osc i llator .. .. ... .. .. .. .. .. .. 23 crys t al oscillat or/ceram ic r e sonators . . . . . . . . ... .. .. .. .. .. .. 22 hs . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 22 , 28 lp . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 22 , 28 oscillat or types . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 22 rc ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 22 , 23 , 28 xt . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 22 , 28 p pac kaging information .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 71 ma rk ing .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 71 pd b i t .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 8 picdem 1 low cost p i cm icro dem onst ration board . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 45 picdem 17 dem onstrat ion boar d . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 46 picdem 2 low cost p i c16 cxx dem onst r at ion board . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 45 picdem 3 low cost p i c16 cxx x dem onst r at ion board . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 46 picsta rt plus entry leve l developm ent pro gr am mer . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 45 pinout des cripti o n s .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 4 pointer, fsr . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 11 po r. se e p ower-on rese t porta . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. 4 , 15 as sociated regis t e rs .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 16 func ti ons . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 16 i nitial iz ing . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 15 porta register ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. . 7 , 15 , 16 , 25 ra 3:ra0 bl ock di a g ra m . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 15 ra 4 b lock d i agram .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 15 ra 4/t0ck i pin . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 4 , 15 , 19 tri s a regist e r . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. . 7 , 15 , 16 , 20 , 25 portb . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. 4 , 17 as sociated regis t e rs .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 18 func ti ons . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 18 i nitial iz ing . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 17 portb register ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. . 7 , 17 , 18 , 25 pull-up enable bit (rb pu b i t) . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 9 rb0/int edge selec t (i nte d g b i t) .. .. .. .. .. .. ... .. .. .. .. .. .. .. 9 rb0/int pin, e x t e rnal. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 4 , 18 , 29 rb 3:rb0 bl ock di a g r a m . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 17 rb 7:rb4 bl ock di a g r a m . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 17 rb7:rb 4 int e rr upt -on - change .. .. .. .. .. .. .. .. .. .. ... . 4 , 17 , 29 rb7:rb 4 int err upt -on - change enable (rb i e bit) . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 10 rb7:rb 4 int err upt -on -change flag ( r bi f bit ) .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. 10 , 17 tri s b regist e r . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. . 7 , 17 , 18 , 25 pos t s c aler, w d t as signment ( ps a bit ) . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 9 rate sel e ct ( ps 2: ps 0 b i ts ) .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 9 pos t s caler. see pr escaler powe r-down (pd ) bit. see power-on reset (por) power-down mode. see sleep
? 2001 microchip technology inc. ds35007b-page 81 pic16f84a power -on r e set (p o r ) . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 21 , 24 , 26 oscillat or start-up t i m e r (os t ) . .. .. .. .. .. .. .. .. .. ... .. .. . 2 1 , 26 pd b i t . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. 8 , 24 , 28 , 32 , 33 power -up timer (p w r t) .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. . 2 1 , 26 t i m e -out s equence . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 28 t i m e -out s equence on p ower-up . . . . . . . . . . . . . . . . ... .. .. . 2 7 , 28 to b i t . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 8 , 24 , 28 , 30 , 32 , 33 pres c aler .. .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 19 as signment ( psa b i t ) . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 19 block diagram .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 20 rat e s e l e ct ( p s 2: ps 0 b i ts ) .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 19 switching p r esc aler a ssignm ent .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 20 presc aler, timer0 as signment ( psa b i t ) . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 9 rat e se l e ct ( ps 2: ps 0 b i ts ) .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 9 pro ma t e ii univers al dev i c e p rogram mer . . . . . . ... .. .. .. .. .. .. 45 prog ram counter . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 11 pcl register . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 7 , 11 , 25 pcla th register . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 7 , 11 , 25 reset co ndi tions ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 24 pro g ram m e mor y . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 5 general p u rpose registers . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 6 i n ter rupt vec tor .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. . 5 , 29 re se t vec tor .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 5 spec i al funct ion registers . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. . 6 , 7 prog ramm ing, device i n s t ruc t ions .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 35 r ram . see data m emory register file . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 6 register file m a p . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 6 registers confi gur at ion w o rd . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 21 ee con1 (e ep rom control) .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 13 i n tcon . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 10 op ti on . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 9 sta tus . .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 8 res et . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. . 2 1 , 24 block diagram .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. . 2 4 , 26 mclr reset. see mclr power -on r e set (p o r ). see powe r-on reset (p or) reset co ndi tions f o r all r egi s t er s . .. .. .. .. .. .. .. ... .. .. .. .. .. .. 25 reset co ndi tions f o r pr ogram counter .. .. .. .. ... .. .. .. .. .. .. 24 reset co ndi tions f o r sta t us reg i s t e r . .. .. .. ... .. .. .. .. .. .. 24 w d t res et . se e w a tchdog t i m e r ( w dt ) revision history . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 75 rp1:rp0 (b ank select) b i ts .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 8 s sav i ng w r egi s t er and status in r a m . . . . . . . . . . . . ... .. .. .. .. .. .. 30 s l ee p .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. . 2 1 , 24 , 29 , 32 soft war e s i m ulat or (m pla b sim) . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 44 speci al feat ur es of the c pu . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 21 spec i al funct ion registers . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. . 6 , 7 speed, oper at ing . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. . 1 , 22 , 23 , 57 stac k . .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. 11 status register . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. . 7 , 8 , 25 , 30 c bit . .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 8 dc b i t . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 8 pd b i t . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. 8 , 24 , 28 , 32 , 33 res e t c ondit ions .. .. .. .. .. ............................................ 24 rp0 bit.......................................................................... 6 to b i t . .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. 8 , 24 , 28 , 30 , 32 , 33 z b i t .. .. .. ...... .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 8 t ti me -o u t (to ) bit. see power- on res et (por) ti mer 0 . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .................. .. 19 as sociated regis t e rs .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 20 block diagra m .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 19 clock sou rce edge select ( t 0s e bit) . ... .. .. .. .. .. .. .. .. .. ... . 9 clock sou rce select (t0cs b i t ) .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 9 overflow e nable (t0ie bit ) .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 10 , 29 overflow flag ( t 0if b i t) . ... .. .. .. .. .. .. .. .. .. ... .. .. .. . 1 0 , 20 , 29 overflow int e r rupt . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 20 , 29 pr escaler. se e p resc aler ra4/t0cki p in, external clock . .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 19 tmr0 register . .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. . 7 , 20 , 25 ti m ing cond i t ions . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 56 ti m ing diagra ms clkout and i/ o . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 58 diagram s an d s pecif ications . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. .. 57 clkout and i/ o requirem ent s . . ... .. .. .. .. .. .. .. .. .. .. 58 ex t e rnal clock requirem ent s . . . . . . ... .. .. .. .. .. .. .. .. .. .. 57 res et, w atchdog t im er, oscillat or s t art-up ti m e r and p ower-up ti m e r requiremen t s .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 59 ti m e r0 clock requirem ent s . . . . . . . . ... .. .. .. .. .. .. .. .. .. .. 60 ex t e rnal clock . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 57 res et, w atchdog t im er, oscillat or start-up ti m e r and p ower-up ti m e r . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. .. 59 ti m e -out s equence on p ower-u p . . . . . . . . ... .. .. .. .. .. .. .. 27 , 28 ti m e r0 clock . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 60 w a ke-up from sle ep through int e rr upt .. .. .. .. .. .. .. .. .. 32 ti m ing p a ram e t e r sy mbology ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 55 to bit . .. .. .. .. .. .. .. .. ... .. .. ................... .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 8 w w regis t e r . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 25 , 30 wak e -up fr om s l ee p. .. .. .. .. .. .. ... .. .. .. .. .. .. .. . 2 1 , 26 , 28 , 29 , 32 i n ter rupts . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 32 , 33 mcl r reset . .. .. .. .. ....... . .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 32 wdt reset ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 32 w a t c hdog timer (w dt) . . . . . . . . . . ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 21 , 30 block diagra m .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 31 pos t s c aler. see pr escaler pr ogramm ing cons iderat ions .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 31 rc o s cill a t or .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 30 time- out per iod .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 30 wdt reset , norm al operat ion .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. .. 24 wdt reset , sle e p . .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. 24 , 32 www, o n -line s uppor t . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 2 z z (zer o) bit . .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... .. .. .. .. .. .. .. .. .. ... . 8
pic16f84a ds35007b-page 82 ? 2001 microchip technology inc. notes :
? 2001 microchip technology inc. ds35007b-page 83 pic16f84a on- l ine suppo rt mi cr o c h i p p r o v id es on - l in e s up p or t on th e m ic r oc h ip w o rl d wi de w e b (w ww) s i t e . the web si te is us ed b y m i c r oc hip as a me ans to m ak e fi le s an d inf o rm atio n ea si ly a v a ila ble t o cu sto m e rs. t o v i e w t he s i te , the use r mu st h av e ac ce ss to th e in tern et a nd a w eb brow s er , s uc h as n et s ca pe ? or m i c ros oft ? ex pl orer . fi les a re als o av ail a b l e for ftp dow n l oa d fro m our ftp s i te . co nn ect i ng t o t h e mi cr o c hi p int e rnet w e b sit e the m i crochip w e b site is availab le by u s ing your f a v o r i te in tern et brows e r t o at t a c h to : w w w .m icroc hip.c om th e fil e tran sfe r sit e is a v a ila ble b y us in g an ftp s er- v i c e to co nn ect to: ftp:/ /ftp.m icroc hip.c om the w eb s i te and file t r ansf er site pr ovide a variet y o f services. u s er s may dow nload files f o r t he late st d e vel opmen t t o ol s, d a t a she e t s , app l i c at ion n o tes , us er' s g u ide s , artic le s a nd sam p le program s . a v a ri- et y of m ic roc hi p sp ec if i c b u s i ne s s i nf o rm a t i o n i s a l so a v ai la ble , i nc l ud ing li st ing s of mi croc hi p s al es of fi ces , d i s t ributors an d fac t o ry rep res en t a ti ve s. o t h e r da t a a v ai la ble for co nsi de ratio n i s : ? l ates t m i c roc hi p pre ss re l eas es ? t ec hni ca l su ppo rt se cti on w i th frequen tly ask e d q u e s ti ons ? d es ig n t i p s ? d ev ic e errat a ? j ob pos t in gs ? m i c ro ch i p co ns ul ta nt p ro g ra m me mb er l i st in g ? l ink s to o t he r us efu l web si tes re lated t o m i c roc hip prod u c t s ? c on ferenc es fo r p rod uc t s , d e v e l opmen t sys t em s, te ch nic al in form ati on and mo re ? l ist i ng of se mi nars an d e v e nt s s y stems inf o r m ation and upgr a d e hot line th e sy st em s i nfo rma t ion an d u p grad e l i ne pr ovi de s s y s t em us ers a l i s t in g of th e lat es t v ers io ns o f all of m i c roc hip ' s d ev elo pm ent s y s t em s so ftw are pro du c t s . pl us, thi s l i n e pro v i des i n form at ion on how c u s t om er s c an re ce iv e an y c urren t ly av ail abl e up gra de k i t s .th e h ot li ne n u mb ers are : 1- 800 -755-23 45 f o r u . s. and m o st of c a na da, and 1- 480 -792-73 02 f o r th e re st of th e w o rld. 013001
pic16f84a ds35007b-page 84 ? 2001 microchip technology inc. reader respo n s e it is ou r in ten t io n to pro v i de you w i t h th e b es t do cu me nt a t ion po ss ib le to e ns ure suc c es s fu l u s e of y ou r m i c roc hip pro d- u c t. if yo u w i sh to prov id e y ou r c om m en t s on org ani za tio n, c l a rity , su bj ect m atte r , a nd w ays i n w h ic h o ur d oc um ent a t io n c an bet ter s erv e y ou , pl eas e f ax y our co mm ent s t o th e t ec hni ca l pu bli c a t io ns ma nag er a t (48 0) 7 92-4 15 0. pl eas e l i s t th e fo llo w i ng in form ati o n , an d u s e this o u tli n e to p rov id e us wi t h y our co mm ent s a b o u t th is da t a she e t. 1. w h a t ar e t h e be st f e at u res of t h i s d o c u me nt ? 2 . h o w d oes th is doc um en t m eet yo ur h a rdw a re a nd s o f t w a re dev el opmen t ne eds ? 3 . do y o u fin d th e o rgan iz ati on of th is da t a s h e e t e a s y to fo llo w? if not , why ? 4 . wh at a ddi tio ns to t he d at a sh ee t do yo u th in k w o uld en han ce the str uct ure and su bje c t ? 5 . wh at d ele tio ns from th e da t a sh eet cou l d be ma de w i tho ut a f fe ct ing the ov era ll u s e f ul nes s? 6 . is the re a n y inc o rre ct or m i s l e adi ng inform ation (w h a t a nd w here)? 7 . h ow wo uld yo u i m p rov e th is doc um en t? 8 . h ow wo uld yo u i m p rov e ou r s oftw a re, s y s t e m s , an d s i l i c on p rod uct s ? to : t e c hni ca l pu bli c a t ions manager re: reader response total pages sent from: name company address city / st ate / zi p / cou n try t e l eph one : (__ ___ __ ) __ ___ ___ _ - _ ___ __ ___ appl ic ati on (o pti ona l): w o uld yo u l i k e a repl y? y n d e vi ce : li tera ture n u m ber: qu es tion s: fax: (______) _________ - _________ ds35007b pic16f84a
2001 microchip technology inc. ds35007b-page85 pic16f84a pic1 6 f 84 a pr o du ct i d entificat i o n system to order or o bt ain i nform at ion (e. g., on pricing or delivery ) r ef er t o the factory or the l isted sales of fi c e. s a les and s uppor t dat a sheet s prod u ct s s upported by a preli m inary dat a s heet may hav e an errat a s heet desc ribing m i n o r oper at ional dif f e renc es and r e com- mended work arounds. t o determ ine if an errat a s heet exist s f or a p art ic ul ar dev i c e, please cont act one of t he f ollowing: 1. y our local m i croc h i p sales of fice 2. t h e m i c rochip corporate l i terature c ent er u.s. f a x: (480) 792-72 77 3. t h e m i c rochip w o r l dw i de site ( www .micr o chip. c o m) please spec if y which device, r e vision of sil i c on and dat a s heet (include li terature #) y ou are using. new customer noti f i cation syst em register on our web sit e (www . m i c rochip.com / cn) to rec eive t he mos t current inform a t ion on our produc t s . device pic16f84a (1) , pic16f84at (2) pic16LF84A (1) , p i c1 6lf 84a t (2 ) frequ ency range 04 = 4 m h z 20 = 20 m h z t e mper at ure r ange -= 0c t o +70 c i = -40c t o +85c pa cka g e p = pd i p so = s oic (gull w ing, 300 mil body ) ss = s so p p att ern q t p , s q t p , rom code (fact o ry specifi ed) or spec i al requirem ent s . b lank f or ot p a nd w i n dowed dev ices. e xampl es: a) p i c16 f 84a -0 4/ p 301 = com mer c ial temp., pd i p p a c k age, 4 m hz , normal v dd limit s, qtp p at t ern #301. b) p i c16 lf 84a - 04i/ s o = industrial temp., s o i c p ack age, 200 khz, e x tended v dd limit s. c ) p i c16 f 84a - 20i/ p = i ndus t r ial temp . , p d ip p a ckag e , 20 m h z, norma l v dd limit s. no t e 1 : f = s t andard v dd range lf = ex t ended v dd range 2: t = in t ape an d reel - s o i c and ss o p p a ckag e s on l y . part no. -xx x /xx xxx pattern p ackage t emperature rang e frequ e ncy range devi ce
ds3500 7b-page 86 ? 2001 mic r ochip t e c hnology i n c. m americas corp orate offi ce 23 55 w e st c h and l e r b l vd. c ha ndl e r , a z 85 22 4-6 199 t el : 48 0-7 92- 72 00 fa x: 4 80 - 79 2-7 27 7 t e ch ni ca l s upp ort : 48 0- 792 -7 627 w eb a ddr ess: http ://w w w . m i cro chi p .com rocky m o unt ain 23 55 w e st c h and l e r b l vd. c ha ndl e r , a z 85 22 4-6 199 t el : 48 0-7 92- 79 66 fa x: 4 80 - 79 2-7 45 6 atlan t a 5 0 0 su g a r m ill ro a d , su ite 2 0 0 b a t l a n t a, ga 3 035 0 t el : 770 -6 40- 003 4 fa x: 77 0- 640 -03 07 austi n - analo g 13 740 no r t h h i g h w a y 18 3 bu ildin g j, s u ite 4 a u sti n , t x 78 750 t el : 512 -2 57- 337 0 fa x: 51 2- 257 -85 26 boston 2 l an d r i ve , s ui t e 12 0 w e stf o rd , m a 01 886 t el : 978 -6 92- 384 8 fa x: 97 8- 692 -38 21 bost on - a n alog un it a - 8 - 1 m i l l b r o o k t a r r y co n d o m in iu m 97 low el l roa d c o n cord , m a 01 74 2 t el : 978 -3 71- 640 0 fa x: 97 8- 371 -00 50 chi cago 33 3 pi er ce r o ad , su i t e 18 0 it a sca, il 601 43 t el : 630 -2 85- 007 1 f ax: 63 0-2 85 - 00 75 dal las 45 70 w e stgr ove dr i ve , s u i t e 1 6 0 a ddi so n, tx 7 500 1 t el : 972 -8 18- 742 3 fa x: 97 2- 818 -29 24 dayton t w o p r es ti ge p l a ce, s u i t e 130 mi a m i sb urg , oh 453 42 t el : 937 -2 91- 165 4 fa x: 93 7- 291 -91 75 detroi t t r i- atr i a of fic e bu ild in g 32 255 nor t hw e ster n h i g hw a y , s ui t e 190 fa rm i ngt on h i l l s, mi 48 334 t el : 248 -5 38- 225 0 f ax: 24 8-5 38 - 22 60 l o s ang e les 18 201 v on k a rm an, s ui t e 109 0 irvin e , ca 92 612 t el : 949 -2 63- 188 8 fa x: 94 9- 263 -13 38 new y o r k 15 0 m oto r p ar kw ay , s u i t e 2 02 h a u ppaug e, n y 1 1 7 8 8 t el : 631 -2 73- 530 5 fa x: 63 1- 273 -53 35 san j o se mi cr och i p t e chno l o g y inc . 21 07 n ort h f i rst s t re et, s u i t e 5 90 s an jose , c a 9 513 1 t el : 408 -4 36- 795 0 fa x: 40 8- 436 -79 55 t o ront o 62 85 n ort ham dr i ve , s ui t e 1 08 mi ssi s saug a, ontari o l4 v 1x 5, c ana da t el : 905 -6 73- 069 9 fa x: 9 05- 67 3-6 509 asia/p acific australi a m i c r oc hi p t e chn o l o g y a u s t ral i a p t y l t d s ui t e 22 , 41 raw son s t re et e pp i ng 212 1, n s w au st r a lia t e l : 61 -2- 98 68- 673 3 f ax : 61 -2- 98 68- 67 55 chi n a - be i j i n g m i c r oc hi p t echn ol og y c o nsul t i ng ( s han gh ai ) co . , l t d . , be ijin g l i a i so n o f fice un it 9 1 5 be i ha i w a n t a i bld g . n o. 6 c h ao yan gme n b e i daj i e be ijin g , 1 0 0 0 2 7 , no . ch in a t e l : 86 -10 - 8 528 210 0 f ax : 86 -10 - 8 528 210 4 chi n a - chengd u m i c r oc hi p t echn ol og y c o nsul t i ng ( s han gh ai ) c o . , ltd., ch e ngd u l i ai son of f i ce r m . 24 01 , 24 th f l oo r , m i n g x i n g f i nan ci al t o w e r no . 8 8 t i du s t r e e t c he ng du 610 016 , c h i na t e l : 86 -28 - 6 766 200 f a x: 86- 28 -67 6 6 599 chi n a - fuz hou m i c r oc hi p t echn ol og y c o nsul t i ng ( s han gh ai ) c o ., l t d . , f u zh ou li ai so n o f fi ce rm . 5 3 1 , no r t h bu ild in g f uj i an fo re i g n t r a de c ent er h ote l 73 w u si r oad f u zh ou 3 5 0 001 , c h i n a t e l : 86 -59 1- 755 756 3 fa x: 86 -5 91- 75 575 72 chi n a - s h anghai m i c r oc hi p t echn ol og y c o nsul t i ng ( s han gh ai ) c o . , ltd. r o o m 701 , bl dg . b fa r e as t in t e rn at i o na l p l a za n o. 31 7 x i an x i a r o ad s ha ngh ai , 2 00 051 t e l : 86 -21 - 6 275 -57 00 f ax: 8 6- 21- 62 75- 506 0 chi n a - s h enz h en m i c r oc hi p t echn ol og y c o nsul t i ng ( s han gh ai ) c o . , ltd., s hen zhe n l i ai son of f i c e r m . 13 15 , 13 /f , sh enzh e n k e rr y c e ntr e , r en m i n nan lu s h e n zh en 5 1 8 001 , c h i n a t e l : 86 -75 5- 235 036 1 fa x: 86 -7 55- 23 660 86 ho n g ko n g m i c r oc hi p t e chn o l o g y ho ngko n g ltd. u n i t 90 1-6 , t o w e r 2, m e tr op l a za 22 3 h i n g f on g r o ad k w ai f o n g , n . t ., h ong k ong t e l : 85 2-2 40 1-1 200 f ax: 852 -2 401 -3 431 in dia m i c r oc hi p t e chn o l o g y in c. in di a li ai so n o f fi ce divya sre e ch amb e r s 1 f l oo r , w i ng a (a 3 / a 4 ) no. 1 1 , osha ugn esse y roa d b an gal o r e , 56 0 0 25, ind i a t e l : 91 -80 - 2 290 061 f ax: 91- 80- 22 900 62 jap an m i cro chi p t e ch nol o g y j apan k . k . b e nex s - 1 6 f 3 - 18 -2 0, s h i nyok oha ma k o h o ku- k u , y o ko ha m a - shi k a nag aw a , 22 2-0 0 3 3 , ja p a n t e l : 8 1-4 5-4 71 - 6 166 f ax: 81- 45- 47 1-6 12 2 korea m i cro chi p t e ch nol o g y k o rea 1 68- 1, y ou ng bo b l d g. 3 f l oor s a msu ng- d on g, k a ngn am -k u s e oul , k o re a 1 35- 88 2 t e l : 8 2-2 -55 4- 720 0 fax : 82 -2 -55 8-5 93 4 si ngap o re m i cro chi p t e ch nol o g y si n gap or e pt e lt d . 2 00 mi dd l e r o ad # 07- 02 p r i m e c e ntre s i ng ap ore , 1 889 80 t e l : 65 - 3 3 4 - 8 87 0 fa x: 65 -3 3 4 - 8 85 0 t a iwan m i cro chi p t e ch nol o g y t a i w a n 11 f - 3 , n o . 2 0 7 t un g h u a n o rth r oad t a ip e i , 1 0 5 , t a iwa n t e l : 8 86- 2-2 71 7-7 17 5 f ax: 88 6-2 - 25 45 -01 39 euro pe denmark m i cro chi p t e ch nol o g y d e nm ar k ap s re gu s busine ss ce ntr e l aut rup ho j 1- 3 b a l l e r u p d k -2 75 0 d e nma r k t e l : 4 5 44 20 98 95 fax : 45 44 20 991 0 france a r i z ona mi c r och i p t e chn o l o g y s a r l p a rc d a c tivite d u m o u lin d e m a ssy 43 rue du s a ul e t r ap u ba t i m e n t a - le r et a g e 9 130 0 m ass y , fr anc e t el : 33 - 1- 6 9- 53 - 63 - 2 0 f ax : 33 - 1- 6 9- 30 - 90 - 7 9 germany a r i z ona mi c r och i p t e chn o l o g y gm bh g u stav-h e i ne man n ri n g 1 2 5 d - 81 739 mu ni ch , ge rm any t e l : 4 9-8 9-6 27 - 14 4 0 f ax: 49- 89- 62 7-1 44 - 44 germany - a n alog l o ch ham er s t ra sse 13 d - 82 152 ma rti n sri ed , g erm an y t e l : 4 9-8 9-8 95 650 -0 fa x: 4 9- 89- 895 65 0-2 2 it aly a r i z ona mi c r och i p t e chn o l o g y s r l ce n t r o dir e zio n a le co lleo n i p a l a zzo t a u r us 1 v . le c o l l e oni 1 2 004 1 a g rat e b r i a nza m i l an, it a l y t e l : 3 9-0 39- 65 791 -1 fa x: 3 9- 039 -68 99 883 unit ed kin gdom a r i z ona mi c r och i p t e chn o l o g y ltd. 50 5 e skd al e r o ad w i n ner sh t r i a ngl e w o ki ngh am b e rksh i r e, e ngl a nd r g 41 5t u t e l : 4 4 1 1 8 92 1 5 86 9 f ax: 44- 1 18 92 1-5 820 08/0 1 /01 w orldwide s ales and s ervice

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