 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LTC4265 1 4265fa typical application description ieee 802.3at high power pd interface controller with 2-event classi cation recognition the ltc ? 4265 is a 3rd generation powered device (pd) interface controller intended for ieee 802.3at high power power-over-ethernet (poe) applications up to 25.5w. by supporting 1-event and 2-event classi? cation signaling as de? ned by ieee 802.3, the LTC4265 can be used in a wide range of product con? gurations. a 100v mosfet isolates the dc/dc converter during detection and classi? cation, and provides 100ma inrush current for a smooth power- up transition. the LTC4265 also includes complementary power good outputs, an on-board signature resistor, undervoltage/overvoltage lockout and comprehensive thermal protection. all linear technology pd solutions include a shutdown pin with signature corrupt to provide ? exible auxiliary power options. the LTC4265 pd interface controller can be used along with a variety of dc/dc converter products to provide a complete, cost effective power solution for high power pd applications. the LTC4265 is available in the space-saving low pro? le (4mm 3mm) dfn package and is drop-in compatible with the ltc4264. turn-on vs time l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. features applications n ieee 802.3af/at powered device (pd) controller n ieee 802.3at 2-event classi? cation signaling n programmable classi? cation current n flexible auxiliary power support using shdn pin n rugged 100v onboard mosfet with 100ma inrush current limit. n complementary power good outputs n onboard signature resistor n comprehensive thermal protection n undervoltage and overvoltage lockout n 12-lead, 4mm 3mm dfn package n 802.11n access points n high power voip video phones n rfid reader systems n ptz security cameras and surveillance equipment gnd r class shdn r class 54v from data pair 54v from spare pair 0.1f pwrgd pwrgd LTC4265 t2pse v + run 5f min 3.3v to logic rtn switching power supply v in v out 4265 ta01a + C + ~ ~ + C ~ ~ + C to logic to aux gnd C v in 50v/div gnd C v out 50v/div pwrgd C v out 50v/div i pd 100ma/div time 25ms/div 4265 ta01b c load = 100f
LTC4265 2 4265fa pin configuration absolute maximum ratings gnd voltage ............................................ C0.3v to 100v v out voltage ........................C0.3v to 100v (and gnd) v out pull-up current ..................................................1a shdn ....................................................... C0.3v to 100v r class , voltage ............................................ C0.3v to 7v r class current .......................................................50ma pwrgd voltage (note 4) low impedance source .....v out C 0.3v to v out +11v pull-up current ....................................................5ma pwrgd , t2pse voltage ........................... C0.3v to 100v pwrgd , t2pse pull-up current ............................10ma junction temperature ........................................... 125c operating ambient temperature range LTC4265c ................................................ 0c to 70c LTC4265i.............................................. C40c to 85c (notes 1, 2, 3) 12 11 10 9 8 7 13 1 2 3 4 5 6 gnd nc pwrgd pwrgd v out v out shdn t2pse r class nc v in v in top view de package 12-lead (4mm s 3mm) plastic dfn t jmax = 125c, ja = 43c/w exposed pad (pin 13) to be soldered to pcb heat sink order information lead free finish tape and reel part marking* package description temperature range LTC4265cde#pbf LTC4265cde#trpbf 4265 12-lead (4mm 3mm) plastic dfn 0c to 70c LTC4265ide#pbf LTC4265ide#trpbf 4265 12-lead (4mm 3mm) plastic dfn C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ LTC4265 3 4265fa electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to v in pin unless otherwise noted. note 3: pins with 100v absolute maximum guaranteed for t 0oc, otherwise 90v. note 4: pwrgd voltage clamps at 14v with respect to v out . note 5: input voltage speci? cations are de? ned with respect to LTC4265 pins and meet ieee 802.3af/at speci? cations when the input diode bridge is included. the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. note 6: signature resistance is measured via the v/ i method with a minimum v of 1v. the LTC4265 signature resistance accounts for the additional series resistance in the input diode bridge. note 7: an invalid signature after the 1st classi? cation event is mandated by ieee 802.3at standard. see applications information. note 8: class accuracy is with respect to the ideal current de? ned as 1.237/r class and does not include variations in r class resistance. note 9: this parameter is assured by design and wafer level testing. parameter conditions min typ max units operating input voltage signature range classi? cation range turn-on voltage undervoltage lock out overvoltage lock out at gnd pin (note 5) l l l l 1.5 12.5 30.0 71 60 9.8 21 37.2 v v v v v v on/uvlo hysteresis window l 4.1 v signature/class hysteresis window l 1.4 v reset threshold state machine reset for 2-event classi? cation l 2.57 5.40 v supply current supply current at 60v measured at gnd pin l 1.35 ma class 0 current gnd = 17.5v, no r class resistor l 0.40 ma signature signature resistance 1.5v gnd 9.8v (note 6) l 23.25 26 k invalid signature resistance, shdn invoked 1.5v gnd 9.8v, v shdn = 3v (note 6) l 11 k invalid signature resistance during mark event (notes 6, 7) l 11 k classification class accuracy 10ma < i class < 40ma, 12.5v < gnd < 21v (note 8, 9) l 3.5 % classi? cation stability time gnd pin step to 17.5v, r class = 30.9, i class within 3.5% of ideal value (notes 8, 9) l 1ms normal operation inrush current gnd = 54, v out = 3v l 60 100 180 ma power fet on resistance tested at 600ma into v out , gnd = 54v l 0.70 1.0 power fet leakage current at v out gnd = shdn = v out = 57v l 1a digital interface shdn input high level voltage l 3v shdn input low level voltage l 0.45 v shdn input resistance gnd = 9.8v, shdn = 9.65v l 100 k pwrgd , t2pse voltage output low tested at 1ma, gnd = 54v. for t2pse , must complete 2-event classi? cation to see active low. l 0.15 v pwrgd , t2pse leakage current pin voltage pulled 57v, gnd = v in = 0 l 1a pwrgd voltage output low tested at 0.5ma, gnd = 52v, v out = 48v, output voltage is with respect to v out l 0.4 v pwrgd voltage clamp tested at 2ma, v out = 0v, voltage with respect to v out l 12 16.5 v pwrgd leakage current v pwrgd = 11v, v out = v in = 0v, gnd = 54v l 1a LTC4265 4 4265fa typical performance characteristics input current vs input voltage 25k detection range input current vs input voltage input current vs input voltage gnd voltage (v) 0 0 input current (ma) 0.1 0.2 0.3 0.4 0.5 2 468 4265 g01 10 t a = 25c gnd voltage (v) (rising) 0 0 input current (ma) 10 20 30 40 50 10 20 30 40 4265 g02 50 60 t a = 25c class 4 class 3 class 2 class 1 class 0 gnd voltage (v) 12 9.5 input current (ma) 10.5 14 16 4265 g03 10.0 18 20 22 11.0 85c C40c class 1 operation signature resistance vs input voltage pwrgd , t2pse output low voltage vs current active high pwrgd output low voltage vs current inrush current vs input voltage current (ma) 0 v pwrgd (v) v t2pse (v) 0.4 0.6 8 4265 g07 0.2 0 2 4 6 10 0.8 t a = 25c current (ma) 0 0 pwrgd (v) 0.4 1.0 0.5 1 4265 g08 0.2 0.8 0.6 1.5 2 t a = 25c gnd C v out = 4v gnd voltage (v) 40 85 current (ma) 115 45 50 4265 g09 55 60 90 100 105 110 95 90 100 105 110 95 class operation vs time on resistance vs temperature gnd voltage (v) 1 22 v1: v2: signature resistance (k) 23 25 26 27 3 5 4265 g04 24 7 9 610 24 8 28 resistance = diodes: hd01 t a = 25c = $ v $ i v2 C v1 i 2 C i 1 ieee upper limit ieee lower limit LTC4265 only LTC4265 + 2 diodes input voltage 10v/div class current 10ma/div time (10s/div) 4265 g05 t a = 25c junction temperature (c) C50 0.2 resistance () 0.4 0.6 0.8 1.0 C25 02550 4265 g06 75 100 LTC4265 5 4265fa pin functions shdn (pin 1): shutdown input. use this pin for auxiliary power application. drive shdn high to disable LTC4265 operation and corrupt the signature resistance. if unused, tie shdn to v in . t2pse (pin 2): type-2 pse indicator, open-drain. low impedance indicates the presence of a type-2 pse. r class (pin 3): class select input. connect a resistor between r class and v in to set the classi? cation load current. (see table 2.) nc (pin 4, 11): no connect. v in (pins 5, 6): input voltage, negative rail. pins 5 and 6 must be electrically tied together at the package. v out (pins 7, 8): output voltage negative rail. connects v out to v in through an internal power mosfet. pins 7 and 8 must be electrically tied together at the package. pwrgd (pin 9): power good output, open collector. high impedance signals power-up completion. pwrgd is referenced to v out and features a 14v clamp. pwrgd (pin 10): complementary power good output, open-drain. low impedance signals power up completion. pwrgd is referenced to v in . gnd (pin 12): input voltage, positive rail. this pin is connected to the pd positive rail. exposed pad (pin 13): tie to v in and pcb heat sink. block diagram 4265 bd bold line indicates high current path 12 t2pse 2 r class 3 nc 4 shdn pwrgd gnd 11 nc 1 10 pwrgd 9 v out 8 v out 7 control circuits classification current load ref C + 25k 14k exposed pad 13 v in 6 v in 5 en LTC4265 6 4265fa applications information overview power over ethernet (poe) continues to gain popularity as more products are taking advantage of having dc power and high speed data available from a single rj45 connector. as poe continues to grow in the marketplace, powered device (pd) equipment vendors are running into the 12.95w power limit established by the ieee 802.3af standard. the iee802.3at standard establishes a higher power alloca- tion for power-over-ethernet while maintaining backwards compatibility with the existing ieee802.3af systems. power sourcing equipments (pse) and powered devices are distinguished as type-1 complying with the ieee 802.3af power levels, or type-2 complying with the ieee 802.3at power levels. the maximum available power of a type-2 pd is 25.5w. the ieee802.3at standard also establishes a new method of acquiring power classi? cation from a pd and communicat- ing the presence of a type-2 pse. a type-2 pse has the option of acquiring pd power classi? cation by performing 2-event classi? cation (layer 1) or by communicating with the pd over the data line (layer 2). in turn, a type-2 pd must be able to recognize both layers of communications and identify a type-2 pse. the LTC4265 is speci? cally designed to support the front end of a pd that must operate under the ieee802.3at standard. in particular, the LTC4265 provides the t2pse indicator bit which recognizes 2-event classi? cation. this indicator bit may be used to alert the LTC4265 output load that a type-2 pse is present. with an internal signature resistor, classi? cation circuitry, inrush control, and ther- mal shutdown, the LTC4265 is a complete pd interface solution capable of supporting in the next generation pd applications. modes of operation the LTC4265 has several modes of operation depending on the input voltage applied between the gnd and v in pins. figure 1 presents an illustration of voltage and current waveforms the LTC4265 may encounter with the various modes of operation summarized in table 1. detection v1 classification on uvlo uvlo power bad uvlo on t = r load c1 pwrgd tracks v in detection v2 50 time 40 30 gnd (v) 20 10 50 40 30 20 10 time gnd C v out (v) C10 time C20 C30 gnd C pwrgd (v) pwrgd C v out (v) C40 C50 20 10 pd current inrush dv dt inrush c1 = power bad pwrgd tracks gnd pwrgd tracks gnd power bad power bad time time power good power good detection i 1 classification detection i 2 load, i load 4265 f01 i class dependent on r class selection inrush = 100ma i 1 = v1 C 2 diode drops 25k i load = v in r load i 2 = v2 C 2 diode drops 25k gnd pse i in r load r class v out c1 gnd r class pwrgd pwrgd LTC4265 v out v in in detection range figure 1. output voltage, pwrgd , pwrgd and pd current as a function of input voltage LTC4265 7 4265fa applications information these modes satisfy the requirements de? ned in the ieee 802.3af/at speci? cation. table 1. LTC4265 modes of operation as a function of input voltage gnd (v) LTC4265 modes of operation 0v to 1.4v inactive (reset after 1st classi? cation event) 1.5v to 9.8v (5.4v to 9.8v) 25k signature resistor detection before 1st classi? cation event (mark, 11k signature corrupt after 1st classi? cation event) 12.5v to on/uvlo* classi? cation load current active on/uvlo* to 60v inrush and power applied to pd load >71v overvoltage lockout, 4265 operations are disabled *on/uvlo includes hysteresis. rising input threshold, 37.2v max. falling input threshold, 30v min. input diode bridge in the ieee 802.3af/at standard, the modes of operation reference the input voltage at the pds rj45 connector. since the pd must handle power received in either polarity from either the data or the spare pair, input diode bridges br1 and br2 are connected between the rj45 connector and the LTC4265 (figure 2). rx C 6 rx + 3 tx C 2 tx + rj45 t1 powered device (pd) input 4265 f02 1 7 8 5 4 spare C spare + to phy br2 0.1f 100v br1 gnd d3 LTC4265 v in figure 2. pd front end using diode bridges on main and spare inputs the input diode bridge introduces a voltage drop that affects the range for each mode of operation. the LTC4265 compensates for these voltage drops so that a pd built with the LTC4265 meets the ieee 802.3af/at-established voltage ranges. note that the electrical speci? cations reference with respect to the LTC4265 package pins. detection during detection, the pse looks for a 25k signature resis- tor which identi? es the device as a pd. the pse will apply two voltages in the range of 2.8v to 10v and measures the corresponding currents. figure 1 shows the detection voltages v1 and v2 and the corresponding pd current. the pse calculates the signature resistance using the v/ i measurement technique. the LTC4265 presents its precision, temperature-compen- sated 25k resistor between the gnd and v in pins, alerting the pse that a pd is present and requests power to be applied. the LTC4265 signature resistor also compensates for the additional series resistance introduced by the input diode bridge. thus a pd built with the LTC4265 conforms to the ieee 802.3af/at detection speci? cations. LTC4265 8 4265fa applications information signature corrupt option in some designs that include an auxiliary power option, it is necessary to prevent a pd from being detected by a pse. the LTC4265 signature resistance can be corrupted with the shdn pin (figure 3). taking the shdn pin high will reduce the signature resistor below 11k which is an invalid signature per the ieee 802.3af/at speci? cation, and alerts the pse not to apply power. invoking the shdn pin also ceases operation for classi? cation and disconnects the LTC4265 load from the pd input. if this feature is not used, connect shdn to v in . during classi? cation probing, the pse presents a ? xed voltage between 15.5v and 20.5v to the pd (figure 2). the LTC4265 asserts a load current representing the pd power classi? cation. the classi? cation load current is programmed with a resistor r class that is chosen from table 2. table 2. summary of power classi? cations and LTC4265 r class resistor selection class usage maximum power levels at input of pd (w) nominal classification load current (ma) LTC4265 r class resistor (, 1%) 0 default 0.44 to 12.95 < 0.4 open 1 optional 0.44 to 3.84 10.5 124 2 optional 3.84 to 6.49 18.5 69.8 3 optional 6.49 to 12.95 28 45.3 4 optional 12.95 to 25.5 40 30.9 2-event classification and the t2pse pin a type-2 pse may declare the availability of high power by performing 2-event classi? cation (layer 1) or by commu- nicating over the high speed data line (layer 2). a type-2 pd must recognize both layers of communication. since layer 2 communications takes place directly between the pse and the LTC4265 load, the LTC4265 concerns itself only with recognizing 2-event classi? cation. figure 3. 25k signature resistor with disable gnd v in shdn LTC4265 to aux 4265 f03 25k signature resistor 14k to pse classification classi? cation provides a method for more ef? cient power allocation by allowing the pse to identify a pd power clas- si? cation. class 0 is included in the ieee speci? cation for pds that dont support classi? cation. class 1-3 partitions pds into 3 distinct power ranges. class 4 includes the new power range under ieee802.3at (see table 2). LTC4265 9 4265fa applications information in 2-event classi? cation, a type-2 pse probes for power classi? cation twice. figure 4 presents an example of a 2-event classi? cation. the 1st classi? cation event occurs when the pse presents an input voltage between 14.5v to 20.5v and the LTC4265 presents a class 4 load current. the pse then drops the input voltage into the mark volt- age range of 6.9v to 10v, signaling the 1st mark event. the pd in the mark voltage range presents a load current between 0.25ma to 4ma. the pse repeats this sequence, signaling the 2nd clas- si? cation and 2nd mark event occurrence. this alerts the LTC4265 that a type-2 pse is present. the type-2 pse then applies power to the pd and the LTC4265 charges up the reservoir capacitor c1 with a controlled inrush cur- rent. when c1 is fully charged, and the LTC4265 declares power good, the t2pse pin presents an active low signal, or low impedance output with respect to v in . the t2pse output becomes inactive when the LTC4265 input voltage falls outside the normal operating range. signature corrupt during mark as a member of the ieee802.3at working group, linear notes that it is possible for a type-2 pd to receive a false indication of a 2-event classi? cation if a pse port is pre-charged to a voltage above the detection voltage range before the ? rst detection cycle. the ieee working group modi? ed the standard to prevent this possibility by requiring a type-2 pd to corrupt the signature resistance during the mark event, alerting the pse not to apply power. the LTC4265 conforms to this standard by internally corrupting the signature resistance. this also discharges the port before the pse begins the next detection cycle. detection v1 on uvlo uvlo uvlo on t = r load c1 tracks v in detection v2 time pd current 50 40 30 gnd (v) 20 10 40ma 50 40 30 20 10 time gnd C v out (v) C10 time C20 C30 gnd C t2pse (v) C40 C50 dv dt inrush c1 = 4265 f04 inrush = 100ma r class = 30.9 i load = v in r load gnd pse i in r load r class v out c1 gnd r class t2pse LTC4265 v out v in 1st class 1st mark 2nd mark detection v1 detection v2 1st mark 2nd mark 2nd class 1st class 2nd class load, i load inrush figure 4. v out , t2pse , and pd current as a result of 2-event classi? cation LTC4265 10 4265fa applications information pd stability during classification classi? cation presents a challenging stability problem due to the wide range of possible classi? cation load current. the onset of the classi? cation load current introduces a voltage drop across the cable and increases the forward voltage of the input diode bridge. this may cause the pd to oscillate between detection and classi? cation with the onset and removal of the classi? cation load current. the LTC4265 prevents this oscillation by introducing a voltage hysteresis window between the detection and clas- si? cation ranges. the hysteresis window accommodates the voltage changes a pd encounters at the onset of the classi? cation load current, thus providing a trouble-free transition between detection and classi? cation modes. the LTC4265 also maintains a positive i-v slope throughout the classi? cation ranges up to the on voltage. in the event a pse overshoots beyond the classi? cation voltage range, the available load current aids in returning the pd back into the classi? cation voltage range. (the pd input may otherwise be trapped by a reverse-biased diode bridge and the voltage held by the 0.1f capacitor.) inrush current once the pse detects and optionally classi? es the pd, the pse then applies powers on the pd. when the LTC4265 input voltage rises above the on voltage threshold, LTC4265 connects v out to v in through the internal power mosfet. to control the power-on surge currents in the system, the LTC4265 provides a ? xed inrush current, allowing c1 to ramp up to the line voltage in a controlled manner. the LTC4265 keeps the pd inrush current below the pse current limit to provide a well-controlled power-up figure 5. LTC4265 undervoltage and overvoltage lockout gnd c1 5f min v in v out LTC4265 4265 f05 to pse undervoltage overvoltage lockout circuit pd load current-limited turn on + input LTC4265 voltage power mosfet 0v to on* off >on* on LTC4265 11 4265fa applications information once c1 is fully charged, the LTC4265 turns on is internal mosfet and passes power to the pd load. the LTC4265 continues to power the pd load as long as the input volt- age does not fall below the uvlo threshold. when the LTC4265 input voltage falls below the uvlo threshold, the pd load is disconnected, and classi? cation mode resumes. c1 discharges through the LTC4265 circuitry. complementary powergood when LTC4265 fully charges the load capacitor (c1), power good is declared and the LTC4265 load can safely begin operation. the LTC4265 provides complementary power good signals that remain active during normal operation and are de-asserted when the input voltage falls below the uvlo threshold, when the input voltage exceeds the over-voltage lockout (ovlo) threshold, or in the event of a thermal shutdown. see figure 6. the pwrgd pin features an open collector output refer- enced to v out which can interface directly with the run pin of a dc/dc converter product. when power good is declared and active, the pwrgd pin is high impedance with respect to v out . an internal 14v clamp protects the dc/dc converter from an excessive voltage. the active low pwrgd pin connects to an internal, open drain mosfet referenced to v in and can interface directly to the shutdown pin of a dc/dc converter product. when power good is declared and active, the pwrgd pin is low impedance with respect to v in . figure 6. LTC4265 power good functional and state diagram 4265 f06 bold line indicates high current path pwrgd power not good inrush complete on < gnd < ovlo and not in thermal shutdown gnd < uvlo gnd > ovlo or thermal shutdown power good 9 pwrgd LTC4265 10 v out 8 v out 7 v in 6 v in ovlo on uvlo tsd 5 control circuit pwrgd pin when shdn is invoked in pd applications where an auxiliary power supply invokes the shdn feature, the pwrgd pin becomes high imped- ance. this prevents the pwrgd pin that is connected to the run pin of the dc/dc converter from interfering with the dc/dc converter operations when powered by an auxiliary power supply. LTC4265 12 4265fa applications information overvoltage lockout the LTC4265 includes an overvoltage lockout (ovlo) feature (figure 5) which protects the LTC4265 and its load from an overvoltage event. if the input voltage exceeds the ovlo threshold, the LTC4265 discontinues pd operation. normal operations resume when the input voltage falls below the ovlo threshold and when c1 is charged up. thermal protection the ieee 802.3af/at speci? cation requires a pd to withstand any applied voltage from 0v to 57v inde? nitely. however, there are several possible scenarios where a pd may encounter excessive heating. during classi? cation, excessive heating may occur if the pse exceeds the 75ms probing time limit. at turn-on, when the load capacitor begins to charge, the instantaneous power dissipated by the pd interface can be large before it reaches the line voltage. and if the pd experiences a fast input positive voltage step in its operational mode (for example, from 37v to 57v), the instantaneous power dissipated by the pd interface can be large. 14 13 12 1 2 3 rx C 6 rx + 3 tx C 2 tx + rj45 t1 coilcraft ethi - 230ld 4265 f07 1 7 8 5 4 10 9 11 5 6 4 d3 smaj58a tvs br1 hd01 br2 hd01 to phy gnd LTC4265 c1 v in v out v out spare C spare + c14 0.1f 100v figure 7. pd front-end with isolation transformer, diode bridges, capacitors, and a transient voltage suppressor (tvs). the LTC4265 includes a thermal protection feature which protects the LTC4265 from excessive heating. if the LTC4265 junction temperature exceeds the over-tempera- ture threshold, the LTC4265 discontinues pd operations and power-good becomes inactive. normal operation resumes when the junction temperature falls below the over-temperature threshold and when c1 is charged up. external interface and component selection transformer nodes on an ethernet network commonly interface to the outside world via an isolation transformer. for pds, the isolation transformer must also include a center tap on the rj45 connector side (see figure 7). the increased current levels in a type-2 pd over a type-1 increase the current imbalance in the magnetics which can interfere with data transmission. in addition, proper termination is also required around the transformer to provide correct impedance matching and to avoid radiated and conducted emissions. transformer vendors such as LTC4265 13 4265fa applications information bel fuse, coilcraft, halo, pulse, and tyco (table 4) can assist in selecting an appropriate isolation transformer and proper termination methods. table 4. power-over-ethernet transformer vendors vendor contact information bel fuse inc. 206 van vorst street jersey city, nj 07302 tel: 201-432-0463 www.belfuse.com coilcraft inc. 1102 silver lake road gary, il 60013 tel: 847-639-6400 www.coilcraft.com halo electronics 1861 landings drive mountain view, ca 94043 tel: 650-903-3800 www.haloelectronics.com pca electronics 16799 shoenborn street north hills, ca 91343 tel: 818-892-0761 www.pca.com pulse engineering 12220 world trade drive san diego, ca 92128 tel: 858-674-8100 www.pulseeng.com tyco electronics 308 constitution drive menlo park, ca 94025-1164 tel: 800-227-7040 www.circuitprotection.com input diode bridge figure 2 shows how two diode bridges are typically con- nected in a pd application. one bridge is dedicated to the data pair while the other bridge is dedicated to the spare pair. the LTC4265 supports the use of either silicon or schottky input diode bridges. however, there are tradeoffs in the choice of diode bridges. an input diode bridge must exceed the maximum current the pd application will encounter at the temperature the pd will operate. diode bridge vendors typically call out the operating current at room temperature, but derate the maximum current with increasing temperature. consult the diode bridge vendors for the operating current derat- ing curve. a silicon diode bridge can consume over 4% of the available power in some pd applications. using schottky diodes can help reduce the power loss with a lower forward voltage. a schottky bridge may not be suitable for some high temperature pd application. the leakage current has a voltage dependency that can reduce the perceived signature resistance. in addition, the ieee 802.3af/at speci? cation mandates the leakage back-feeding through the unused bridge cannot generate more than 2.8v across a 100k resistor when a pd is powered with 57v. sharing input diode bridges at higher temperatures, a pd design may be forced to consider larger bridges in a bigger package because the maximum operating current for the input diode bridge is drastically de-rated. the larger package may not be ac- ceptable in some space-limited environments. one solution to consider is to reconnect the diode bridges so that only one of the four diodes conducts current in each package. this con? guration extends the maximum operating current while maintaining a smaller package pro? les. figure 7 shows how to reconnect the two diode bridges. consult the diode bridge vendors for the de-rating curve when only one of four diodes is in operation. LTC4265 14 4265fa applications information input capacitor the ieee 802.3af/at standard includes an impedance requirement in order to implement the ac disconnect function. a 0.1f capacitor (c14 in figure 7) is used to meet this ac impedance requirement. transient voltage suppressor the LTC4265 speci? es an absolute maximum voltage of 100v and is designed to tolerate brief overvoltage events. however, the pins that interface to the outside world can routinely see excessive peak voltages. to protect the LTC4265, install a transient voltage suppressor (d3) be- tween the input diode bridge and the LTC4265 as shown in figure 7. classi? cation resistor (r class ) the r class resistor sets the classi? cation load current, corresponding to the pd power classi? cation. select the value of r class from table 2 and connect the resistor between the r class and v in pins as shown in figure 4, or ? oat the r class pin if the classi? cation load current is not required. the resistor tolerance must be 1% or better to avoid degrading the overall accuracy of the classi? ca- tion circuit. load capacitor the ieee 802.3af/at speci? cation requires that the pd maintains a minimum load capacitance of 5f and does not specify a maximum load capacitor. however, if the load capacitor is too large, there may be a problem with inadvertent power shutdown by the pse. this occurs when the pse voltage drops quickly. the input diode bridge reverses bias, and the pd load momentarily powers off the load capacitor. if the pd does not draw power within the pses 300ms disconnection delay, the pse may remove power from the pd. thus, it is necessary to evaluate the load current and capacitance to ensure that an inadvertent shutdown cannot occur. the load capacitor can store signi? cant energy when fully charged. the pd design must ensure that this energy is not inadvertently dissipated in the LTC4265. for example, if the gnd pin shorts to v in while the capacitor is charged, current will ? ow through the parasitic body diode of the internal mosfet and may cause permanent damage to the LTC4265. power good interface the LTC4265 provides complementary power good sig- nals to simplify the dc/dc converter interface. using the power good signal to delay converter operation until the load capacitor is fully charged is highly recommended to ensure trouble free start up. figure 8 presents examples of power good interface cir- cuits. the active high pwrgd pin has an open collector transistor referenced to vout while the active low pwrgd pin has a high voltage, open-drain mosfet referenced to v in . the designer can choose either signal to enable the dc/dc converter. when using pwrgd , diode d9 and resistor r s protects the converter shutdown pin from excessive reverse voltage. LTC4265 15 4265fa figure 9. t2pse interface examples 4265 f09 option 1: series configuration for active low/low impedance output C54v to pse r p to pd load gnd LTC4265 v in t2pse v + option 2: shunt configuration for active high/open collector output C54v to pse r p to pd load gnd LTC4265 v in v out t2pse v + applications information figure 8. power good interface examples gnd r s 10k r10 100k pwrgd d9 mmbd4148 q1 fmmt2222 C54v 4265 f08 to pse LTC4265 active-low enable v in v out v + pd load gnd r s 10k r9 100k pwrgd d9 5.1v mmbz5231b C54v to pse LTC4265 active-low enable v in v out pd load C54v to pse active-high enable pd load run shdn gnd pwrgd LTC4265 v in v out figure 9 shows two interface options using the t2pse pin and the opto-isolator. the t2pse pin is active low and connects to an opt-isolater to communicate across the dc/dc converter isolation barrier. the pull up resistor r p is sized according to the requirements of the opto-isolator operating current, the pull-down capability of the t2pse pin, and the choice of v + . v + for example can come from the poe supply rail (which the LTC4265 gnd is tied to), or from the voltage source that supplies power to the dc/dc converter. option 1 has the advantage of not drawing power unless t2pse is declared active. t2pse interface when a 2-event classi? cation sequence successfully completes, the LTC4265 recognizes this sequence, and provides an indicator bit, declaring the presence of a type-2 pse. the open drain output provides the option to use this signal to communicate to the LTC4265 load, or to leave the pin unconnected. LTC4265 16 4265fa applications information shutdown interface to corrupt the signature resistance, the shdn pin can be driven high with respect to v in or connected to gnd. if unused, connect shdn directly to v in . exposed pad the LTC4265 uses a thermally enhanced dfn12 package that includes an exposed pad. the exposed may be elec- trically connected to v in and must connect to a printed circuit board heat sink. auxiliary power source in some applications, it is desirable to power the pd from an auxiliary power source such as a wall adapter. auxiliary power can be injected into an LTC4265-based pd at the input of the LTC4265, the output of the LTC4265, or even the output of the dc/dc converter. in addition, some pd application may desire auxiliary supply dominance or may be con? gured for poe dominance. furthermore, pd applications may also opt for a seamless transition that is, without power disruption between poe and auxiliary power. the most common auxiliary power option injects power between the LTC4265 and the dc/dc converter. figure 10 presents an example of this application. in this example, the auxiliary port injects 48v onto the line via diode d1. the components surrounding the shdn pin are selected so that the LTC4265 disconnects power to the output when the auxiliary supply reaches 36v. this con? guration is an auxiliary-dominant con? guration. that is, the auxiliary power source supplies the power even if poe power is already present. this con? guration also provides a seamless transition from poe to auxiliary power when auxiliary power is applied, however, the removal of auxiliary power to poe power is not seamless. contact linear technology applications support for detail information on implementing a custom auxiliary power supply. figure 10. auxiliary power dominant pd interface t1 4265 f10 tvs to phy 36v 100k 10k 10k d1 br1 + C br2 + C 0.1f 100v c1 gnd LTC4265 v in shdn v out + C isolated wall transformer pd load rx C 6 rx + 3 tx C 2 tx + rj45 1 7 8 5 4 spare C spare + LTC4265 17 4265fa applications information ieee 802.3at system power-up requirement under the ieee 802.3at standard, a pd must operate under 12.95 watts in accordance with ieee 802.3af standards until it recognizes a type-2 pse. initializing pd operation in 12.95-watt mode eliminates interoperability issue in case a type-2 pd is connects to a type-1 pse. once the pd recognizes a type-2 pse, the ieee 802.3at standard requires the pd to wait 80ms in 12.95w operation before 25.5w operation can commence. maintain power signature in an ieee 802.3af/at system, the pse uses the maintain power signature (mps) to determine if a pd continues to require power. the mps requires the pd to periodically draw at least 10ma and also have an ac impedance less than 26.25k in parallel with 0.05f. if one of these conditions is not met, the pse may disconnect power to the pd. layout consideration for the LTC4265 the LTC4265 is relatively immune to layout problems. here are some recommendations. avoid excessive parasitic capacitance on the r class pin and place resistor r class close to the LTC4265. connect the LTC4265 exposed pad to a pc board heat sink. make the heat sink as large as possible. place the input capacitor and transient voltage suppres- sor (c14 and d3 in figure 7) as close to the LTC4265 as possible. if using the shdn pin for auxiliary power application, separate the shdn pin from other high voltage connec- tions, like gnd and v out , to avoid leakage and capacitive coupling shutting down the LTC4265. LTC4265 18 4265fa 100k 12k ? ? ? ? 25m fds2582 14k 3.01k 20 30k 15f 16v 29.4k 383k 30.9 bas21 1.8k 38.3k 10k 51k 1nf 10k 20k 15 15 150 pe-68386 bat54 100 33pf 10f 100v 0.1f 100v smaj58a b1100 s 8 plcs 1f 100v 0.1f 4.7nf 2.2nf mmbt3906 mmbt3904 1f 1f 16v pa2467nl 4265 ta02 t on sync pgdly uvlo sense C v c sense + r cmp endly osc sfst lt3825 gnd sg fb v cc sg sg pg c cmp gnd r class shdn LTC4265 t2pse v in v out 4.7 h C54v from data pair C54v from spare pair 47pf ? 10f 16v 0.33h 12v 2a 47f 16v fds3572 + gnd 4 5 1 8 gnd ltv357ta t2p (to microcontroller) 2.2nf 2kv 470pf 2kv + high ef? ciency 12v isolated power supply (contact ltc for 3.3v and 5v power supply applications) applications information load current (a) 0.2 0.4 efficiency (%) 85 89 87 2.0 4265 ta02a 81 83 77 79 0.6 0.8 1.2 1.0 1.6 1.8 1.4 93 91 57v 48v excluding bridges 42v load current (a) 0.2 output (v) 12.0 12.1 12.2 12.3 2.0 4265 ta02b 11.8 11.9 11.6 11.7 0.6 0.8 0.4 1.2 1.0 1.6 1.8 1.4 12.4 57v 48v 42v ef? ciency vs load current output regulation vs load current LTC4265 19 4265fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description de/ue package 12-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1695 rev c) 4.00 p 0.10 (2 sides) 3.00 p 0.10 (2 sides) note: 1. drawing proposed to be a variation of version (wged) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 p 0.10 bottom viewexposed pad 1.70 p 0.10 0.75 p 0.05 r = 0.115 typ r = 0.05 typ 2.50 ref 1 6 12 7 pin 1 notch r = 0.20 or 0.35 s 45 o chamfer pin 1 top mark (note 6) 0.200 ref 0.00 C 0.05 (ue12/de12) dfn 0806 rev d 2.50 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 p 0.05 0.70 p 0.05 3.60 p 0.05 package outline 3.30 p 0.10 0.25 p 0.05 0.50 bsc 1.70 p 0.05 3.30 p 0.05 0.50 bsc 0.25 p 0.05 LTC4265 20 4265fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0909 rev a ? printed in usa related parts part number description comments lt1952 lt1952-1 single switch synchronous forward controller adjustable switching frequency, programmable undervoltage lockout, optional burst mode ? operation at light load ltc3805 adjustable frequency current mode flyback controller slope comp overcurrent protect, internal/external clock ltc3825 isolate no-opto synchronous flyback controller with wide input supply range adjustable switching frequency, programmable undervoltage lockout, accurate regulation without trim, synchronous for high ef? ciency. ltc4257-1 ieee 802.3af pd interface controller 100v 400ma internal switch, programmable classi? cation current limit ltc4258 quad ieee 802.3af power over ethernet controller dc disconnect only, ieee-compliant pd detection and classi? cation, autonomous operation or i 2 c control ltc4259a-1 quad ieee 802.3af power over ethernet pse controller with ac disconnect ac or dc disconnect ieee-compliant pd detection and classi? cation, autonomous operation or i 2 c control ltc4263/ltc4263-1 single ieee 802.3af power over ethernet controller internal switch, autonomous operation or i 2 c control. 15.4w or 30w. ltc4264 high power pd interface controller with 750ma current limit 750ma internal switch, programmable classi? cation current limit with disable, complementary power good ltc4267 ltc4267-1 ltc4267-3 ieee 802.3af pd interface with integrated switching regulator 100v 400ma internal switch, programmable classi? cation, 200khz or 300khz constant frequency pwm, interface and switcher optimized for ieee-compliant pd system. ltc4268-1 high power pd with synchronous no opto flyback controller 750ma internal switch, programmable class, current limit, synchronous programmable switching frequency and uvlo, high ef? ciency thinsot is a trademark of linear technology corporation. ? ? fds2582 10.0k 33k 10f 16v 237k 30.9 82k 158k 332k 22.1k 1.2k 4.7nf 100pf 10f 100v 0.1f 100v smaj58a b1100 s 8 plcs 2.2f 100v pa2431nl 4265 ta03a pgnd gnd sd_vsec oc isense comp fb vref ss_maxdc out blank delay rosc lt1952 v in v cc s out gnd r class shdn LTC4265 t2pse v in v out 10 h C54v from data pair C54v from spare pair ? 5v 5a 220f 6.3v pslvoj227m(12) fds8880 fds8880 + gnd gnd 5v 2.2nf 2kv bas516 bas516 10k 133 0.1f 1mh do1608c-105 irf6217 4.7nf 250v 50m 5.1 158k 0.22f 5.1 1nf 5.1 1nf 6.8h pg0702.682 + 2k ps2801-1-l ps22801-1-l bc857bf tlv431a 1.5k 33k 22k 0.1f 10nf 11.3k 3.65k 51k 20k t2p (to microcontroller) bas516 bas516 18v pdz18b v cc poe-based self-driven synchronous forward power supply typical application load (a) 0.5 efficiency (%) 80 85 90 5 4265 ta03b 75 65 70 1.5 2 1 3 2.5 4 4.5 3.5 95 42v 50v 57v ef? ciency vs load current |
Price & Availability of LTC4265
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |