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PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:1 version: 7.0 technical specification model no : PD035OX1 the content of this information is s ubject to be changed without notice. please contact pvi or its agent for further information. customer?s confirmation customer date by pvi?s confirmation confirmed by prepared by p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:2 revision history rev. eng issued date revised contents 0.1 jan .03 , 2005 preliminary 0.2 feb .02 , 2005 modify: page07: note5-2 v gh typ.= +15v. page16: register r2 ? bit d5, d4 change to reserved, register r3 ? bit d6,d5,d4 change to reserved. page18: absolute max. ratings ? storage and operation temperature. delete: page21: 9.4.4 output signal character for digital/analog rgb mode. 0.3 apr. 15, 2005 modify: page04: mechanical drawing of tft-lcd module (fpc outline drawing) add: appendix ( led b/l driving reference circuit) 0.4 may.17, 2005 modify: page05: pol i/o condition to output. page25: uniformity typ. from 80% to 75%. 1.0 jun. 07, 2005 modify: page31: packing 2.0 jul. 22, 2005 modify: page20:9.4.1 serial 8 bit rgb interface page21:9.4.2parallel 24 bits rgb interface page22: 9.5.1clock and data waveform page23: 9.5.2digital/analog rgb timing waveform 3.0 sep.19,2005 modify: page6: 5. input / output terminals(con2) pin15 symbol from if1 change to if2 pin16 symbol from if2 change to if1 page18:11.1 function control register register r0 : register r1 : register r2 : register r3 : change to register r0 :address(a3~a0) 0000 register r1 :address(a3~a0) 0001 register r2 :address(a3~a0) 0010 register r3 :address(a3~a0) 0011 page21 11-2 spi timing characteristic 8spi write timing 8spi read timing add: page16: 9. display color and gray scale reference page26:.15.reliability test p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:3 high temperature operation test 4.0 mar.8,2006 modify page3:3.mechanical specification outline dimension from 84.15 (w) 65.3 (h) 3.45 (d) change to 84.03 (w) 65.24(h) 3.43 (d) page4: mechanical drawing of tft-lcd module page10:7-4 timing characteristics of input signals 7.4.1 serial 8 bits rgb interface vs-den time from 18t h change to 21 t h page11: 7.4.2 parallel 24 bits rgb interface vs-den time from 18t h change to 21 t h 5.0 june,22,2006 page 26: 15. reliability test high temperature storage test: from ta = +70 , 240 hrs modify to ta = +80 , 240 hrs. low temperature storage test: from ta = -20 , 240 hrs modify to ta = -30 , 240 hrs. high temperature operation test from ta = +60 , 240 hrs modify to ta = +70 , 240 hrs. low temperature operation test from ta = 0 , 240 hrs modify to ta = -30 , 240 hrs. 6.0 ? july,24,2006 modify page 24 13. optical characteristics led life time 10000 hrs modify to 30000 hrs 7.0 nov,12,2007 modify page 27 14. delete carton and change packing p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:4 technical specification contents no. item page - cover 1 - revision history 2 - contents 3 1 application 5 2 features 5 3 mechanical specifications 5 4 mechanical drawing of tft-lcd module 7 5 input / output terminals 7 6 absolute maximum ratings 10 7 electrical characteristics 11 8 pixel arrangement 17 9 display color and gray scale reference 18 10 block diagram 19 11 spi register description and timing characteristics 20 12 power on sequence 24 13 optical characteristics 25 14 handling cautions 27 15 reliability test 28 16 packing 29 - appendix - p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:5 1.application this data sheet applies to a color tft lcd module, PD035OX1. the module applies to oa product, gps, which require high quality flat panel display. if you must use in high reliability environment can?t over reliability test condition. if you use PD035OX1, prime view advises your system sides must use pvi-2002a(2005/8 new product change to pvi-2003a) which one generates signal to control PD035OX1. 2. features . amorphous silicon tft lcd panel with back-light unit . pixel in delta configuration . display colors 262,144 colors . optimum viewing direction 6 o?clock . ttl transmission interface 3.mechanical specifications parameter specifications unit screen size 3.5 (diagonal) inch display format 320 (rgb) x 234 dot display colors 262,144 active area 71.6 (h) 52.65 (v) mm pixel pitch 0.22375 (h) 0.225 (v) mm pixel configuration delta outline dimension 84.03 (w) 65.24(h) 3.43 (d) mm surface treatment anti ? glare back-light 6-led weight 42 5 g display model normally white gray scale inversion direction 6 o?clock [note13-1] p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:6 4. mechanical drawing of tft-lcd module no bending area p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:7 5. input / output terminals con1 fpc down connect , 30pins , pitch : 0.5 mm pin no symbol i/o description remark 1 d15(g5) i green data 2 d14(g4) i green data 3 d13(g3) i green data 4 d12(g2) i green data 5 d11(g1) i green data 6 d10(g0) i green data(lsb) note 5-1 7 v dd2 i analog power supply for source driver note 5-2 8 v8 i gamma correction voltage 8 9 v7 i gamma correction voltage 7 10 v6 i gamma correction voltage 6 11 v5 i gamma correction voltage 5 12 v4 i gamma correction voltage 4 13 v3 i gamma correction voltage 3 14 v2 i gamma correction voltage 2 15 v1 i gamma correction voltage 1 note 5-3 16 v ss2 i analog ground for source driver 17 d07(r7) i red data(msb) 18 d06(r6) i red data 19 d05(r5) i red data 20 d04(r4) i red data 21 d03(r3) i red data 22 d02(r2) i red data 23 d01(r1) i red data 24 d00(r0) i red data(lsb) note 5-1 25 clk i clock signal. latching data at the rising edge 26 hs i horizontal sync input in rgb mode and ccir601 note 5-4 27 vs i vertical sync input in rgb mode and ccir601 note 5-5 28 den i input data enable control.(normally pull low) note 5-6 29 v cc i digital power supply for source driver ic note 5-7 30 v com i voltage for common electrode note 5-8 p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:8 con2 fpc down connect , 30pins , pitch : 0.5 mm pin no symbol i/o description remark 1 vled i power supply for led note 5-9 2 gled1 i ground for led 3 gled2 i ground for led 4 nc - nc 5 v gh i positive power for gate driver note 5-10 6 v dd1 i power supply for gate logic circuit note 5-11 7 v ss1 i ground for gate driver 8 v ee i negative power for gate driver note 5-12 9 v dd1 i power supply for gate logic circuit note 5-11 10 gnd i digital ground for source driver ic 11 resetb i hardware global reset, (low active) 12 vset i externally/internally gamma voltage setup 13 u/d i up/down control for gate driver 14 l/r i left/right control for source driver note 5-13 15 if2 i 16 if1 i select the input data format (serial rgb, parallel rgb, ccir601/656) note 5-14 17 spena i serial port data enable signal (normally pull high) `18 spck i serial port clock. (normally pull high) 19 spda i/o serial port data input/output 20 pol o polarity select for the line inversion control signal note 5-15 21 d27(b7) i blue data(msb) 22 d26(b6) i blue data 23 d25(b5) i blue data 24 d24(b4) i blue data 25 d23(b3) i blue data 26 d22(b2) i blue data 27 d21(b1) i blue data 28 d20(b0) i blue data(lsb) note 5-1 29 d17(g7) i green data(msb) 30 d16(g6) i green data p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:9 note 5-1 : digital data input. dx0 is lsb and dx7 is msb. if parallel rgb input mode is used, d0x, d1x, and d2x indicate r, g and b data in turn. if serial rgb or ccir601/656 input mode is selected, only d07~d00 are used, and others short to vss. note 5-2 : v dd2 typ. = +5v note 5-3 : the output voltage is determined by the digital input data. if digital rgb or ccir601/656 input mode is selected, the 8 gamma correction reference voltages can be set to externally or generate internally. if vset = ?h?, the gamma correction voltage generated externally if vset = ?l?, the default value is as below : (when v dd =+5v) v1 v2 v3 v4 v5 v6 v7 v8 default voltage(v) 4.29 3.73 3.33 2.94 2.62 2.22 1.51 0.48 note 5-4 : horizontal sync input in digital rgb mode. or href input in ccir601 mode. ( short to vss if not used ) note 5-5 : vertical sync input in digital rgb mode. or v123 input in ccir601 mode. ( short to vss if not used ) note 5-6 : digital rgb data input format for digital rgb input data format, both sync. mode and den mode are supported. if den signal is fixed low, sync. mode is used. otherwise , den mode is used. note 5-7 : v cc typ. = +3.3v note 5-8 : v com typ. +6.0vpp note 5-9 : iled typ. = 20ma., vled typ. = 9v note 5-10 : v gh typ. =+15v. note 5-11 : v dd1 typ. +3.3v. note 5-12 : v ee typ. = -15v. note 5-13 : the definition of l/r , u/d p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:10 u/d(pin 13)=low l/r(pin 14)=high u/d(pin 13)=high l/r(pin 14)=lo w note 5-14 : if1,if2 control the input data format. if2,if1 input data format l,l (default) serial rgb l,h parallel rgb h,l ccir601 h,h ccir656 note 5-15 : when pol=l, output voltage is negative polarity. when pol=h, output voltage is positive polarity. 6. absolute maximum ratings v ss1 =v ss2 =0 v ta = 25 parameter symbol min. max. unit remark v cc -0.3 +7.0 v supply voltage for source driver v dd2 -0.3 +7.0 v v dd1 -0.3 +7.0 v h level v gh -0.3 +32.0 v l level v ee -22.0 +0.3 v supply voltage for gate driver v gh -v ee -0.3 +45.0 v input signal voltage v in -0.3 v dd +0.3 v p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:11 7. electrical characteristics 7-1 operating condition v ss1 =v ss2 =0 v ta = 25 parameter symbol min. typ. max. unit remark logic v cc +3.0 +3.3 +3.6 v supply voltage for source driver a nalo g v dd2 +3.8 +5.0 +5.5 v logic v dd1 +3.0 +3.3 +3.6 v h level v gh +10 +15 +30 v supply voltage for gate driver l level v ee -17 -15 -5 v h level v ih 0.7v cc - v cc v signal input voltage l level v il 0 - 0.3v cc v h level vo h 0.8v cc - v cc v signal output voltage l level vo l 0 - 0.2v cc v v comac - +6.0 - v p-p ac component of v com v com v comdc - 1.0 - v dc component of v com note 7-1 note 7-1 : pvi strongly suggests that the v comdc level shall be adjustable , and the adjustable level range is 1v 1v , every module?s v comdc level shall be carefully adjusted to show a best image performance. 7-2 recommended driving condition for led backlight ta = 25 parameter symbol min typ max unit remark supply voltage of led backlight vled - - (11.0) v note 7-1 supply current of led backlight iled - 20 - ma note 7-2 backlight power consumption pled - - 440 mw note 7-3 note 7-1 i led =20ma, constant current note 7-2 : the led driving condition is defined for each led module. (3 led serial) input current = 20ma * 2 note 7-3 : p led = 2*i led *v led . vled-2 vled-1 anode cathode p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:12 7-3 power consumption v ss1 =v ss2 =0 v ta = 25 parameter symbol conditions typ. max. unit remark supply current for gate driver (hi level) i gh v gh +15v 0.2 0.5 ma supply current for gate driver(logic) idd1 v dd1 +3.3v 0.05 0.1 ma supply current for gate driver (low level) i ee v ee -15v 0.2 0.5 ma vee center voltage supply current for source driver(analog) v dd2 v dd2 +5v 5.0 8.0 ma supply current for source driver(logic) v cc v cc +3.3v 4.5 7.0 ma lcd panel power consumption - 48 80 mw backlight power consumption p led 400 440 mw total power consumption - 0.45 0.52 w ~ above data measured on serial mode: if on parallel mode, i cc typ.= 3.0ma, max.=5.0ma ; panel power consumption typ.= 41.5mw max.= 72.8mw. if on ccir601/656 mode, i cc typ.= 6.0ma, max.=10.0ma ; panel power consumption typ.= 51.4mw max.= 89.3mw. 7-4 timing characteristics of input signals 7.4.1 serial 8 bits rgb interface characteristics symbol min. typ. max. unit remark clk period t osc - 52 - ns note 7-4 data setup time t su 12 - - ns data hold time t hd 12 - - ns hs period t h - 1224 - t osc hs pulse width t hs 5 90 - t osc hs rising time t cr - - 700 ns hs falling time t cf - - 300 ns vs pulse width t vs 1 3 5 t h vs rising time t vr - - 700 ns vs falling time t vf - - 1.5 us hs falling to vs falling time for odd field t hvo 0 3 - t osc vs falling to hs falling time for even field t hve 0 3 - t osc vs-den time t vse - 21 - t h hs-den time t he 108 204 264 t osc den pulse width t ep - 960 - t osc vs period - 262 - t h note 7-4 : when sync mode is used, 1 st data start from 204 th clk after hs fallings. p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:13 7.4.2 parallel 24 bits rgb interface characteristics symbol min. typ. max. unit remark clk period t osc - 156 - ns note 7-5 data setup time t su 12 - - ns data hold time t hd 12 - - ns hs period t h - 408 - t osc hs pulse width t hs 5 30 - t osc hs rising time t cr - - 700 ns hs falling time t cf - - 300 ns vs pulse width t vs 1 3 5 t h vs rising time t vr - - 700 ns vs falling time t vf - - 1.5 us hs falling to vs falling time for odd field t hvo 0 3 - t osc vs falling to hs falling time for even field t hve 0 3 - t osc vs-den time t vse - 21 - t h hs-den time t he 36 68 88 t osc den pulse width t ep - 320 - t osc vs period - 262 - t h note 7-5 : when sync mode is used, 1 st data start from 68 th clk after hs fallings. 7.4.3 ccir601/656 interface characteristics symbol min. typ. max. unit remark clk period t osc - 37 - ns data setup time t su 12 - - ns data hold time t hd 12 - - ns 7.4.4 hardware reset timing characteristics symbol min. typ. max. unit remark resetb low pulse width t rsb 200 - - ns p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:14 7.5 timing controller timing chart 7.5.1 clock and data waveform clk d07~d00 d17~d10 d27~d20 den blanking data rgb rgb rgb rgb rgb tosc t su t hd digital parallel rgb clk d00~d07 hs blanking data y0 cb0 cr0 y1 cb2 tosc t su t hd clk d07~d00 y cr cb y cr tosc t su t hd ccir 656 y cb ccir 601 ( hs_pol ="l " in register r2 ) clk d07~d00 den blanking data g rbrg tosc t su t hd digital serial rgb p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:15 7.5.2 hs,vs,den timing waveform hs and vs timing relationship hs vs t hvo odd field hs vs t hve even field hs and den timing relationship hs den t he t hs hs, vs and den timing relationship hs vs den t vse t ep t vs p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:16 7.5.3 ccir601 timing waveform (vs_pol=?h?, hs_pol=?l? in register r2) itu-r bt.601 ntsc input timing data blanking data 524 523 href 22 23 6 5 4 3 2 1 v123 1st field blanking 261 262 href 285 286 268 267 266 265 264 263 v123 2st field href clk data y719 y1 cr0 y0 cb0 y718 cr 718 cb 718 y719 276 clock 1440 clock itu-r bt.601 pal input timing data blanking data 622 623 href 22 23 4 3 2 1 625 624 v123 1st field blanking 309 310 href 335 336 316 315 314 313 312 311 v123 2st field href clk data y719 y1 cr0 y0 cb0 y718 cr 718 cb 718 y719 288 clock 1440 clock p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:17 8. pixel arrangement p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:18 9. display color and gray scale reference input color data red green blue color r7 r6 r5 r4 r3 r2 r1 r0 g7 g6 g5 g4 g3 g2 g1 g0 b7 b6 b5 b4 b3 b2 b1 b0 black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r ed ( 2 55) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g r ee n ( 2 55) 0 0 0 0 0 0 0 0 1111111 1 0 0 0 0 0 0 0 0 bl ue ( 2 55) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 cya n 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 m age n ta 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 y e ll ow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 basic colors whi te 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 red (00) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r ed (0 1 ) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r ed (0 2 ) 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d a rk er bri g h ter r ed ( 2 53) 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r ed ( 2 5 4 ) 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 red r ed ( 2 55) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 green (00) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 g r ee n (0 1 ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 g r ee n (0 2 ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 d a rk er bri g h ter g r ee n ( 2 53) 0 0 0 0 0 0 0 0 111111 0 1 0 0 0 0 0 0 0 0 g r ee n ( 2 5 4 ) 0 0 0 0 0 0 0 0 1111111 0 0 0 0 0 0 0 0 0 green g r ee n ( 2 55) 0 0 0 0 0 0 0 0 1111111 1 0 0 0 0 0 0 0 0 blue (00) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bl ue (0 1 ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 bl ue (0 2 ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 d a rk er bri g h ter bl ue ( 2 53) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 bl ue ( 2 5 4 ) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 blue bl ue ( 2 55) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:19 10. block diagram lcd panel input h driver (source) v driver (gate) back-light p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:20 11. spi register description and timing characteristics 11.1 function control register register r0 :address(a3~a0) 0000 bit d7 d6 d5 d4 d3 d2 d1 d0 name reserve d sthd1 sthd0 sthp4 sthp3 sthp2 sthp1 sthp0 default 0 0 0 0 0 0 0 0 sthd [1:0] : adjust start pulse position by dot sthd1 sthd0 sth position adjust by dot 1 1 -1 1 0 -2 0 0 0 0 1 +1 sthp [4:0] : adjust start pulse position by pixel sthp4 sthp3 sthp2 sthp1 sthp0 sth position adjust by pixel 1 1 1 1 1 -1 1 1 1 1 0 -2 1 1 1 0 1 -3 1 1 1 0 0 -4 1 1 0 1 1 -5 1 1 0 1 0 -6 1 1 0 0 1 -7 1 1 0 0 0 -8 1 0 1 1 1 -9 1 0 1 1 0 -10 1 0 1 0 1 -11 1 0 1 0 0 -12 1 0 0 1 1 -13 1 0 0 1 0 -14 1 0 0 0 1 -15 1 0 0 0 0 -16 0 0 0 0 0 0 0 0 0 0 1 +1 0 0 0 1 0 +2 0 0 0 1 1 +3 0 0 1 0 0 +4 0 0 1 0 1 +5 0 0 1 1 0 +6 0 0 1 1 1 +7 0 1 0 0 0 +8 0 1 0 0 1 +9 0 1 0 1 0 +10 0 1 0 1 1 +11 0 1 1 0 0 +12 0 1 1 0 1 +13 0 1 1 1 0 +14 0 1 1 1 1 +15 p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:21 register r1 :address(a3~a0) 0001 bit d7 d6 d5 d4 d3 d2 d1 d0 name stvp3 stvp2 stvp1 stvp0 stvnt1 stvnt0 stvpal1 stvpal0 default 0 0 0 0 0 0 0 1 stvp [3:0] : adjust first line position by line stvp3 stvp2 stvp1 stvp0 stv position adjust by line 1 1 1 1 -1 1 1 1 0 -2 1 1 0 1 -3 1 1 0 0 -4 1 0 1 1 -5 1 0 1 0 -6 1 0 0 1 -7 1 0 0 0 -8 0 0 0 0 0 0 0 0 1 +1 0 0 1 0 +2 0 0 1 1 +3 0 1 0 0 +4 0 1 0 1 +5 0 1 1 0 +6 0 1 1 1 +7 stvnt[1:0]: when ntsc mode, the relationship of first line in even field and odd field. 00: first line in even field = first line in odd field. 01: first line in even field = first line in odd field +1. 10: no use. 11: first line in even field = first line in odd field ?1. stvpal[1:0]: when pal mode, the relationship of first line in even field and odd field. (only for ccir601/656 mode) 00: first line in even field = first line in odd field. 01: first line in even field = first line in odd field +1. 10: no use. 11: first line in even field = first line in odd field ?1. p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:22 register r2 :address(a3~a0) 0010 bit d7 d6 d5 d4 d3 d2 d1 d0 name reserved reserved reserved reserved hs_pol vs_pol npc_in npc_se t default 0 0 0 1 0 0 1 0 hs_pol: hs polarity setting. hs_pol = ?l?, negative polarity. hs_pol = ?h?, positive polarity. vs_pol: vs polarity setting. vs_pol = ?l?, negative polarity. vs_pol = ?h?, positive polarity. npc_in: define the ntsc/pal mode by spi. npc_in = ?l?, pal. (only for ccir601/656 mode) npc_in = ?h?, ntsc. npc_set: set the ntsc/pal auto detection or define by npc_in. npc_set = ?l?, auto detection. npc_set = ?h?, define by spi. register r3 :address(a3~a0) 0011 bit d7 d6 d5 d4 d3 d2 d1 d0 name reserved reserved reserved reserved pwd_en osdclk p osdhsp osdvsd default 0 0 1 0 1 0 1 1 pwd_en: set dac power saving function. pwd_en = ?l?, disable. the dac is always power on. pwd_en = ?h?, enable. p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:23 11-2 spi timing characteristic characteristics symbol min. typ. max. unit remark spck period t ck 60 - - ns spck high width t ckh 30 - - ns spck low width t ckl 30 - - ns data setup time t su1 12 - - ns data hold time t hd1 12 - - ns spena to spck setup time t cs 20 - - ns spena to spda hold time t ce 20 - - ns spena high pulse width t cd 50 - - ns spda output latency t cr - 1/2 - t ck 1a 3 a 2a 1 a 0 s p d a d 7d 6d 5d 4d 3d 2 d 1d 0 t s u 1 s p c k s p e n a t h d 1 t c r t c k t c kh t c k l t c e t c d s p i "read" tim ing t c s s p i "w rite" tim ing 0a 3a 2a 1a 0 t su 1 s p c k s p e n a t h d 1 t c k t c k h t c k l t c d t c s s p d a d 7d 6d 5d 4d 3d 2d 1d 0 t c e p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:24 12. power on sequence the power on sequence only effect by v cc ,v ss ,v dd ,v ee and v gh, the others do not care. v ss (0v) v gh on off off v dd ,v cc v ee t1 t2 t3 t4 logic signal rgb-video signal off off backlight on >10ms >10ms 1) 10ms Q t1 PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:25 13. optical characteristics ta = 25 parameter symbol condition min. typ. max. unit remarks horizontal 21, 22 45 50 --- deg 11 30 35 --- deg viewing angle vertical 12 cr R 10 10 15 --- deg note 13-1 contrast ratio cr at optimized viewing angle 200 400 --- note 13-2 rise tr --- 15 30 ms response time fall tf =0 --- 25 50 ms note 13-3 uniformity u 9 point 70 75 - % note 13-4 brightness - center point 200 250 - cd/ O note 13-5 x =0 0.28 0.31 0.34 - white chromaticity y =0 0.30 0.33 0.36 - note 13-5 led life time - 25 - 30000 - hrs note13-6 note 13-1 : the definitions of viewing angles luminance when testing point is white note 13-2 : cr luminance when testing point is black contrast ratio is measured in optimum common electrode voltage. p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:26 note 13-3 : the definition of response time : 100% 90% 10% 0% white white brightness black tr tf note 13-4 : the uniformity of lcd is defined as the minimum brightness of the 9 testing points u = the maximum brightness of the 9 testing points luminance meter : bm-5a or bm-7 fast (topcon) measurement distance : 500 mm +/- 50 mm ambient illumination : < 1 lux measuring direction : perpendicular to the surface of module the test pattern is white (gray level 63). 1/6 1/6 2/6 2/6 1/6 1/6 2/6 2/6 note 13-5 : topcon bm-7(fast) luminance meter 1.0 field of view is used in the testing (use pvi backlight after 5 minutes operating), iled = 20ma. note 13-6 : the ?led life time ? is defined as the module brightness decrease to 50% original brightness that the ambient temperature is 25 and i led =20ma. p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:27 14. handling cautions 14-1) mounting of module a) please power off the module when you connect the input/output connector. b) please connect the ground pattern of the inverter circuit surely. if the connection is not perfect, some following problems may happen possibly. 1.the noise from the backlight unit will increase. 2. the output from inverter circuit will be unstable. 3. in some cases a part of module will heat. c) polarizer which is made of soft material and susceptible to flaw must be handled carefully. d) protective film (laminator) is applied on surface to protect it against scratches and dirts. it is recommended to peel off the laminator before use and taking care of static electricity. 14-2) precautions in mounting a) when metal part of the tft-lcd module (shielding lid and rear case) is soiled, wipe it with soft dry cloth. b) wipe off water drops or finger grease immediately. long contact with water may cause discoloration or spots. c) tft-lcd module uses glass which breaks or cracks easily if dropped or bumped on hard surface. please handle with care. d) since cmos lsi is used in the module. so take care of static electricity and earth yourself when handling. 14-3) adjusting module a) adjusting volumes on the rear face of t he module have been set optimally before shipment. b) therefore, do not change any adjusted values. if adjusted values are changed, the specifications described may not be satisfied. 14-3) others a) do not expose the module to direct sunlight or intensive ultraviolet rays for many hours. b) store the module at a room temperature place. c) the voltage of beginning electric discharge may over the normal voltage because of leakage current from approach conductor by to draw lump read lead line around. d) if lcd panel breaks, it is possibly that the liquid crystal escapes from the panel. avoid putting it into eyes or mouth. when liquid crystal sticks on hands, clothes or feet. wash it out immediately with soap. e) observe all other precautionary requirements in handling general electronic components. f)please adjust the voltage of common electrode as material of attachment by 1 module. p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:28 15. reliability test no test item test condition 1 high temperature storage test ta = +80 , 240 hrs 2 low temperature storage test ta = -30 , 240 hrs 3 low temperature operation test ta =-30 , 240 hrs 4 high temperature operation test ta=+70 ,240hrs 5 high temperature & high humidity operation test ta = +60 , 90%rh, 240 hrs 6 thermal cycling test (non-operating) -20 +70 , 200 cycles 30 min 30 min 7 vibration test (non-operating) frequency : 10 ~ 55hz amplitude : 1mm , sweep time : 11 mins test period : 6 cycles for each direction of x,y, z 8 shock test(non-operating) 100g , 6ms , 3cycles for each direction of x,y,z 9 electrostatic discharge test (non-operating) 200pf, 0 machine mode = 200v 1 time / each terminal ta: ambient temperature note : the protective film must be removed before temperature test. [criteria] in the standard conditions, there is not display function ng issue occurred. (including: line defect ,no image). all the cosmetic specification is judged before the reliability stress. p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:29 16. packing p-511-254(v:7)
PD035OX1 the information contained herein is the excl usive property of prime view internati onal co., ltd. and sha ll not be distributed, reproduced, or disclosed in whole or in part without prior written permission of prime view international co., ltd. page:30 appendix 20k 5% 1kvr 2k 5% 2sc2412 20ma , 1v 0.1f 0.1f 47f 25v led vled (pin 01) 15+ 0.5v gled1 (pin 02) v c1 v e1 v b1 49.9 ,1% 1/16w 20k 5% 1kvr 2k 5% 2sc2412 20ma , 1v 0.1f 0.1f 47f 25v led vl e d (pin 01) 15+ 0.5v v c2 v e2 v b2 49.9 ,1% 1/16w gled2 (pin 03) con 2 p-511-254(v:7)

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