w3hg2128m72eer-d4 october 2006 rev. 1 concept* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 2gb ? 2x128mx72 ddr2 sdram registered, ecc, w/pll description the w3hg2128m72eer is a 2x128mx72 double data rate ddr2 sdram high density sodimm. this memory module consists of eighteen 128mx8 (1gb) bit with 4 banks ddr2 synchronous drams in fbga packages, mounted on a 200-pin so-dimm fr4 substrate. * this product is under development, is not quali ed or characterized and is subject to change or cancellation without notice. note: consult factory for availability of: ? vendor source control options ? industrial temperature option features ? 200-pin, small-outline dual in-line memory module (so-dimm) ? fast data transfer rates: pc2-6400*, pc2-5300*, pc2-4200 and pc2-3200 ? utilizes 800*, 667*, 533 and 400 mt/s ddr2 sdram components ? v cc = v cc = 1.8v ( 0.1v) ? v ccspd = 1.7v to 3.6v ? jedec standard 1.8v i/o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ? four-bit prefetch architecture ? multiple internal device banks for concurrent operation ? supports duplicate output strobe (rdqs/rdqs#) ? programmable cas# latency (cl): 3, 4, 5 and 6 ? adjustable data-output drive strength ? on-die termination (odt) ? posted cas# latency: 0, 1, 2, 3 and 4 ? serial presence detect (spd) with eeprom ? 64ms: 8,192 cycle refresh ? gold edge contacts ? dual rank ? rohs compliant ? jedec package ? 200 pin (so-dimm): 30.00mm (1.181") typ. operating frequencies pc2-3200 pc2-4300 pc2-5300* pc2-6400* clock speed 200mhz 266mhz 333mhz 400mhz cl-t rcd -t rp 3-3-3 4-4-4 5-5-5 6-6-6 * consult factory for availability
w3hg2128m72eer-d4 october 2006 rev. 1 concept 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs pin configuration pin# symbol pin# symbol pin# symbol pin# symbol 1v ref 51 dq18 101 v cc 151 v ss 2v ss 52 v ss 102 a6 152 v ss 3 dq0 53 dq19 103 a5 153 dqs5# 4 dq4 54 dq28 104 a4 154 dm5 5v ss 55 v ss 105 a3 155 dqs5 6 dq5 56 dq29 106 v cc 156 v ss 7 dq1 57 dq24 107 a2 157 v ss 8v ss 58 v ss 108 a1 158 dq46 9 dqs0# 59 dq25 109 v cc 159 dq42 10 dm0 60 dm3 110 a0 160 dq47 11 dqs0 61 v ss 111 a10/ap 161 dq43 12 v ss 62 v ss 112 ba1 162 v ss 13 v ss 63 dqs3# 113 ba0 163 v ss 14 dq6 64 dq30 114 v cc 164 dq52 15 dq2 65 dqs3 115 ras# 165 dq48 16 dq7 66 dq31 116 we# 166 dq53 17 dq3 67 v ss 117 v cc 167 dq49 18 v ss 68 v ss 118 s0# 168 v ss 19 v ss 69 dq26 119 cas# 169 v ss 20 dq12 70 cb4 120 odt0 170 dm6 21 dq8 71 dq27 121 nc/s1# 171 dqs6# 22 dq13 72 cb5 122 a13 172 v ss 23 dq9 73 v ss 123 v cc 173 dqs6 24 v ss 74 v ss 124 v cc 174 dq54 25 v ss 75 cb0 125 odt1 175 v ss 26 dm1 76 dm8 126 ck 176 dq55 27 dqs1# 77 cb1 127 nc/s3# 177 dq50 28 v ss 78 v ss 128 ck# 178 v ss 29 dqs1 79 v ss 129 dq32 179 dq51 30 dq14 80 cb6 130 v ss 180 dq60 31 v ss 81 dqs8# 131 v ss 181 v ss 32 dq15 82 cb7 132 dq36 182 dq61 33 dq10 83 dqs8 133 dq33 183 dq56 34 v ss 84 v ss 134 dq37 184 v ss 35 dq11 85 v ss 135 dqs4# 185 dq57 36 dq20 86 cb2 136 v ss 186 dm7 37 v ss 87 cke0 137 dqs4 187 v ss 38 dq21 88 cb3 138 dm4 188 dq62 39 dq16 89 nc/cke1 139 v ss 189 dqs7# 40 v ss 90 v ss 140 v ss 190 v ss 41 dq17 91 nc/s2# 141 dq34 191 dqs7 42 reset# 92 nc/ba2 142 dq38 192 dq63 43 v ss 93 v cc 143 dq35 193 dq58 44 dm2 94 nc 144 dq39 194 sda 45 dqs2# 95 a12 145 v ss 195 v ss 46 v ss 96 a11 146 v ss 196 scl 47 dqs2 97 a9 147 dq40 197 dq59 48 dq22 98 v cc 148 dq44 198 sa1 49 v ss 99 a7 149 dq41 199 v ccspd 50 dq23 100 a8 150 dq45 200 sa0 pin names pin name function a0 ~ a13 address inputs ba0 ~ ba1 bank address inputs dq0 ~ dq63 data input/output cb0 ~ cb7 check bits dqs0 ~ dqs8 data strobes dqs0# ~ dqs8# data strobes complement odt0, odt1 on-die termination control ck,ck# clock imput cke0, cke1 clock enables cs0# ~ cs3# chip selects ras# row address strobes cas# column address strobes we# write enable dm0 ~ dm8 data masks v cc voltage supply 1.8v +/- 0.1v a10/ap address input/autoprecharge v cc spd spd voltage supply 1.7v to 3.6v v ccq i/o power (1.8v) v ss ground sa0 ~ sa2 spd address sda spd data input/output scl spd clock input v ref sstl_18 refrence voltage nc no connect
w3hg2128m72eer-d4 october 2006 rev. 1 concept 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs functional block diagram r e g i s t e r s cs0# cs1# ba0-ba1 a0-a13 ras# cas# we# cke0 cke1 odt0 odt1 reset#** rst# ck** ck# ** rcs0# -> cs#: ddr2 sdrams rcs1# -> cs: ddr2 sdrams rba0-rba1 -> ba0-ba1: ddr2 sdrams ra0-ra13 -> a0-a13: ddr2 sdrams rras# -> ras#: ddr2 sdrams rcas# -> cas#: ddr2 sdrams rwe# -> we#: ddr2 sdrams rcke0 -> cke: ddr2 sdrams rcke1 -> cke: ddr2 sdrams rodt0 -> odt: ddr2 sdrams rodt1 -> odt: ddr2 sdrams v ref v ss ddr2 sdrams ddr2 sdrams v cc ddr2 sdrams v ccspd serial pd v ccq ddr2 sdrams a0 serial pd a1 a2 sa0 sa1 sa2 sda scl wp pll ck0 ck0# 120? ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 register x 2 reset# i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 rcs1# rcs0# dqs0 dqs0# dm0 dqs4 dqs4# dm4 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs1 dqs1# dm1 dqs5 dqs5# dm5 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs2 dqs2# dm2 dqs6 dqs6# dm6 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dqs3 dqs3# dm3 dqs7 dqs7# dm7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dm/ rdqs cs# dqs dqs# rdqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# dm/ rdqs cs# dqs dqs# rdqs dqs8 dqs8# dm8 **reset#. ck and ck# connects to both registers. other signals connect to one of two registers. note: ? unless otherwise noted, resister values are 22 ohms.
w3hg2128m72eer-d4 october 2006 rev. 1 concept 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs dc operating conditions all voltages referenced to v ss parameter symbol min typical max unit notes supply voltage v cc 1.7 1.8 1.9 v1 i/o supply voltage v ccq 1.7 1.8 1.9 v 4 v ccl supply voltage v ccl 1.7 1.8 1.9 v 4 i/o reference voltage v ref 0.49 x v ccq 0.50 x v ccq 0.51 x v ccq v2 i/o termination voltage v tt v ref -0.04 v ref v ref +0.04 v 3 notes: 1. v cc & v ccq must track each other. v ccq must be less than or equal to v cc. 2. v ref is expected to equal v ccq/2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not excedd +/-1percent of the dc value. peak-to-peak ac noise on v ref may not exceed +/-2 percent of v ref . this measurement is to be taken at the nearest v ref bypass capacitor. 3. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal. 4. v ccq tracks with v cc ;v ccl tracke with v cc absolute maximum ratings symbol parameter min max units v cc voltage on v cc pin relative to v ss -1.0 2.3 v v ccq voltage on v ccq pin relative to v ss -0.5 2.3 v v ccl voltage on v ccl pin relative to v ss -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature -55 100 c t cas device operating temperature 0 85 c i l input leakage current; any input 0v w3hg2128m72eer-d4 october 2006 rev. 1 concept 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs operating temperature condition parameter symbol rating units notes operating temperature toper 0 c to 85c c 1, 2 notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ease refer to jeded jesd51.2 2. at 0c - 85c, operation temperature range, all dram speci cation will be supported. input dc logic level all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage v ih (dc) v ref + 0.125 v cc + 0.300 v input low (logic 0) voltage v il (dc) -0.300 v ref - 0.125 v input ac logic level all voltages referenced to v ss parameter symbol min max units input high (logic 1) voltage ddr2-400 & ddr2-533 v ih (dc) v ref + 0.250 - v input low (logic 1) voltage ddr2-667 v ih (dc) v ref + 0.200 - v input low (logic 0) voltage ddr2-400 & ddr2-533 v il (dc) - v ref - 0.250 v input low (logic 0) voltage ddr2-667, ddr2-800(tbd) v il (dc) - v ref - 0.200 v
w3hg2128m72eer-d4 october 2006 rev. 1 concept 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs i cc specification symbol proposed conditions 806 665 534 403 units i cc0* operating one bank active-precharge; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching ma i cc1* operating one bank active-read-precharge; i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t rc = t rc (i cc ), t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; address businputs are switching; data pattern is same as i cc 4w ma i cc2p** precharge power-down current; all banks idle; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating ma i cc2q** precharge quiet standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputsare stable; data bus inputs are floating ma i cc2n** precharge standby current; all banks idle; t ck = t ck (i cc ); cke is high, cs# is high; other control and address bus inputs are stable; data bus inputs are switching ma i cc3p** active power-down current; all banks open; t ck = t ck (i cc ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma i cc3n** active standby current; all banks open; t ck = t ck (i cc ), t rc = t rc (i cc, t ras = t ras min(i cc ); cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma i cc4w* operating burst write current; all banks open, continuous burst writes; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching ma i cc4r* operating burst read current; all banks open, continuous burst reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = 0; t ck = t ck (i cc ), t ras = t ras max(i cc ), t rp = t rp (i cc ); cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc 4w ma i cc5** burst auto refresh current; t ck = t ck (i cc ); refresh command at every t rfc (i cc ) interval; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma i cc6** self refresh current; ck and ck# at 0v; cke 0.2v; other control and address bus inputs vre floating; data bus inputs are floating normal ma i cc7* operating bank interleave read current; all bank interleaving reads, i out = 0ma; bl = 4, cl = cl(i cc ), al = t rc d(i cc )-1*t ck (i cc ); t ck = t ck (i cc ), t rc = t rc (i cc ), t rrd = t rrd (i cc ), t rcd = 1*t ck (i cc ); cke is high, cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching. ma i cc speci cation is based on xxxx components. other dram manufactures speci cation may be different. note: * value calculated as one module rank in this operating condition, and all other module ranks in i cc 2p (cke low) mode. ** value calculated re ects all module ranks in this operating condition.
w3hg2128m72eer-d4 october 2006 rev. 1 concept 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ddr2 sdram componentac timing parameters & specifications ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit clock clock cycle time cl = 6 t ck (6) ps cl = 5 t ck (5) ps cl = 4 t ck (4) ps cl = 3 t ck (3) ps ck high-level width t ch t ck ck low-level width t cl t ck half clock period t hp ps clock jitter t j i t ps data dq output access time from ck/ck# t ac ps data-out high-impedance window from ck/ck# t hz ps data-out low-impedance window from ck/ck# t lz ps dq and dm input setup time relative to dqs t ds ps dq and dm input hold time relative to dqs t dh ps dq and dm input pulse width (for each input) t d i pw t ck data hold skew factor t qhs ps dq?dqs hold, dqs to rst dq to go nonvalid, per access t qh ps data valid output window (dvw) t dvw ns data strobe dqs input high pulse width t dqsh t ck dqs input low pulse width t dqsl t ck dqs output access time from ck/ck# t dqsck ps dqs falling edge to ck rising ? setup time t dss t ck dqs falling edge from ck rising ? hold time t dsh t ck dqs?dq skew, dqs to last dq valid, per group, per access t dqsq ps dqs read preamble t rpre t ck dqs read postamble t rpst t ck dqs write preamble setup time t wpres p s dqs write preamble t wpre t ck dqs write postamble t wpst t ck write command to rst dqs latching transition t dqss t ck address and control input pulse width for each input t ipw t ck address and control input setup time t is ps address and control input hold time t ih ps address and control input hold time t ccd t ck ac speci cation is based on xxxx components. other dram manufactures speci cation may be different. continued on next page
w3hg2128m72eer-d4 october 2006 rev. 1 concept 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ddr2 sdram componentac timing parameters & specifications (cont'd) ac characteristics 806 665 534 403 parameter symbol min max min max min max min max unit command and address active to active (same bank) command t rc ns active bank a to active bank b command t rrd ns active to read or write delay t rcd ns four bank activate period t faw ns active to precharge command t ras ns internal read to precharge command delay t rtp ns write recovery time t wr ns auto precharge write recovery + precharge time t dal ns internal write to read command delay t wtr ns precharge command period t rp ns precharge all command period t rpa ns load mode command cycle time t mrd t ck cke low to ck,ck# uncertainty t delay ns self refresh refresh to active of refresh to refresh command interval t rfc ns average periodic refresh interval t ref i s exit self refresh to non-read command t xsnr ns exit self refresh to read command t xsrd t ck exit self refresh timing reference ti sxr ps odt odt turn-on delay t aond t ck odt turn-on t aon ps odt turn-off delay t aofd t ck odt turn-off t aof ps odt turn-on (power-down mode) t aonpd ps odt turn-off (power-down mode) t aofpd ps odt to power-down entry latency t anpd t ck odt power-down exit latency t axpd t ck power-down exit active power-down to read command, mr[bit12=0] t xard t ck exit active power-down to read command, mr[bit12=1] t xards t ck a exit precharge power-down to any non- read command. t xp t ck cke minimum high/low time t cke t ck ac speci cation is based on xxxx components. other dram manufactures speci cation may be different.
w3hg2128m72eer-d4 october 2006 rev. 1 concept 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 3.80 (0.150) max 1.10 (0.043) 0.90 (0.035) pin 1 67.75 (2.667) 67.45 (2.656) 20.00 (0.787) typ 1.80 (0.071) (2x) 0.60 (0.024) typ 0.45 (0.018) typ pin 199 pin 200 pin 2 2.15 (0.085) 6.00 (0.236) 63.60 (2.504) 2.55 (0.100) 1.00 (0.039) typ typ back view front view 30.15 (1.187) 29.85 (1.175) 47.40 (1.866) typ 11.40 (0.449) typ 4.2 (0.165) typ 4.10(0.161) (2x) 3.90(0.154) package dimensions for d4 ** all dimensions are in millimeters and (inches) ordering information for d4 part number speed/data rate frequency cas latency t rcd t rp height** w3hg2128m72eer806d4xg* 400mhz/800mb/s 6 6 6 30.00mm (1.181") typ w3hg2128m72eer665d4xg* 333mhz/667mb/s 5 5 5 30.00mm (1.181") typ w3hg2128m72eer534d4xg 266mhz/533mb/s 4 4 4 30.00mm (1.181") typ w3hg2128m72eer403d4xg 200mhz/400mb/s 3 3 3 30.00mm (1.181") typ * consult factory for availability notes: ? rohs product. (?g? = rohs compliant) ? vendor speci c part numbers are used to provide memory component source control. the place holder for this is shown as a lower case "x" in the part numbers above and is to be replaced with respective vendors code. consult factory for quali ed sourcing options. (m = micron, s = samsung & consult factory for others)
w3hg2128m72eer-d4 october 2006 rev. 1 concept 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs part numbering guide w 3 h g 2 128m 72 e e r xxx d4 x g wedc memory (sdram) ddr 2 gold dual rank depth bus width component width x8 1.8v registered speed (mb/s) package 200 pin so-dimm component vendor name (m = micron) (s = samsung) g = rohs compliant
w3hg2128m72eer-d4 october 2006 rev. 1 concept 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs document title 2gb ? 2x128mx72 ddr2 sdram registered,pll, so-dimm revision history rev # history release date status rev 0 created january 2006 concept rev 1 1.0 updated ac title to indicate component ac spec only october 2006 advanced
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