cystech electronics corp. spec. no. : 794n3 issued date : 2010.06.17 revised date : 2014.01.17 page no. : 1/ 9 mtp3lp01n3 cystek product specification 30v p-channel enhancement mode mosfet bv dss -30v mtp3lp01n3 i d -230ma 3 @-4v 4.6 @-2.5v r dson(typ) 10.9 @-1.5v features ? ultra high speed switching. ? low gate charge. ? 2.5v drive. ? pb-free lead plating and halogen-free package. equivalent circuit outline ordering information device package shipping MTP3LP01N3-0-T1-G sot-23 (pb-free lead plating an d halogen-free package) 3000 pcs / tape & reel mtp3lp01n3 sot-23 d g gate s s source g d drain environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pc s / tape & reel,7? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : 794n3 issued date : 2010.06.17 revised date : 2014.01.17 page no. : 2/ 9 mtp3lp01n3 cystek product specification absolute maximum ratings (t a =25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds -30 v gate-source voltage v gs 10 v continuous drain current i d -230 ma pulsed drain current (note 1) i dm -920 ma maximum power dissipation (note 2) p d 250 mw thermal resistance, junction-to-ambient r th,ja 500 c/w operating junction and storage temperature tj, tstg -55~+150 c note : 1. pulse width 10 s, duty cycle 1%. 2. when mounted on a glass epoxy with a dimension of 100mm2 ? 1mm. electrical characteristics (ta=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -30 - - v v gs =0v, i d =-250 a v gs(th) -0.6 0.9 -1.1 v v ds =-10v, i d =-100 a g fs 100 210 - ms v ds =-10v, i d =-100ma i gss - - d 1 a v gs = d 8v, v ds =0 - - -1 v ds =-30v, v gs =0 i dss - - -10 a v ds =-24v, v gs =0; tj=125 c c - 3 5 v gs =-4v, i d =-100ma - 4.6 8 v gs =-2.5v, i d =-30ma *r ds(on) - 10.9 18 v gs =-1.5v, i d =-1ma dynamic ciss - 35.7 - coss - 11.9 - crss - 3.7 - pf v ds =-20v, v gs =0, f=1mhz *t d(on) - 26.4 - *t r - 12.8 - *t d(off) - 31.5 - *t f - 46.4 - ns v ds =-15v, i d =-100ma, v gs =-4v, r l =150 , r g =50 *qg - 0.78 - *qgs - 0.1 - *qgd - 0.1 - nc v ds =-10v, i d =-100ma, v gs =-10v source-drain diode *i s - - -230 *i sm - - -920 ma *v sd - 0.83 -1.2 v v gs =0v, i s =-100ma *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : 794n3 issued date : 2010.06.17 revised date : 2014.01.17 page no. : 3/ 9 mtp3lp01n3 cystek product specification typical characteristics (the minus sign in voltage and current is omitted) typical output characteristics 0 0.05 0.1 0.15 0.2 0.25 0.3 00.511.52 drain-source voltage ---v ds (v) drain current --- i d (a) vgs=1.5v 6v 2v 2.5v 3v 3.5v t a =25c 4v typical transfer characteristics 0 50 100 150 200 0 0.5 1 1.5 2 2.5 3 gate-source voltage-v gs (v) drain current -i d (a) v ds =10v 75c 25c 125c static drain-source on-state resistance vs gate-source voltage 0 2 4 6 8 10 024681 0 gate-source voltage-vgs(v) static drain-source on-state resistance-r ds( on) () t a =75c t a =125c t a =25c i d =30ma static drain-source on-state resistance vs gate-source voltage 0 2 4 6 8 10 0246810 gate-source voltage-v gs (v) static drain-source on-state resistance-r ds( on) () t a =75c t a =125c t a =25c i d =50ma static drain-source on-state resistance vs drain current 1 10 100 0.1 1 10 drain current-i d (ma) static drain-source on-state resistance- r ds(on) () t a =125c t a =75c t a =25c v gs =1.5v static drain-source on-state resistance vs drain current 1 10 100 1 10 100 drain current-i d (ma) static drain-source on-state resistance- r ds(on) () t a =75c t a =25c t a =125c v gs =2.5v
cystech electronics corp. spec. no. : 794n3 issued date : 2010.06.17 revised date : 2014.01.17 page no. : 4/ 9 mtp3lp01n3 cystek product specification typical characteristics(cont.) static drain-source on-state resistance vs drain current 1 10 1 10 100 1000 drain current-id(ma) static drain-source on-state resistance- rds(on)() ta=125c ta=75c ta=25c vgs=4v static drain-source on-state resistance vs ambient temperature 0 2 4 6 8 10 0 50 100 150 ambient temperature-t a (c) static drain-source on-state resistance-r ds(on) () i d =50ma, v gs =4v i d =30ma, v gs =2.5v reverse drain current vs source-drain voltage 0 0.2 0.4 0.6 0.8 1 1.2 0.1 1 10 100 1000 reverse drain current -i dr (ma) source-drain voltage-v sd (v) t a =125c t a =25c t a =75c v gs =0v capacitance vs drain-to-source voltage 1 10 100 0 5 10 15 20 25 30 drain-source voltage -v ds (v) capacitance---(pf) c oss ciss crss f=1mhz forward transfer admittance vs drain current 10 100 1000 10 100 1000 drain current-i d (ma) forward transfer admittance---g fs (ms) t a =125c t a =25c t a =75c brekdown voltage vs ambient temperature 30 35 40 45 -100 -50 0 50 100 150 200 ambient temperature-tj(c) drain-source breakdown voltage bv dss (v) i d =250a, v gs =0v
cystech electronics corp. spec. no. : 794n3 issued date : 2010.06.17 revised date : 2014.01.17 page no. : 5/ 9 mtp3lp01n3 cystek product specification typical characteristics(cont.) static drain-source on-resistance vs ambient temperature 0 1 2 3 4 5 6 -100 -50 0 50 100 150 200 ambient temperature-ta(c) static drain-source on-state resistance-r ds(on) () i d =100ma, v gs =4v gate charge characteristics 0 1 2 3 4 5 6 7 8 9 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 total gate charge---qg(nc) gate-source voltage---v gs (v) v ds =10v, id=100ma power derating curves 0 50 100 150 200 250 300 0 50 100 150 200 ambient temperature---t a () power dissipation---p d (mw) maximum safe operating area 0.0001 0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 100 drain-source voltage -v ds (v) drain current --- i d (a) dc 10ms 100ms 1ms pw<100 s single pulse tc=25c; tj=150c implemented on a glass epoxy
cystech electronics corp. spec. no. : 794n3 issued date : 2010.06.17 revised date : 2014.01.17 page no. : 6/ 9 mtp3lp01n3 cystek product specification typical characteristics(cont.) transient thermal response curves 0.001 0.01 0.1 1 10 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) z ja (t), normalized transient thermal resistance single pulse z ja (t)=500c/w max. implemented on a glass epoxy recommended soldering footprint
cystech electronics corp. spec. no. : 794n3 issued date : 2010.06.17 revised date : 2014.01.17 page no. : 7/ 9 mtp3lp01n3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : 794n3 issued date : 2010.06.17 revised date : 2014.01.17 page no. : 8/ 9 mtp3lp01n3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : 794n3 issued date : 2010.06.17 revised date : 2014.01.17 page no. : 9/ 9 mtp3lp01n3 cystek product specification sot-23 dimension *: typical dim marking: te date code ab xx device name style: pin 1.gate 2.source 3.drain 3-lead sot-23 plastic surface mounted package cystek package code: n3 inches millimeters inches millimeters min. max. min. max. dim min. max. min. max. a 0.1102 0.1204 2.80 3.04 j 0.0032 0.0079 0.08 0.20 b 0.0472 0.0669 1.20 1.70 k 0.0118 0.0266 0.30 0.67 c 0.0335 0.0512 0.89 1.30 l 0.0335 0.0453 0.85 1.15 d 0.0118 0.0197 0.30 0.50 s 0.0830 0.1161 2.10 2.95 g 0.0669 0.0910 1.70 2.30 v 0.0098 0.0256 0.25 0.65 h 0.0000 0.0040 0.00 0.10 l1 0.0118 0.0197 0.30 0.50 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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