document number: 91188 www.vishay.com s09-0010-rev. a, 19-jan-09 1 power mosfet irfiz34g, sihfiz34g vishay siliconix features ? isolated package ? high voltage isolation = 2.5 kv rms (t = 60 s; f = 60 hz) ? sink to lead creepage distance = 4.8 mm ? 175 c operating temperature ? dynamic dv/dt rating ? low thermal resistance ? lead (pb)-free available description third generation power mosfet s from vishay provide the designer with the best combi nation of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. the to-220 fullpak eliminates the need for additional insulating hardware in commercial-industrial applications. the molding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. the isolation is equivalent to using a 100 micron mica barrier with standard to-220 product. the fullpak is mounted to a heatsink using a single clip or by a single screw fixing. notes a. repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. v dd = 25 v, starting t j = 25 c, l = 875 h, r g = 25 , i as = 20 a (see fig. 12). c. i sd 30 a, di/dt 200 a/s, v dd v ds , t j 175 c. d. 1.6 mm from case. product summary v ds (v) 60 r ds(on) ( )v gs = 10 v 0.050 q g (max.) (nc) 46 q gs (nc) 11 q gd (nc) 22 configuration single n -channel mosfet g d s s d g to-220 fullpak a v aila b le rohs* compliant ordering information package to-220 fullpak lead (pb)-free IRFIZ34GPBF sihfiz34g-e3 snpb irfiz34g sihfiz34g absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 60 v gate-source voltage v gs 20 continuous drain current v gs at 10 v t c = 25 c i d 20 a t c = 100 c 14 pulsed drain current a i dm 80 linear derating factor 0.28 w/c single pulse avalanche energy b e as 300 mj maximum power dissipation t c = 25 c p d 42 w peak diode recovery dv/dt c dv/dt 5.0 v/ns operating junction and storage temperature range t j , t stg - 55 to + 175 c soldering recommendations (p eak temperature) for 10 s 300 d mounting torque 6-32 or m3 screw 10 lbf in 1.1 n m * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91188 2 s09-0010-rev. a, 19-jan-09 irfiz34g, sihfiz34g vishay siliconix notes a. repetitive rating; pulse width limited by maximum junction temper ature (see fig. 11). b. pulse width 300 s; duty cycle 2 % thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -65 c/w maximum junction-to-case (drain) r thjc -3.6 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 60 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma - 0.065 - v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 2.0 - 4.0 v gate-source leakage i gss v gs = 20 v - - 100 na zero gate voltage drain current i dss v ds = 60 v, v gs = 0 v - - 25 a v ds = 48 v, v gs = 0 v, t j = 150 c - - 250 drain-source on-state resistance r ds(on) v gs = 10 v i d = 12 a b - - 0.050 forward transconductance g fs v ds = 25 v, i d = 12 a b 9.2 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 1200 - pf output capacitance c oss - 600 - reverse transfer capacitance c rss - 100 - drain to sink capacitance c f = 1.0 mhz - 12 - total gate charge q g v gs = 10 v i d = 30 a, v ds = 48 v see fig. 6 and 13 b --46 nc gate-source charge q gs --11 gate-drain charge q gd --22 turn-on delay time t d(on) v dd = 30 v, i d = 30 a r g = 12 , r d = 1.0 , see fig. 10 b -13- ns rise time t r - 100 - turn-off delay time t d(off) -29- fall time t f -52- internal drain inductance l d between lead, 6 mm (0.25") from package and center of die contact -4.5- nh internal source inductance l s -7.5- drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode --20 a pulsed diode forward current a i sm --80 body diode voltage v sd t j = 25 c, i s = 20 a, v gs = 0 v b --1.6v body diode reverse recovery time t rr t j = 25 c, i f = 30 a, di/dt = 100 a/s b - 120 230 ns body diode reverse recovery charge q rr - 0.70 1.4 c forward turn-on time t on intrinsic turn-on time is neglig ible (turn-on is dominated by l s and l d ) d s g s d g
document number: 91188 www.vishay.com s09-0010-rev. a, 19-jan-09 3 irfiz34g, sihfiz34g vishay siliconix typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics, t c = 25 c fig. 2 - typical output characteristics, t c = 175 c fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature
www.vishay.com document number: 91188 4 s09-0010-rev. a, 19-jan-09 irfiz34g, sihfiz34g vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area
document number: 91188 www.vishay.com s09-0010-rev. a, 19-jan-09 5 irfiz34g, sihfiz34g vishay siliconix fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f
www.vishay.com document number: 91188 6 s09-0010-rev. a, 19-jan-09 irfiz34g, sihfiz34g vishay siliconix fig. 12a - unclamped inductive test circuit fig. 12b - unclamped inductive waveforms fig. 12c - maximum avalanche energy vs. drain current fig. 13a - basic gate charge waveform fig. 13b - gate charge test circuit r g i as 0.01 t p d.u.t l v ds + - v dd 10 v v ary t p to o b tain re qu ired i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + -
document number: 91188 www.vishay.com s09-0010-rev. a, 19-jan-09 7 irfiz34g, sihfiz34g vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91188 . p. w . period di/dt diode reco v ery d v /dt ripple 5 % body diode for w ard drop re-applied v oltage re v erse reco v ery c u rrent body diode for w ard c u rrent v gs = 10 v * v dd i sd dri v er gate dri v e d.u.t. i sd w a v eform d.u.t. v ds w a v eform ind u ctor c u rrent d = p. w . period + - + + + - - - * v gs = 5 v for logic le v el de v ices peak diode recovery dv/dt test circuit v dd ? d v /dt controlled b y r g ? dri v er same type as d.u.t. ? i sd controlled b y d u ty factor "d" ? d.u.t. - de v ice u nder test d.u.t. circ u it layo u t considerations ? lo w stray ind u ctance ? gro u nd plane ? lo w leakage ind u ctance c u rrent transformer r g
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