View ADN2850_7858970.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

nonvolatile memory, dual 1024 - position digital resistor data sheet ADN2850 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. tra demarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2004 C 2012 analog devices, inc. all rights reserved. features dual - channel, 1024 - position resolution 25 k? , 250 k ? nominal resistance maximum 8% nominal resistor tolerance error low temperature coefficient: 35 ppm/c 2.7 v to 5 v single supply or 2.5 v dual supply current monitoring configurable function s pi - compatible serial interface nonvolatile memory stores wiper settings power - on refreshed with eemem settings permanent memory write protection resistance tolerance stored in eemem 26 bytes extra nonvolatile memory for user - defined information 1m program ming cycles 100- year typical data retention applications sonet, sdh, atm, gigabit ethernet, dwdm laser diode driver, optical supervisory systems mechanical rheostat replacement instrumentation gain adjustment programmable filters, delays, time constants se nsor calibration general description the ADN2850 is a dual - channel, nonvolatile memory 1 , digitally controlled resistors 2 with 1024 - step resolution , offering guaranteed maximum low resistor tolerance error of 8% . the device performs the same electronic adj ustment function as a mechanical rheostat with enhanced resolution, solid state reliability, and superior low temperature coefficient performance. the versatile programming of the ADN2850 via a n spi ? - compatible serial interface allows 16 modes of operation and adjustment including scratchpad programming, memory storing and restoring, increment/decrement, 6 db/step log taper adjustment, wiper setting readback, and extra eemem 1 for user - defined information such as memory data for other components, look - up ta ble, or system identification information. functional block dia gram addr decod e ADN2850 rdac1 serial interf ace cs clk sdi sdo pr wp rdy rdac1 regis ter eemem1 current monit or eemem2 26 bytes rt ol* user eemem power-on reset w1 b1 rdac2 w2 b2 v dd v 1 v 2 eemem control *r wb full scale t olerance. 0266 0-00 1 v ss gnd rdac1 register i 1 i 2 figure 1. in the scratchpad programming mode, a specific setting can be programmed directly to the rdac 2 register, which sets the resistance between terminal w and terminal b . this setting can be stored into the eemem and is restored automatically to the rdac register during system power - on. the eemem content can be restored dynamically or through external e e aa strobing, and a a a wp e e aa function protects eemem contents. to simplify the programming, the independent or simultaneous linear - step increment or decrement commands can be used to move the rdac wiper up or down, one step at a time. for logarithmic 6 db changes i n the wiper setting, the left or right bit shift command can be used to double or hal ve the rdac wiper setting. pr the ADN2850 patterned resistance tolerance is stored in the eemem. the actual full scale resistance can, therefore, be known by the host proces sor in readback mode. the host can execute the appropriate resistance step through a software routine that simplifies open - loop applications as well as precision calibration and tolerance matching applications. the ADN2850 is available in the 5 mm 5 mm 1 6 - lead frame chip scale lfcsp and thin , 16 - lead tssop package. the part is guaranteed to operate over the extended industrial temperature range of ?40c to +85c. 1 the terms nonvolatile memory and eemem are used interchangeably. 2 the terms digital resist or and rdac are used interchangeably.
ADN2850 data sheet rev. e | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 25 k?, 250 k? ve rsions ............... 3 interface timing and eemem reliability ch aracteristics 25 k?, 250 k? versions ............................................................... 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configuration and function descriptions ............................. 8 typical performance characteristics ........................................... 10 test circuits ................................................................................. 12 theory of operation ...................................................................... 13 scratchpad and eemem programming .................................. 13 basic operation .......................................................................... 13 eemem protection .................................................................... 14 digital input and output configuration ................................. 14 serial data interface ................................................................... 14 daisy - chain operation ............................................................. 14 terminal voltage operating range ......................................... 15 advanced control modes ......................................................... 17 rdac structure .......................................................................... 18 programming the variable resistor ......................................... 19 programming examples ............................................................ 19 e va l - ADN2850sdz evaluation kit ....................................... 20 applications information .............................................................. 21 gain control compensation .................................................... 21 programmable low - pass filter ................................................ 21 prog rammable oscillator .......................................................... 21 optical transmitter calibration with adn2841 ................... 22 incoming optical power monitoring ...................................... 22 resistance scaling ...................................................................... 23 resistance tolerance, drift, and temperature coefficient mismatch considerations ......................................................... 24 rdac circuit simulation model ............................................. 24 outline dimensions ....................................................................... 25 ordering guide .......................................................................... 25 revision history 6 /1 2 rev. d to rev. e changes to table 1 conditions ....................................................... 4 removed positive supply current rdy and/or sdo floating parameters and negative supply current rdy and/or sdo floating parameters, table 1 ........................................................... 4 updated outline dimensions ....................................................... 25 added endno te 2 to ordering guide .......................................... 25 4/11 rev. c to rev. d changes to figure 10 ...................................................................... 10 4 /11 r ev . b to r ev . c updated format .................................................................. universal changes to eemem performance ................................... universal changes to features section ............................................................ 1 changes to applications section .................................................... 1 changes to general description sec tion ...................................... 1 changes to figure 1 .......................................................................... 1 changes to specifications section .................................................. 3 changes to table 2 ............................................................................ 5 changes to absolute maximum ratings section ......................... 7 changes to pin configuration and function descriptions section ................................................................................................ 8 changes to typical performance characteristics section ........ 10 a dded figure 15, figure 16, figure 17 ........................................ 11 changes to figure 21 ...................................................................... 12 changes to theory of operation section .................................... 13 changes to figure 25 ...................................................................... 14 changes to programming variable resister section ................. 19 changes to table 13 ....................................................................... 19 changes to eval - ADN2850ebz evaluation kit section ........ 2 0 added gain control compensation section .............................. 21 added programmable low - pass filter section .......................... 21 added programmable oscillator section .................................... 21 added resistance tolerance, drift, and temperature coeffcient mistmatch considerations section .............................................. 24 changes to outline dimensi ons section .................................... 25 changes to ordering guide .......................................................... 25 9 /0 2 r ev . a to r ev . b changes to general description ..................................................... 1 changes to electrical characteristics ............................................. 2 changes to calculating actual full - scale resistance section ..... 9 changes to table vi .......................................................................... 9 updated o utline dimensions ....................................................... 18
data sheet ADN2850 rev. e | page 3 of 28 specifications electrical character istics 25 k ?, 250 k ? versions v dd = 2.7 v to 5.5 v, v ss = 0 v; v dd = 2.5 v, v ss = ? 2.5 v, v a = v dd , v b = v ss , ?40c < t a < +85c, unless otherwise noted. these specifications apply to versions with a date code 1 2 0 9 or lat er. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode (all rdacs) resolution n 10 resistor differential nonlinearity 2 r - dnl r wb ? 1 +1 lsb resistor integral nonlinearity 2 r - inl r wb ? 2 +2 lsb nominal resistor tolerance ? r w b /r w b code = full scale ? 8 + 8 % resistance temperature coefficient 3 (? r w b /r w b )/ ? t 10 6 code = full scale 35 ppm/c wiper resistance r w c ode = half scale v dd = 5 v 30 60 ? v dd = 3 v 50 ? nominal resistance match 3 r wb1 /r wb2 code = full scale 0.1 % resistor terminals terminal voltage range 3 v b , v w v ss v dd v capacitance bx 3 c b f = 1 mhz, measured to gnd, code = half - scale 11 pf capacitance wx 3 c w f = 1 mhz, measured to gnd, code = half - scale 80 pf common - mode leakage current 3 , 4 i cm v w = v dd /2 0.01 1 a digital inputs and outputs input logic 3 high v ih v dd = 5 v 2.4 v v dd = 2.7 v 2.1 v v dd = +2.5 v, v ss = ? 2.5 v 2.0 v low v il v dd = 5 v 0.8 v v dd = 2.7 v 0.6 v v dd = +2.5 v, v ss = ? 2.5 v 0.5 v output logic high (sdo, rdy) v oh r pull - up = 2.2 k ? to 5 v (see figure 25 ) 4.9 v output logic low v ol i ol = 1.6 ma, v logic = 5 v (see figure 25 ) 0.4 v input current i il v in = 0 v or v dd 1 a input capacitance 3 c il 5 pf power supplies single - supply power range v dd v ss = 0 v 2.7 5.5 v dual - supply powe r range v dd /v ss 2.25 2.75 v positive supply current i dd v ih = v dd or v il = gnd 2 5 a negative supply current i ss v dd = +2.5 v, v ss = ? 2.5 v v ih = v dd or v il = gnd ? 4 ? 2 a eemem store mode current i dd (store) v ih = v dd or v il = gnd, v ss = gnd, i ss 0 2 ma i ss (store) v dd = +2.5 v, v ss = ?2.5 v ?2 ma eemem restore mode current 5 i dd (restore) v ih = v dd or v il = gnd, v ss = gnd, i ss 0 320 a i ss (restore) v dd = +2.5 v, v ss = ?2.5 v ?320 a power dissipation 6 p diss v ih = v dd or v il = gnd 10 30 w power supply sensitivity 3 p ss ? v dd = 5 v 10% 0.006 0.01 %/%
ADN2850 data sheet rev. e | page 4 of 28 parameter symbol conditions min typ 1 max unit current monitor te rminals current sink at v 1 i 1 0.0001 10 ma current sink at v 2 i 2 0.0001 10 ma dynamic characteristics 3 , 7 resistor noise density e n_wb code= full scale r wb = 25 k ? /250 k ? , t a = 25c 20/64 nv/ hz analog crosstalk c t v bx = gnd, measured v w1 with v w2 = 1 v rms , f = 1 khz, code 1 = midscale, code 2 = midscale, r wb = 25 k ? /250 k ? ?95/?80 db 1 typical s represent average readings at 25 c and v dd = 5 v. 2 resistor position nonlinearity error ( r - inl ) is the devia tion from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. t he maximum current in each code is defined by i wb = (v dd ? 1) /r wb . (s ee figure 20) . 3 guaranteed by design and not subject to production test. 4 common - mode leakage current is a measure of the dc leakage from any t erminal b, or t erminal w to a common - mode bias level of v dd /2. 5 eemem restore mode current is not continuous. current is consumed while eemem locations are read and transferred to the rdac register. 6 p diss is calculated from (i dd v dd ) + (i ss v ss ). 7 all dynamic characteristics use v dd = +2.5 v and v ss = ? 2.5 v.
data sheet ADN2850 rev. e | page 5 of 28 interface timing and eemem reliability ch aracteristics 25 k ?, 250 k ? versions guaranteed by design and no t subject to production test. see the timing diagrams section for the location of measured values. all input control voltages are specified with t r = t f = 2.5 ns (10% to 90% of 3 v) and timed from a voltage level of 1.5 v. switch ing characteristics are measured using both v dd = 3 v and v dd = 5 v. table 2 . parameter symbol conditions min typ 1 max unit clock cycle time (t cyc ) t 1 20 ns e e aa setup time cs t 2 10 ns clk shutdown time to a a cs e e aa rise t 3 1 t cyc input clock pulse width t 4 , t 5 clock level high or low 10 ns data setup time t 6 from positive clk transition 5 ns data hold time t 7 from positive clk transition 5 ns a a cs e e aa to sdo - spi lin e acquire t 8 40 ns a a cs e e aa to sdo - spi line release t 9 50 ns clk to sdo propagation delay 10f 2 t 10 r p = 2.2 k ? , c l < 20 pf 50 ns clk to sdo data hold time t 11 r p = 2.2 k ? , c l < 20 pf 0 ns a a cs e e aa high pulse width 11f 3 t 12 10 ns a a cs e e a a high to a a cs e e aa high 3 t 13 4 t cyc rdy rise to a a cs e e aa fall t 14 0 ns a a cs e e aa rise to rdy fall time t 15 0.15 0.3 ms store eemem time 12f 4 , 13f 5 t 16 applies to instructions 0x2, 0x3 15 50 ms read eemem time 4 t 16 applies to instruc tions 0x8, 0x9, 0x10 7 30 s a a cs e e aa rise to clock rise/fall setup t 17 10 ns preset pulse width (asynchronous) 14f 6 t prw 50 ns preset response time to wiper setting 6 t presp a a pr e e aa puls ed low to refresh wiper positions 30 s power - on eemem restore time 6 t eemem 30 s flash/ee memory reliability endurance 15f 7 t a = 25c 1 mcycles 100 kcycles data retention 16f 8 100 years 1 typicals rep resent average readings at 25 c and v dd = 5 v. 2 propagation delay depends on the value of v dd , r pull - up , and c l . 3 valid for commands that do not activate the rdy pin. 4 rdy pin low only for instruction 2, instruction 3, instruction 8, instruction 9, ins truction 10, and the pr hardware pulse: cmd_8 ~ 20 s; cmd_9, cmd_10 ~ 7 s; cmd_2, cmd_3 ~ 15 ms, pr hardware pulse ~ 30 s. 5 store eemem time depends on the temperature and eemem write cycles. higher timing is exp ecte d at lower temperature and high er write cycles. 6 not shown in figure 2 and figure 3 . 7 e ndurance is qualified to 100,000 cycles per jedec standard 22, method a117 and measured at ? 40 c, +25 c, and +85 c. 8 retention lifetime equivalent at junction temperature ( t j ) = 85c per jedec standard 22, method a117. retention lifetime based on an activation energy of 1 ev derate s with junction temperature in the flash/ee memory.
ADN2850 data sheet rev. e | page 6 of 28 timing diagra ms cpol = 1 t 12 t 13 t 3 t 17 t 9 t 1 1 t 5 t 4 t 2 t 1 clk t 8 b24* b23 (msb) b0 (lsb) b23 (msb) high or low high or low b23 b0 b0 (lsb) rd y cpha = 1 t 10 t 7 t 6 t 14 t 15 t 16 *the extra bit tha t is not defined is normall y the lsb of the character previousl y transmitted. the cpol = 1 microcontroller command aligns the incoming da t a t o the positive edge of the clock. sdo sdi cs 02660-002 figure 2 . cpha = 1 timing diagram t 12 t 13 t 3 t 17 t 9 t 1 1 t 5 t 4 t 2 t 1 clk cpo l = 0 t 8 b23 (msb out) b0 (lsb) sdo b23 (msb in) b23 b0 high or low h ig h o r l o w b0 (lsb) sdi rdy cpha = 0 t 10 t 7 t 6 t 14 t 15 t 16 *the extra bit tha t is not defined is normall y the msb of the character just received. the cpol = 0 microcontroller command aligns the incoming da t a t o the positive edge of the clock. * cs 02660-003 figure 3 . cpha = 0 timing diagram
data sheet ADN2850 rev. e | page 7 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 3 . parameter rating v dd to gnd C 0 .3 v to +7 v v ss to gnd +0.3 v to ? 7 v v dd to v ss 7 v v b , v w to gnd v ss ? 0.3 v to v dd + 0.3 v i b , i w pulsed 0f 0f 1 20 ma continuous 2 ma digital input and output voltage to gnd ? 0.3 v to v dd + 0.3 v operating temperature range 1f 1f 2 ? 40c to +85c m aximum junction temperature (t j max) 150c storage temperature range ? 65c to +150c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c thermal resistance junction -to - ambient ja ,tssop - 16 150c/w junction -to - ambient ja ,lfscp - 16 35c/w junction - to - case jc , tssop - 16 28c/w package power dissipation (t j max ? t a )/ ja 1 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 includes programming of nonvolatile memory. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operatio n of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ADN2850 data sheet rev. e | page 8 of 28 pin configuration an d function descripti ons sdi sdo gnd v1 v ss w1 clk b1 cs pr wp v dd v2 w2 b2 rdy 1 2 3 4 5 6 7 8 16 15 14 13 12 1 1 10 9 ADN2850 t op view (not to scale) 02660-005 figure 4 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 clk serial input register clock. shifts in one bit at a time on positive clock edges. 2 sdi serial data input. shifts in one bit at a time on positive clock clk edges. msb loads first. 3 sdo serial data output. serves readback and daisy - chain functions. command 9 and command 10 activate the sdo output for the readbac k function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and after the data - word (see figure 2 and figure 3 ) . in other commands, the sdo shifts out the previously loaded sdi bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (s ee figure 2 and figure 3 ). this pre viously shifted out sdi can be used for daisy - chaining multiple devices. whenever sdo is used, a pull -up resistor in the range of 1 k ? to 10 k? is needed. 4 gnd ground pin, logic ground reference. 5 v ss negative supply. connect to 0 v for single - supply applications. if v ss is used in dual supply, it must be able to sink 2 ma for 15 ms when storing data to eemem. 6 v 1 log o utput v olta ge 1 . generates voltage from an internal diode configured transistor . 7 w1 wiper t erminal of rdac1. addr (rdac1) = 0x0. 8 b1 terminal b of rdac1. 9 b2 terminal b of rdac2. 10 w2 wiper terminal of rdac2. addr (rdac2) = 0x1. 11 v 2 log o utput v oltage 2 . generates voltage from an internal diode configured transistor . 12 v dd positive power supply. 13 a a wp e e optional write protect. when active low, a a wp e e aa prevents any changes to the present contents, except a a pr e e aa strobe. cmd_1 and comd_8 refresh the rdac register from eemem. tie a a wp e e aa to v dd , if not used. 14 a a pr e e optional hardware override preset. refreshes the scratchpad register with current contents of the eemem reg ister. factory default loads midscale 512 10 until eemem is loaded with a new value by the user. a a pr e e aa is activated at the logic high transition. tie a a pr e e aa to v dd , if not used. 15 a a cs e e serial register chip select active low. serial register operation takes place when a a cs e e aa returns to logic high. 16 rdy ready. active high open - drain output. identifies completion of instruction 2, instruction 3, instruction 8, instruction 9, instructio n 10, and a a pr e e aa .
data sheet ADN2850 rev. e | page 9 of 28 pin 1 indicator 1 sdo 2 gnd 3v ss 4v 1 11 wp 12 pr 10 v dd 9v 2 5 w 1 6 b 1 7 b 2 8 w 2 1 5 c l k 1 6 s d i 1 4 r d y 1 3 c s a dn2850 notes 1. the exposed pad is left floating or is tied to v ss . top view (not to scale) (exposed pad) 02660-105 figure 5. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 sdo serial data output. serves readback and daisy-chain functions. command 9 and command 10 activate the sdo output for the readback function, delayed by 24 or 25 cloc k pulses, depending on the clock polarity before and after the data-word (see figure 2 and figure 3). in othe r commands, the sdo shifts o ut the previously loaded sdi bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see figure 2 and figure 3). this previously shifted out sdi can be used for daisy-chaining multiple devices. whenever sdo is used, a pull-up resistor in the range of 1 k to 10 k is needed. 2 gnd ground pin, logic ground reference. 3 v ss negative supply. connect to 0 v for single-supply applications. if v ss is used in dual supply, it must be able to sink 2 ma for 15 ms when storing data to eemem. 4 v1 log output voltage 1. generates voltage from an internal diode configured transistor. 5 w1 wiper terminal of rdac1. addr (rdac1) = 0x0. 6 b1 terminal b of rdac1. 7 b2 terminal b of rdac2. 8 w2 wiper terminal of rdac2. addr (rdac2) = 0x1. 9 v2 log output voltage 2. generates voltage from an internal diode configured transistor. 10 v dd positive power supply. 11 a wp e optional write protect. when active low, a wp e a prevents any changes to the present contents, except a pr e a strobe. cmd_1 and comd_8 refresh the rdac register from eemem. tie a wp e a to v dd , if not used. 12 a pr e optional hardware override preset. refreshes the scra tchpad register with current contents of the eemem register. factory default loads midscale until eemem is loaded with a new value by the user. a pr e a is activated at the logic high transition. tie a pr e a to v dd , if not used. 13 a cs e serial register chip select active low. serial register operation takes place when a cs e a returns to logic high. 14 rdy ready. active high open-drain output. identifies completi on of instruction 2, instruction 3, instruction 8, instruction 9, instruction 10, and a pr e a . 15 clk serial input register clock. shifts in one bit at a time on positive clock edges. 16 sdi serial data input. shifts in one bit at a time on positive clock clk edges. msb loads first. ep exposed pad. the exposed pad is left floating or is tied to v ss .
ADN2850 data sheet rev. e | page 10 of 28 typical performance characteristics digital code 0 200 400 600 1000 inl error (lsb) 800 0.20 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 ?40c +25c +85c 02660-008 figure 6. r - inl vs. code, t a = ? 40c, +25c, +85 c overlay, r ab = 25 k ? digital code 0 200 400 600 1000 dnl error (lsb) 800 0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 02660-009 ?40c +25c +85c figure 7. r - dnl vs. code, t a = ? 40c, +25c, +85c overlay, r ab = 25 k ? 02660-0 1 1 code (decimal) rheostat mode tempco (ppm/c) 200 180 160 140 120 100 80 60 40 20 0 0 1023 768 512 256 25k? 250k? figure 8. ( ? r wb /r wb )/ ?t 10 6 rheostat mode tempco code (decimal) 0 200 400 800 600 1000 wiper on resistance (?) 60 50 40 30 20 10 0 2.7v 3.0v 3.3v 5.0 v 5.5v 02660-012 figure 9 . wiper on resi stance vs. code temper ature (c) ?40 ?20 0 25 40 60 85 i dd /i ss (a) 3 ? 3 ? 2 ? 1 0 1 2 i dd = 2.7v i dd = 3.3v i dd = 3.0v i dd = 5.5v i dd = 5.0v i ss = 2.7v i ss = 3.3v i ss = 3.0v i ss = 5.5v i ss = 5.0v 02660-013 figure 10 . i dd vs. temperature, r ab = 25 k ? frequency (mhz) 1 10 9 8 7 6 5 4 3 2 i d d ( a ) 50 10 20 30 40 0 full scale midscale zero scale 02660-014 figure 11 . i dd vs. clock frequency
data sheet ADN2850 rev. e | page 11 of 28 0 100 200 300 400 i dd (a) vdio (v) 2.7v 3.0v 3.3v 5.0v 5.5v 02660-0 15 0 1 2 3 4 5 figure 12 . i dd vs d igital i nput v oltage frequency (hz) 10 100 1k 10k 100k 1m psrr (db) ?80 ?60 ?70 ?50 ?40 ?30 ?20 ?10 0 r ab = 250k? r ab = 25k? 02660-019 v dd = 5v 10% ac v ss = 0v, i w (25k) = 200a i w (250k) = 20a, v b = 0v measured at v w with code = 0x200 t a = 25c figure 13 . psrr vs. frequency 02660-020 v dd = 5v i w = 200a v b = 0v t a = 25c 1v/div 10s/div v dd v w (full scale) figure 14 . power - on reset 2.5982 2.5975 2.5970 2.5965 2.5960 2.5955 2.5950 2.5945 2.5940 2.5935 2.5930 2.5925 2.5920 2.5915 2.5910 2.5905 2.5900 2.5895 2.5890 2.5885 2.5880 2.5873 ?19.8 ?10 0 10 20 30 40 50 60 70 80 02660- 1 15 volt age (v) time (s) v dd = 5v v ss = gnd v b = v ss i w = 200a figure 15 . midscale glitch energy, r ab = 25 k ?, code 0x200 to code 0x1ff 2.2492 2.2490 2.2485 2.2425 0 50 ?39.8 100 150 200 250 300 02660- 1 16 volt age (v) time (s) 2.2480 2.2475 2.2470 2.2465 2.2460 2.2455 2.2450 2.2445 2.2440 2.2435 2.2430 360 v dd = 5v v ss = gnd v b = v ss i w = 20a figure 16 . midscale glitch energy, r ab = 250 k ?, code 0x200 to code 0x1ff 2.80 2.50 0.8 0.7 0.9 1.0 1.1 1.2 1.3 1.4 1.5 02660-117 time (s) 2.75 2.70 2.65 wiper voltage (v) 2.60 2.55 v dd = 5v v ss = gnd v b = gnd i w (25k) = 200a i w (250k) = 20a figure 17 . digital f eedthrough
ADN2850 data sheet rev. e | page 12 of 28 02660-023 cs (5v/di v) clk (5v /di v) sdi (5v/d iv) i dd (2ma/d iv) v dd = 5v t a = 25c figure 18 . i dd vs. time when storing data to eemem code (decimal) 02660-025 100 1 0.01 1023 theorectical (i wb_max ? ma) 0.1 10 896 768 640 512 384 128 256 0 t a = 25c r wb = 25k? r wb = 250k? figure 19 . i wb_max vs. code test circuits figure 20 to figure 24 define the test conditions used in the specifications section. w b i w d u t v m s 02660-026 figure 20 . resistor position nonlinearity error (rheostat operation; r - inl , r - dnl) w b i w = v dd /r no m inal v ms1 v w r w = v ms1 /i w 02660-028 figure 21 . wiper resistance w b v ms v+ = v dd 10% psr r (db ) = 20 log v d d ( ) ~ v d d pss (% /% ) = v+ v ms v d d % v ms % 02660-029 i w = v dd /(r no m inal / 2) c od e = m id sc ale figure 22 . power supply sensitivity (pss, psrr) + ? dut 0.1v v ss t o v dd r sw = 0.1v i sw i sw w b 0266 0-03 3 figure 23 . incremental on resistance dut v s s i c m w b v d d nc v c m gnd nc = no connect 02660-0 34 figure 24 . commo n - mode leakage current
data sheet ADN2850 rev. e | page 13 of 28 theory of operation the ADN2850 digital programmable resistor is designed to operate as a true variable resistor. the resistor wiper position is determined by the rdac register contents. the rdac register acts as a scratchpad re gister, allowing unlimited changes of resistance settings. the scratchpad register can be programmed with any position setting using the standard spi serial interface by loading the 24 - bit data - word. in the format of the data - word, the first four bits are commands, the following four bits are addresses, and the last 16 bits are data. when a specified value is set, this value can be stored in a corresponding eemem register. during subsequent power - up s , the wiper setting is automatically loaded to that value. storing data to the eemem register takes about 15 ms and consumes approximately 2 ma. during this time, the shift register is locked, preventing any changes from taking place. the rdy pin pulses low to indicate the completion of this eemem storage. there are also 13 addresses with two bytes each of user - defined data that can be stored in the eemem register from a ddress 2 to a ddress 1 4 . the following instructions facilitate the programming needs of the user (see table 8 for detail s): 0. do nothing. 1. restore eemem content to rdac. 2. store rdac setting to eemem. 3. store rdac setting or user data to eemem. 4. decrement by 6 db. 5. decrement all by 6 db. 6. decrement by one step. 7. decrement all by one step. 8. reset eemem content to rdac. 9. read eemem conte nt from sdo. 10. read rdac wiper setting from sdo. 11. write data to rdac. 12. increment by 6 db. 13. increment all by 6 db. 14. increment by one step. 15. increment all by one step. table 14 to table 20 provide programming e xamples that use some of these commands. scratchpad and eemem programming the scratchpad rdac register directly controls the position of the digital resistor wiper. for example, when the scratchpad register is loaded with all 0 s, the wiper is connected to te rm in a l b of the variable resistor. the scratchpad register is a standard logic register with no restriction on the number of changes allowed, but the eemem registers have a program erase/write cycle limitation. basic operation the basic mode of setting the variable resistor wiper position (programming the scratchpad register) is accomplished by loading the serial data input register with instruction 11 (0xb), address 0, and the desired wiper position data. when the proper wiper position is determined, th e user can load the serial data input register with instruction 2 (0x2), which stores the wiper position data in the eemem register. after 1 5 ms, the wiper position is permanently stored in nonvolatile memory. table 6 provides a programming example listing the sequence of the serial data input (sdi) words with the serial data output appearing at the sdo pin in hexadecimal format. table 6 . write and store rdac settings to eemem registers sdi sdo action 0xb 00100 0xxxxxxx writes data 0x100 to the rdac1 register, wiper w1 moves to 1/4 full - scale position. 0x20xxxx 0xb00100 stores rdac1 register content into the eemem1 register. 0xb10200 0x20xxxx writes d ata 0x200 to the rdac2 register, wiper w2 moves to 1/2 full - scale position. 0x21xxxx 0xb10200 stores rdac2 register contents into the eemem2 register. at system power - on, the scratchpad register is automatically refreshed with the value previously stored in the corresponding eemem register. the factory - prese t eemem value is midscale. the scratchpad register can also be refreshed with the contents of the eemem register in three different ways. first, executing instruction 1 (0x1) restores the corresponding eemem value. second, executing instruction 8 (0x8) res ets the eemem values of both channels . finally, pulsing the e e aa pin refreshes both eemem settings. operating the hardware control a a pr e e aa function requires a complete pulse signal. when a a pr e e aa goes low, the internal logic sets the wiper at midscale. the eemem value is not loaded until a a pr e e aa returns high. pr
ADN2850 data sheet rev. e | page 14 of 28 eemem protection the write protect ( a a wp e e aa ) pin disables any changes to the scratchpad register contents, except for the eemem setting, which can still be restored using instruction 1, instruction 8, and the a a pr e e aa pulse. therefore, a a wp e e aa can be used to provide a hardware eemem protection feature. digital input and output configuration all digital inputs are esd protected, high input impedance that can be driven directly from most digital sources. active at logic low, a a pr e e aa and a a wp e e aa must be tied to v dd , if they are not used. no internal pull - up resis tors are present on any digital input pins. to avoid floating digital pins that might cause false triggering in a noisy environment, add pull - up resistors. this is applicable when the device is detached from the driving source when it is programmed. the s do and rdy pins are open - drain digital outputs that only need pull - up resistors if these functions are used. to optimize the speed and power trade - off, use 2.2 k? pull - up resistors. the equivalent serial data input and output logic is shown in figure 25 . the open - drain output sdo is disabled whenever chip - select ( a a cs e e aa ) is in logic high. esd protection of the digital inputs is shown in figure 26 and figure 27. v alid command counter command pr ocessor and address decode (for daisy chain onl y) serial register clk sdi 5v r pull-up sdo gnd pr wp ADN2850 cs 02660-037 figure 25 . equivalent digital input and output logic logic pins v dd gnd inputs 300? 02660-038 figure 26 . equivalent esd digital input protection v d d gn d in pu t 3 00? wp 02660-039 figure 27 . equivalent a a wp e e aa input protection serial data interface the ADN2850 contains a 4 - wire spi - compatible digital interface (sdi, sdo, a a cs e e aa , and clk). the 24 - bit serial data - word must be loaded with msb first. the format of the word is shown in table 7 . the command bits (c0 to c3) control the operation of the digital resistor according to the command shown in table 8 . a0 to a3 are the address bits. a0 is used to address rdac1 or rdac2. address 2 to address 14 are accessible by u sers for extra eemem. address 15 is reserved for factory usage. table 10 provides an address map of the eemem locations. d0 to d9 are the values for the rdac registers. d0 to d15 are the values for the eemem registers. the adn28 50 has an internal counter that counts a multiple of 24 bits (a frame) for proper operation. for example, ADN2850 works with a 24 - bit or 48 - bit word, but it cannot work properly with a 23 - bit or 25 - bit word. to prevent data from mislocking (due to noise, f or example), the counter resets, if the count is not a multiple of four when a a cs e e aa goes high but remains in the register if it is multiple of four. in addition, the ADN2850 has a subtle feature that, if a a cs e e aa is pulsed w ithout clk and sdi, the part repeats the previous command (except during power - up). as a result, care mu st be taken to ensure that no excessive noise exists in the clk or a a cs e e aa line that might alter the effective number - of - bits pattern. the spi interface can be used in two slave modes: cpha = 1, cpol = 1 and cpha = 0, cpol = 0. cpha and cpol refer to the control bits that dictate spi timing in the following microconverters ? and microprocessors: aduc812 , aduc824 , m68hc11, mc68hc16r1 , and mc68hc916r1. daisy - chain operation the serial data output pin (sdo) serves two purposes. it can be used to read the contents of the wiper setting and eemem values using instruction 10 and instruction 9, respectively. the remaining instructions ( instruction 0 to instruction 8, instruction 11 to instruction 15) are valid for daisy - chaining multiple devices in simultaneous operations. daisy - chaining minimizes the numbe r of port pins required from the controlling ic ( see figure 28 ). the sdo pin contains an open - drain n - ch fet that requires a pull - up resistor, if this function is used. as shown in figure 28 , users need to tie the sdo pin of one package to the sdi pin of the next package. users m ay need to increase the clock period because the pull - up
data sheet ADN2850 rev. e | page 15 of 28 resistor and the capacitive loading at the sdo - to - sdi interface m ay require additional time delay between subsequent devi ces. when two ADN2850 s are daisy - chained, 48 bits of data are required. the first 24 bits (formatted 4 - bit command, 4 - bit address, and 16 - bit data) go to u2, and the second 24 bits with the same format go to u1. keep a a cs e e aa low until all 48 bits are clocked into their respective serial registers. a a cs e e aa is then pulled high to complete the operation. clk r p 2.2k? sdi sdo u2 cs clk sdi sdo u1 ADN2850 cs v dd scl k ss mo si micro- controller 02660-040 ADN2850 figure 28 . daisy - chain configuration using sdo terminal voltage ope rating range the positive v dd a nd negative v ss power supplies of the ADN2850 define the boundary conditions for proper 2 - terminal digital r esistor operation. supply signals present on te rm i na l b, and terminal w that exceed v dd or v ss are clamped by the internal forward - biased diodes (se e figure 29). v ss v dd w b 02660-041 figure 29 . maximum terminal voltages set by v dd and v ss the gnd pin of the ADN2850 is primarily used as a digital ground reference. to minimize the digital ground bounce, the ADN2850 grou nd terminal should be joined remotely to the common ground (see figure 30 ). the digital input control signals to the ADN2850 must be referenced to the device ground pin (gnd) and must satisfy the logic level defined in the specifications section. an internal level - shift circuit ensures that the common - mode voltage range of the three terminals extends from v ss to v dd , regardless of the digital input level. power - up sequence because there are diodes to li mit the voltage compliance at terminal b, and terminal w ( see figure 29 ), it is important to power v dd and v ss first before applying any voltage to terminal b, and terminal w. otherwise, the diode is forward - biased such that v dd and v ss are powered unintentionally . for example , applying 5 v across terminal w and terminal b prior to v dd causes the v dd terminal to exhibit 4.3 v. it is not destructive to the device, but it might affect the rest of the users system. the ideal power - u p sequence is gnd, v dd and v ss , digital inputs, and v b , and v w . the order of powering v b , v w , and the digital inputs is not important as long as they are powered after v dd and v ss . regardless of the power - up sequence and the ramp rates of the power suppl ies, when v dd and v ss are powered, the power - on preset activates, which restores the eemem values to the rdac registers. layout and power supply bypassing it is a good practice to employ compact, minimum lead - length layout design. the leads to the input s hould be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is good practice to bypass the power supplies with quality capacitors for optimum stability. bypass s upply leads to th e device with 0.01 f to 0.1 f disk or chip ceramic capacitors. also, apply l ow esr, 1 f to 10 f tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance (see figure 30). ADN2850 v dd gnd v ss c3 10f c4 10f c2 0.1f c1 0.1f + + v dd v ss 02660-042 figure 30 . power supply bypassing
ADN2850 data sheet rev. e | page 16 of 28 in table 7 , command bits are c0 to c3, address bits are a0 to a3, data bit d0 to data bit d9 are applicable to rdac, and d0 to d15 are applicable to eemem. table 7 . 24 - bit serial data - word msb command byte 0 data byte 1 data byte 0 lsb rdac c3 c2 c1 c0 0 0 0 a0 x x x x x x d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 eemem c3 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 command instruction codes are defined in table 8 . table 8 . command operation truth table 17f 1, 18f 2, 19f 3 command number command byte 0 data byte 1 data byte 0 operation b23 b16 b15 b8 b7 b0 c3 c2 c1 c0 a3 a2 a1 a0 x d9 d8 d7 d0 0 0 0 0 0 x x x x x x x x x nop . do nothing. s ee table 19 1 0 0 0 1 0 0 0 a0 x x x x x restore eemem (a0) contents to rdac (a0) register. see table 16 . 2 0 0 1 0 0 0 0 a0 x x x x x store wiper setting . store rdac (a0) setting to eemem (a0). see table 15 . 3 20f 4 0 0 1 1 a3 a2 a1 a0 d15 d8 d7 d0 store contents of serial register data byte 0 and serial register data bytes 1 (total 16 bits) to eemem (addr). see table 18 . 4 21f 5 0 1 0 0 0 0 0 a0 x x x x x decrement by 6 db . right - shift contents of rdac (a0) register, stop at all 0s. 5 5 0 1 0 1 x x x x x x x x x decrement all by 6 db . rig ht- shift contents of all rdac registers, stop at all 0s. 6 5 0 1 1 0 0 0 0 a0 x x x x x decrement contents of rdac (a0) by 1, stop at all 0s. 7 5 0 1 1 1 x x x x x x x x x decrement cont ents of all rdac registers by 1, stop at all 0s. 8 1 0 0 0 0 0 0 0 x x x x x reset . refresh all rdacs with their corresponding eemem previously stored values. 9 1 0 0 1 a3 a2 a1 a0 x x x x x read contents of eemem (addr) from sdo output in the ne xt frame. see table 19 . 10 1 0 1 0 0 0 0 a0 x x x x x read rdac wiper setting from sdo output in the next frame. see table 20 . 11 1 0 1 1 0 0 0 a0 x d9 d8 d7 d0 write contents of serial re gister data byte 0 and serial register data byte 1 (total 10 bits) to rdac (a0). see table 14 . 12 5 1 1 0 0 0 0 0 a0 x x x x x increment by 6 db: left - shift contents of rdac (a0), stop at all 1s . see table 17 . 13 5 1 1 0 1 x x x x x x x x x increment all by 6 db . left - shift contents of all rdac registers, stop at all 1s. 14 5 1 1 1 0 0 0 0 a0 x x x x x increment contents of rdac (a0) by 1, stop at all 1s. see table 15 . 15 5 1 1 1 1 x x x x x x x x x increment contents of all rdac registers by 1, stop at all 1s. 1 the sdo output shifts out the last 2 4 bits of data clocked into the serial register for daisy - chain operation. exception: for any instruction following instruction 9 or instruction 10, the selected internal register data is present in d ata b yte 0 and d ata b yte 1. the instruction s following i nstruction 9 and instruction 10 must also be a full 24- bit data - word to completely clock out the contents of the serial register. 2 the rdac register is a volatile scratchpad register that is refreshed at power - on from the corresponding nonvolatile eemem r egister. 3 execution of these operations takes place when the cs strobe returns to logic high. 4 instruction 3 writes two data bytes (16 bits of data) to eemem. in the case of address 0 and address 1, only the last 10 bits are valid for w iper position setting. 5 the increment, decrement, and shift instructions ignore the contents of the shift register , d ata b yte 0 and d ata byte 1.
data sheet ADN2850 rev. e | page 17 of 28 advanced control mod es the ADN2850 digital resistor includes a set of user programming features to address the wide number of applications for these universal adjustment devices. key programming features include the following : ? scratchpad programming to any desirable values ? nonv olatile memory storage of the scratchpad rdac register value in the eemem register ? increment and decrement instructions for the rdac wiper register ? left and right bit shift of the rdac wiper register to achieve 6 db level changes ? 26 extra bytes of user - ad dressable nonvolatile memory linear increment and decrement instructions the increment and decrement instructions ( instruction 14, instruction 15, instruction 6, and instruction 7) are useful for linear step adjustment applications. these commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the device. the adjustment can be individual or in a ganged resistor arrangement where both wiper positions are changed at the same time. for an i ncrement command, executing instruc tion 14 automati cally moves the wiper to the next resistance segment position. the master increment command, instruction 15, moves all resistor wipers up by one position. logarithmic taper mode adjustment four programmin g instructions produce logarithmic taper increment and decrement of the wiper position control by an individual resistor or by a ganged resistor arrangement where both wiper positions are changed at the same time . the 6 db increment is activated by instru ction 12 and instruction 13, and the 6 db decrement is activated by instruction 4 and instruction 5. for example, starting with the wiper connected to terminal b, executing 11 increment instructions (command instruction 12) moves the wiper in 6 db steps fr om 0% of the r ba (terminal b) position to 100% of the r ba position of the ADN2850 10- bit resistor . when the wiper position is near the maximum setting, the last 6 db increment instruction causes the wiper to go to the full - scale 1023 code position. further 6 db per increment instructions do not change the wiper position beyond its full scale (see table 9 ). the 6 db step increments and 6 db step decrements are achieved by shifting the bit internally to the left or right, respective ly. the following information explains the nonideal 6 db step adjustment under certain conditions. table 9 illustrates the operation of the shifting function on the rdac register data bits. each table row represents a successive shift operation. note that the left - shift 12 and 13 instructions were modified such that, if the data in the rdac register is equal to zero and the data is shifted left, the rdac register is then set to code 1. similarly, if the data in the rdac register is greater than or equal to midscale and the data is shifted left, then the data in the rdac register is automatically set to full scale. this makes the left - shift function as ideal a logarithmic adjustment as possible. the right - shift 4 instruction and r ight - shift 5 instruction are ideal only if the lsb is 0 (ideal logarithmic = no error). if the lsb is 1, the right - shift function generates a linear half - lsb error, which translates to a number - of - bits dependent logarithmic error, as shown in figure 31. figure 31 shows the error of the odd number s of bits for the ADN2850 . table 9 . detail left - shift and right - shift functions for 6 db step increment and decrement left - shift (+6 db/s tep) right - shift( C 6 db/step) 00 0000 0000 11 1111 1111 00 0000 0001 01 1111 1111 00 0000 0010 00 1111 1111 00 0000 0100 00 0111 1111 00 0000 1000 00 0011 1111 00 0001 0000 00 0001 1111 00 0010 0000 00 0000 1111 00 0100 0000 00 0000 0111 00 1000 0000 00 0000 0011 01 0000 0000 00 0000 0001 10 0000 0000 00 0000 0000 11 1111 1111 00 0000 0000 11 1111 1111 00 0000 0000 actual conformance to a logarithmic curve between the data contents in the rdac register and the wiper position for each right - sh ift 4 command and right - shift 5 command execution contains an error only for odd numbers of bits. even numbers of bits are ideal. figure 31 shows plots of log error [20 log 10 (error/code)] for the ADN2850 . for example, code 3 l og error = 20 log 10 (0.5/3) = ?15.56 db, which is the worst case. the log error plot is more significant at the lower codes (see figure 31) . code (from 1 to 1023 by 2.0 10 3 ) 0 gain (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 ?40 ?20 ?60 ?80 02660-043 figure 31 . log error conformance for odd number s of bits o nly (even number s of bits are ideal)
ADN2850 data sheet rev. e | page 18 of 28 using cs to re - execute a previous command another subtle feature of the ADN2850 is that a subsequent a a cs e e aa strobe, without clock and data, repeats a previous command. using additional internal nonvolatile eemem the ADN2850 contains additional user eemem registers for storing any 16 - bit data such as memory data for other components, look - up tables, or system identification information. table 10 pro - vides an address map of the internal storage registers shown in the functional block diagram (see figure 1 ) as eemem1, eemem2, and 26 bytes (13 addresses 2 bytes each) of u ser eemem. table 10 . eemem add ress map eemem no. address eemem content for 1 0000 rdac1 1 2 0001 rdac2 3 0010 user1 2 4 0011 user2 15 1110 user13 16 1111 r w b1 t olerance 3 1 rdac data stored in eemem locations is transferred to the corresponding rdac register at power - on, or when instruc tion 1, instruc tion 8, and a a pr e e aa are executed. 2 userx are internal nonvolatile eemem registers available to store and retrieve constants and other 16 - bit information using instruc tion 3 and instruction 9, respectively. 3 read only. calculating actual end - to - end terminal resistance the resistance tolerance is stored in the eemem register during factory testing. the actual end - to - end resistance can, therefore, be calculated, which is valuable for calibration, tolerance mat ching, and precision applications. note that this value is read only and the r w b2 at full scale matches with r w b1 at full scale , typically 0.1%. the resistance tolerance in percentage is contained in the last 16 bits of data in eemem register 15. the forma t is the sign magnitude binary format with the msb designate for sign (0 = negative and 1 = positive), the next 7 msb designate the integer number, and the 8 lsb designate the decimal number (see table 12). for example, if r w b_ rated = 250 k? and the data in the sdo shows xxxx xxxx 1001 1100 0000 1111, r w b at full scale can be calculated as follows: msb: 1 = p ositive next 7 lsb: 001 1100 = 28 8 lsb: 0000 1111 = 15 2 ?8 = 0.06 % t olerance = 28.06% therefore, r w b at full scale = 3 20.15 k? rdac structure the rdac contains multiple strings of equal resistor segments with an array of analog switches that acts as the wiper connection. the number of positions is the resolution of the device. the ADN2850 has 1024 connection points, allow ing it to provide better than 0.1% setability resolution. figure 32 shows an equivalent structure of the connections among the three terminals of the rdac. the sw b is always on, while t he switches , sw(0) to sw(2 n ? 1) , are on one at a time, depending on the resistance position decoded from the data bits. because the s witch is not ideal, there is a 3 0 ? wiper resistance, r w . wiper resistance is a function of supply voltage and temperature. the lower the supply voltage or the higher the temperature, the higher the resulting wiper resistance. users should be aware of the wiper resistance dynamics, if accurate prediction of the output resistance is needed. sw (1) sw (0) sw b b r s r s sw(2 n ? 1) w sw(2 n ? 2) rd a c wiper register and decoder r s = r wb_nominal /2 n r s digit al circuitr y omitted for clarity 0266 0-04 4 figure 32 . equivalent rdac structure table 11 . nominal individual segment resistor values device resolution 25 k? 250 k ? 1024 - step 24.4 ? 244? table 12 . calculating end -to - end terminal resistance bit d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sign mag sign 2 6 2 5 2 4 2 3 2 2 2 1 2 0 . 2 ?1 2 ?2 2 ?3 2 ?4 2 ?5 2 ?6 2 ?7 2 ?8 7 bits for integer number decimal point 8 bits for decimal number
data sheet ADN2850 rev. e | page 19 of 28 programming the vari able resistor the nominal resistance of the rdac between terminal w and terminal b, r wb , is available with 25 k? and 250 k? with 1024 positions (10 - bit resolution). the final d igits of the part number determine the nominal resistance value, for example, 25 k? = 24.4 ?; 250 k? = 244 ? . the 10 - bit data - word in the rdac latch is decoded to select one of the 1024 possible settings. the following descri ption provid es the calculation of resistance , r wb , at different codes of a 25 k? part. the first connection of the wiper starts at terminal b for d ata 0x000. r wb (0) is 3 0 ? because of the wiper resistance, and it is independent of the nominal resistance. the second connection is the fir st tap point where r wb (1) becomes 24.4 ? + 30 ? = 5 4.4 ? for d ata 0x001. the third connection is the next tap point representing r wb (2) = 48.8 ? + 30 ? = 7 8.8 ? for d ata 0x002, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at r wb (1023) = 2500 6 ?. see figure 32 for a simplified diagram of the equivalent rdac circuit. code (decimal) 100 75 0 0 1023 256 r wb (d) (% r wf ) 512 768 50 25 r wb 02660-045 figure 33 . r wb (d) vs. decimal code the general equation that determine s the programmed output resistance between t erminal bx and terminal wx is w nom wb wb r r d d r + = _ 1024 ) ( (1) where: d is the decimal equivalent of the data contained in the rdac register. r wb_nom i s the nomin al resistance value r w is the wiper resistance. table 13. r wb (d) at selected codes for r w b _nom = 25 k? d (d ec ) r wb (d) ( ? ) output state 1023 25,00 6 full scale 512 12,53 0 midscale 1 5 4.4 1 lsb 0 3 0 zero scale (wiper contact resistor) note that, in the zero - scale condition , a finite wiper resistance of 3 0 ? is present. care should be taken to lim it the current flow between w and b in this state to no more than 20 ma to avoid degradation or possible destruction of the internal switches. the typical distribution of r w b _nom from channel to channel is 0.2% within the same package. device - to - device ma tching is process lot dependent upon the worst case of 30% variation. however, the change in r w b at full scale with temperature has a 35 ppm/c temperature coefficient. programming examples the following programming examples illustrate a typical sequence of events for various features of the ADN2850 . see table 8 for the instructions and data - word format. the instruction numbers, addresses, and data appearing at the sdi and sdo pins are in hexadecimal format. table 14 . scratchpad programming sdi sdo action 0xb00100 0xxxxxxx writes d ata 0x100 into rdac1 register, wiper w1 moves to 1/4 full - scale position. 0xb10200 0xb00100 loads d ata 0x200 into rdac2 register, wiper w2 moves to 1/2 full - scale position. ta ble 15 . incrementing rdac followed by storing the wiper setting to eemem sdi sdo action 0xb00100 0xxxxxxx writes d ata 0x100 into rdac1 register, wiper w1 moves to 1/4 full - scale position. 0xe0xxxx 0xb00100 increments rdac1 regist er by one to 0x101. 0xe0xxxx 0xe0xxxx increments rdac1 register by one to 0x102. continue until desired wiper position is reached. 0x20xxxx 0xxxxxxx stores rdac2 register data into eemem1. optionally , tie a a wp e e aa to gnd to protect ee mem values. the eemem values for the rdacs can be restored by power - on, by strobing the a a pr e e aa pin, or by the two commands shown in table 16. table 16 . restoring the eemem values to rdac registers sdi sdo action 0x10xxxx 0xxxxxxx restores the eemem1 value to the rdac1 register.
ADN2850 data sheet rev. e | page 20 of 28 table 17 . using left - shift by one to increment 6 db steps sdi sdo action 0xc0xxxx 0xxxxxxx moves wiper 1 to double the present dat a contained in the rdac1 register. 0xc1xxxx 0xc0xxxx moves wiper 2 to double the present data contained in the rdac2 register. table 18 . storing additional user data in eemem sdi sdo action 0x32aaaa 0xxxxxxx stores d ata 0xaaaa i n the extra eemem location user1. (allowable to address in 13 locations with a maximum of 16 bits of data.) 0x335555 0x32aaaa stores d ata 0x5555 in the extra eemem location user2. (allowable to address in 13 locations with a maximum of 16 bits of data.) table 19 . reading back data from memory locations sdi sdo action 0x92xxxx 0xxxxxxx prepares data read from user1 eemem location. 0x00xxxx 0x92aaaa nop instruction 0 sends a 24 - bit word out of sdo, where the last 16 bits contain the contents in user1 eemem location. table 20 . reading back wiper settings sdi sdo action 0xb00200 0xxxxxxx writes rdac1 to midscale. 0xc0xxxx 0xb00200 doubles rdac1 from midscale to full scale. 0xa0xxxx 0xc0xxxx prepares re ading wiper setting from rdac1 register. 0xxxxxxx 0xa003ff reads back full - scale value from sdo. eval - ADN2850 sd z evaluation kit analog devices , inc., offers a user - friendly e va l - ADN2850 sd z evaluation kit that can be controlled by a pc in conjunction wit h the dsp platform . the driving program is self - contained; no programming languages or skills are needed.
data sheet ADN2850 rev. e | page 21 of 2 8 applications information gain control compens ation a digital resistor is commonly used in gain control such as the noninverting gain amplifier show n in figure 34. u1 v o r2 250k? v i r1 47k? c1 1 1p f w b c2 2.2pf 02660-047 figure 34 . typical noninverting gain amplifier when the rdac b terminal parasitic capacitance is connected to the op amp noninverting node, it introduces a zero for the 1/ o term with 2 0 db/dec, wh ereas a typical op amp gain bandwidth product (gbp ) has ?20 db/dec characteristics. a large r2 and finite c1 can cause th e frequency of this zero to fall well below the crossover frequency. therefore, the rate of closure becomes 40 db/dec, and the system has a 0 phase margin at the crossover frequency. if an input is a rectangular pulse or step function, t he output can ring or oscillate . similarly, it is also likely to ring when switching between two gain values; this is equivalent to a stop c hange at the input. depending on the op amp gbp, reducing the feedback resistor might extend the frequency of the zero far enough to overcome the problem. a better approach is to include a compensation capacitor, c2, to cancel the effect caused by c1. opt imum compensation occurs when r1 c1 = r2 c2. this is not an option because of the variation of r2. as a result, one can use the previous relationship and scale c2 as if r2 were at its maximum value. doing this might overcompensate and compromise the p erformance when r2 is set at low values. alternatively , it avoids the ringing or oscillation at the worst case. for critical applications, find c2 empirically to suit the oscillation . in general, c2 in the range of a few p icofarads to no more than a few t enths of picofarads is usually adequate for the compensation. similarly, w and a terminal capacitances are connected to the output (not shown); their effect at this node is less significant and the compensation can be avoided in most cases. programmable lo w - pass filter in analog - to - digital conversions (adcs) , it is common to include an antialiasing filter to band limit the sampling signal. therefore, t he dual - channel ADN2850 can be used to construct a second - order sallen - key low - pass filter, as shown in figure 35. b v i ad8601 +2.5v v o adjust ed concur rentl y ?2.5v v+ v? w r r2 r1 b w r c1 c2 u1 02660-055 figure 35 . sallen - key low - pass filter the design equations are 2 2 2 f f f i o s q s v v (10) c2 c1 r2 r1 o 1 z (11) q = c2 r2 1 c1 r1 1 (12) f irst , users should select convenient v alues for the capacitors. to achieve maximally flat bandwidth, where q = 0.707, let c1 be twice the size of c2 and let r1 equal r2. as a result, the user can adjust r1 and r2 concurrently to the same setting to achieve the desirable bandwidth. programmable oscillator in a classic wien bridge oscillator, the wien network (r || c , r'c') provides positive feedback, w hereas r1 and r2 provide negative feedback (see figure 36). d1 d2 op1 177 v+ v? +2.5v + ? ?2.5v v o u1 r2a 2.1k? r2b 10k? b a w r1 1k? amplitude adjustment r = r' = ADN2850 r2b = ad5231 d1 = d2 = 1n4148 r' 25k? a b w c' vp r 25k? b w c 2.2nf frequency adjustment 2.2nf 02660-056 figure 36 . programmable oscillator with amplitude control
ADN2850 data sheet rev. e | page 22 of 28 at the resonant frequency, f o , the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. with r = r ' , c = c ', and r2 = r2a /(r2b + r diode ), the oscillation frequency is rc o 1 = or rc f o = 2 1 (13) where r is equal to r wa such that : w nom wb wb r r d d r + = _ 1024 ) ( (14) at resonance, setting r2/r1 = 2 balances the bridge. in practice, r2/r1 should be set slightly larger than 2 to ensure that the oscillation can start. on the other hand, the alternate turn - on of the diodes , d1 and d2 , ensures that r2/ r1 is smaller than 2, momentarily stabilizing the oscillation. when the frequency is set, the oscillation amplitude can be turned by r2b because d d o v i v + = r2b 3 2 (1 5 ) v o , i d , a nd v d are interdependent variables. with proper selection of r2b, an equilibrium is reached such that v o converges. r2b can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to saturate the output . in figure 35 and figure 36 , the frequency tuning requires that both rdacs be adjusted concurrently to the same settings. because the two channels might be adjusted one at a time, an intermediate stat e occurs that might not be acceptable for some applications. of course, the increment/decrement instructions ( instruction 5, instruction 7, instruction 13, and instruction 15) can all be used. different devices can also be used in daisy - chain mode so that parts can be programmed to the same settings simultaneously. optical transmitter calibration with adn2841 the ADN2850 , together with the multirate 2.7 gbps laser diode driver , adn2841 , forms an optical supervi sory system in which the dual digital resistor can be used to set the laser average optical power and extinction ratio ( see figure 37 ). the ADN2850 is particularly suited for the optical parameter settings because of its high res olution and superior temperature coefficient characteristics. cs clk sdi w1 b1 eemem adn2841 pset erset imodp ibia s impd datap datan clkp clkn clkn clkp datap datan w2 b2 eemem control ADN2850 v cc v cc rdac1 rdac2 02660-057 figure 37 . optical supervisory system the adn2841 is a 2.7 gbps laser diode driver that uses a unique control algorithm to manage the average power and extinction ratio of the laser after its initial factory calibration . the adn2841 stabilizes the data transmission of the laser by continuously monitoring its optical power and correcting the variations caused by temperature and the degradation of the laser over time. in the adn2841 , the impd monitors the laser diode current. through its dual - loop power and extinction ratio control c alibrated by the dual rdacs of the ADN2850 , the internal driver controls the bias current, ibias, and consequently the average power. it also regulates the modulation current, imodp, by changing the modulation current linearly with slope efficiency. theref ore, a ny changes in the laser threshold current or slope efficiency are compensated for . as a result, th e optical supervisory system minimizes the laser characterization efforts and, therefore, enables designers to apply comparable lasers from multiple sou rces. incoming o ptical p ower m onitoring the ADN2850 comes with a pair of matched diode connected pnps, q1 and q2, that can be used to configure an incoming optical power monitoring function. with a reference current source, an instrumentation amplifier, th is feature can be used to m o nitor the optical power by knowing the dc average photodiode current from the following relationships: 1 1 1 1 ln s c t be i i v v v = = (16) 2 2 2 2 ln s c t be i i v v v = = (17) knowing i c1 = 1 i pd , ic 2 = 2 x i ref , and q 1 - q 2 are matched, therefore and i s are matched. combining equation 16 and equation 17 theoretically yields: pd ref t i i v v v ln 1 2 = ? (18)
data sheet ADN2850 rev. e | page 23 of 28 where: i s1 and i s2 are saturation current. v 1 , v 2 are v be , base-emitted voltages of the diode connector transistors. v t is the thermal voltage, which is equal to k t/q (v t = 26 mv @ 25c) k is the boltzmanns constant, 1.38e-23 joules/kelvin. q is the electron charge, 1.6e-19 coulomb. t is the temperature in kelvin. i pd is the photodiode current. i ref is the reference current. figure 38 shows a conceptual circuit. lpf 0.75 bit rate tia ad623 in amp 10nf cdr post amp vt compensation ADN2850 log average power w 1 b 1 b 2 v dd v ss i pd i ref r g w 2 v 1 v 2 q 1 q 2 c prc thermistor data clock log amp gnd ?5v (1 + 100k/r g )(v 1 ?v 2 ) 02660-137 figure 38. conceptual incoming op tical power monitoring circuit the output voltage represents the average incoming optical power. the output voltage of the log stage does not have to be accurate from device to device, as the responsivity of the photodiode will change between devices. an op amp stage is shown after the log amp stage, which compensates for v t variation over temperature. equation 19 is ideal. if the reference current is 1 ma at room temperature, characterization shows that there is an additional 30 mv offset between v 2 and v 1 . a curve fit approximation yields 03.0 001.0 ln026.0 12 ? ?? pd i vv (19) the offset is caused by the transistors self-heating and the thermal gradient effect. as seen in figure 39, the error between an approximation and the actual performance ranges is less than 0% to C4% from 0.1 ma to 0.1 a. 0.30 0.25 0.20 0.15 0.10 0.05 0 12 9 error 6 3 0 ?3 ?6 0.1 1 10 100 1m 02660-138 v 2 ?v 1 (v) approximating error (%) i pd (a) i ref =1ma t a = 25c device 1 device 2 device 3 curve fit figure 39. v 2 C v 1 error versus input current. resistance scaling the ADN2850 offers 25 k or 250 k nominal resistance. when users need lower resistance but must maintain the number of adjustment steps, they can parallel multiple devices. for example, figure 40 shows a simple scheme of paralleling two channels of rdacs. to adjust half the resistance linearly per step, program both rdacs concurrently with the same settings. b1 w1 w2 b2 02660-058 figure 40. reduce resistance by half wi th linear adjustment characteristics figure 40 shows that the digital rheostat change steps linearly. alternatively, pseudo log taper adjustment is usually preferred in applications such as audio control. figure 41 shows another type of resistance scaling. in this configuration, the smaller the r2 with respect to r ab , the more the pseudo log taper characteristic of the circuit behaves. b1 w1 r 02660-060 figure 41. resistor scaling with pseudo log adjustment characteristics the equation is approximated as r r r r wb wb quivalent ??? ? ? 1024200,51 200,51 e (17) users should also be aware of the need for tolerance matching as well as for temperature coefficient matching of the components.
ADN2850 data sheet rev. e | page 24 of 28 res istance tolerance, d rift, and temperature coeffici ent mismatch considerations in operation , such as gain control, the tolerance mismatch between the digital resistor and the discrete resistor can cause repeatability issues among various systems (see figure 42) . because of the inherent matching of the silicon process, it is practical to apply the dual - channel device in this type of application. as such, r1 can be replaced by one of the channels of the digital resistor and programme d to a sp ecific value. r2 can be used for the adjustable gain. although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between r1 and r2. this approach also tracks the resistance drift over time. as a result, these less than ideal parameters become less sensitive to system variations. ad8601 + ? v i u1 v o c1 b w r2 r1 * * replaced with another channel of rdac 02660-061 figure 42 . linear gain control with tracking resistance tolerance, drift, and temperature coefficient rdac circuit simulat ion model the internal parasitic c apacitances and the external capacitive loads dominate the ac characteristics of the rdacs. a parasitic simulation model is shown in figure 43. rdac 25k? w 80pf c b 1 1pf b 02660-063 figure 43 . rdac circuit simulation model (rdac = 25 k?) t he following code provides a macro model net list for the 25 k? rdac: .param d = 1024 , rdac = 25e3 * .subckt dpot ( w, b) * cw w 0 80e - 12 rwb w b {d/1024 * rdac + 50} cb b 0 11e - 12 * .ends dpot
data sheet ADN2850 rev. e | page 25 of 28 outline dimensions compliant to jedec standards mo-220-vggc 05-09-2012- a 1 0.80 bsc pin 1 indic a t or 2.40 ref 0.75 0.60 0.50 t o p view 12 max 0.80 max 0.65 ty p sea ting plane coplanarit y 0.08 1.00 0.85 0.80 0.35 0.30 0.25 0.05 max 0.02 nom 0.20 ref 3.25 3.10 sq 2.95 16 5 1 3 8 9 1 2 4 0.60 max 0.60 max pin 1 indic a t or 5.10 5.00 sq 4.90 4.75 bsc sq exposed pad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.25 min bot t om view figure 44 . 16 - lead lead frame chip scal e package [lfcsp _vq ] 5 5 mm body, very thin quad (cp - 16 - 6) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 45 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters ordering guide mode l 1 , 2 r wb (k ? ) temperature range package description package option ADN2850bruz25 25 ? 40c to +85c 16- lead tssop ru -16 ADN2850bruz25 - rl7 25 ? 40c to +85c 16- lead tssop ru -16 ADN2850bcpz25 25 ? 40c to +85c 16- lead lfcsp_vq cp -16-6 ADN2850bcpz25 - rl7 25 ? 40c to + 85c 16- lead lfcsp _vq cp -16-6 ADN2850bcpz250 250 ? 40c to +85c 16- lead lfcsp_vq cp -16-6 ADN2850bcpz250 - rl7 250 ? 40c to +85c 16- lead lfcsp_vq cp -16-6 eval - ADN2850sdz evaluation board 1 z = rohs compliant part. 2 the evaluation board is shipped with the 25 k ? r wb resistor option; however, the board is compatible with all available resistor value options.
ADN2850 data sheet rev. e | page 26 of 28 notes
data sheet ADN2850 rev. e | page 27 of 28 notes
ADN2850 data sheet rev. e | page 28 of 28 notes ? 2004 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02660 - 0 - 6/12(e)

▲Up To Search▲

Price & Availability of ADN2850

	To Download ADN2850 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .