vishay siliconix DG9454 document number: 67185 s11-0345-rev. c, 07-mar-11 www.vishay.com 1 compact, low power consumption, triple spdt (triple 2:1 multiplexers) features ? operates with v+ = 2.7 v to 13.2 v; v l = 2.5 v to 5.5 v ? guaranteed 1.8 v logic control at full v+ range ? low power consumption, < 1 a ? high bandwidth: 540 mhz ? low charge injection over the full signal range (less than 0.9 pq) ? low switch capacitance (c s(off) 2 pf typ.) ? good isolation and crosstal k performance (typ. - 65 db at 10 mhz) ? compact and light miniqfn16 package (1.8 mm x 2.6 mm) ? compliant to rohs directive 2002/95/ec ? halogen-free according to iec 61249-2-21 definition applications ? 3d glasses (goggles) ? touch panels ? data acquisition ? medical and healthcare devices ? control and automation equipments ? test instruments functional block diagram and pin configuration pin 1 de v ice marking: 5xx for DG9454 (miniqf n 16) xx = date/lot tracea b ility code yxx z1 z z0 1 2 3 4 7 8 9 10 11 12 5 8 7 6 13 14 15 16 y y1 y0 g n d top v ie w DG9454 mqf n -16 v cc ena b le v l a b c x1 x x0 description the DG9454 is a triple spdt (triple 2:1 multiplexers) with enhanced performance on low power consumption, while guarantees 1.8 v logic compatib le over the full operation voltage range. the DG9454 is designed to operate from a + 2.7 v to + 13.2 v supply at v+, and + 2.5 v to + 5.5 v at v l . the DG9454 is a high precision switch of low parasitic capacitance, low leakage, low charge injection, and fast switching speed. processed with advanced cmos technology, the DG9454 conducts equally well in both directions, offers rail to rail analog signal handling and can be used both as multiplexers as well as de-multiplexers. the advantages of DG9454 at size, weight, power consumption, and low voltage control capability make it ideal for portable consumer applications such as 3d glasses (3d goggles). its precise swit ching, wide dynamic range, and low parasitic characters make it a high performance switch for healthcare, data acquisit ion, and instrument products. the DG9454 operating temperatur e is specified from - 40 c to + 85 c and are available and the ultra compact 1.8 mm x 2.6 mm miniqfn16 packages. as a comitted partner to the community and the environment, vishay siliconix manufactur es this product with lead (pb)-free device terminations. DG9454 is offered in a miniqfn package. the miniqfn package has a nickel- palladium-gold device termination and is represented by the lead (pb)-free ?-e4? suffix. the nickel-palladium-gold device terminations meet all jedec standards for reflow and msl ratings.
www.vishay.com 2 document number: 67185 s11-0345-rev. c, 07-mar-11 vishay siliconix DG9454 notes: a. - 40 c to 85 c datasheet limits apply. notes: a. signals on sx, dx, v l or inx exceeding v+ will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6.6 mw/c above 70 c. d. manual soldering with iron is not re commended for leadless components. the miniqfn- 16 is a leadless package. the end of the lead terminal is exposed copper (not plated) as a result of the singulation pr ocess in manufacturing. a solder fillet at the exposed copper l ip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. truth table enable input select inputs on switches c b a DG9454 h x x x all switches open l l l l x to x0, y to y0, z to z0 l l l h x to x1, y to y0, z to z0 l l h l x to x0, y to y1, z to z0 l l h h x to x1, y to y1, z to z0 l h l l x to x0, y to y0, z to z1 l h l h x to x1, y to y0, z to z1 l h h l x to x0, y to y1, z to z1 l h h h x to x1, y to y1, z to z1 ordering information temp. range package part number DG9454 - 40 c to 125 c a 16-pin miniqfn DG9454en-t1-e4 absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter limit unit digital inputs a , v s , v d , v l gnd - 0.3 to (v+) + 0.3 or 30 ma, whichever occurs first v v+ to gnd 14 continuous current (any terminal) 30 ma peak current, s or d (pulsed 1 ms, 10 % duty cycle) 100 storage temperature - 65 to 150 c power dissipation b 16-pin miniqfn c, d 525 mw thermal resistance b 16-pin miniqfn d 152 c/w latch-up (per jesd78) ma specifications for unipolar supplies parameter symbol test conditions unless otherwise specified v cc = + 12 v, v l = 2.7 v v in(a, b, c and enable) = 1.6 v, 0.5 v a temp. b typ. c - 40 c to + 125 c - 40 c to + 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 0 12 0 12 v on-resistance r ds(on) i s = 1 ma, v d = 0.7 v, 6.0 v, 11.3 v room full 80 120 143 120 137 ? on-resistance match ? r on i s = 1 ma, v d = + 0.7 v room full 47 10 7 8 on-resistance flatness r flatness i s = 1 ma, v d = 0.7 v, 6.0 v, 11.3 v room full 32 26 30 26 28
document number: 67185 s11-0345-rev. c, 07-mar-11 www.vishay.com 3 vishay siliconix DG9454 notes: a. v in = input voltage to perform proper function. b. room - 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, no t subject to production test. specifications for unipolar supplies parameter symbol test conditions unless otherwise specified v cc = + 12 v, v l = 2.7 v v in(a, b, c and enable) = 1.6 v, 0.5 v a temp. b typ. c - 40 c to + 125 c - 40 c to + 85 c unit min. d max. d min. d max. d analog switch switch off leakage current i s(off) v+ = + 13.2 v, v l = 2.7 v v d = 1 v/12.2 v, v s = 12.2 v/1 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 na i d(off) room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 channel on leakage current i d(on) v+ = + 13.2 v, v l = 2.7 v v d = v s = 1 v/12.2 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 digital control logic low input voltage v inl v l = 2.7 v full 0.5 0.5 v logic high input voltage v inh full 1.6 1.6 logic low input current i l v in a0, a1, a2 and enable under test = 0.5 v full 0.01 - 1 1 - 1 1 a logic high input current i h v in a0, a1, a2 and enable above test = 1.6 v full 0.01 - 1 1 - 1 1 dynamic characteristics transition time t trans r l = 300 ? , c l = 35 pf see figure 1, 2, 3 room full 80 135 205 135 170 ns enable turn-on time t on(en) room full 115 180 250 180 215 enable turn-off time t off(en) room full 46 110 180 110 145 break-before-make time delay t d room full 37 12 12 charge injection e q c l = 1 nf, r gen = 0 ? , v gen = 0 v full 0.86 pc off isolation e oirr f = 1 mhz, r l = 50 ? , c l = 5 pf 100 khz room < - 90 db 1 mhz room - 80 10 mhz room - 61 crosstalk e x ta l k 100 khz room < - 90 1 mhz room - 81 10 mhz room - 65 bandwidth, - 3db e bw r l = 50 ? room 540 mhz source off capacitance e c s(off) f = 1 mhz room 2 pf drain off capacitance e c d(off) room 3 channel on capacitance e c d(on) room 6 total harmonic distortion e thd signal = 1 v rms , 20 hz to 20 khz, r l = 600 ? room 0.01 % power supply power supply range i+ v in(a, b, c and enable) = 0 v or + 12 v room full 0.05 1 10 1 10 a ground current i gnd room full 0.05 - 1 - 10 - 1 - 10 logic supply current i l v l = 2.7 v room full 0.05 1 10 1 10
www.vishay.com 4 document number: 67185 s11-0345-rev. c, 07-mar-11 vishay siliconix DG9454 notes: a. v in = input voltage to perform proper function. b. room - 25 c, full = as determi ned by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, not subject to production test. specifications for unipolar supplies parameter symbol test conditions unless otherwise specified v cc = + 5 v, v l = 2.7 v v in(a, b, c and enable) = 1.5 v, 0.6 v a temp. b typ. c - 40 c to + 125 c - 40 c to + 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 0 5 0 5 v on-resistance r on i s = 1 ma, v d = 0 v, + 3.5 v room full 105 165 205 165 194 ? on-resistance match ? r on i s = 1 ma, v d = + 3.5 v room full 3.2 8 13 8 10 on-resistance flatness r flatness i s = 1 ma, v d = 0 v, + 3 v room full 17 26 30 26 28 switch off leakage current i s(off) v+ = + 5.5 v, v- = 0 v v d = 1 v/4.5 v, v s = 4.5 v/1 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 na i d(off) room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 channel on leakage current i d(on) v+ = + 5.5 v, v- = 0 v v d = v s = 1 v/4.5 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 digital control v in(a, b, c and enable) low v il v l = 2.7 v full 0.6 0.6 v v in(a, b, c and enable) high v ih v l = 2.7 v full 1.5 1.5 input current, v in low i l v in(a, b, c and enable) under test = 0.6 v full 0.01 - 1 1 - 1 1 a input current, v in high i h v in(a, b, c and enable) under test = 1.5 v full 0.01 - 1 1 - 1 1 dynamic characteristics transition time t trans r l = 300 ? , c l = 35 pf see figure 1, 2, 3 room full 96 175 250 175 210 ns enable turn-on time t on room full 200 295 365 295 330 enable turn-off time t off room full 60 155 225 155 190 break-before-make time delay t d room full 50 20 20 charge injection e q v g = 0 v, r g = 0 ? , c l = 1 nf full 0.4 pc off isolation e oirr r l = 50 ? , c l = 5 pf f = 100 khz room < - 90 db channel-to-channel crosstalk e x ta l k room < - 90 source off capacitance e c s(off) f = 1 mhz room 2 pf drain off capacitance e c d(off) room 4 channel on capacitance e c d(on) room 7 power supply power supply current i+ v in(a, b, c and enable) = 0 v or 5 v room full 0.05 1 10 1 10 a ground current i gnd room full - 0.05 - 1 - 10 - 1 - 10 logic supply current i l v l = 2.7 v room full 0.05 1 10 1 10
document number: 67185 s11-0345-rev. c, 07-mar-11 www.vishay.com 5 vishay siliconix DG9454 notes: a. v in = input voltage to perform proper function. b. room - 25 c, full = as determined by the operating temperature suffix. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. e. guaranteed by design, no t subject to production test. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications for unipolar supplies parameter symbol test conditions unless otherwise specified v cc = + 3 v, v l = 2.7 v v in(a, b, c and enable) = 1.5 v, 0.6 v a temp. b typ. c - 40 c to + 125 c - 40 c to + 85 c unit min. d max. d min. d max. d analog switch analog signal range e v analog full 0 3 0 3 v on-resistance r ds(on) i s = 1 ma, v d = 1.5 v room full 171 265 310 265 289 ? switch off leakage current i s(off) v+ = 3.3 v, v l = 2.7 v v d = 0.3 v/3.0 v, v s = 3.0 v/0.3 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 na i d(off) room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 channel on leakage current i d(on) v+ = 3.3 v, v l = 2.7 v v s = v d = 0.3 v/3.0 v room full 0.02 - 1 - 50 1 50 - 1 - 5 1 5 digital control logic low input voltage v inl v l = + 2.7 v full 0.6 0.6 v logic high input voltage v inh full 1.5 1.5 logic low input current i l v in a0, a1, a2 and enable under test = 0.6 v full 0.01 - 1 1 - 1 1 a logic high input current i h v in a0, a1, a2 and enable above test = 1.5 v full 0.01 - 1 1 - 1 1 dynamic characteristics transition time t trans r l = 300 ? , c l = 35 pf see figure 1, 2, 3 room full 151 270 355 270 315 ns enable turn-on time t on(en) room full 390 510 610 510 565 enable turn-off time t off(en) room full 90 220 320 220 275 break-before-make time delay t d room full 90 35 35 charge injection e q c l = 1 nf, r gen = 0 ? , v gen = 0 v full 0.5 pc off isolation e oirr f = 1 mhz, r l = 50 ? , c l = 5 pf 100 khz room < - 90 db crosstalk e x ta l k 100 khz room < - 90 source off capacitance e c s(off) f = 1 mhz room 2 pf drain off capacitance e c d(off) room 4 channel on capacitance e c d(on) room 7 power supply power supply range i+ v in(a, b, c and enable) = 0 v or + 3 v room full 0.05 1 10 1 10 a ground current i gnd room full 0.05 - 1 - 10 - 1 - 10 logic supply current i l v l = 2.7 v room full 0.05 1 10 1 10
www.vishay.com 6 document number: 67185 s11-0345-rev. c, 07-mar-11 vishay siliconix DG9454 typical characteristics (25 c, unless otherwise noted) on-resistance vs. v d and signal supply voltage on-resistance vs. analog voltage and temperature leakage current vs. temperature 0 024 8 14 61012 200 50 400 300 100 500 150 350 250 450 v d - analog voltage (v) r on - on-resistance ( ) v cc = 10.8 v v cc = 12.0 v v cc = 13.2 v t = 25 c v l = 2.7 v i s = 1 ma v cc = 2.7 v v cc = 3.3 v v cc = 4.5 v v cc = 5.0 v v cc = 5.5 v v cc = 3.0 v 0 0 1.0 0.5 1.5 2.5 3.5 4.5 2.0 4.0 5.0 3.0 300 50 100 400 200 350 150 250 v d - analog voltage (v) r on - on-resistance ( ) + 125 c + 85 c + 25 c - 40 c v cc = 5.0 v v l = 2.7 v i s = 1 ma 0.1 - 60 - 20 20 100 60 140 1 10 1000 100 000 100 10 000 temperature (c) leakage current (pa) v cc = + 13.2 v v l = 2.7 v i s(off) i d(off) i d(on) on-resistance vs. analog voltage and temperature on-resistance vs. analog voltage and temperature switching time vs. temperature 0 0 0.5 1.0 2.0 3.0 1.5 2.5 300 50 100 500 200 400 350 150 250 450 v d - analog voltage (v) r on - on-resistance ( ) + 125 c v cc = 3.0 v, v l = 2.7 v i s = 1 ma + 85 c + 25 c - 40 c 0 02 13579 4811 10 12 6 50 75 25 100 250 200 150 175 225 125 250 v d - analog voltage (v) r on - on-resistance ( ) + 125 c + 85 c + 25 c - 40 c v cc = 12 v, v l = 2.7 v i s = 1 ma 0 100 200 600 300 500 400 temperature (c) t on(en) , t off(en) - switching time (ns) - 50 50 150 0 100 v cc = + 5 v, v l = 2.7 v, t off v cc = + 3 v, v l = 2.7 v, t off v cc = + 12 v, v l = 2.7 v, t off v cc = + 12 v, v l = 2.7 v, t on v cc = + 3 v, v l = 2.7 v, t on v cc = + 5 v, v l = 2.7 v, t on
vishay siliconix DG9454 document number: 67185 s11-0345-rev. c, 07-mar-11 www.vishay.com 7 typical characteristics (25 c, unless otherwise noted) insertion loss, off-isolation, crosstalk vs. frequency switching threshold vs. logic supply voltage - 100 100k 1m 10m 1g 100m - 20 - 80 - 60 10 - 40 0 - 30 - 90 - 70 - 50 - 10 frequency (hz) loss, oirr, x talk (db) v cc = + 12 v v l = 2.7 v r l = 50 loss oirr x talk v+ - supply voltage (v) v t - switching threshold (v) - 40 c to + 125 c v il v l = + 2.5 v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 4 5 6 7 8 9 10 11 12 13 14 = 125 c; v l = 2.5 v v ih = - 40 c; v l = 2.5 v switching threshold vs. logic supply voltage charge injection vs. analog voltage v+ - supply voltage (v) v t - switching threshold (v) - 40 c to + 125 c v il v l = + 5 v 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 4 5 6 7 8 9 10 11 12 13 14 = 125 c; v l = 5 v v ih = - 40 c; v l = 5 v 0123456789101112 - 2.00 0 - 1.50 - 1.00 2.00 - 0.50 1.00 0.50 1.50 v s - analog voltage (v) q inj - charge injection (pc) v cc = + 5 v v l = 2.7 v v cc = + 3 v v l = 2.7 v v cc = + 12 v v l = 2.7 v current vs. frequency 10 ma 1 ma 100 a 10 a 1 a 100 na 10 na 1 na 100 pa 10 pa 10 100 1k 100k 10k 1m 10m input switching frequency (hz) i+ - supply current v cc = + 13.2 v v l = 2.7 v i gnd i l i cc
www.vishay.com 8 document number: 67185 s11-0345-rev. c, 07-mar-11 vishay siliconix DG9454 test circuits a or b or c e n able g n d v cc v l v l v cc v o 50 300 35 pf x or y or z x0 or y0 or z0 x1 or y1 or z1 DG9454 v x0 or v y0 or v z0 v x1 or v y1 or v z1 0 v 1. 8 v 50 % 50 % 90 % t tra n s o n v o v a, b, c v x7 t tra n s 90 % v x0 or v y0 or v z0 v x3 or v y3 v x1 or v y1 or v z1 x1 or y1 or z1 o n (DG9454) v 0 or y 0 or z 0 figure 1. transition time a or b or c e n able g n d v cc v l v l v cc v o 50 300 35 pf x or y or z x0 or y0 or z0 x1 or y1 or z1 DG9454 v cc 0 v 1. 8 v 50 % 50 % 90 % t off ena b le x or y or z disa b le x or y or z v o v enable 0 v t o n 90 % v x0 or v y0 or v z0 figure 2. enable switching time a or b or c e n able g n d v cc v l v l v cc v o 50 300 35 pf x or y or z x0, x1 or y0, y1 or z0, z1 DG9454 v cc 0 v 1. 8 v 50 % 8 0 % t d v o v a, b, c 0 v v x0 or v y0 or v z0 figure 3. break-before-make
vishay siliconix DG9454 document number: 67185 s11-0345-rev. c, 07-mar-11 www.vishay.com 9 test circuits vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67185 . figure 4. charge injection a b c e n able g n d v cc v l v l v cc v o 1 nf x xx 0 v v cc v o v enable r g channel select v g o n off off v o t r < 5 ns t f < 5 ns figure 5. insertion loss figure 7. crosstalk a b c e n able g n d v cc v l v l v cc v out x x0 v g r g = 50 50 v i n n et w ork analyzer insertion loss = 20 log v out v i n a b c e n able g n d v cc v l v l v cc v out x x0 v g r g = 50 50 v i n n et w ork analyzer crosstalk = 20 log v out v i n 50 xx figure 6. off isolation figure 8. source, drain capacitance a b c e n able g n d v cc v l v l v cc v out x x0 v g r g = 50 50 v i n n et w ork analyzer off isolation = 20 log v out v i n v cc a b c e n able g n d v cc v l v l v cc x x0 | to | xx impedance analyzer channel select
document number: 91000 www.vishay.com revision: 18-jul-08 1 disclaimer legal disclaimer notice vishay all product specifications and data are subject to change without notice. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, ?vishay?), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. vishay disclaims any and all li ability arising out of the use or application of any product describ ed herein or of any information provided herein to the maximum extent permit ted by law. the product specifications do not expand or otherwise modify vishay?s terms and conditions of purcha se, including but not limited to the warranty expressed therein, which apply to these products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of vishay. the products shown herein are not designed for use in medi cal, life-saving, or life-sustaining applications unless otherwise expressly indicated. customers using or selling vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify vishay for any damages arising or resulting from such use or sale. please contact authorized vishay personnel to obtain written terms and conditions regarding products designed for such applications. product names and markings noted herein may be trademarks of their respective owners.
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