|
If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
Datasheet File OCR Text: |
september 2006 hys72t32000hp?[3s/3.7]?a HYS72T64001HP?[3s/3.7]?a hys72t64020hp?[3s/3.7]?a 240-pin registered ddr2 sdram modules ddr2 sdram rdimm sdram rohs compilant internet data sheet rev. 1.01
we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the quality of this document. please send your proposal (including a reference to this document) to: techdoc@qimonda.com internet data sheet hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules qag_techdoc_rev400 / 3.2 qag / 2006-07-21 2 03292006-zzhp-pr83 hys72t32000hp?[3s/3.7]?a, HYS72T64001HP? [3s/3.7]?a, hys72t64020hp?[3s/3.7]?a revision history: 2006-09, rev. 1.01 page subjects (major chan ges since last revision) all qimonda update all adapted internet edition 24 modified ac timing parameters previous revision: 2006-03, rev. 1.0 internet data sheet rev. 1.01, 2006-09 3 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules 1overview this chapter gives an overview of the 240-pin registered ddr2 sdram modules wit h parity bit product family and describes its main characteristics. 1.1 features ? 240-pin pc2?5300 and pc2?4200 ddr2 sdram memory modules. ? one rank in 32m 72, 64m x 72 and two rank in 64m 72 module organization and 32m 8, 64m 4 chip organization ? 256m, 512 mbyte modules are built with 256-mbit ddr2 sdrams in p-tfbga-60 chipsize packages. ? standard double-data-rate-two synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply ? all speed grades faster than ddr2-400 comply with ddr2-400 timing specifications as well. ? registered dimm with parity bit for address and control bus ? programmable cas latencies (3, 4 and 5), burst length (4 & 8) and burst type ? auto refresh (cbr) and self refresh ? average refresh period 7.8 s at a t lower than 85 c, 3.9 s between 85 c and 95 c ? programmable self refres h rate via emrs2 setting ? all inputs and outputs sstl_18 compatible ? off-chip driver impedance adjustment (ocd) and on-die termination (odt) ? serial presence detect with e 2 prom ? based on standard reference layouts raw cards ?f?, ?g? and ?h? ? rdimm with parity bit dimensions (nominal): 30.00 mm high, 133.35 mm wide ? rohs compliant products 1) table 1 performance table for ?3s 1) rohs compliant product: restriction of the use of certain hazar dous substances (rohs) in el ectrical and electronic equipment as defined in the directive 2002/95/ec issued by the european parliament and of the council of 27 january 2003. these substances include m ercury, lead, cadmium, hexavalent chromium, polybro minated biphenyls and polybrominated biphenyl ethers. product type speed code ?3s unit speed grade pc2?5300 5?5?5 ? max. clock frequency @cl5 f ck5 333 mhz @cl4 f ck4 266 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 45 ns min. row cycle time t rc 60 ns internet data sheet rev. 1.01, 2006-09 4 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules table 2 performance table for ?3.7 table 3 performance table for ?5 product type speed code ?3.7 unit speed grade pc2?4200 4?4?4 ? max. clock frequency @cl5 f ck5 266 mhz @cl4 f ck4 266 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 45 ns min. row cycle time t rc 60 ns product type speed code ?5 units speed grade pc2?3200 3?3?3 ? max. clock frequency @cl5 f ck5 200 mhz @cl4 f ck4 200 mhz @cl3 f ck3 200 mhz min. ras-cas-delay t rcd 15 ns min. row precharge time t rp 15 ns min. row active time t ras 40 ns min. row cycle time t rc 55 ns internet data sheet rev. 1.01, 2006-09 5 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules 1.2 description the qimonda hys72t[32/64] xxxhp?[3s/3.7]?a module family are registered dimm (rdimm with parity) with 30.00 mm height based on ddr2 technology. dimms are available as ecc modules in 32m 72 (256 mbyte) and 64m x 72 (512 mbyte) organization and density, intended for mounting into 240-pin connector sockets. the memory array is designed with 256-mbit double-data- rate-two (ddr2) synchronous drams. all control and address signals are re-driven on the dimm using register devices and a pll for the clock distribution. this reduces capacitive loading to the system bus, but adds one cycle to the sdram timing. decoupling capacitors are mounted on the pcb board. the dimms feat ure serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. table 4 ordering information for rohs compliant products table 5 address format product type 1) 1) all product types end with a place code, designating the silicon die re vision. example: hys72t64020hp?3.7?a, indicating rev. ?a? dies are used for ddr2 sdram components. for all qi monda ddr2 module and component nomenclature see chapter 6 of this data sheet. compliance code 2) 2) the compliance code is printed on the module label and describes the speed grade, for example ?pc2?4200p?444?12?g0?, where 4200p means very low profile registered dimm modules with 4. 26 gb/sec module bandwidth and ?444-12? means column address strobe (cas) latency = 4, row column delay (rcd) latency = 4 and row precharge (rp) latency = 4 using the latest jedec spd revision 1.2 and produced on the raw card ?g? description sdram technology pc2-5300 hys72t32000hp?3s?a 256mb 1r 8 pc2?5300p?555?12?f0 1 rank, ecc 256 mbit ( 8) HYS72T64001HP?3s?a 512mb 1r 4 pc2?5300p?555?12?h0 1 rank, ecc 256 mbit ( 4) hys72t64020hp?3s?a 512mb 2r 8 pc2?5300p?555?12?g0 2 rank, ecc 256 mbit ( 8) pc2-4200 hys72t32000hp?3.7?a 256mb 1r 8 pc2?4200p?444?12?f0 1 rank, ecc 256 mbit ( 8) HYS72T64001HP?3.7?a 512mb 1r 4 pc2?4200p?444?12?h0 1 rank, ecc 256 mbit ( 4) hys72t64020hp?3.7?a 512mb 2r 8 pc2?4200p?444?12?g0 2 rank, ecc 256 mbit ( 8) dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/columns bits raw card 256 mb 32m 72 1 ecc 9 13/2/10 f 512 mb 64m 72 1 ecc 18 13/2/11 h 512 mb 64m 72 2 ecc 18 13/2/10 g internet data sheet rev. 1.01, 2006-09 6 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules table 6 components on modules product type 1) 1) green product dram components 1) dram density dram organization note 2) 2) for a detailed description of all avail able functions of the dram components on these modules see the component data sheet. hys72t32000hp hyb18t256800af 256 mbit 32m 8 HYS72T64001HP hyb18t256400af 256 mbit 64m 4 hys72t64020hp hyb18t256800af 256mbit 32m 8 internet data sheet rev. 1.01, 2006-09 7 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules 2 pin configuration this chapter contains the pin configuration and block diagrams. 2.1 pin configuration the pin configuration of the registered ddr2 sdram dimm is listed by function in table 7 (240 pins). the abbreviations used in columns pin and buffer type are explained in table 8 and table 9 respectively. the pin numbering is depicted in figure 1 . table 7 pin configuration of rdimm ball no. name pin type buffer type function clock signals 185 ck0 i sstl clock signal ck0, comple mentary clock signal ck0 186 ck0 isstl 52 cke0 i sstl clock enables 1:0 note: 2-ranks module 171 cke1 i sstl nc nc ? not connected note: 1-rank module control signals 193 s0 isstl chip select rank 1:0 note: 2-ranks module 76 s1 isstl nc nc ? not connected note: 1-rank module 192 ras isstl row address strobe (ras), column address strobe (cas), write enable (we) 74 cas isstl 73 we isstl 18 reset icmos register reset address signals 71 ba0 i sstl bank address bus 1:0 190 ba1 i sstl 54 ba2 i sstl bank address bus 2 nc i sstl not connected internet data sheet rev. 1.01, 2006-09 8 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules 188 a0 i sstl address bus 12:0, address signal 10/autoprecharge 183 a1 i sstl 63 a2 i sstl 182 a3 i sstl 61 a4 i sstl 60 a5 i sstl 180 a6 i sstl 58 a7 i sstl 179 a8 i sstl 177 a9 i sstl 70 a10 i sstl ap i sstl 57 a11 i sstl 176 a12 i sstl 196 a13 i sstl address signal 13 nc nc ? not connected 174 a14 i sstl address signal 14 nc nc ? not connected 173 a15 i sstl address signal 14 nc nc ? not connected ball no. name pin type buffer type function internet data sheet rev. 1.01, 2006-09 9 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules data signals 3 dq0 i/o sstl data bus 63:0 4 dq1 i/o sstl 9 dq2 i/o sstl 10 dq3 i/o sstl 122 dq4 i/o sstl 123 dq5 i/o sstl 128 dq6 i/o sstl 129 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 21 dq10 i/o sstl 22 dq11 i/o sstl 131 dq12 i/o sstl 132 dq13 i/o sstl 140 dq14 i/o sstl 141 dq15 i/o sstl 24 dq16 i/o sstl 25 dq17 i/o sstl 30 dq18 i/o sstl 31 dq19 i/o sstl 143 dq20 i/o sstl 144 dq21 i/o sstl 149 dq22 i/o sstl 150 dq23 i/o sstl 33 dq24 i/o sstl 34 dq25 i/o sstl 39 dq26 i/o sstl 40 dq27 i/o sstl 152 dq28 i/o sstl 153 dq29 i/o sstl 158 dq30 i/o sstl 159 dq31 i/o sstl 80 dq32 i/o sstl 81 dq33 i/o sstl 86 dq34 i/o sstl 87 dq35 i/o sstl 199 dq36 i/o sstl 200 dq37 i/o sstl 205 dq38 i/o sstl ball no. name pin type buffer type function internet data sheet rev. 1.01, 2006-09 10 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules 206 dq39 i/o sstl data bus 63:0 89 dq40 i/o sstl 90 dq41 i/o sstl 95 dq42 i/o sstl 96 dq43 i/o sstl 208 dq44 i/o sstl 209 dq45 i/o sstl 214 dq46 i/o sstl 215 dq47 i/o sstl 98 dq48 i/o sstl 99 dq49 i/o sstl 107 dq50 i/o sstl 108 dq51 i/o sstl 217 dq52 i/o sstl 218 dq53 i/o sstl 226 dq54 i/o sstl 227 dq55 i/o sstl 110 dq56 i/o sstl 111 dq57 i/o sstl 116 dq58 i/o sstl 117 dq59 i/o sstl 229 dq60 i/o sstl 230 dq61 i/o sstl 235 dq62 i/o sstl 236 dq63 i/o sstl check bits 42 cb0 i/o sstl check bits 7:0 43 cb1 i/o sstl 48 cb2 i/o sstl 49 cb3 i/o sstl 161 cb4 i/o sstl 162 cb5 i/o sstl 167 cb6 i/o sstl 168 cb7 i/o sstl ball no. name pin type buffer type function internet data sheet rev. 1.01, 2006-09 11 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules data strobe bus 7 dqs0 i/o sstl data strobes 17:0 6 dqs0 i/o sstl 16 dqs1 i/o sstl 15 dqs1 i/o sstl 28 dqs2 i/o sstl 27 dqs2 i/o sstl 37 dqs3 i/o sstl 36 dqs3 i/o sstl 84 dqs4 i/o sstl 83 dqs4 i/o sstl 93 dqs5 i/o sstl 92 dqs5 i/o sstl 105 dqs6 i/o sstl 104 dqs6 i/o sstl 114 dqs7 i/o sstl 113 dqs7 i/o sstl 46 dqs8 i/o sstl 45 dqs8 i/o sstl 125 dqs9 i/o sstl 126 dqs9 i/o sstl 134 dqs10 i/o sstl 135 dqs10 i/o sstl 146 dqs11 i/o sstl 147 dqs11 i/o sstl 155 dqs12 i/o sstl 156 dqs12 i/o sstl 202 dqs13 i/o sstl 203 dqs13 i/o sstl 211 dqs14 i/o sstl 212 dqs14 i/o sstl 223 dqs15 i/o sstl 224 dqs15 i/o sstl 232 dqs16 i/o sstl 233 dqs16 i/o sstl 164 dqs17 i/o sstl 165 dqs17 i/o sstl ball no. name pin type buffer type function internet data sheet rev. 1.01, 2006-09 12 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules data mask 125 dm0 i sstl data masks 8:0 note: 8 based module 134 dm1 i sstl 146 dm2 i sstl 155 dm3 i sstl 202 dm4 i sstl 211 dm5 i sstl 223 dm6 i sstl 232 dm7 i sstl 164 dm8 i sstl eeprom 120 scl i cmos serial bus clock 119 sda i/o od serial bus data 239 sa0 i cmos serial address select bus 2:0 240 sa1 i cmos 101 sa2 i cmos parity 55 err_out ocmos parity bits par_in i cmos power supplies 1 v ref ai ? i/o reference voltage 238 v ddspd pwr ? eeprom power supply 51, 56, 62, 72, 75, 78, 170, 175,, 181, 191, 194 v ddq pwr ? i/o driver power supply 53, 59, 64, 67, 69, 172, 178, 184,, 187, 189, 197 v dd pwr ? power supply 2, 5, 8, 11, 14, 17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 65, 66, 79, 82, 85, 88, 91, 94, 97, 100, 103, 106, 109, 112, 115, 118, 121, 124, 127, 130, 133, 136, 139, 142, 145, 148, 151, 154, 157, 160, 163, 166, 169, 198, 201, 204, 207, 210, 213, 216, 219, 222, 225, 228, 231, 234, 237 v ss gnd ? ground plane ball no. name pin type buffer type function internet data sheet rev. 1.01, 2006-09 13 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules table 8 abbreviations for buffer type table 9 abbreviations for pin type other pins 19, 55, 68, 102, 137, 138, 173, 220, 221 nc nc ? not connected 195 odt0 i sstl on-die termination control 1:0 note: 2-ranks module 77 odt1 i sstl nc nc ? note: 1-rank modules abbreviation description sstl serial stub terminated logic (sstl_18) cmos cmos levels od open drain. the corresponding pin has 2 ope rational states, active low and tristate, and allows multiple devices to share as a wire-or. abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectio nal input/output signal. ai input. analog levels. pwr power gnd ground nu not usable nc not connected ball no. name pin type buffer type function internet data sheet rev. 1.01, 2006-09 14 03292006-zzhp-pr83 hys72t[32/64]xxxhp?[3s/3.7]?a registered ddr2 sdram modules figure 1 pin configuration for rdimm (240 pins) 0 3 3 7 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 9 5 ( ) ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 1 & 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 ' 4 9 6 6 ' 4 6 5 ( 6 ( 7 9 6 6 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q 3 l q ' 4 ' 4 9 6 6 ' 4 6 ' 4 9 6 6 ' 4 ' 4 6 9 6 6 ' 4 & |