cystech electronics corp. spec. no. : c930n6 issued date : 2013.11.06 revised date : page no. : 1/8 MTA17A02CDN6 cystek product specification dual n-channel enhancement mode mosfet MTA17A02CDN6 bv dss 20v i d v gs =4.5v 6a 16.1m v gs =4.5v, i d =6a features v gs =4.0v, i d =6a 16.7m ? simple drive requirement ? low on-resistance ? small package outline ? pb-free lead plating and halogen-free package equivalent circuit ordering information device package shipping MTA17A02CDN6-0-t1-g sot-26 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel MTA17A02CDN6 g gate s source d drain environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t1 : 3000 pc s / tape & reel,7? reel product rank, zero for no rank products product name v gs =3.0v, i d =6a 18.4 m r dson ( typ .) v gs =2.5v, i d =6a 20.2 m
cystech electronics corp. spec. no. : c930n6 issued date : 2013.11.06 revised date : page no. : 2/8 MTA17A02CDN6 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds 20 gate-source voltage v gs 10 v t a =25 c (note 1) 6 continuous drain current @ v gs =4.5v t a =70 c (note 1) i d 4.8 pulsed drain current (note 2, 3) i dm 24 a t a =25 c 1.25 total power dissipation (note 1) t a =70 c p d 0.8 w operating junction temperature and storage temperature range tj, tstg -55~+150 c thermal data parameter symbol value unit thermal resistance, junction-to-ambient, max (note 1) r ja 100 c/w note : 1.surface mounted on 1 in2 copper pad of fr-4 board, t 10sec. 156 /w when mounted on minimum copper pad. : 2.pulse width lim ited by maximum junc tion temperature. 3.pulse width 300 s, duty cycle 2% e lectrical characteristics (ta=25 c, unless otherwise noted) symbol min. typ. max. unit test conditions static bv dss 20 - - v v gs =0, i d =250 a bv dss / tj - 0.2 - v/ : reference to 25 , i : d =250 a v gs(th) 0.5 0.63 1.0 v v ds =v gs , i d =250 a i gss - - 10 v gs =10v, v ds =0 - - 1 v ds =16v, v gs =0, tj=25: i dss - - 10 a v ds =16v, v gs =0, tj=55: - 16.1 26 i d =6a, v gs =4.5v - 16.7 27 i d =6a, v gs =4v - 18.4 30 i d =6a, v gs =3v *r ds(on) - 20.2 32 m i d =6a, v gs =2.5v *g fs - 15 - s v ds =5v, i d =6a dynamic ciss - 365 - coss - 75 - crss - 30 - pf v ds =10v, v gs =0, f=1mhz t d(on) - 260 - t r - 670 - t d(off) - 3850 - t f - 1800 - ns v ds =10v, i d =1a, v gs =4.5v, r g =6 ? qg - 7 - qgs - 1.5 - qgd - 1.5 - nc v ds =16v, i d =6a, v gs =4.5v
cystech electronics corp. spec. no. : c930n6 issued date : 2013.11.06 revised date : page no. : 3/8 MTA17A02CDN6 cystek product specification source-drain diode *i s - - 1.7 *i sm - - 5 a *v sd - 0.8 1.2 v i s =3a,v gs =0v *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c930n6 issued date : 2013.11.06 revised date : page no. : 4/8 MTA17A02CDN6 cystek product specification typical characteristics typical output characteristics 0 5 10 15 20 25 30 012345 v ds , drain-source voltage(v) i d , drain current(a) 5v, 4.5v,4v,3.5v,3v v gs =2v v gs =1.5v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 1.6 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =1.5v v gs =1.8v 2.5v 3v 4v 10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 i dr , reverse drain current(a) v sd , source-drain voltage(v) static drain-source on-state resistance vs gate-source voltage 0 100 200 300 400 500 600 700 024681 0 0 tj=25c tj=150c drain-source on-state resistance vs junction tempearture 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =4.5v, i d =6a r ds( on) @ tj=25c : 15 m v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =6a
cystech electronics corp. spec. no. : c930n6 issued date : 2013.11.06 revised date : page no. : 5/8 MTA17A02CDN6 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) pulsed ta=25c v ds =10v v ds =5v gate charge characteristics 0 2 4 6 8 10 0 4 8 12 16 20 total gate charge---qg(nc) v gs , gate-source voltage(v) v ds =16v i d =6a maximum safe operating area 0.001 0.01 0.1 1 10 100 0.01 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 100ms 1ms 100 s 1s r ds( on) limit t a =25c, tj(max)=150c, v gs =4.5v, r ja =100c/w single pulse maximum drain current vs junction temperature 0 1 2 3 4 5 6 7 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c, v gs =4.5v, r ja =100c/w
cystech electronics corp. spec. no. : c930n6 issued date : 2013.11.06 revised date : page no. : 6/8 MTA17A02CDN6 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 4 8 12 16 20 24 00.511.522.53 v gs , gate-source voltage(v) i d , drain current (a) v ds =5v single pulse maximum power dissipation 0 50 100 150 200 250 300 350 400 450 500 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width(s) peak transient power (w) t j(max) =150c t a =25c ja =100c/w transient thermal response curves 0.0001 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =100 c/w recommended soldering footprint
cystech electronics corp. spec. no. : c930n6 issued date : 2013.11.06 revised date : page no. : 7/8 MTA17A02CDN6 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c930n6 issued date : 2013.11.06 revised date : page no. : 8/8 MTA17A02CDN6 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c930n6 issued date : 2013.11.06 revised date : page no. : 9/8 MTA17A02CDN6 cystek product specification sot-26 dimension marking: 6-lead sot-26 plastic surface mounted package cystek package code: n6 style: pin 1. source 1 (s1) pin 2. drain 1 / drain 2 (d1 / d2) pin 3. source 2 (s2) pin 4. gate 2 (g2) pin 5. drain 1 / drain 2 (d 1 / d2) pin 6. gate 1 (g1) 17a02 ???? device name date code millimeters inches millimeters inches dim min. max. min. max. dim min. max. min. max. a 1.050 1.250 0.041 0.049 e 1.500 1.700 0.059 0.067 a1 0.000 0.100 0.000 0.004 e1 2.650 2.950 0.104 0.116 a2 1.050 1.150 0.041 0.045 e 0.950 (bsc) 0.037 (bsc) b 0.300 0.500 0.012 0.020 e1 1.800 2.000 0.071 0.079 c 0.100 0.200 0.004 0.008 l 0.300 0.600 0.012 0.024 d 2.820 3.020 0.111 0.119 0 8 0 8 notes : 1.controlling dimension : millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material : ? lead : pure tin plated. ? mold compound : epoxy resin family, flammability solid burning class:ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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