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r09ds0052ej0100 rev.1.00 page 1 of 18 oct 23, 2012 preliminary data sheet pc3250t7l sige cmos/bicmos integrated circuit if down-converter mmic fo r ku-band lnb converter description the pc3250t7l is a cmos/bicmos mmic for ku-band lnb converter. this device is housed in a 24-pin plastic qfn (quad flat non-leaded) (t7l) package. features ? low power consumption : 3.3 v/63 ma, 208 mw ? switched lo frequency : 9.75 g hz, 10.6 ghz, 10.75 ghz ? 2 step gain selected function : 41 db/36 db ? low noise figure : 7.5 db ? fully integrated mixer/oscillator/pll synthesizer/i f amplifier/4-channel fet bias supply circuit/ polarity control voltage detector/tone control signal detector ? integrated power save detector ? 24-pin plastic qfn (t7l) package (4.0 4.0 0.6 mm) applications ? ku-band low noise block (lnb) converters for satellite receiver (dvb-s , abs-s application) ordering information part number order number package marking supplying form pc3250t7l-e1 pc3250t7l-e1-a 24-pin plastic qfn (0.5 mm pitch) (pb-free) c3250 ? embossed tape 12 mm wide ? pin 7 to 12 face the perforation side of the tape ? qty 5 kpcs/reel ? dry packing specification (msl 3 equivalent) remark to order evaluation samples, please contact your nearby sales office. part number for sample order: pc3250t7l caution observe precautions when handling because these devi ces are sensitive to electrostatic discharge. r09ds0052ej0100 rev.1.00 oct 23, 2012
pc3250t7l r09ds0052ej0100 rev.1.00 page 2 of 18 oct 23, 2012 pin connections (bottom view) 123456 18 17 16 15 14 13 7 8 9 10 11 12 24 23 22 21 20 19 gnd (bottom view) 654321 13 14 15 16 17 18 24 23 22 21 20 19 7 8 9 10 11 12 c3250 pin 1 identifier pin no. pin name pin no. pin name pin no. pin name pin no. pin name 1 nc 7 v dv 13 g sw 19 v ddpll 2 rf in 8 v gv 14 cvneg 20 tonepol 3 nc 9 v d 1 15 xo2 21 if out 4 r cal 10 v g 1 16 xo1 22 v ccif 5 v dh 11 v d 2 17 v ref 23 v ccrf 6 v gh 12 v g 2 18 cp out 24 lo sel remark nc means no connection pin. heat sink of bottom side of this device is connected to gnd. absolute maximum ratings parameter symbol ratings unit supply voltage v ccrf , v ccif , v ddpll +4.0 v control voltage (tonepol, lo sel , g sw ) v pola , v losel , g sw +4.0 v power dissipation note p tot 1.53 mw storage temperature t stg ? 55 to +125 c operating ambient temperature t a ? 40 to +85 c input power p in 0 dbm note: mounted on double-sided copper-clad 50 50 0.51 mm laminated pwb, t a = +85 c
pc3250t7l r09ds0052ej0100 rev.1.00 page 3 of 18 oct 23, 2012 block diagram v ddpll tonepol if out v ccif v ccrf lo sel v g 2 v d 2 v g 1 v d 1 v gv v dv cp out v ref xo1 xo2 cvneg g sw rf in nc nc r cal v dh v gh 1 pin divider ivref vco pdcp tone polarity xo vnega bias1 bias2 bias3 bias4 if amp pre amp mix top view 16 18 13 7 12 24 19 pin no. name description 1 nc no connection 2 rf in ku band rf signal input, ac coupling required. 3 nc no connection 4 r cal lnfet drain current adjust by resister 5 v dh horizontal lnfet drain voltage supply 6 v gh horizontal lnfet gate bias voltage 7 v dv vertical lnfet drain voltage supply 8 v gv vertical lnfet gate bias voltage 9 v d 1 common lnfet drain voltage supply 1 10 v g 1 common lnfet gate bias voltage 1 11 v d 2 common lnfet drain voltage supply 2 12 v g 2 common lnfet gate bias voltage 2 13 g sw gain control input terminal 14 cvneg negative voltage line decoupling 15 xo2 crystal oscillator connection terminal 2 16 xo1 crystal oscillator connection terminal 1 17 v ref reference voltage line decoupling 18 cp out charge pump output, connect capacitor for loop filter 19 v ddpll pll power supply terminal. decoupling capacitor required 20 tonepol tone and polarity control signal input terminal 21 if out l band if signal output, ac coupling required 22 v ccif if power supply terminal. decoupling capacitor required 23 v ccrf rf power supply terminal. decoupling capacitor required 24 lo sel local oscillator frequency control input terminal remark nc means no connection pin. heat sink of bottom side of this device is connected to gnd.
pc3250t7l r09ds0052ej0100 rev.1.00 page 4 of 18 oct 23, 2012 recommended operating range (t a = +25 c, unless otherwise specified) parameter symbol min. typ. max. unit supply voltage v ccrf , v ccif , v ddpll +3.0 +3.3 +3.6 v high level of control voltage (lo sel , g sw ) v_ high v dd ? 0.5 ? v dd note 1 v low level of control voltage (lo sel , g sw ) v_ low 0 ? 0.5 v operating ambient temperature t a ? 40 +25 +85 c rf input frequency f rf 10.7 ? 12.75 ghz if output frequency f if 950 ? 2 150 ghz ? 9.75 ? ? 10.6 ? lo frequency f lo ? 10.75 ? ghz tone control signal frequency f tone 18 22 26 khz tone control signal voltage v tone 0.4 0.6 0.8 vp-p polarity control voltage note 2 v pola 13 ? 18 v input voltage of pin 20 (tonepol) v tp 0 ? v dd v adjustment supply current for each fet i d 5 10 18 ma notes: 1 v dd : supply voltage = v ccrf = v ccif = v ddpll 2 see the evaluation (application) circuit. the detail connection of pin 20 (tonepol) is shown in the evaluation circuit. this pin cannot be directly connected to 13 v/18 v polarity control voltage. the polarity control voltage must be divided to a low voltage by the external resistors. electrical characteristics (t a = +25 c, v ccrf = v ccif = v ddpll = +3.3 v, z s = z l = 50 , f xtal = 25 mhz, unless otherwise specified) parameter symbol test conditions min. typ. max. unit total supply current 1 note (v ccrf , v ccif , v ddpll ) normal mode (high gain selected) i cc 1 v pola > 7.0 v , non-rf input, g sw = +3.3 v (without fets bias supply current) 50 63 80 ma total supply current 2 note (v ccrf , v ccif , v ddpll ) normal mode ( low gain selected) i cc 2 v pola > 7.0 v , non-rf input, g sw = 0 v (without fets bias supply current) 48.5 61.5 78.5 ma total supply current 3 note (v ccrf , v ccif , v ddpll ) power save mode i cc 3 v pola = 0 v ( < 3.6v) non-rf input (without fets bias supply current) ? 5 10 ma note: see the evaluation (application) circuit. the detail connection of pin 20 (tonepol) is shown in the evaluation circuit. this pin cannot be directly connected to 13 v/18 v polarity control voltage. the polarity control voltage must be divided to a low voltage by the external resistors.
pc3250t7l r09ds0052ej0100 rev.1.00 page 5 of 18 oct 23, 2012 electrical characteristics (t a = +25 c, v ccrf = v ccif = v ddpll = +3.3 v, g sw = +3.3 v, z s = z l = 50 , f xtal = 25 mhz, unless otherwise specified) parameter symbol test conditions min. typ. max. unit conversion gain 1 note 1 g conv 1 f lo = 9.75 ghz, f if = 1.5 ghz, p in = ? 50 dbm 37 41 45 db conversion gain 2 note 1 g conv 2 f lo = 10.6 ghz, f if = 1.5 ghz, p in = ? 50 dbm 37 41 45 db conversion gain 3 note 1 g conv 3 f lo = 10.75 ghz, f if = 1.5 ghz, p in = ? 50 dbm 37 41 45 db pola control threshold voltage 1 note 1 v th_pola 1 power save mode to normal mode dividing resistor : 8.2 k /51 k 3.6 ? 7.0 v pola control threshold voltage 2 note 1 (channel selection ) v th_pola 2 vertical mode to horizontal mode dividing resistor : 8.2 k /51 k 15.2 15.7 16.2 v tone control signal threshold voltage note 1 (channel selection) v th_tone low band to high band f tone = 22 khz, duty cycle = 50%, pulse wave divider capacitor : 0.1 f/0.1 f 0.1 0.15 0.35 v p-p drain voltage h note 1, 2 v dh v pola = 18 v, i d = 10 ma, r cal = 22 k 1.8 2.0 2.2 v drain voltage v note 1, 2 v dv v pola = 13 v, i d = 10 ma, r cal = 22 k 1.8 2.0 2.2 v drain voltage 1 note 1, 2 v d 1 i d = 10 ma, r cal = 22 k 1.8 2.0 2.2 v drain voltage 2 note 1, 2 v d 2 i d = 10 ma, r cal = 22 k 1.8 2.0 2.2 v drain current h note 1, 2 i dh v pola = 18 v, r cal = 22 k 8.5 10 11.5 ma drain current v note 1, 2 i dv v pola = 13 v, r cal = 22 k 8.5 10 11.5 ma drain current 1 note 1, 2 i d 1 r cal = 22 k 8.5 10 11.5 ma drain current 2 note 1, 2 i d 2 r cal = 22 k 8.5 10 11.5 ma gate voltage h note 1, 2 of fet off mode v gh v pola = 13 v ? 2.0 ? 2.5 ? 3.0 v gate voltage v note 1, 2 of fet off mode v gv v pola = 18 v ? 2.0 ? 2.5 ? 3.0 v notes: 1 see the evaluation (application) circuit. the detail connection of pin 20 (tonepol) is shown in the evaluation circuit. this pin cannot be directly connected to 13 v/18 v polarity control voltage. the polarity control voltage must be divided to a low voltage by the external resistors. 2 see the graph of ?r cal vs. i dfet , v dfet .? fet?s drain current can be adjusted by the external resisters (r cal ).
pc3250t7l r09ds0052ej0100 rev.1.00 page 6 of 18 oct 23, 2012 standard characteristics for reference (t a = +25 c, v ccrf = v ccif = v ddpll = +3.3 v, g sw = +3.3v, z s = z l = 50 , f xtal = 25 mhz, unless otherwise specified) parameter symbol test conditions reference value unit conversion gain flatness 1 g conv 1 f lo = 9.75 ghz, f if = 0.95 g to 1.95 ghz, p in = ? 50 dbm 2.5 db conversion gain flatness 2 g conv 2 f lo = 10.6 ghz, f if = 1.1 g to 2.15 ghz, p in = ? 50 dbm 2.0 db conversion gain flatness 3 g conv 3 f lo = 10.75 ghz, f if = 0.95 g to 2.0 ghz, p in = ? 50 dbm 2.0 db noise figure 1 nf1 f lo = 9.75 ghz, f if = 1.5 ghz 7.5 db noise figure 2 nf2 f lo = 10.6 ghz, f if = 1.5 ghz 7.5 db noise figure 3 nf3 f lo = 10.75 ghz, f if = 1.5 ghz 7.5 db gain 1 db compression output power 1 p o(1 db) 1 f lo = 9.75 ghz, f if = 1.5 ghz 5 dbm gain 1 db compression output power 2 p o (1 db) 2 f lo = 10.6 ghz, f if = 1.5 ghz 5 dbm gain 1 db compression output power 3 p o(1 db) 3 f lo = 10.75 ghz, f if = 1.5 ghz 5 dbm output 3rd order intercept point 1 oip 3 1 f lo = 9.75 ghz, f if 1 = 1 500 mhz, f if 2 = 1 501 mhz 16 dbm output 3rd order intercept point 2 oip 3 2 f lo = 10.6 ghz, f if 1 = 1 500 mhz, f if 2 = 1 501 mhz 16 dbm output 3rd order intercept point 3 oip 3 3 f lo = 10.75 ghz, f if 1 = 1 500 mhz, f if 2 = 1 501 mhz 16 dbm rf input return loss rl rf f rf = 10.7 g to 12.75 ghz 10 db if output return loss rl if f rf = 950 m to 2 150 mhz 10 db phase noise 1 pn1 1 khz offset ? 78 dbc/hz phase noise 2 pn2 10 khz offset ? 80 dbc/hz phase noise 3 pn3 100 khz offset ? 88 dbc/hz phase noise 4 pn4 1 mhz offset ? 108 dbc/hz integrated phase noise density n (itg) integrated offset frequency 10 k to 15 mhz 1.7 rms local signal leakage 1 l o_leakage 1 f lo = 9.75 ghz, local to rf in ? 58 dbm local signal leakage 2 l o_leakage 2 f lo = 10.6 ghz, local to rf in ? 58 dbm local signal leakage 3 l o_leakage 3 f lo = 10.75ghz, local to rf in ? 57 dbm total circuit current 1 (reference status 1) i cc 1 2ch fet bias supplied v pola > 7.0 v, non-rf 83 ma total circuit current 2 (reference status 2 ) i cc 2 3ch fet bias supplied v pola > 7.0 v, non-rf 93 ma note: see the evaluation (application) circuit.
pc3250t7l r09ds0052ej0100 rev.1.00 page 7 of 18 oct 23, 2012 standard characteristics for reference (t a = +25 c, v ccrf = v ccif = v ddpl l = +3.3 v, g sw = 0 v, z s = z l = 50 , f xtal = 25 mhz, unless otherwise specified) parameter symbol test conditions reference value unit conversion gain 1 g conv 1 f lo = 9.75 ghz, f if = 1.5 ghz, p in = ? 50 dbm 36 db conversion gain 2 g conv 2 f lo = 10.6 ghz, f if = 1.5 ghz, p in = ? 50 dbm 36 db conversion gain 3 g conv 3 f lo = 10.75ghz, f if = 1.5 ghz, p in = ? 50 dbm 36 db conversion gain flatness 1 g conv 1 f lo = 9.75 ghz, f if = 0.95 g to 1.95 ghz, p in = ? 50 dbm 2.5 db conversion gain flatness 2 g conv 2 f lo = 10.6 ghz, f if = 1.1 g to 2.15 ghz, p in = ? 50 dbm 2.0 db conversion gain flatness 3 g conv 3 f lo = 10.75 ghz, f if = 0.95 g to 2.0 ghz, p in = ? 50 dbm 2.0 db noise figure 1 nf1 f lo = 9.75 ghz, f if = 1.5 ghz 7.5 db noise figure 2 nf2 f lo = 10.6 ghz, f if = 1.5 ghz 7.5 db noise figure 3 nf3 f lo = 10.75 ghz, f if = 1.5 ghz 7.5 db gain 1 db compression output power 1 p o(1 db) 1 f lo = 9.75 ghz, f if = 1.5 ghz 2 dbm gain 1 db compression output power 2 p o(1 db) 2 f lo = 10.6 ghz, f if = 1.5 ghz 2 dbm gain 1 db compression output power 3 p o(1 db) 3 f lo = 10.75 ghz, f if = 1.5 ghz 2 dbm output 3rd order intercept point 1 oip 3 1 f lo = 9.75 ghz, f if 1 = 1 500 mhz, f if 2 = 1 501 mhz 12 dbm output 3rd order intercept point 2 oip 3 2 f lo = 10.6 ghz, f if 1 = 1 500 mhz, f if 2 = 1 501 mhz 12 dbm output 3rd order intercept point 3 oip 3 3 f lo = 10.75 ghz, f if 1 = 1 500 mhz, f if 2 = 1 501 mhz 12 dbm rf input return loss rl rf f rf = 10.7 g to 12.75 ghz 10 db if output return loss rl if f rf = 950 m to 2 150 mhz 10 db note: see the evaluation (application) circuit.
pc3250t7l r09ds0052ej0100 rev.1.00 page 8 of 18 oct 23, 2012 truth table local oscillator frequency select pi n function description (pin 24 (lo sel )) lo sel = low (dvb-s mode) lo sel = high (abs-s mode) lo sel tone signal = 0 khz tone signal = 22 khz ? local oscillator frequency 9.75 ghz 10.6 ghz 10.75 ghz note: the relationships between the lo sel state and the pin connection are as follows. by connecting this pin to gnd line (0 v dc), lo sel becomes ?low? state. by connecting this pin to v dd line (v dd dc), lo sel becomes ?high? state. the v dd described above means the power supply volt age. its value is 3.3 v the same as v ccrf , v ccif , and v ddpll . fet?s dc bias control pin function description (pin 20 (tonepol), polarity control voltage) horizontal fet vertical fet common fet 1 common fet 2 fets v pola v gh v dh v gv v dv v g 1 v d 1 v g 2 v d 2 v pola > 16.2 v note controlled ( ? 2.5 v to +1 v) controlled ( 2 v) disable ( ? 2.5v) disable (0 v) controlled ( ? 2.5 v to + 1 v) controlled ( 2 v) controlled ( ? 2.5 v to + 1 v) controlled ( 2 v) normal mode v pola < 15.2 v note disable ( ? 2.5 v) disable (0 v) controlled ( ? 2.5 v to + 1 v) controlled ( 2 v) controlled ( ? 2.5 v to + 1 v) controlled ( 2 v) controlled ( ? 2.5 v to + 1 v) controlled ( 2 v) power save mode v pola < 3.6 v note disable ( ? 2.5 v) disable (0 v) controlled ( ? 2.5 v to + 1 v) controlled ( 2 v) controlled ( ? 2.5 v to + 1 v) controlled ( 2 v) controlled ( ? 2.5 v to + 1 v) controlled ( 2 v) note: dividing resistor: 8.2 k /51 k see the evaluation (application) circuit. the detail connection of pin 20 (tonepol) is shown in the evaluation circuit. this pin cannot be directly connected to 13 v/18 v polarity control voltage. the polarity control voltage must be divided to a low voltage.
pc3250t7l r09ds0052ej0100 rev.1.00 page 9 of 18 oct 23, 2012 typical characteristics (t a = +25 c, unless otherwise specified ) r cal vs. i d fet , v d fet r cal (k ) adjustment resistor of drain current of low noise fet drain current of low noise fet i d fet (ma) v d fet (v) drain voltage of low noise fet 25 50 75 125 100 0 20 18 16 14 12 10 8 6 4 2 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 i d fet v d fet ta= +85 c if frequency vs. conversion gain conversion gain gconv (db) 500 1 000 1 500 2 000 2 500 3 000 0 45 40 35 30 25 20 if frequency f if (mhz) low gain mode high gain mode abs-s_lowgain highband_lowgain lowband_lowgain abs-s_highgain highband_highgain lowband_highgain t a = +25 c if frequency vs. conversion gain conversion gain gconv (db) 500 1 000 1 500 2 000 2 500 3 000 0 45 40 35 30 25 20 if frequency f if (mhz) high gain mode low gain mode abs-s_lowgain highband_lowgain lowband_lowgain abs-s_highgain highband_highgain lowband_highgain t a = ? 40 c if frequency vs. conversion gain conversion gain gconv (db) 500 1 000 1 500 2 000 2 500 3 000 0 45 40 35 30 25 20 if frequency f if (mhz) low gain mode high gain mode abs-s_lowgain highband_lowgain lowband_lowgain abs-s_highgain highband_highgain lowband_highgain remark the graphs indicate nominal characteristics.
pc3250t7l r09ds0052ej0100 rev.1.00 page 10 of 18 oct 23, 2012 if frequency f if (ghz) if frequency f if (ghz) if frequency f if (ghz) noise figure nf (db) frequency vs. noise figure 0.5 1.0 1.5 2.5 3.0 3.5 2.0 0.0 15 14 13 12 11 10 9 8 7 6 5 abs-s_lowgain abs-s_highgain highband_lowgain highband_highgain lowband_highgain lowband_lowgain t a = +25 ?c noise figure nf (db) frequency vs. noise figure 0.5 1.0 1.5 2.5 3.0 3.5 2.0 0.0 15 14 13 12 11 10 9 8 7 6 5 t a = ? 40 ?c abs-s_lowgain abs-s_highgain highband_lowgain highband_highgain lowband_highgain lowband_lowgain noise figure nf (db) frequency vs. noise figure 0.5 1.0 1.5 2.5 3.0 3.5 2.0 0.0 15 14 13 12 11 10 9 8 7 6 5 t a = +85 ?c lowband_highgain lowband_lowgain highband_lowgain highband_highgain abs-s_lowgain abs-s_highgain remark the graphs indicate nominal characteristics.
pc3250t7l r09ds0052ej0100 rev.1.00 page 11 of 18 oct 23, 2012 evaluation circuit v ddpll tonepol if out v ccif v ccrf lo sel v g 2 v d 2 v g 1 v d 1 v gv v dv cp out v ref xo1 xo2 cvneg g sw rf in r cal nc v dh v gh 1 pin nc gnd (top view) 100 pf 47 nh 100 pf 1 f 0.1 f if out rf in 10 f 0.1 f tone polar 220 nf 15 pf 15 pf 1 f 390 pf tone v ddpll (3.3 v) 1 nf 0.1 f 1 f 10 51 1 nf 0.1 f 1 f 10 51 1 nf 0.1 f 1 f common fet2 10 51 1 nf 22 k for example, r cal = 22 k , i d = 10 ma is set. 1 f 10 51 lo sel v cc (3.3 v) 220 47 g sw 1 nf at-41cd2 (f xtal = 25 mhz) 8.2 k 51 k common fet1 vertical fet horizontal fet for example, polarity control voltage is v pola = +13 v and +18 v, v tp is divided to a low voltage, +1.8 v and +2.5 v, respectively, by the resistors (8.2 k , 51 k ). remark nc means non-connection. heat sink (bottom side of the device) is connected to gnd. board material is ro4003c (rogers, t = 0.508 mm). 118 613 19 24 12 7 0.1 f
pc3250t7l r09ds0052ej0100 rev.1.00 page 12 of 18 oct 23, 2012 application circuit for single lnb (reference only) 5v v ddpll tonepol if out v ccif v ccrf lo sel v g 2 v d 2 v g 1 v d 1 v gv v dv cp out v ref xo1 xo2 cvneg g sw rf in r cal v dh v gh 1 pin gnd (top view) 1 nf 1 f 390 pf 220 nf 220 0.1 f 10 f 51 k 8.2 k 78m05 out in gnd 100 pf 47 0.1 f 56 47 nh 1 f 100 pf 30 22 k bpf 0.1 f 1 nf 0.1 f 0.1 f 1 nf 1 nf horizontal vertical if out nc nc
pc3250t7l r09ds0052ej0100 rev.1.00 page 13 of 18 oct 23, 2012 for twin lnb (double single lnb) (reference only) 5v 5v 0.1 f 0.1 f 1 nf bpf 22 k if out 1 100 0.1 f 1 nf 0.1 f 0.1 f 1 nf horizontal 1 nf 0.1 f 1 nf 1 nf 0.1 f 1 f 100 pf 47 nh 0.1 f 0.1 f 10 f 1 f 0.1 f 10 f 220 nf 0.1 f 220 nf 390 pf 220 30 12 8.2 k 51 k 1 nf 78m05 1 nf 100 pf 47 100 pf 30 8.2 k 51 k 1 nf 47 out in gnd 390 pf 220 22 k bpf 1 f 1 f 100 pf 47 nh 78m05 out in gnd if out 2 vertical 0.1 f 100 1 nf 1 nf v ddpll tonepol if out v ccif v ccrf lo sel v g 2 v d 2 v g 1 v d 1 v gv v dv cp out v ref xo1 xo2 cvneg g sw rf in r cal v dh v gh 1 pin gnd (top view) v ddpll tonepol if out v ccif v ccrf lo sel v g 2 v d 2 v g 1 v d 1 v gv v dv cp out v ref xo1 xo2 cvneg g sw rf in r cal v dh v gh 1 pin gnd (top view) nc nc nc nc
pc3250t7l r09ds0052ej0100 rev.1.00 page 14 of 18 oct 23, 2012 mounting pad layout dimensions 24-pin plastic qfn (t7l) package (4.0 4.0 0.6 mm) (unit : mm) 2.15 2.15 1.65 1.65 1.35 1.35 0.5 pitch 0.25 0.25 24-0.2 2.15 2.15 1.65 1.65 1.35 1.35
pc3250t7l r09ds0052ej0100 rev.1.00 page 15 of 18 oct 23, 2012 package dimensions 24-pin plastic qfn (t7l) package (4.0 4.0 0.6 mm) (unit : mm) 4.0?.1 4.0?.1 (bottom view) 0.57 +0.03 ? 0.05 0.2 + 0.07 ? 0.05 2.7?.1 2.7?.1 0.5?.1 0.35?.075 (c0.2) (top view) (side view) (dimensions of each pin part) a a 0.08 min. pin1 remark a > 0
pc3250t7l r09ds0052ej0100 rev.1.00 page 16 of 18 oct 23, 2012 recommended soldering conditions this product should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact your nearby sales office. soldering method soldering conditions condition symbol infrared reflow peak temperature (package surface temperature) : 260 c or below time at peak temperature : 10 seconds or less time at temperature of 220 c or higher : 60 seconds or less preheating time at 120 to 180 c : 120 30 seconds maximum number of reflow processes : 3 times maximum chlorine content of rosin flux (% mass) : 0.2% (wt.) or below ir260 partial heating peak temperature (package surface temperature) : 350 c or below soldering time (per side of device) : 3 seconds or less maximum chlorine content of rosin flux (% mass) : 0.2% (wt.) or below hs350 caution do not use different soldering methods together (except for partial heating).
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history pc3250t7l data sheet description rev. date page summary 1.00 oct 23, 2012 ? first edition issued
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(note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. htt p ://www.renesas.co m refer to "htt p ://www.renesas.com/" for the latest and detailed information . california eastern laboratories , inc. 4590 patrick henr y drive, santa clara, california 95054, u.s.a . tel: +1-408-919-2500, fax: +1-408-988-0279 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co. , ltd . 11f., samik lavied' or bld g ., 720-2 yeoksam-don g , kan g nam-ku, seoul 135-080, korea tel: +82-2-558-3737 , fax: +82-2-558-514 1 s ale s o ffi c e s ? 2012 renesas electronics corporation. all ri g hts reserved . [ colo p hon 2.2 ]

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