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i ntegrated c ircuits d ivision ds-CPC7701-r03 www.ixysic.com 1 features ? processed with bcdmos on soi (silicon on insulator) ? flexible high voltage supplies up to v pp -v nn =200v ? internal output bleed resistors ? dc to 10mhz analog signal frequency ? 60db minimum output-off isolation at 5mhz ? low quiescent power dissipation (< 1 ? a typical) ? low output on-resistance ? surface mount package applications ? ultrasound imaging ? printers ? industrial controls and measurement ? piezoelectric transducer drivers figure 1. block diagram description the CPC7701 is a low charge injection 16-channel high-voltage analog switch integrated circuit (ic) for use in applications requiring high voltage switching. bleed resistors are incorporated into both terminals of each output switch. control of the high voltage switching is via low voltage cmos logic level inputs for direct connectivity to the system controller. switch manipulation is managed by an 16-bit serial to parallel shift register whose outputs are buffered and stored by a 16-bit transparent latch. level shifters buffer the latch outputs and operate the high voltage switches. because the CPC7701 is capable of switching high load voltages and has a flexible load voltage range, e.g. v pp /v nn : +40v/160v or +100v/100v, it is well suited for many medical and industrial applications such as medical ultrasound imaging, printers, and industrial measurement equipment. the bleed resistors enable the discharge of capacitive loads, such as piezoelectric transducers, connected to the output switches of the CPC7701. construction of the high voltage switches using ixys integrated circuits divisi on's reliable soi bcdmos process technology allows the switches to be organized as solid state switches with direct gate drive. ordering information v nn v pp cl d i n clk d out v dd 16 bit shift register latches output switches le rg n d sw0 cl d le sw1 cl d le sw2 cl d le sw3 cl d le sw4 cl d le sw5 cl d le sw6 cl d le sw15 cl d le le v el shifters part number description CPC7701k 48-pin lqfp in trays (250/tray) CPC7701ktr 48-pin lqfp tape & reel (2000/reel) e 3 pb CPC7701 16-channel high voltage analog switch with integrated bleed resistors
i ntegrated c ircuits d ivision CPC7701 2 www.ixysic.com r03 1. specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3. manufacturing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 moisture sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 board wash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 mechanical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 tape and reel specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
i ntegrated c ircuits d ivision CPC7701 r03 www.ixysic.com 3 1. specifications 1.1 package pinout 1.2 pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 pin name description 3 sw4 sw4 output 4 sw4 sw4 output 5 sw3 sw3 output 6 sw3 sw3 output 7 sw2 sw2 output 8 sw2 sw2 output 9 sw1 sw1 output 10 sw1 sw1 output 11 sw0 sw0 output 12 sw0 sw0 output 13 v nn switch negative high voltage supply 15 v pp switch positive high voltage supply 17 gnd ground: all voltages are referenced to ground 18 v dd logic positive supply voltage 19 d in serial data input 20 clk clock input, positive edge trigger 21 le latch enable, active low 22 cl latch clear, active high, asynchronously clears latches and opens switches 23 d out serial data output 24 r gnd ground for bleed resistors, connect to gnd 25 sw15 sw15 output 26 sw15 sw15 output 27 sw14 sw14 output 28 sw14 sw14 output 29 sw13 sw13 output 30 sw13 sw13 output 31 sw12 sw12 output 32 sw12 sw12 output 33 sw11 sw11 output 34 sw11 sw11 output 37 sw10 sw10 output 38 sw10 sw10 output 39 sw9 sw9 output 40 sw9 sw9 output 41 sw8 sw8 output 42 sw8 sw8 output 43 sw7 sw7 output 44 sw7 sw7 output 45 sw6 sw6 output 46 sw6 sw6 output 47 sw5 sw5 output 48 sw5 sw5 output 1, 2, 14, 16, 35, 36 n/c no connection
i ntegrated c ircuits d ivision 4 www.ixysic.com r03 CPC7701 1.3 absolute maximum ratings electrical absolute maximum ratings are at 25c. all voltages are referenced from ground (gnd). absolute maximum ratings ar e stress ratings. stresses in excess of these ratings can cause permanent damage to the device. functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. 1.4 operating conditions 1 power up/down sequence is arbitrary except that gnd must be powered-up first and powered-down last. 2 v s w must be v nn ? v s w ? v pp or floating during power up/down transition. parameter min max units v dd logic power supply voltage -0.5 7 v v pp - v nn supply voltage -220v v pp positive high voltage supply -0.5 v nn +200 v v nn negative high voltage supply -0.5 v pp -200 v r gnd -gnd differential -0.3 +0.3 v logic input voltages -0.5 v dd +0.3 v analog signal range v nn v pp v peak analog signal current per channel - 1 a power dissipation - 2.3 w storage temperature - 65 +150 ? c parameter symbol value logic power supply voltage 1 v dd 3v to 5.5v positive high voltage supply 1 v pp 40v to v nn + 200v negative high voltage supply 1 v nn -40v to -160v analog signal voltage, peak-to-peak 2 v sw v nn +10v to v pp -10v operating temperature t a 0c to 70c
i ntegrated c ircuits d ivision CPC7701 r03 www.ixysic.com 5 1.5 electrical characteristics 1.5.1 switch characteristics (over recommended operating conditi ons unless otherwise noted.) * does not include the leakage current contribution due to the bleed resistors. parameter symbol test conditions 0c +25c +70c units min max min typ max min max switch on-resistance, small signal r ons v pp =40v, v nn =-160v i sw =5ma - 30 - 27 35 - 48 ? i sw =200ma - 26 - 22 29 - 40 v pp =100v, v nn =-100v i sw =5ma - 30 - 27 35 - 48 i sw =200ma - 26 - 22 29 - 40 v pp =160v, v nn =-40v i sw =5ma - 30 - 27 35 - 48 i sw =200ma - 26 - 22 29 - 40 switch on-resistance matching, small signal ? r ons v pp =100v, v nn =-100v, i sw =5ma -20- 420-20% switch on-resistance, large signal r onl v sw =v pp -10v, i sw =1a ---15--- ? output bleed resistors r int output switch to r gnd , i rint =0.5ma - - 20 28 50 - - k ? switch off leakage, per switch* i sol v sw =v pp -10v and v nn +10v -5-0.410-15 ? a dc offset, switch off v os no load - 300 - - 300 - 300 mv dc offset, switch on v os no load - 500 - - 500 - 500 switch output peak current i sw v sw duty cycle = 0.1% ----1--a output switch frequency f sw duty cycle = 50% ----50--khz maximum v sw slew rate dv/dt v pp =160v, v nn =-40v -20- -20-20v/ns v pp =100v, v nn =-100v v pp =40v, v nn =-160v off isolation k o f=5mhz, z l =1k ? || 15pf load 30-30- -30- db f=5mhz, r l =50 ? load 58-58- -58- switch crosstalk k cr f=5mhz, r l =50 ? load -60 - -60 - - -60 - db output switch isolation diode current i id 300ns pulse width, 2.0% duty cycle - 300 - - 300 - 300 ma off capacitance, sw to gnd c sg(off) v sw =0v, f=1mhz 5175 -17517 pf on capacitance, sw to gnd c sg(on) v sw =0v, f=1mhz 25 50 20 - 50 25 50 output voltage spike +v spk v pp =40v, v nn =-160v r l =50 ? ----150-- mv -v spk +v spk v pp =100v, v nn =-100v ----150-- -v spk +v spk v pp =160v, v nn =-40v ----150-- -v spk charge injection q v pp =100v, v nn =-100v, v sw =0v -820- pc
i ntegrated c ircuits d ivision 6 www.ixysic.com r03 CPC7701 1.5.2 logic timing characteristics (over recommended operating conditi ons unless otherwise noted.) 1.5.3 logic timing waveforms parameter symbol test conditions 0c +25c 70c units min max min typ max min max setup time before le rises t sd - 150 - 150 - - 150 - ns time width of le t wle v dd =3v 56-56- -56- v dd =5v 12-12- -12- clock delay time to data out t do v dd =3v 10 100 10 - 100 10 100 v dd =5v 5455 -45545 time width of cl t wcl - 55 - 55 - - 55 - setup time, data to clock t su v dd =3v 21 - - 21 - 21 - v dd =5v 7--7-7- hold time, data from clock t h -2-2--2- clock frequency f clk 50% duty cycle, f data = ? f clk , v dd =3v -8--8-8 mhz 50% duty cycle, f data = ? f clk , v dd =5v -20- -20-20 clock rise and fall times t r , t f - - 50 - - 50 - 50 ns tu r n - o n t i m e t on v sw =v pp -10v, rl=10k ? -5--5-5 ? s turn-off time t off d n-1 d n d n+1 50% 50% 50% 50% d in le t wle t sd 50% 50% clk t su t h t do 50% d out t off t on 90% 10% off on cl 50% 50% t wcl v out
i ntegrated c ircuits d ivision CPC7701 r03 www.ixysic.com 7 1.5.4 logic dc characteristics (over recommended operating conditi ons unless otherwise noted.) 1.5.5 supply dc characteristics (over recommended operating conditi ons unless otherwise noted.) 1.5.6 thermal characteristics parameter symbol test conditions 0c +25c +70c units min max min typ max min max d out source capability v oh i out = -400 ? a -- v dd -0.7 v dd -0.1 --- v d out sink capability v ol i out = +400 ? a - - - 0.04 0.7 - - input (logic) capacitance c in - - 10 - - 10 - 10 pf input, logic high v ih - 0.9 v dd - 0.9 v dd -- 0.9 v dd - v input, logic low v il -- 0.1 v dd -- 0.1 v dd - 0.1 v dd parameter symbol test conditions 0c +25c +70c units min max min typ max min max v pp quiescent supply current i ppq all switches off ---0.150-- ? a all switches on, i sw =5ma v nn quiescent supply current i nnq all switches off ----0.1- 50-- all switches on, i sw =5ma v pp operating supply current i pp v pp =40v, v nn =-160v 50khz output switching frequency with no load -6.5- - 7 - 8 ma v pp =100v, v nn =-100v - 4 - - 5.5 - 5.5 v pp =160v, v nn =-40v -4--5-5.5 v nn operating supply current i nn v pp =40v, v nn =-160v 50khz output switching frequency with no load -6.5- - 7 - 8 ma v pp =100v, v nn =-100v - 4 - - 5.5 - 5.5 v pp =160v, v nn =-40v -4--5-5.5 v dd average supply current i dd f clk =5mhz, v dd =5v -4--4-4ma v dd quiescent supply current i ddq - - 10 - 0.03 10 - 10 ? a parameter conditions symbol minimum typical maximum units thermal resistance (junction to ambient) free air r ? ja --53c/ w
i ntegrated c ircuits d ivision 8 www.ixysic.com r03 CPC7701 2. functional description the CPC7701 takes a serial stream of input data along with a synchronous clock signal. as the clock transits from low to high, the data at the input of each shift register is shifted through from sr(n) to sr(n+1). a high data bit, a ?1,? represents an on switch; a low data bit, a ?0,? represents an off switch. data is input and shifted through the internal shift register until all sixteen shift register positions, sr0 through sr15, are in the desired state. d in : the data-in line presents data bits to the CPC7701 to be shifted through the internal shift register. the last bit into the shift register is the s w 0 control bit. clk: the clock signal's risi ng edge is associated only with shifting data into and through the shift register. cl: the clear line overrides all other inputs. w hen cl is high, the shift register is asynchronously cleared to all 0s and all latches are set low, which causes all output switches to be turned off immediately. w hen cl is low, all output switches remain in whatever state they are in, on or off, in response to clk, latch inputs, and the le signal. le : latch enable controls the state of the latches and the state of the sixteen switches. if le is high, then the latches do not change states, but retain their most recent status: either on or off. w ith le high, input data and clk have no effect on the state of the output switches. if le is low, then all latch outputs and their switch states follow the inputs from the shift register. le is overridden by cl: no matter what state le is in, cl clears the latches. see ?truth table? on page 9 . note that holding le active while clocking in new data will cause the outputs to toggle with the shifting data. d out : the data-out pin is the output of sr15. after sixteen clock pulses, the first bit of sixteen shifted input data bits is output at sr15, and appears on d out . sw0 - sw15: the CPC7701 provides sixteen high-voltage spst output switches with a nominal small signal on-resistance of 25 ? . the two connections of each switch are not polarity-sensitive. as can be seen in ?block diagram? on page 1 , integrated bleed resistors are provided to facilitate charge dissipation for capa citive load applications. v pp and v nn : voltage inputs to the level shifters for each switch channel that translate the voltage level of the latch output signals to an appropriate level for the voltages being switched. the high-voltage output switches are turned on and off in response to the data sent into the latches from the shift register: data 0 turns a switch off, data 1 turns a switch on. two or more CPC7701 devices can be cascaded to form an n-switch arrangement. the d out pin of the first is connected to the d in pin of the next in the series. all devices are connected to the same clock (clk) signal. le of all devices would normally be connected, as would cl, but this is not necessary. the first data bit applied to d in of the CPC7701, whether it's a single device or several cascaded devices, ripples through to the last switch output in line after the application of a full clocking sequence of 16 clock pulses. setting the serial i/o device to output the most significant bit (msb) first, results in the msb appearing on s w 15 of the last device in line after a full clocking sequence. cl d i n clk le sw0 sw15 sw0 sw15 sw0 sw15 d out le cl d i n clk d out le cl d i n clk d out le cl d i n clk CPC7701 CPC7701 CPC7701
i ntegrated c ircuits d ivision CPC7701 r03 www.ixysic.com 9 2.1 truth table 1. the sixteen s w itches operate independently. 2. serial data is clocked in on the rising edge of the clk signal. 3 . the s w itches go to a state retaining their present condition at the rising edge of le. when le is lo w , the shift register data flo w s thro u gh the latch. 4. d out is high w hen s w itch sw15 is on. 5. shift register clocking has no effect on the s w itch states if le is h. 6. the clear inp u t o v errides all other inp u ts. d2 sw0 d0 d1 d3 d4 d5 d6 d7 d 8 d9 d10 d11 d12 d13 d14 d15 le cl sw1 sw2 sw3 sw4 sw5 sw6 sw7 sw 8 sw9 sw10 sw11 sw12 sw13 sw14 sw15 off l on h off l on h off l on h off l on h off l on h off l on h off l on h off l on h off l on h off l on h off l on h off l on h off l on h off l on h off l on h off l on h ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll ll hl xh xxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx off off off off off off off off off off off off off off off off hold previous state
i ntegrated c ircuits d ivision 10 www.ixysic.com r03 CPC7701 3. manufacturing information 3.1 moisture sensitivity all plastic encapsulated semiconductor packages are susc eptible to moisture ingression. ixys integrated circuits division clas sified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, ipc/jedec j-std-020 , in force at the time of product evaluation. w e test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. failure to adhere to the warnings or limitations as establ ished by the listed specificati ons could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. this product carries a moisture sensitivity level (msl) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard ipc/jedec j-std-033 . 3.2 esd sensitivity this product is esd sensitive , and should be handled according to the industry standard jesd-625 . 3.3 reflow profile this product has a maximum body temperature and time rating as shown below. all other guidelines of j-std-020 must be observed. 3.4 board wash ixys integrated circuits division recommends the use of no-clean flux formulations. however, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. chlorine-based or fluorine-based solvents or fluxes should not be used. clean ing methods that employ ultrasonic energy should not be used. device moisture sensitivity level (msl) rating CPC7701k msl 3 device maximum temperature x time CPC7701k 260c for 30 seconds e 3 pb
i ntegrated c ircuits d ivision CPC7701 r03 www.ixysic.com 11 3.5 mechanical dimensions 3.6 tape and reel specifications dimensions mm (inches) 0.60, +0.15/-0.10 (0.024, +0.006/-0.004) 1.60 max (0.063max) 1.40 0.05 (0.055 0.002) 0.05 min / 0.15 max (0.002 min - 0.006 max) 0.50 (0.020) pcb land pattern 8 .40 (0.331) 0.50 (0.020) 0.30 (0.012) 1.50 (0.059) 8 .40 (0.331) pin 4 8 pin 1 0.22 0.05 (0.009 0.002) 7.00 0.10 (0.276 0.004) 9.00 0.20 (0.354 0.00 8 ) 9.00 0.20 (0.354 0.00 8 ) 7.00 0.10 (0.276 0.004) dimensions mm (inches) k 0 =2.20 (0.0 8 7) k 1 =1.60 (0.063) 16.00.3 (0.630.012) 12.00 (0.472) a 0 =9.30 (0.366) b 0 =9.30 (0.366) em b ossment em b ossed carrier top co v er tape thickness 0.102 max. (0.004 max.) 330.2 dia. (13.00 dia.) n ote: unless other w ise specified, tolerance 0.1 (0.004) for additional information please visit www.ixysic.com ixys integrated circuits division makes no representations or warranties with respect to the accuracy or completeness of the co ntents of this publication and reserves the right to make changes to s pecifications and product descri ptions at any time without notice. neither circuit paten t licenses or indemnity are expressed or implied. except as set forth in ixys integrated circuits div ision?s standard terms and conditions of sale, ixys integrated c ircuits division assumes no liability whatsoever, and disclaims any express or implied warranty relating to its products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. the products described in this document ar e not designed, intended, aut horized, or warranted for use as components in systems i ntended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of ixys integrated circuits divisi on?s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. ixys integrated circuits division reserves the r ight to discontinue or make changes to its products at any time without notice. specification: ds-CPC7701-r03 ? copyright 2012, ixys in tegrated circuits division all rights reserved. printed in usa. 12/18/2012

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