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datasheet 8-output low-power buffer for pcie gen1-2-3 and qpi 9ZXL0831 idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 1 9ZXL0831 rev b 073014 general description the 9ZXL0831 is a low-power 8-output differential buffer that meets all the performance requirements of the intel db800zl specification. the 9ZXL0831 is backwards compatible to pcie gen1-2 and qpi 6.4gt/s specifications. a fixed, internal feedback path maintains low drift for critical qpi applications. recommended application 8-output low power pcie gen1-2-3/ qpi buffer output features ? 8 - 0.7v low-power hcsl-compatible output pairs features/benefits ? low-power push-pull outputs; save power and board space - no rp ? space-saving 48-pin vfqfpn package ? fixed feedback path for 0ps input-to-output delay ? 8 oe# pins; hardware control of each output ? pll or bypass mode; pll can dejitter incoming clock ? 100mhz or 133mhz pll mode operation; supports pcie and qpi applications ? selectable pll bandwidth; minimizes jitter peaking in downstream pll's ? spread spectrum compatible; tracks spreading input clock for low emi key specifications ? cycle-to-cycle jitter <50ps ? output-to-output skew <65 ps ? input-to-output delay variation <50ps ? pcie gen3 phase jitter <1.0ps rms ? qpi 9.6gt/s 12ui phase jitter <0.2ps rms block diagram logic dif(7:0) hibw_bypm_lobw# smbdat smbclk ckpwrgd/pd# 100m_133m# z-pll (ss compatible) dfb_out_nc dif_in dif_in# oe(7:0)#
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 2 9ZXL0831 rev b 073014 pin configuration power management table functionality at power-up (pll mode) power connections smbus address pll operating mode readback table tri-level input thresholds pll operating mode hibw_bypm_lobw# 100m_133m# nc nc vdda nc vdd voe7# dif_7# dif_7 vdd voe6# 48 47 46 45 44 43 42 41 40 39 38 37 ckpwrgd_pd# 1 36 dif_6# gnd 2 35 dif_6 vddr 3 34 vdd dif_in 4 33 dif_5# dif_in# 5 32 dif_5 smbdat 6 31 vo e 5# smbclk 7 30 vo e 4# dfb_out_nc# 8 29 dif_4# dfb_out_nc 9 28 dif_4 vdd 10 27 vdd vo e 0# 11 26 dif_3# nc 12 25 dif_3 13 14 15 16 17 18 19 20 21 22 23 24 dif_0 dif_0# vdd dif_1 dif_1# voe1 # vdd nc dif_2 dif_2# voe2 # voe3 # 48-pin vfqfpn, 6x6 mm, 0.4mm pitch 9ZXL0831 paddle is pin 49 connect to gnd ckpwrgd_pd# dif_in/ dif_in# smbus en bit dif(7:0)/ dif(7:0)# pll state if not in bypass mode 0 x x low/low off 0 low/low on 1 running on running 1 100m_133m# dif_in mhz dif(7:0) 1 100.00 dif_in 0 133.33 dif_in vdd gnd 44 49 analo g pll 3 2 analog input 10,15,19, 27,34,38, 42 49 dif clocks pin number description address 1101100 x + read/write bit hibw_bypm_lobw# byte0, bit 7 byte 0, bit 6 low (low bw) 0 0 mid (bypass) 0 1 high (high bw) 1 1 level voltage low <0.8v mid 1.2 2.2v hibw_bypm_lobw# mode low pll lo bw mid bypass high pll hi bw note: pll is off in bypass mode
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 3 9ZXL0831 rev b 073014 pin descriptions pin # pin name type description 1 ckpwrgd_pd# in 3.3v input notifies device to sample latched inputs and start up on first high assertion, or exit power down mode on subsequent assertions. low enters power down mode. 2 gnd gnd ground pin. 3vddr pwr 3.3v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 4 dif_in in 0.7 v differential true input 5 dif_in# in 0.7 v differential complementary input 6 smbdat i/o data pin of smbus circuitry, 5v tolerant 7 smbclk in clock pin of smbus circuitry, 5v tolerant 8 dfb_out_nc# out complementary half of differential feedback output, provides feedback signal to the pll for synchronization with input clock to eliminate phase error. this pin should not be connected on the circuit board, the feedback is internal to the package. 9 dfb_out_nc out true half of differential feedback output, provides feedback signal to the pll for synchronization with the input clock to eliminate phase error. this pin should not be connected on the circuit board, the feedback is internal to the package. 10 vdd pwr power supply, nominal 3.3v 11 voe0# in active low input for enabling dif pair 0. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 12 nc n/a no connection. 13 dif_0 out 0.7v differential true clock output 14 dif_0# out 0.7v differential complementary clock output 15 vdd pwr power supply, nominal 3.3v 16 dif_1 out 0.7v differential true clock output 17 dif_1# out 0.7v differential complementary clock output 18 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 19 vdd pwr power supply, nominal 3.3v 20 nc n/a no connection. 21 dif_2 out 0.7v differential true clock output 22 dif_2# out 0.7v differential complementary clock output 23 voe2# in active low input for enabling dif pair 2. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 24 voe3# in active low input for enabling dif pair 3. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 25 dif_3 out 0.7v differential true clock output 26 dif_3# out 0.7v differential complementary clock output 27 vdd pwr power supply, nominal 3.3v 28 dif_4 out 0.7v differential true clock output 29 dif_4# out 0.7v differential complementary clock output 30 voe4# in active low input for enabling dif pair 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 31 voe5# in active low input for enabling dif pair 5. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 4 9ZXL0831 rev b 073014 pin descriptions (cont.) pin # pin name type description 32 dif_5 out 0.7v differential true clock output 33 dif_5# out 0.7v differential complementary clock output 34 vdd pwr power supply, nominal 3.3v 35 dif_6 out 0.7v differential true clock output 36 dif_6# out 0.7v differential complementary clock output 37 voe6# in active low input for enabling dif pair 6. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 38 vdd pwr power supply, nominal 3.3v 39 dif_7 out 0.7v differential true clock output 40 dif_7# out 0.7v differential complementary clock output 41 voe7# in active low input for enabling dif pair 7. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 42 vdd pwr power supply, nominal 3.3v 43 nc n/a no connection. 44 vdda pwr 3.3v power for the pll core. 45 nc n/a no connection. 46 nc n/a no connection. 47 100m_133m# in 3.3v input to select operating frequency. see functionality table for definition 48 hibw_bypm_lobw# in trilevel input to select high bw, bypass or low bw mode. see pll operating mode table for details. 49 gnd pwr ground
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 5 9ZXL0831 rev b 073014 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9ZXL0831. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical pa rameters are guaranteed only over the recommended operating temperature range. electrical characteristics?clock in put parameters (hcsl-compatible) parameter symbol conditions min typ max units notes 3.3v supply voltage vdd, vdda, vddr vdd for core logic and pll 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor g uaranteed. t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode volta g e - dif_in v com common mode input voltage (sin g le-ended measurement) 300 1000 mv 1 input amplitude - dif_in v swing peak to peak (differential) 300 mv 1 input slew rate - dif_in dv/dt measured differentially 0.35 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured throu g h +/-75mv window centered around differential zero
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 6 9ZXL0831 rev b 073014 electrical characteristics?in put/supply/common parameters t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes ambient operating temperature t com commmercial range 0 70 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ib yp v dd = 3.3 v, bypass mode 33 150 mhz 2 f i p ll v dd = 3.3 v, 100mhz pll mode 90 100.00 110 mhz 2 f i p ll v dd = 3.3 v, 133.33mhz pll mode 120 133.33 147 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c i ndi f_i n dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 0.250 1 ms 1,2 input ss modulation frequency f modi n allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 4 12 cycles 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 10 ns 1,2 trise t r rise time of control inputs 10 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4ma1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swin g . 5 the differential input clock must be running for the smbus to be active input current 3 time from deassertion until outputs are >200 mv 4 dif_in input capacitance input frequency
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 7 9ZXL0831 rev b 073014 electrical characteristics?dif 0.7v low power differential outputs electrical characterist ics?current consumption t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes slew rate trf scope avera g in g on 2 3.3 4 v/ns 1, 2, 3 slew rate matching ? trf slew rate matching, scope averaging on 6.8 20 % 1, 2, 4 voltage high vhigh 660 778 850 1 voltage low vlow -150 0 150 1 max voltage vmax 918 1150 1 min voltage vmin -300 -71 1 vswing vswing scope averaging off 300 1556 1812 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 300 458 550 mv 1, 5 crossing voltage (var) ? -vcross scope averaging off 17 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting ? -vcross to be smaller than vcross absolute. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. c l = 2pf with r s = 27 ? for zo = 85 ? differential trace impedance). 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and fa lling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# fa lling). t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes i ddvdd 133mhz, vdd rail 59 75 ma 1 i ddvdda 133mhz, vdda + vddr rail, pll mode 19 25 ma 1 i ddvddpd power down, vdd rail 1.2 2ma1 i ddvddapd power down, vdda rail 2.5 5ma1 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 c l = 2pf with r s = 27 ? for zo = 85 ? differential trace impedance operating current powerdown current
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 8 9ZXL0831 rev b 073014 electrical characteristics?skew and differential jitter parameters t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes clk_in, dif[x:0] t spo_pll input-to-output skew in pll mode nominal value @ 25c, 3.3v -100 -60 100 ps 1,2,4,5,8 clk_in, dif[x:0] t pd_byp input-to-output skew in bypass mode nominal value @ 25c, 3.3v 2.5 3.2 4.5 ns 1,2,3,5,8 clk_in, dif[x:0] t dspo_pll input-to-output skew varation in pll mode across volta g e and temperature -50 50 ps 1,2,3,5,8 clk_in, dif[x:0] t dspo_byp input-to-output skew varation in bypass mode across voltage and temperature -250 250 ps 1,2,3,5,8 clk_in, dif[x:0] t dte random differential tracking error beween two 9zx devices in hi bw mode 15 ps (rms) 1,2,3,5,8 clk_in, dif[x:0] t dsste random differential spread spectrum tracking error beween two 9zx devices in hi bw mode 5 75 ps 1,2,3,5,8 dif{x:0] t skew_all output-to-output skew across all outputs (common to bypass and pll mode) 53 65 ps 1,2,3,8 pll jitter peaking j p eak-hibw lobw#_bypass_hibw = 1 0 1.2 2.5 db 7,8 pll jitter peaking j p eak-lobw lobw#_bypass_hibw = 0 0 0.76 2 db 7,8 pll bandwidth pll hi bw lobw#_bypass_hibw = 1 2 3 4 mhz 8,9 pll bandwidth pll lobw lobw#_bypass_hibw = 0 0.7 1.1 1.4 mhz 8,9 duty cycle t d c measured differentially, pll mode 45 50.1 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 0 2 % 1,10 pll mode 34 50 ps 1,11 additive jitter in bypass mode 17 50 ps 1,11 notes for preceding table: 6. t is the period of the input clock 7 measured as maximum pass band g ain. at frequencies within the loop bw, hi g hest point of ma g nification is called pll jitter peakin g . 8. guaranteed by design and characterization, not 100% tested in production. 9 measured at 3 db down or half power point. 10 duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in by pass mode. 11 measured from differential waveform jitter, cycle to cycle t jcyc-cyc 1 c l = 2pf with rs = 27 ? for zo = 85 ? differential trace impedance. input to output skew is measured at the first output edge following the corresponding input. 2 measured from differential cross- p oint to differential cross- p oint. this p arameter can be tuned with external feedback p ath , if p resent. 3 all bypass mode input-to-output specs refer to the timing between an input edge and the specific output edge created by it. 4 this parameter is deterministic for a given device 5 measured with scope averaging on to find mean value.
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 9 9ZXL0831 rev b 073014 electrical characteristi cs?phase jitter parameters t a = t com ; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes t jphpcieg1 pcie gen 1 34 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.2 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.2 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.5 1 ps (rms) 1,2,4 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.24 0.5 ps (rms) 1,5 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.14 0.3 ps (rms) 1,5 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.12 0.2 ps (rms) 1,5 t jp hpcieg1 pcie gen 1 3.7 10 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.1 0.3 ps (rms) 1,2,6 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.4 0.6 ps (rms) 1,2,6 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, 2-5mhz, cdr = 10mhz) 0.00 0.2 ps (rms) 1,2,4,6 qpi & smi (100mhz or 133mhz, 4.8gb/s, 6.4gb/s 12ui) 0.14 0.2 ps (rms) 1,5,6 qpi & smi (100mhz, 8.0gb/s, 12ui) 0.00 0.1 ps (rms) 1,5,6 qpi & smi (100mhz, 9.6gb/s, 12ui) 0.00 0.1 ps (rms) 1,5,6 1 applies to all outputs. 6 for rms figures, additive jitter is calculated by solving the following equation: (additive jitter)^2 = (total jittter)^2 - (i nput jitter)^2 4 subject to final ratification by pci sig. 5 calculated from intel-supplied clock jitter tool v 1.6.3 2 see http://www.pcisig.com for complete specs additive phase jitter, bypass mode t jphpcieg2 t jphqpi_smi 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. t jphqpi_smi phase jitter, pll mode t jphpcieg2
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 10 9ZXL0831 rev b 073014 clock periods?differential outputs with spread spectrum disabled clock periods?differential outputs with spread spectrum enabled test loads 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3 133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4 ssc off dif measurement window units notes center freq. mhz 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock -c2c jitter absper min -ssc short-term average min - ppm long-term average min 0 ppm period nominal + ppm long-term average ma x +ssc short-term average ma x +c2c jitter absper max 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3 133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4 notes: 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, 100 mhz pll mode or bypass mode 4 driven by cpu output of main clock, 133 mhz pll mode or bypass mode notes 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck420bq/ck410b+ accuracy requirements (+/-100ppm). the device itself does not contribute to ppm error. dif measurement window units ssc on center freq. mhz differential output terminations dif zo ( ? )rs ( ? ) 100 33 85 27 85ohm differential zo low-power hcsl- compatible output buffer differential test loads rs rs 2pf 2pf 10 inches
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 11 9ZXL0831 rev b 073014 general smbus serial interf ace information for 9ZXL0831 how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o o o o o o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o o o o o o byte n + x - 1 n not acknowledge pstop bit
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 12 9ZXL0831 rev b 073014 smbustable: pll mode, and frequency select register pin # name control function t yp e 0 1 default bit 7 pll mode 1 pll o p eratin g mode rd back 1 r latch bit 6 pll mode 0 pll o p eratin g mode rd back 0 r latch bit 5 0 bit 4 0 bit 3 pll_sw_en enable s/w control of pll bw r w hw latch smbus control 0 bit 2 pll mode 1 pll o p eratin g mode 1 r w 1 bit 1 pll mode 0 pll o p eratin g mode 0 r w 1 bit 0 100m_133m# fre q uenc y select readback r 133mhz 100mhz latch smbustable: output control register pin # name control function t yp e 0 1 default bit 7 dif_5_en out p ut control - '0' overrides oe# p in r w 1 bit 6 dif_4_en out p ut control - '0' overrides oe# p in r w 1 bit 5 dif_3_en out p ut control - '0' overrides oe# p in r w 1 bit 4 dif_2_en out p ut control - '0' overrides oe# p in r w 1 bit 3 1 bit 2 dif_1_en out p ut control - '0' overrides oe# p in r w 1 bit 1 dif_0_en out p ut control - '0' overrides oe# p in r w 1 bit 0 1 smbustable: output control register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 1 bit 2 dif_7_en out p ut control - '0' overrides oe# p in r w low/low enable 1 bit 1 1 bit 0 dif_6_en out p ut control - '0' overrides oe# p in r w low/low enable 1 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 smbustable: reserved register pin # name control function t yp e 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved low/low enable low/low enable reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved b y te 3 35/36 21/22 47 b y te 1 b y te 2 28/29 25/26 b y te 4 16/17 13/14 b y te 0 48 48 32/33 39/40 see pll operating mode readback table see pll operating mode readback table note: setting bit 3 to '1' allows the user to overide the latch value from pin 5 via use of bits 2 and 1. use the values from the pl l operating mode readback table. note that bits 7 and 6 will keep the value originally latched on pin 5. a warm reset of the system will h ave to accomplished if the user changes these bits. reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 13 9ZXL0831 rev b 073014 smbustable: vendor & revision id register pin # name control function t yp e0 1default bit 7 rid3 r x bit 6 rid2 r x bit 5 rid1 r x bit 4 rid0 r x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbustable: device id pin # name control function t yp e0 1default bit 7 r1 bit 6 r1 bit 5 r1 bit 4 r0 bit 3 r0 bit 2 r1 bit 1 r1 bit 0 r1 smbustable: byte count register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 r w 0 bit 3 bc3 r w 1 bit 2 bc2 r w 0 bit 1 bc1 r w 0 bit 0 bc0 r w 0 smbustable: reserved register pin # name control function t yp e0 1default bit 7 0 bit 6 0 bit 5 0 bit 4 0 bit 3 0 bit 2 0 bit 1 0 bit 0 0 reserved reserved device id 7 ( msb ) reserved device id 5 device id 6 device id 0 device id 3 reserved reserved - reserved b y te 7 - - - - - - - - b y te 5 - - - b y te 6 - - - - - b y te 8 reserved reserved - device id 2 device id 1 device id 4 revision id - - - reserved reserved writing to this register configures how many bytes will be read back. default value is 8 hex, so 9 bytes (0 to 8) will be read back by default. reserved 0831 is 231 decimal or e7 hex a rev = 0000 vendor id
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 14 9ZXL0831 rev b 073014 marking diagram notes: 1. ?l? denotes rohs compliant package. 2. ?yyww? is the last two digits of the year and week that the part was assembled. 3. ?coo?: country of origin. 4. ?lot? denotes the lot number. ics zxl0831al yyww coo lot
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 15 9ZXL0831 rev b 073014 package outline and package dimensions (48-pin vfqfpn) ordering information "lf" suffix to the part number are the pb -free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with th e datasheet revision). while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt does not authorize or warrant any idt product for use in life support dev ices or critical medical instruments. millimeters symbol min max a0.81.0 a1 0 0.05 a3 0.20 reference b 0.18 0.3 e 0.40 basic d x e basic 6.00 x 6.00 d2 min./max. 3.95 4.25 e2 min./max. 3.95 4.25 l min./max. 0.30 0.50 n48 n d 12 n e 12 anvil singulation -- or -- sawn singulation 1 2 n e d index area top view seating plane a3 a1 c a l e2 e2 2 d2 d2 2 e c 0.08 (ref) n d & n e odd (ref) n d & n e even (n d -1)x (ref) e n 1 2 b thermal base (typ) if n d & n e are even (n e -1)x (ref) e e 2 part / order number shipping package package temperature 9ZXL0831aklf trays 48-vfqfpn 0 to +70c 9ZXL0831aklft tape and reel 48-vfqfpn 0 to +70c
9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi idt? 8-output low-power buffer for pcie gen1-2-3 and qpi 16 9ZXL0831 rev b 073014 revision history rev. issue date issuer description page # a 10/21/2013 rdw updated electrical tables with char data. move to final various b 7/30/2014 rdw changed db1200zl reference in "general description" to db800zl 1
? 2013 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, ic s, and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp pcclockhelp@idt.com innovate with idt and accelerate your future netw orks. contact: www.idt.com 9ZXL0831 8-output low-power buffer for pcie gen1-2-3 and qpi synthesizers

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