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this is information on a product in full production. november 2013 docid024079 rev 3 1/17 17 STL8N80K5 n-channel 800 v, 0.80 typ., 4.5 a zener-protected supermesh? 5 power mosfet in a powerflat? 5x6 vhv package datasheet ? production data figure 1. internal schematic diagram features ? outstanding r ds(on) *area ? worldwide best fom (figure of merit) ? ultra low gate charge ? 100% avalanche tested ? zener protected applications ? switching applications description this n-channel zener-protected power mosfet is designed using st's revolutionary avalanche- rugged very high voltage supermesh? 5 technology, based on an innovative proprietary vertical structure. the result is a dramatic reduction in on-resistance, and ultra-low gate charge for applications which require superior power density and high efficiency. am15540v1 5 6 7 8 12 34 top view d(5, 6, 7, 8) g(4) s(1, 2, 3) powerflat? 5x6 vhv 1 2 3 4 order code v ds r ds(on)max. i d STL8N80K5 800 v 0.95 4.5 a table 1. device summary order code marking package packaging STL8N80K5 8n80k5 powerflat? 5x6 vhv tape and reel www.st.com
contents STL8N80K5 2/17 docid024079 rev 3 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
docid024079 rev 3 3/17 STL8N80K5 electrical ratings 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v gs gate-source voltage 30 v i d (1) 1. the value is rated according to r thj-case and limited by package. drain current (continuous) at t c = 25 c 4.5 a i d (1) drain current (continuous) at t c = 100 c 3 a i dm (1),(2) 2. pulse width limited by safe operating area. drain current (pulsed) 18 a p tot (1) total dissipation at t c = 25 c 42 w i ar (3) 3. pulse width limited by t jmax avalanche current, repetitive or not- repetitive (pulse width limited by t j max) 2a e as (4) 4. starting t j =25 c, i d =i ar , v dd =50 v single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 114 mj dv/dt (5) 5. i sd 4.5 a, di/dt 100 a/s, v ds(peak) v (br)dss peak diode recovery voltage slope 4.5 v/ns dv/dt (6) 6. v ds 640 v mosfet dv/dt ruggedness 50 v/ns t stg storage temperature - 55 to 150 c t j max. operating junction temperature c table 3. thermal data symbol parameter value unit r thj-case thermal resistance junction-case max 3 c/w r thj-amb (1) 1. when mounted on 1inch2 fr-4 board, 2 oz cu. thermal resistance junction-amb max 59 c/w
electrical characteristics STL8N80K5 4/17 docid024079 rev 3 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4. on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage (v gs = 0) i d = 1 ma 800 v i dss zero gate voltage drain current (v gs = 0) v ds = 800 v 1 a v ds = 800 v, t c =125 c 50 a i gss gate-body leakage current (v ds = 0) v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 4 5 v r ds(on) static drain-source on- resistance v gs = 10 v, i d = 3 a 0.80 0.95 ? table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 - 450 - pf c oss output capacitance - 50 - pf c rss reverse transfer capacitance -1-pf c o(tr) (1) 1. c oss eq. time related is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss equivalent capacitance time related v ds = 0 to 640 v, v gs = 0 -57-pf c o(er) (2) 2. c oss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss equivalent capacitance energy related -24-pf r g intrinsic gate resistance f = 1 mhz, i d =0 - 6 - ? q g total gate charge v dd = 640 v, i d = 6 a, v gs = 10 v (see figure 16 ) -16.5-nc q gs gate-source charge - 3.2 - nc q gd gate-drain charge - 11 - nc
docid024079 rev 3 5/17 STL8N80K5 electrical characteristics the built-in back-to-back zener diodes have been specifically designed to enhance not only the device's esd capability, but also to make them capable of safely absorbing any voltage transients that may occasionally be applied from gate to source. in this respect, the zener voltage is appropriate to achieve efficient and cost-effective protection of device integrity. the integrated zener diodes thus eliminate the need for external components. table 6. switching times symbol parameter test conditions min. typ. max unit t d(on) turn-on delay time v dd = 400 v, i d = 3 a, r g = 4.7 w, v gs = 10 v (see figure 15 ), (see figure 20 ) -12-ns t r rise time - 14 - ns t d(off) turn-off delay time - 32 - ns t f fall time - 20 - ns table 7. source drain diode symbol parameter test conditions min. typ. max. unit i sd source-drain current - 4.5 a i sdm source-drain current (pulsed) - 18 a v sd (1) 1. pulsed: pulse duration = 300 s, duty cycle 1.5% forward on voltage i sd = 6 a, v gs = 0 - 1.5 v t rr reverse recovery time i sd = 6 a, di/dt = 100 a/s v dd = 60 v (see figure 17 ) -300 ns q rr reverse recovery charge - 3 c i rrm reverse recovery current - 20 a t rr reverse recovery time i sd = 6 a, di/dt = 100 a/s v dd = 60 v, t j = 150 c (see figure 17 ) -415 ns q rr reverse recovery charge - 3.8 c i rrm reverse recovery current - 18 a table 8. gate-source zener diode symbol parameter test conditions min typ. max unit v (br)gso gate-source breakdown voltage i gs = 1ma, i d =0 30 - - v
electrical characteristics STL8N80K5 6/17 docid024079 rev 3 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance i d 10 1 0.1 0.01 0.1 1 100 v ds (v) 10 (a) operation in this area is limited by max r ds(on) 10s 100s 1ms 10ms tj=150c tc=25c single pulse am15762v1 single pulse =0.5 0.05 0.02 0.01 0.1 0.2 k 10 t p (s) -4 10 -3 10 -2 10 -1 10 -5 10 -3 10 -2 10 -1 10 0 pcb 10 1 zthpowerflat_5x6_27 figure 4. output characteristics figure 5. transfer characteristics figure 6. gate charge vs gate-source voltage figure 7. static drain-source on-resistance i d 12 8 4 0 0 8 v ds (v) 16 (a) 4 12 6v v gs =10, 11v 2 6 10 7v 8v 9v am15633v1 i d 12 8 4 0 5 7 v gs (v) 9 (a) 6 8 10 2 6 10 v ds =20v am15634v1 v gs 6 4 2 0 0 4 q g (nc) (v) 16 8 8 12 10 12 300 200 100 0 400 500 v ds v ds (v) 600 v dd =640v i d =6a am15635v1 r ds(on) 1.2 0.8 0.4 0 1 4 i d (a) ( ) 3 5 1.6 v gs =10v 6 2 am15636v1
docid024079 rev 3 7/17 STL8N80K5 electrical characteristics figure 8. capacitance variations figure 9. output capacitance stored energy figure 10. normalized gate threshold voltage vs. temperature figure 11. normalized on-resistance vs. temperature figure 12. drain-source diode forward characteristics figure 13. normalized v ds vs. temperature c 1000 100 10 1 0.1 10 v ds (v) (pf) 1 100 ciss coss crss am15637v1 e oss 6 4 2 0 0 v ds (v) (j) 400 200 600 am15638v1 v gs(th) 1 0.8 0.6 0.4 -50 0 t j (c) (norm) 50 100 i d =100a v ds =v gs am15639v1 r ds(on) 2 1.2 0.4 -50 0 t j (c) (norm) 50 100 0.8 1.6 v gs =10v i d =3 a 2.4 am15640v1 v sd 1 3 i sd (a) (v) 2 4 5 0.5 0.6 0.7 0.8 0.9 t j =-50c t j =150c t j =25c am15641v1 v ds -50 0 t j (c) (norm) 50 100 0.9 0.94 0.98 1.02 1.06 1.1 i d = 1ma am15642v1
electrical characteristics STL8N80K5 8/17 docid024079 rev 3 figure 14. maximum avalanche energy vs. starting t j e as 0 40 t j (c) (mj) 80 0 20 40 120 60 80 100 v dd =50v i d =2a am15643v1
docid024079 rev 3 9/17 STL8N80K5 test circuits 3 test circuits figure 15. switching times test circuit for resistive load figure 16. gate charge test circuit figure 17. test circuit for inductive load switching and diode recovery times figure 18. unclamped inductive load test circuit figure 19. unclamped inductive waveform figure 20. switching time waveform am01468v1 v gs p w v d r g r l d.u.t. 2200 f 3.3 f v dd am01469v1 v dd 47k 1k 47k 2.7k 1k 12v v i =20v=v gmax 2200 f p w i g =const 100 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 a a b b r g g fast diode d s l=100 h f 3.3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3.3 f v dd am01472v1 v (br)dss v dd v dd v d i dm i d am01473v1 v ds t on td on td off t off t f t r 90% 10% 10% 0 0 90% 90% 10% v gs
package mechanical data STL8N80K5 10/17 docid024079 rev 3 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
docid024079 rev 3 11/17 STL8N80K5 package mechanical data table 9. powerflat? 5x6 vhv mechanical data dim mm. min. typ. max. a 0.80 1.00 a1 0.02 0.05 a2 0.25 b 0.30 0.50 d 5.00 5.20 5.40 e 5.95 6.15 6.35 d2 4.30 4.40 4.50 e2 2.40 2.50 2.60 e 1.27 l 0.50 0.55 0.60 k 2.60 2.70 2.80 aaa 0.15 bbb 0.15 ccc 0.10 eee 0.10
package mechanical data STL8N80K5 12/17 docid024079 rev 3 figure 21. powerflat? 5x6 vhv bottom view side view to p v i e w 8368144_rev_b
docid024079 rev 3 13/17 STL8N80K5 package mechanical data figure 22. powerflat? 5x6 vhv (dimensions are in mm) 8368144_rev_b_footprint
packaging mechanical data STL8N80K5 14/17 docid024079 rev 3 5 packaging mechanical data figure 23. powerflat? 5x6 tape figure 24. powerflat? 5x6 package orientation in carrier tape. measured from centerline of sprocket hole to centerline of pocket. cumulative tolerance of 10 sprocket holes is 0.20 . measured from centerline of sprocket hole to centerline of pocket. (i) (ii) (iii) all dimensions are in millimeters 2 2.00.1 (i) bo (5.300.1) ko (1.200.1) 0.05) ?1.5 min. ?1.550.05 p ao(6.300.1) f(5.500.1)(iii) w(12.000.3) 1.750.1 4.00.1 (ii) p 0 y y section y-y c l p1(8.000.1) do d1 e 1 (0.30 t ref.r0.50 ref 0.20 base and bulk quantity 3000 pcs 8234350_tape_rev_c pin 1 identification
docid024079 rev 3 15/17 STL8N80K5 packaging mechanical data figure 25. powerflat? 5x6 reel 2.20 ?21.2 13.00 core detail 2.50 1.90 r0.60 77 128 ?a r1.10 2.50 4.00 r25.00 part no. w1 w2 18.4 (max) w3 06 ps esd logo at t e n t i o n observe precautions for handling electrostatic sensitive devices 11.9/15.4 12.4 (+2/-0) a 330 (+0/-4.0) all dimensions are in millimeters ?n 178(2.0) 8234350_reel_rev_c
revision history STL8N80K5 16/17 docid024079 rev 3 6 revision history table 10. document revision history date revision changes 18-dec-2012 1 first release. 22-apr-2013 2 ? deleted: v ds , drain current (continuous) at t amb = 25 c and t amb = 100 c, total dissipation at t amb = 25 c in table 2 ? modified: p tot , i ar and e as values in table 2 ? added: mosfet dv/dt ruggedness parameter and note 6 in table 2 ? modified: values in table 3 , r ds(on) typ in table 4 , the entire typical values in table 5 , 6 and 7 ? inserted: section 2.1: electrical characteristics (curves) 19-nov-2013 3 ? modified: figure 3 , 15 , 16 , 17 and 18 ? minor text changes
docid024079 rev 3 17/17 STL8N80K5 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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