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ADC1295X 0.18 m m m 8-bit 800k adc 1 general description the ADC1295X is a cmos 8bit a/d converter which combines an auto offset calibration comparator, high resolution r-string dac, clock generator, 8bit successive approximation register (sar), output register, and ainc which controls analog input selection. the ADC1295X provides software-selection power-down mode. the device operates with a single +3.3v supply and a/d conversion rate is 800ksps, external clock xp1 is 40mhz. the operating temperature range is -40?85 c for commercial specification. features ? resolution : 8-bit ? maximum conversion rate : 800ksps ? power supply : 3.3v single (typ) ? differential linearity error : 1.0 lsb ? integral linearity error : 2.0 lsb ? folding, interpolation and pipelined scheme ? low power consumption : at operating, 3.3mw(typ) : at standby, 330nw(typ) ? guaranteed monotonicity ? no missing code ? latched tri-state output ? operating temperature range : -40 c ? 85 c typical applications ? micom ? battery charger ? game pack ? digital still camera ? hand held computer & organizer. ? other low power equipments.
0.18 m m m 8-bit 800k adc adc 1295x 2 functional block diagram cops ckgens sar8s outregs ain refp refn xp1 stby dget aden flag do[7:0] avdd33a avss33a avbb33a vrgs aiscs avdd33d avss33d avbb33d ver 1.2 (apr. 2002) no responsibility is assumed by sec for its use nor for any infringements of patents or other rights of third parties that may result from its use. the content of this data sheet is subject to change without any notice.
ADC1295X 0.18 m m m 8-bit 800k adc 3 core pin description name i/o type i/o pad pin description refp ai phia_abb internal reference top bias. 3.3v refn ai phia_abb internal reference bottom bias. 0v avdd33a ap vdd3t_abb analog power(3.3v) avss33a ag vss3t_abb analog ground avbb33a ag vbb3_abb analog substrate ain ai phiar50_abb analog input xp1 di phicc_abb main clock(external) stby di phicc_abb system power down(active high) aden di phicc_abb a/d conversion enable do[7:0] do phoa_abb digital outputs dget di phicc_abb douts read enable flag do phoa_abb test pin for checking the adc state avbb33d dg vbb3_abb digital substrate avss33d dg vss3t_abb digital ground avdd33d dp vdd3t_abb digital power(3.3v) i/o type abbr. ? ai: analog input ? di: digital input ? ao: analog output ? do: digital output ? ab: analog bi-direction ? db: digital bi-direction ? ap: analog power ? ag: analog ground ? dp: digital power ? dg: dig ital ground
0.18 m m m 8-bit 800k adc adc 1295x 4 core configuration ADC1295X ain refp refn xp1 stby dget aden flag do[7:0] avdd33a avss33a avbb33a avdd33d avss33d avbb33d
ADC1295X 0.18 m m m 8-bit 800k adc 5 absolute maximum ratings characteristic symbol value unit supply voltage v dd 4.5 v analog input voltage ain v ss to v dd v digital input voltage din v ss to v dd v digital output voltage v oh, vol v ss to v dd v reference voltage refp/refn v ss to v dd v storage temperature range tstg -55 to 125 c operating temperature range topr -40 to 85 c notes: 1. absolute maximum rating specifies the values beyond which the device may be damaged permanently. exposure to absolute maximum rating conditions for extended periods may affect reliability. each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. all voltages are measured with respect to vss unless otherwise specified. 3. 100pf capacitor is discharged through a 1.5k w resistor (human body model) recommended operating conditions characteristics symbol min typ max unit supply voltage avdd33a avdd33d 3.3-5% 3.3 3.3+5% v supply voltage difference avdd33a avss33d -0.1 0.0 0.1 v reference input voltage refp refn ? ? avdd33a 0 ? ? v analog input voltage ain refn ? refp v clock high time clock low time tpwh tpwl ? ? 19 19 ? ? ns digital input 'l' voltage digital input 'h' voltage v il v ih 0 0.9*avdd33d ? ? 0.1*avdd33d avdd33d v operating temperature topr -40 ? 85 c note: it is strongly recommended that all the supply pins (avdd33a, avdd33d) be powered from the same source to avoid power latch-up.
0.18 m m m 8-bit 800k adc adc 1295x 6 dc electrical characteristics characteristics symbol min typ max unit test conditions resolution ? ? 8 ? bits differential linearity error dle ? 0.5 1.0 lsb xp1 : 40mhz integral linearity error ile ? 0.5 2.0 lsb offset voltage error(top) eot ? 2.0 4.0 lsb eot = refp-ain(255,256) offset voltage error(bottom) eob ? 2.0 4.0 lsb eob = ain(0,1)-refn notes: 1. converter specifications (unless otherwise specified) avdd33a=3.3v avdd33d=3.3v avss33a=gnd avss33d=gnd avbb33 a=gnd avbb33d=gnd refp=3.3v refn=0.0v ta=25 c 2. tbd : to be determined ac electrical characteristics characteristics symbol min typ max unit test conditions clock high time tpwh ? 19 ? ns xp1 : 25mhz (typ) clock low time tpwl ? 19 ? ns 40mhz (max) conversion rate f ad ? 500 800 ksps conversion time t ad 1.25 2 ? us dynamic supply current is ? 1 1.5 ma power load cap:10uf//0.1uf output load cap.=1pf isd ? 0.1 0.5 ua at power down. power dissipation pd ? 3.3 5.4 mw during a/d operation pdd ? 0.33 1.8 uw at power down. digital output data delay t d ? 20 25 ns output load cap.=1pf
ADC1295X 0.18 m m m 8-bit 800k adc 7 timing diagram xp1 stby 50 clock aden ain 34 clock 16 clock flag dget do[7:0]
0.18 m m m 8-bit 800k adc adc 1295x 8 functional description 1. xp1 the xp1 is the system main clock. if 25mhz clock is applied, 10bit 500ksps or 8bit 650ksps outputs are produced. in case of 10mhz clock, 10bit 200ksps or 8bit 250ksps outputs are made. 2. stby this pin is used for keeping standby without a/d conversion operation. for a/d operation, its state must be changed from '1' to '0' after at least one xp1 period. in the timing chart, 3.5-xp1 period is drawn and this state transition can occur even at rising or falling edges. if not needed, it can be tied to gnd. 3. aden this is a a/d conversion enable signal. it is for one xp1 period at falling edge. in a 10bit, at least 45-xp1 periods are required until the next aden, and 37-xp1 periods are delayed until the next aden for an 8bit. 4. do[7:0] digital output pins. 5. dget data read signal. if dget is applied during a/d conversion, selected ain pin information is produced(refer to timing chart). it is to check if the right analog input is selected. after a/d operation, the state of the test pin, flag, changes to '1', and a/d converted data are produced by applying dget signal. 6. ain analog input 7. flag test pin. its state goes low during a/d conversion, and goes high after the a/d conversion. if stby signal is applied even at a/d conversion mode, its state goes high immediately.
ADC1295X 0.18 m m m 8-bit 800k adc 9 core evaluation guide 1. you can test adc function by th e dget. if you don't use the dget pin, this adc function is evaluated by external check on the bi-directional pads connected to input nodes of host dsp back-end circuit. 2. the reference voltages may be biased externally through refp and refn pins digital mux ADC1295X ain do[7:0] xpi stby dget aden power used : avdd33a,avss33a,avbb33a avdd33d,avss33d,avbb33d 3.3v gnd refp refn do[7:0] host dsp core do[7:0] bidirectional pad (adc function test & externally forced digital input) : 10 m f electronic capacitor unless otherwise specified : 0.1 m f ceramic capacitor unless otherwise specified flag
0.18 m m m 8-bit 800k adc adc 1295x 10 package configuation 1 nc refp nc refn nc avdd33a nc avbb33a nc avss33a nc nc ain nc nc nc stby avdd33d avss33d xp1 nc avbb33d nc rp nc avdd33r nc avss33r avbb3r nc nc nc nc do[7] do[6] do[5] do[4] do[3] do[2] do[1] do[0] nc dget aden nc 10u 0.1u rn flag nc 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 10u 0.1u 0.1u 10u ADC1295X digital output 0v 10u 0.1u 50 50 3.3v 3.3v 3.3v 3.3v 0.1u 10u 0.1u
ADC1295X 0.18 m m m 8-bit 800k adc 11 package pin description pin name pin no. i/o type i/o pad pin description refp 2 ai phia_abb internal reference top bias. 3.3v refn 4 ai phia_abb internal reference bottom bias. 0v avdd33a 6 ap vdd3t_abb analog power(3.3v) avbb33a 8 ag vbb3_abb analog substrate avss33a 10 ag vss3t_abb analog ground ain 13 ai phiar10_abb analog inputs. input span : refp ? refn stby 17 di phicc_abb system power down(active high) avdd33d 18 dp vdd3t_abb digital power(3.3v) avss33d 19 dg vss3t_abb digital ground xp1 20 di phicc_abb main clock(external) avbb33d 22 dg vbb3_abb digital substrate aden 26 di phicc_abb a/d conversion enable dget 27 di phicc_abb read enable do[7:0] 29~36 do phot12_abb digital outputs flag 38 do phot12_abb testpin. adc operation checking. avbb33r 44 dg vbb3_abb driver substrate avss33r 45 dg vss3t_abb driver ground avdd33r 47 dp vdd3t_abb driver power(3.3v)
0.18 m m m 8-bit 800k adc adc 1295x 12 user guide 1. speed up ? the initial target speed(conversion rate) of ADC1295X was 8bit 500ksps~ 800ksps, but it proved to operate well even at 8bit 900ksps because of a lot of design margin. it would be realized by speed-up of xp1. 2. input range variation ? the analog input of this adc is single input and the range is from refn to refp. this ain voltage follows reference voltage range fundamentally. therefore, in order to alter into another input voltage range, change the voltage value of refp. ? you can use the ain voltage whose minimum range is 2.7v. in this case, the refp is 2.7v and refn is 0.0v. if the range is 3.0v, the refp is 3.0v and refn is 0.0v. it is an user selection item. in case of maximum voltage range, the refp is the power level(3.3v) and the refn is the ground level. 3. note that this adc has not the sample and hold circuit, therefore during the a/d conversion the analog input voltage variation should not deviate more than 1 lsb voltage range.
ADC1295X 0.18 m m m 8-bit 800k adc 13 phantom cell information ? pins of the core can be assigned externally (package pins) or internally (internal ports) depending on design methods. the term "external" implies that the pins should be assigned externally like power pins. the term "external/internal" implies that the applications of these pins depend on the user. ADC1295X 8-bit 800ksps adc flag do[3] do[4] do[5] refn refp stby ain aden xp1 dget avdd33d avss33d avbb33d avss33a avdd33a avbb33a do[0] do[1] do[2] do[6] do[7]
0.18 m m m 8-bit 800k adc adc 1295x 14 pin name pin usage pin layout guide avdd33a external - maintain the large width of lines as far as the pads. avss33a external - place the port positions to minimize the length of power lines. avbb33a external - do not merge the analog powers with anoter power from other avdd33d external blocks. avss33d external - use good power and ground source on board. avbb33d external ain external/internal - do not overlap with digtal lines. - maintain the shotest path to pads. xp1 external/internal - separate from all other analog signals refp external/internal - maintain the larger width and the shorter length as far as the pads. refb external/internal - separate from all other digital lines. stby external/internal aden external/internal dget external/internal flag external/internal do[7] external/internal do[6] external/internal do[5] external/internal do[4] external/internal do[3] external/internal do[2] external/internal do[1] external/internal do[0] external/internal
ADC1295X 0.18 m m m 8-bit 800k adc 15 feedback request it should be quite helpful to our adc core development if you specify your system requirements on adc in the following characteristic checking table and fill out the additional questions. we appreciate your interest in our products. thank you very much. characteristic min typ max unit remarks analog power supply voltage v digital power supply voltage v bit resolution bit reference input voltage v analog input voltage v pp number of analog input channel operating temperature c integral non-linearity error lsb differential non-linearity error lsb bottom offset voltage error mv top offset voltage error mv conversion rate ksps conversion time(aden~aden) us dynamic supply current ma power dissipation mw power dissipation at power down uw digital output format (provide detailed description & timing diagram)
0.18 m m m 8-bit 800k adc adc 1295x 16 feedback request-2 1. i want to know the detail of the analog input waveform. which one is adeq uate for your analog input waveform among the a, b, and c below. if none of the three is adequate, please describe the analog input waveform to be used. if your analog input signal is sine-wave as c, please let me know what is your analog input signal's frequency and how many number of sampling points are required for 1-period? ain[n] ain[0] a. (fixed dc input) b. (ramp dc input) c. (sine-wave input) n-channel analog mux 2. between single input-output and differential input-output configurations, which one is suitable for your system and why? 3. please comment on the internal/external pin configurations and draw the timing diagram you want our adc to have, if you have any reason to prefer some type of configuration. 4. freely list those functions you want to be implemented in our adc, if you have any.
ADC1295X 0.18 m m m 8-bit 800k adc 17 history card version date modified items comments ver 1.0 00.6.30 original version published (preliminary) ver 1.2 02.04.26 add the phantom information (final version)

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