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preliminary rev. 0.4 6/12 copyright ? 2012 by silicon laboratories si85xx this information applies to a product under development. its characteristics and specifications are subject to change without n otice. si85xx si85 xx u nidirectional ac c urrent s ensors features applications description the si85xx products are unidirectional ac current sensors available in full-scale ranges of 5, 10, and 20 a. si85xx produc ts are ideal upgrades for older current- sensing technologies offering size, performance, and cost advantages over current transformers, hall effect devices, dcr circuits, and other approaches. the si85xx are extremely low-loss, adding less than 1.3 m ? of series resistance and less than 2 nh series inductance in the sensing path at 25 c. current-sensing terminals are isolated from the other package pins, providing up to 5 kv rms isolation level per safety approval ratings. safety approval (20-pin soic only) functional block diagram ? single-chip ac current sensor ? low loss: <1.3 m ? primary series resistance and <2 nh inductance ? leading-edge noise suppression eliminates need for leading-edge blanking ? "ping-pong" output version allows one si85xx to replace two current transformers in full-bridge designs ? 5, 10, and 20 a full-scale versions ? 5% initial accuracy ? 50 khz to 1 mhz input frequency range ? fault output to safeguard operation ? large 2 v pp min output at full scale ? high-side or low-side current sensing ? compact 4x4x1 mm qfn package (1 kv rms isolation) ? 20-pin wide-body soic (5 kv rms isolation) ? ?40 to 125 c operating range ? ul/vde/csa approval ? power supplies ? motor controls ? lighting equipment ? industrial equipment ? ul 1577 recognized ?? 5000 v rms for 1 minute ? csa component notice 5a approval ?? iec 60950, 61010, 60601 approved ? vde certification conformity ?? iec 60747-5-2 (vde0884 part 2) typical application vdd vout iin iout l c q1 q2 ph1 ph2 r1 out vdd1 gnd2 vin si850x trst r2 si851x metal slug vdd trst/fault iout iin gnd integrator signal conditioning adc auto calibration logic temp sensor out1 out2 mode logic mode r1 r2 r3 r4 reset logic gnd1 patents pending ordering information: see page 26. pin assignments: see page 24 vdd mode r1 r3 r4 out1 r2 out2 trst/fault gnd iin iin iin iin iin iout iout iout iout iout si851x 20-pin soic 12-pin qfn si851x r1 r2 r3 r4 out1 out2 trst/fault gnd iout iin mode vdd
si85xx 2 preliminary rev. 0.4
si85xx preliminary rev. 0.4 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2.1. under voltage lockout (uvlo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3. integrator reset and cu rrent measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4. total measurement error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.5. effect of temperature on accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6. leading edge noise suppressi on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7. fault output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8. safe operating limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3. application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.1. board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2. layout requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3. device configurati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.4. single-phase buck conver ter example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5. full-bridge converter exam ple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6. push-pull converter example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4. pin descriptions?12-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 5. pin descriptions?20-pin soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. package outline?12-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 8. recommended pcb land pattern (12- pin qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9. package outline: wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 10. recommended pcb land pa ttern (20-pin soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11. top marking (qfn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 12. top marking (soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
si85xx 4 preliminary rev. 0.4 1. electrical specifications table 1. electrical specifications t a = ?40 to +125 oc (typical specified at 25 oc), vdd = 3 v (10%) to 5 v (10%), f = 400 khz, unless specified parameter conditions min typ max unit supply voltage (v dd ) 2.7 ? 5.5 v supply current fully enabled, input frequency = 1 mhz ? 4 7 ma undervoltage lockout (v uvlo ) 2.1 2.3 2.5 v undervoltage lockout hysteresis (v hyst ) ? 100 ? mv logic input high level mode, r1, r2, r3, r4 inputs (ttl compatible) 2.0 ? ? v logic input low level ? ? 0.8 v reset time (t r ) time for 5% initial accuracy 150 ? ? ns reset time resistor range 1 15 ? 2500 k ? r1, r2, r3, r4 in put rise time (t rr ) ? ? 30 ns r1, r2, r3, r4 in put fall time (t fr ) ? ? 30 ns measurement watchdog timeout (t wd ) 30 50 80 s series input resistance measured from iin to iout ? 1.3 ? m ? series inductance measured from iin to iout ? 2 ? nh input/output delay 1 out, out1, out2 delay relative to input ? 150 200 ns start-up self-cal delay (t cal ) 1 time from vdd = v uvlo + v hyst to cal complete ? 150 200 s input common mode voltage range (dc) 1 4x4 mm qfn 1000 ? ? v rms soic-20 5000 ? ? v rms operating input frequency range (f) 1 50 ? 1000 khz dc power supply rejection ratio ? 40 ? db sensitivity @ vdd = 3 v si8501/11/17 ? 404 ? mv/a si8502/12/18 ? 202 ? mv/a si8503/13/19 ? 101 ? mv/a sensitivity @ vdd = 5 v si8501/11/17 ? 392 ? mv/a si8502/12/18 ? 196 ? mv/a si8503/13/19 ? 98 ? mv/a notes: 1. guaranteed by design and/ or characterization. 2. maximum output load is not recommended to exceed 200 pf and 5 k ? . 3. production tested at 400 khz (50% duty cycle) at vdd = 3.3 v. 4. see "2.4. total measurement error" on page 11 for more information.
si85xx preliminary rev. 0.4 5 out, out1, out2 offset voltage (v outmin ) current flow from i in to i out =0 ? 50 ? mv v out slew rate 1,2 out, out1, out2 load = 5k || 50 pf ? 50 ? v/s out, out1, out2 output resistance 20 ? 130 ? total measurement error (%) (?40 to 125 oc temp range) 20% of full scale 3,4 (all devices) ?30 ? +30 % 100% of full scale 3,4 ?10 ? +10 % table 2. regulatory information 1 (soic-20 only) csa the si85xx is certified under csa component acceptan ce notice 5a. for more details, see file 232873. vde 2 the si85xx is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. ul the si85xx is certified under ul1577 component recognition program. for more details, see file e257455. notes: 1. all 5.0 kv rms rated devices are production tested to > 6.0 kv rms for 1 sec. for more information, see "6. ordering guide" on page 26. 2. pending. table 1. electrical specifications (continued) t a = ?40 to +125 oc (typical specified at 25 oc), vdd = 3 v (10%) to 5 v (10%), f = 400 khz, unless specified parameter conditions min typ max unit notes: 1. guaranteed by design and/ or characterization. 2. maximum output load is not recommended to exceed 200 pf and 5 k ? . 3. production tested at 400 khz (50% duty cycle) at vdd = 3.3 v. 4. see "2.4. total measurement error" on page 11 for more information.
si85xx 6 preliminary rev. 0.4 table 3. insulation and safety-related specifications parameter symbol test condition value unit soic-20 minimum air gap (clearance) l(1o1) 7.6 min mm minimum external tracking (creepage) l(1o2) 7.6 min mm minimum internal gap (internal clearance) 0.2 mm tracking resistance (comparative tracking index) cti din iec 60112/vde 0303 part 1 >175 v resistance (input-output) 1 r io 10 12 ? capacitance (input-output) 1 c io f=1mhz 1.4 pf input capacitance 2 c i 4.0 pf notes: 1. to determine resistance and capacitance, the si85xx is converted into a 2-terminal device. pins 1?10 are shorted together to form the first terminal and pins 11?20 are shorted together to form t he second terminal. the parameters are then measured between these two terminals. 2. measured from input pin to ground. table 4. iec 60664-1 (vde 0884 part 2) ratings parameter test conditions specification soic-20 basic isolation group material group iiia installation classification rated mains voltages < 150 v rms i-iv rated mains voltages < 300 v rms i-iv rated mains voltages < 400 v rms i-iv rated mains voltages < 600 v rms i-iv rated mains voltages < 1000 v rms i-iii
si85xx preliminary rev. 0.4 7 table 5. iec 60747-5-2 insulation characteristics* parameter symbol test condition characteristic unit soic-20 maximum working insulation voltage v iorm 1414 v peak input to output test voltage v pr method b1 (v iorm x 1.875 = v pr , 100% production test, t m =1 sec, partial discharge < 5 pc) 2652 v peak transient overvoltage v iotm t = 60 s 8000 v peak pollution degree (din vde 0110, table 1) 2 insulation resistance at t s , v io =500v r s >10 9 w note: the si85xx is suitable for basic and reinforced electrical isol ation only within the safety lim it data. maintenance of the safety data is ensured by protective circuits. the si85xx pr ovides a climate classification of 40/125/21. note that the si85xx is compliant with the iec60747-5-2 but neither ce rtified nor inspected to iec60747-5-2. the si85xx is compliant, certified, and factory-inspected to iec60950. table 6. iec safety limiting values 1 parameter symbol test condition soic-20 unit case temperature t s 150 c safety input current i s ? ja = 85, v dd =5.5v, iin to iout = 20 a, t j =150c, t a =25c 30 a device power dissipation 2 p d 0.9 w notes: 1. maximum value allowed in the event of a failure. refer to the thermal derating curve in figure 1. 2. the si85xx is tested with v dd = 5.5 v, t j =150oc, c l = 15 pf, and with an input current from iin to iout equal to 20 amps at 500 khz (duty cycle = 50%).
si85xx 8 preliminary rev. 0.4 figure 1. soic-20 thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 7. thermal characteristics parameter symbol test condition soic-20 4x4 mm qfn unit ic junction-to-air thermal resistance ? ja 85 55 c/w table 8. absolute maximum ratings 1 parameter symbol min typ max units storage temperature t stg ?65 ? +150 c ambient temperature under bias t a ?40 ? +125 c junction temperature t j ? ? 150 c supply voltage v dd ? ? 5.75 v voltage on any pin with respect to ground (not including iin, iout) v in ?0.5 ? vdd + 0.5 v output current drive l o ?? 10ma lead solder temperature (10 s) ? ? 260 oc maximum input current rate of change ? ? 1000 a/s maximum peak ac input current limit ? ? 200 a thermal limit (dc current) 2 ? ? 30 a maximum isolation voltage (qfn) ? ? 1400 v rms maximum isolation voltage (soic-20) ? ? 6000 v rms esd (cdm) jedec (jesd 22-c101c) ?1.5 +1.5 kv esd (hbm) jedec (jesd22-a114e) ?2500 +2500 v esd (mm) jedec (jesd22-a115a) ?250 + 250 v notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. refer to ?an329: extending the full-scale range of the si85xx? for more information. 02 0 0 150 100 50 40 20 0 case temperature (oc) safety-limiting current (a) 10 30 vdd = 5.5 v iin to iout = 20 amps
si85xx preliminary rev. 0.4 9 2. functional overview the si85xx ac current sensor family of products mimics the functionality of traditio nal current transformer (ct) circuits with burden resistor, diode, and output filter, but offers enhanced performanc e and added capabilities. these devices use inductive current sensing and on- board signal conditioning electronics to generate a 2 v full-scale output signal proportional to the ac current flowing from the iin to the iout terminals. as shown in figures 2 and 3, current flowing through the metal package slug induces a signal in the pickup coil on the si85xx die. this signal is applied to the input of an integrator that reconstructs the ac current flowing from iin to iout. onboard circuitry provides cycle-by-cycle integrator reset and temperature and offset voltage compensation to achieve initial measurement accuracy to within 5%. figure 2. si850x (single output) block diagram figure 3. si851x (ping pong output) block diagram the si85xx is superior to other current sensing approaches and benefits the system in a number of ways: ? small size: with its 4x4 mm footprint and 1 mm height (qfn package option), the si85xx is among the smallest current sensors available. ? large output signal: the nominal 2.0 v full-scale output swing offers superior noise immunity versus other current sensing technologies. ? low loss: the si85xx adds only 1.3 m ? (at 25 c) to the sensing path, making it one of the lowest-loss current sensors available. low 2 nh primary series inductance is 2,000 times lower compared to a ct and results in significantly less ringing. ? high precision: all versions are available with an initial maximum error of 5 % of reading; one of the most accurate current sensors available. ? ping-pong output mode (si851x): alternately routes the current measurements from each side of a full-bridge circuit to separate output pins for comparison, which is very useful for transformer flux balancing applications. eliminates a second ct in a full-bridge application. ? leading edge noise suppression: filters out reflected noise due to long reverse recovery time of output rectifier. eliminates the need for external leading edge blanking circuit. ? high common-mode voltage: the si85xx offers a minimum of 1,000 v rms (for qfn package) or 5kv rms (for soic package) of common-mode voltage range (or isolation), making it useful over a very wide voltage range. si850x metal slug vdd1 trst iout iin gnd1 integrator signal conditioning adc auto calibration logic temp sensor out vdd2 r1 r2 reset logic gnd2 nc gnd3 pickup coil si851x metal slug vdd trst/fault iout iin gnd integrator signal conditioning adc auto calibration logic temp sensor out1 out2 mode logic mode r1 r2 r3 r4 reset logic pickup coil
si85xx 10 preliminary rev. 0.4 ? fault output (si8517/8/9): goes low when external reset timing is in error. ? ease-of-use: other than conventional power and grounding techniques, no special board layout considerations are required. built-in timing interface circuits allow already-available system switching signals to be used for reset with no external circuits required. 2.1. under voltage lockout (uvlo) uvlo is provided to prevent erroneous operation during device start-up and shutdown or when vdd is significantly below the spec ified operating range. the si85xx is in uvlo state when vdd < v uvlo (figure 4). during uvlo, the output(s) are held at minimum value regardless of the amount of current flowing from iin to iout, and signals on integrator reset inputs r1?r4 are ignored. the si85xx exits uvlo when vdd > (v uvlo + v hyst ). 2.2. device startup upon exit from uvlo, the si85xx performs a voltage offset and temperature self-calibration cycle. during this time, output(s) are held at minimum value and reset inputs (r1-r4) are ignored. the reset inputs are enabled at the end of the self-calibration cycle, and an integrator reset cycle is init iated on the fi rst occurrence of active signals on r1?r4. a current measurement is initiated immediately after the completion of the integrator reset cycle, and the resulting current waveforms appear on the output pins. this "reset- measure-reset" pattern repeats throughout steady-state operation. 2.3. integrator reset and current measurement the si85xx measures current flowing from the iin to iout terminals. current is allowed to flow in the opposite direction, but will not be measured (out1 and out 2 remain at their minimum values during reverse current flow. reverse curr ent flow will not damage the si85xx). to achieve the specified accuracy, the integrator capacitor must be discharged (reset) for time period t r prior to the start of every measurement cycle. this cycle-by-cycle reset is implemented by connecting existing system gate control signals to the r1?r4 inputs in a way that resets the integrator when no current is flowing from iin to iout. to achieve rated accuracy, the reset cycle must be complete d prior to the start of the measurement cycle. for maxi mum flexibility, integrator reset operation can be configured in one of two ways: option 1: the start and duration of reset is determined by the states of the timing signals applied to r1?r4. option 2: the timing signals applied to r1?r4 trigger the start of reset, and the duration of the reset is determined by an onboard programmable reset timer. figure 4. si85xx startup and control timing under voltage lockout state measure current vdd supply integrator reset si85xx status si85xx output first positive edge following end of self-cal start-up self-cal cycle tcal reset reset don?t care tr vout min out1, out2 valid trp tr v uvlo + v hyst trp
si85xx preliminary rev. 0.4 11 integrator reset option 1 is selected by connecting t rst to vdd. in this mode, the si85xx is held in reset as long as the signals on r1?r4 satisfy the logic equations of table 11. it is typically used in applications where the gate drivers are external to the system controller ic (the gate driver delay ensures reset is completed prior to the start of measurement). reset option 2 is selected by connecting a timing resistor (r trst in figure 5) from the trst input to ground. it is typically used in applications where the gate drivers are on-board the controller. in this mode, the on-chip reset timer is triggered when the signals on r1?r4 satisfy the logic equations in table 11. once triggered, the timer maintains integrator in reset for time duration t r as programmed by the value of resistor r trst . the user must select the value of resistor r trst to terminate the reset cycle prior to the start of measurement under worst-case timing conditions. note that values of t r below the specified value in "1. electrical specifications" on page 4 results in increased integrator output offset erro r and increased output noise on v out . moreover, t r ?s time is summarized by the following equation (see table 9): t r = 10 ns/k ? where values of r trst that produce a reset time less than 150 ns (r trst < 15 k ? ) should not be used. figure 5. programming reset time (t r ) 2.4. total measurement error the si85xx?s absolute accuracy is affected by the following factors: ? ambient operating temperature ? vdd supply voltage ? time table 10 includes a composite of all environmental and operating conditions that can ultimately affect the absolute measurement accuracy of the si85xx. the total worst-case a ccuracy at full scale can be estimated by the sum of the initial accuracy (up to 5%) plus aging (up to 1.5%) and supply variations (up to 3.5%). for example, the total measurement error expected for a device operating at a given v dd supply of 5 v (10%) is 10% if the device is operated over a temperature range of ?40 to 125 c for up to 10 years. if the temperature range is limited to 0 to 85 c, the measurement error can be improved by up to 2%. see figure 6 for details. 2.5. effect of te mperature on accuracy offset voltage present at the si85xx output terminals (output offset voltage) is calibrated out each time vdd is applied to the si85xx; so, its error contribution is minimized when the temperature at which calibration occurred is at or near the steady-state operating temperature of the si85xx. for example, applying vdd at 25 c (offset cal is performed) and operating at 85 c will result in a larger offset error than oper ating at 50 c. the effect of this error is summarized in figure 6. the chart is referenced to 25 c . if the si85xx is powered up at 25 c and then operated at 125 c with no auto- calibration performed (i.e ., the power is not cycled at 125 c, which causes an auto-calibration), a 3% measurement error can be expected. table 9. typical reset time vs. r trst resistance r trst reset time (t r ) 15 k ? 150 ns 100 k ? 1s 1m ? 9s 2.2 m ? 20 s si85xx trst r trst table 10. total measurement error contributors error contributo r % error added initial error @ given v dd 10%, 25 c 5% temperature variation ?40 to 125 c 3.5% aging (10 years) 1.5%
si85xx 12 preliminary rev. 0.4 figure 6. differential temperature calibration error figure 7 shows the si85xx thermal characteristics of the on-chip sense resistance over the temperature range of ?40 to +125 c. series inductance is constant at 2 nh (max) across this same temperature range. figure 7. series resistance thermal characteristics 2.6. leading e dge noise suppression high-amplitude spikes on the leading edge of the primary switching waveforms can cause the pwm latch to be erroneously reset at th e start of the switching cycle when operating in current mode control. to prevent this problem, leading edge blanking is commonly used to disable the current comparator during the early portion of the primary-side switching cycle. the si85xx eliminates leading-edge noise spikes by including them in the signal integration. as shown in the output waveform of figure 8 (si8502 waveform measured directly on out pin with no ex ternal filter), noise present in the input waveform is e liminated without the use of blanking. figure 8. leading-edge noise suppression waveforms (200 khz, 9.3 a load) 2.7. fault output the fault output (si8517/8/9) guards against si85xx output signal errors caused by missing reset cycles. fault is asserted when a measurement cycle exceeds the internal watchdog timer times limit of t wd . fault can be used to alert a local microcontroller or digital power controller of a current se nse failure or to initiate a system shutdown. to detect faults, tie a 200 k ? resistor from trst/fault to vdd. 2.8. safe operating limits the si85xx is a very robust current sensor. its maximum input current rate of change is limited to 1000 a/s. the maximum peak ac input current limit is 200 a. the thermal limit or continuous dc current flow limit is 30 a. exceeding these limits may ca use long-term reliability issues. refer to ?an329: extending the full-scale range of the si85xx? for more information. -3.5% -3.0% -2.5% -2.0% -1.5% -1.0% -0.5% 0.0% 0.5% 1.0% 0 25 50 75 100 125 temperature (celcius) % typical erro r 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -20 0 20 40 60 80 100 120 temperature (c) typical series resistance (mohm) current sense transformer si8502
si85xx preliminary rev. 0.4 13 3. application information 3.1. board layout the si85xx is connected in the series path of the current to be measured. the si85xx must be located as far as possible from transformer and other magnetic field sources. like other analog components, the si85xx should be powered from a low-noise dc source and, preferably, to a low-noise analog ground plane. recommended bypass capacitors are 1 f in parallel with a 0.1 f, positioned as close to the si85xx as possible. when using the si850x (single output versions), all three ground pins must be connected to the same ground point, and both vdd1 and vdd2 pins must be tied to the vdd system power supply. 3.2. layout requirements the si85xx requires special layout techniques to ensure proper operation (see figures 9 and 10). due to the close proximity of the curr ent-carrying slug and current sensor silicon, magnetic co upling between the current- carrying slug and the silic on can form a ground loop causing the output voltage to be 0 v even though current is flowing through the slug. to eliminate any such coupling issues, a red fly-wire vdd trace (see figures 9 and 10) should be implemented in the layout. for the soic package, the red fly-wire trace should be approximately 3.5 mm from the center edge of the package intersecting approximately in the center of the package (see figure 9). for the qfn package, the red fly-wire should be approximately in the center of the package (see figure 10). standard wire thicknesses for 10 ma current-carrying ca pabilities should be used. moreover, note that the fly-wire trace should be completely under the grou nd plane since this will also reduce coupling. regarding isolation voltage requirements, the trace does not need to follow the lead frame and bonding traces exactly, as long as th e net magnetic flux is close to zero. the goal here is to keep the magnetic coupling small and, at the same time, keep the isolation distance large. moreover, to ensure that the layout meets the design?s required creepage and clearance requirements, the vdd trace should be placed on one of the inner layers or even the back side of the board. for example, one can lay out the return vdd trace on the other side of the pcb so the pcb itself can help to provide high isolation voltage. figure 9. soic layout requirements figure 10. qfn layout requirements vdd pin gnd pin soic package current carrying slug current sensor die top view vdd fly wire 5 v vdd trace mode pin (non-ping-pong) ground plane edge 3.5 mm bonding wire ground plane edge bypass capacitor 5v vdd trace vdd pin qfn package current carrying slug current sensor die top view vdd fly wire mode pin (non-ping-pong) ground plane edge 2 mm bonding wires ground plane edge gnd pin bypass capacitor
si85xx 14 preliminary rev. 0.4 3.3. device configuration configuring the si85xx involves the following steps: 1. selecting an output mode 2. configuring integrator reset timing 3. setting integrator reset time t r 3.3.1. device selection the si85xx family offers three output modes: single output (si850x), and 2 and 4-wire ping pong (si851x). the si851x products can be c onfigured to operate in all three of these output modes. the si850x products operate only in single output mode. most half-wave and single-phase applications require only single output mode and will typically use the si850x. in single output mode, output current always appears on the out pin (si850x) or the out1 pin (si851x). a single integrator reset signal is typically sufficient when operating in this mode. ping-pong mode routes the current waveform to two different output pins on alternate measurement cycles. it is useful in full-wave and push-pull topologies where external circuitry can be used to monitor and/or control transformer flux balance. (section "3. application information" on page 13 shows design examples using both output modes in various power topologies.) 2-wire ping-pong mode is useful mainly in non- overlapping two-phase buck converters but may also be used in full-bridge applications. in this output mode, reset inputs r1 and r2 are used, and input r3 is grounded. measured current appears on out1 when r1 is high and on out2 when r2 is high as shown in the full-bridge timing example of figures 11 and 12. figure 11. two-phase buck timing example a figure 12. full-bridge timing example b 4-wire ping-pong mode is recommended for full-bridge applications over 2-wire because it uses all four inputs, making the reset function tolerant to single-point signal failures. in 4-wire ping-pong mode, current appears on out2 when r1 is high and r2 is low, and appears on out1 when r3 is high and r4 is low as shown in the full-bridge timing example of figure 13. table 11 shows the states of the mode and r4 inputs that select each output, and the resulting reset logic functions and truth tables. figure 13. full-bridge timing example c r1 r2 reset si85xx state measure out1 out2 measure reset tr tr time r1 r2 reset si85xx state measure out1 out2 measure reset tr tr time r1 r3 r2 r4 measure out1 out2 measure reset tr reset tr
si85xx preliminary rev. 0.4 15 3.3.2. selecting reset timing signals reset timing signals should be chosen to meet the following conditions: ? satisfy reset time t r ? not overlap integrator reset into the desired measurement period ? not violate reset watchdog timeout period t wd 3.3.3. configuring integrator reset per section ?2. functional overview?, the integrator must be reset (zeroed) prior to the start of each measurement cycle to achieve specified measurement accuracy. this reset must be synchronized with the system switch timing signals to ensure that current is measured during the appropriate time; so, the si85xx integrator reset circuitry uses system timing as its reference. timing signals connect to reset inputs r1 through r4 where built-in lo gic functions allow the user to choose the conditions that cause an integrator reset event. important note: reset inputs r1?r4 are rated to a maximum input voltage of vdd. external resistor dividers must be used when connecting driver output signals to r1?r4 that swing beyond vdd. as shown in table 11, the si850x integrator reset logic is a simple xor gate where reset is maintained (or triggered, depending on use of the trst input) when states of reset inputs r1 and r2 are not equal. figure 14 shows the logic for the si851x products, where any one of three reset logic functions can cause integrator reset. the output mode (si851x) is determined by the states of the mode and r4 inputs, as shown in table 11.
si85xx 16 preliminary rev. 0.4 table 11. si85xx output and reset mode summary output mode mode r4 r3 r2 r1 reset state 1 reset logic expression single-ended 2 10 0 00 0 reset = xor[r1, (r2|r3)] 01 1 10 1 11 0 1 00 1 01 0 10 1 11 0 2-wire ping pong 1 1 0 00 1 reset = xnor[r1,(r2|r3)] 01 0 10 0 11 1 4-wire ping pong 0 0 0 00 0 reset = (r1&r2)|(r3&r4) 01 0 10 0 11 1 1 00 0 01 0 10 0 11 1 1 0 00 0 01 0 10 0 11 1 1 00 1 01 1 10 1 11 1 notes: 1. device is in reset when reset state = 1. 2. for si850x devices, reset = xor [r1, r2].
si85xx preliminary rev. 0.4 17 as explained in section ?2.3. integrator reset and cu rrent measurement?, the signals applied to r1?r4 can control integrator reset in real time (option 1), or they can trigger a reset event of programmable duration (option 2). referring to figure 14, re set timing is exclusively a function of the signals applied to r1?r4 when trst is tied to vdd. if not connected to vdd, the re set timer is enabled, and trst must be connected through a resistor to ground to set the reset duration (t r ). note that the reset timer is retriggerab le and generates a timed integrator discharge pulse whenever the reset logic output transitions from low to high. figure 14. si851x integrator reset logic r4 r2 r1 r3 integrator mode = 1 r4 = 0 mode = 1 r4 = 1 mode = 0 system controller logic level gate control signals (to rn inputs) logic level gate control signals (to rn inputs) external driver internal driver required if driver output voltage > vdd output 1 output 2 output 3 reset timer out clk trst pgm vref reset timing determined only by inputs r1?r4. reset triggered by inputs r1?r4. reset time (t r ) set by value of resistor r trst . trst = r1 to gnd trst = vdd 0 + 1
si85xx 18 preliminary rev. 0.4 3.3.4. setting reset time t r the programmable reset timer is triggered when the stat es of the signals applied to r1?r4 cause the associated logic expression in table 11 to go high (transition to the true state). because this timer is re-triggerable, r1?r4 must remain true for the duration of the desired t r as shown in figure 15. should r1?r4 transition false during t r , integrator reset will be immediat ely halted, resulting in lower measurement accuracy due to higher integrator offset error. figure 15. correct t r programming using resistor from trst input to ground current true false r1?r4 state reset measure si85xx status programmed value of t r si85xx output r1?r4 true for programmed t r (minimum) 0 ns (min)
si85xx preliminary rev. 0.4 19 3.3.5. measurement wa tchdog timer and fault output a built-in watchdog timer disables measurement and holds out or out1 and out2 at their minimum values when the time between integrator resets exceeds the fault detect time. the output signal from this watchdog is available on the fault output pin (si8517/8/9 only). figure 16 illustrates two means of enterin g a fault condition. either fault condition 1 or 2 occurs when the reset period exceeds the fault detect time, which ranges from 30 to 80 s due process variations. the fault condition ends when the next logic reset cycle begins. figure 16. measurement watchdog timer operation t cycle reset fault detect time 30-80 s fault condition 1 fault detect time 30-80 s fault condition 2 output reset logic reset logic output fault output fault output
si85xx 20 preliminary rev. 0.4 3.3.6. output over-range the si85xx can be over-ranged by more than 100% with no adverse effects. for instance, if the si8512 (a 10 a nominal full-scale device) has a 15 a peak current appli ed, then the outp ut voltage (out) will be 3 v (assuming vdd = 5 v). if a 10 a peak current is applied, then the ou tput returns to the nominal 2 v output. the head room of out is vdd?1.4 v. figure 17 illustrates the head room limitation of the si85xx versus supply. figure 17. headroom limitation 0 1 2 3 4 5 50% 100% 150% 200% 250% out (v) i (amps) percent nominal full-scale input vdd = 5 v vdd = 2.7 v 3.6 v
si85xx preliminary rev. 0.4 21 3.4. single-phase buck converter example in this example, the si850x is configured to operate in a single-phase synchronous buck converter (figure 18). this converter has a pwm frequency of 1 mhz and a maximum duty cycle of 80%. this is an example of a half-wave application that can be addressed with single-ended output mode. the pwm period is calculated to be 1/10 ?6 = 1.0 s, and the worst-case value, t r , is 0.2 x 1.0 x 10 ?6 = 200 ns at 80% maximum duty cycle (r trst =20k ? ). in this example, the current measurement is made when the buck switch is on; so, ph 2 is chosen as the reset signal by connecting ph2 to r1 and grounding r2. the ph2 signal can be obtained at the input of the driver external to the pwm controller or the output of the controller's internal driver (through a resistor divider if the driver output swings beyond the device vdd range). figure 18. si850x single-phase buck converter vdd vout 2 vpp iin iout l1 c3 q1 q2 ph1 ph2 r1 out vdd1 gnd1 vin si850x vdd2 r2 pwm reset ph2 si850x state i > 0 i = 0 current measure gnd2 trst r trst 100 ns gnd3 c1 0.1 f c2 1 f
si85xx 22 preliminary rev. 0.4 3.5. full-bridge converter example the full-bridge circuit of figure 19 uses an si851x config ured in 4-wire ping-pong output mode. the switching frequency of this phase-shifted full-bridge is 150 khz, and the maximum control phase overlap is 70%. figure 19. full-bridge converter given the 150 khz switching frequency (duty cycle fixed at 50%), the equivalent period is 1/150 x 10 3 = 6.6 s. at 70% maximum overlap, this equates to a worst-case t r value of 0.3 x 6.6 x 10 ?6 = 1.98 s. the default value for t r can, therefore, be used and is selected by connecting trst to vdd. as shown in the timing diagram of figure 19, integrator reset occurs when current circulates between q1 and q2 and between q3 and q4 (i.e. when current is not being sourced from vin). the external driver delay ensures reset is complete prior to the start of measurement. iin iout ti q1 q3 ph1 ph2 r1 out1 gnd vin si851x mode ph4 ph3 q2 q4 r2 vdd vdd out2 out1 out2 ph1 ph3 ph2 ph4 3?4 1?4 1?2 2?3 reset reset si85xx state measure trst out1 out2 measure r3 r4 switches turned on vdd c1 0.1 f c2 1 f
si85xx preliminary rev. 0.4 23 3.6. push-pull converter example the push-pull converter of figure 20 uses 2-wire ping po ng output mode. as shown in the timing diagram, the integrator reset occurs when the inputs of both the ph1 and ph2 drivers are low. as shown, trst is connected to vdd, selecting the default value of t r (250 ns). assuming an 80% maximum duty cycle, this value of t r would deliver specified accuracy over a pwm frequency ran ge of 50 to 400 khz. frequencies above 400 khz would require the selection of a lower t r value by connecting a resistor from trst to ground. figure 20. push-pull example using default t r value vdd iin iout q1 q2 ph2 r1 out1 vdd gnd vin si851x mode si85xx status t1 ph1 ph2 measure reset ph1 r2 r3 r4 out2 measure reset measure out1 out2 trst c1 0.1 f c2 1 f
si85xx 24 preliminary rev. 0.4 4. pin descriptions?12-pin qfn figure 21. example pin configurations table 12. si85xx family pin descriptions pin# si850x pin name description si851x pin name description 1 r1 integrator reset input 1 r1 integrator reset input 1 2 r2 integrator reset input 2 r2 integrator reset input 2 3 gnd2 ground r3 integrator reset input 3 4 gnd3 r4 integrator reset input 4 5 out output out1 output in single-ended output mode, or one of two outputs in ping-pong mode. 6 nc no connect out2 second of two ping-pong mode outputs 7 trst reset time control t rst reset time control 8 gnd1 ground gnd ground 9 iout current output terminal iout current ou tput terminal 10 iin current input terminal iin current input terminal 11 vdd1 power supply input vdd power supply input 12 vdd2 mode mode control input si850x r1 r2 gnd2 gnd3 out nc trst gnd1 vdd2 vdd1 iin iout si851x r1 r2 r3 r4 out1 out2 trst/fault gnd mode vdd iin iout
si85xx preliminary rev. 0.4 25 5. pin descriptions?20-pin soic figure 22. example pin configurations table 13. si85xx family pin descriptions pin# si850x pin name description si851x pin name description 1 vdd1 power supply input vdd power supply input 2 vdd2 mode mode control input 3 r1 integrator reset input 1 r1 integrator reset input 1 4 r2 integrator reset input 2 r2 integrator reset input 2 5 gnd2 ground r3 integrator reset input 3 6 gnd3 r4 integrator reset input 4 7 out output out1 output in single-ended output mode, or one of two outputs in ping-pong mode. 8 nc no connect out2 second of two ping-pong mode outputs 9 trst reset time control t rst reset time control 10 gnd1 ground gnd ground 11?15 iout current output termi nal iout current ou tput terminal 16?20 iin current input terminal iin current input terminal vdd mode r1 r3 r4 out1 r2 out2 trst/fault gnd iin iin iin iin iin iout iout iout iout iout si851x 20-pin soic vdd1 vdd2 r1 gnd2 out r2 nc trst gnd1 iin iin iin iin iin iout iout iout iout iout si850x 20-pin soic gnd3
si85xx 26 preliminary rev. 0.4 6. ordering guide new opns full scale current (a) initial accuracy % 1 temp range pin 7 function isolation rating output mode package 2 old obsolete opns 3 (previously specified with 5% accuracy and ?40c to +85 c) old obsolete opns 3 (previously specified with 20% accuracy) si8501-c-im 5 5% ?40 to 125 c integrator reset pro- gramming time input 1kv rms single qfn-12 si8501-c-gm si8504-c-im si8502-c-im 10 si8502-c-gm si8505-c-im si8503-c-im 20 si8503-c-gm si8506-c-im si8501-c-is 5 5kv rms soic-20 new package offering si8502-c-is 10 si8503-c-is 20 si8511-c-im 5 1kv rms ping- pong qfn-12 si8511-c-gm si8514-c-im si8512-c-im 10 si8512-c-gm si8515-c-im si8513-c-im 20 si8513-c-gm SI8516-C-IM si8511-c-is 5 5kv rms soic-20 new package offering si8512-c-is 10 si8513-c-is 20 si8517-c-im 5 fault output 1kv rms qfn-12 si8517-c-gm ? si8518-c-im 10 si8518-c-gm si8519-c-im 20 si8519-c-gm si8517-c-is 5 5kv rms soic-20 new package offering si8518-c-is 10 si8519-c-is 20 notes: 1. see "2.4. total measurement error" on page 11 for more information. 2. all packages are rohs-compliant. moisture sensitivity level is msl3 with peak reflow temperature of 260 c according to the jede c industry classification, and peak solder temperature. 3. since the initial accuracy for all devices is now specifie d as 5%, si8504/5/6 and si8514/15/16 opns have been replaced with si8501/2/3 and si8511/12/13 opns, respectively.
si85xx preliminary rev. 0.4 27 7. package outline?12-pin qfn figure 23 illustrates the packa ge details for the si85xx. table 14 lists the values for the dimens ions shown in the illustration. figure 23. 12-pin qfn package diagram table 14. qfn-12 package diagram dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.03 0.05 b1 0.20 0.25 0.30 b2 0.95 1.00 1.05 d 4.00 bsc. e 0.50 bsc. e 4.00 bsc. f 0.75 bsc. g 2.45 bsc. h 1.30 bsc. l1 0.35 0.40 0.45 l2 0.85 0.90 0.95 aaa 0.05 bbb 0.05 ccc 0.08 ddd 0.10 eee 0.10 notes: 1. all dimensions shown are in millimeters (mm). 2. dimensioning and tolerancing per ansi y14.5m-1994.
si85xx 28 preliminary rev. 0.4 8. recommended pcb la nd pattern (12-pin qfn) figure 24 illustrates the pcb land patt ern details for the 12-pin qfn package. table 15 lists the values for the dimensions shown in the illustration. figure 24. 12-pin qfn pcb land pattern table 15. 12-pin qfn pcb land pattern dimensions dimension mm c1 1.95 c2 1.30 d1 3.90 d2 2.45 e0 . 5 0 x1 0.80 x2 1.00 y1 0.30 y2 1.10 notes: 1. this land pattern design is based on ipc-7351 design guidelines for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
si85xx preliminary rev. 0.4 29 9. package outline: wide body soic figure 25 illustrates the package details for the wide -body soic package. table 16 lists the values for the dimensions shown in the illustration. figure 25. 20-pin wide body soic
si85xx 30 preliminary rev. 0.4 table 16. 20-pin wide body soic package diagram dimensions dimension min max a ? 2.65 a1 0.10 0.30 a2 2.05 ? b0 . 3 10 . 5 1 c0 . 2 00 . 3 3 d 12.80 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l0 . 4 01 . 2 7 h0 . 2 50 . 7 5 0 8 aaa ? 0.10 bbb ? 0.33 ccc ? 0.10 ddd ? 0.25 eee ? 0.10 fff ? 0.20 notes: 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation ac. 4. recommended reflow profile per jedec j-st d-020c specification for small body, lead-free components.
si85xx preliminary rev. 0.4 31 10. recommended pcb land pattern (20-pin soic) figure 26 illustrates the pcb land patter n details for the 20-pin soic packag e. table 17 lists the values for the dimensions shown in the illustration. figure 26. 20-pin soic pcb land pattern table 17. 20-pin soic pcb land pattern dimensions dimension mm c1 9.40 e1 . 2 7 x1 0.60 y1 1.90 notes: 1. this land pattern design is based on ipc-7351 design guidelines for density level b (median land protrusion). 2. all feature sizes shown are at maxi mum material cond ition (mmc) and a card fabrication toleranc e of 0.05 mm is assumed.
si85xx 32 preliminary rev. 0.4 11. top marking (qfn) figure 27. qfn top marking table 18. top marking explanation line 1 marking: device part number si85xx: where xx = 01, 02, 03, 11, 12, 13, 17, 18, 19 line 2 marking: rttttt = mfg code manufacturing code from assembly house ?r? indicates revision line 3 marking: circle bottom-left justified pin 1 identifier yy = year ww = work week corresponds to the year and work week of the assembly build date. si85xx rttttt yyww
si85xx preliminary rev. 0.4 33 12. top marking (soic) figure 28. soic top marking table 19. top marking explanation line 1 marking: device part number si85xx-is where xx = 01, 02, 03, 11, 12, 13, 17, 18, 19 line 2 marking: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. rttttt = mfg code manufacturing code from assembly house ?r? indicates revision line 3 marking: circle = 1.5 mm diameter (center justified) ?e3? pb-free symbol country of origin iso code abbreviation tw = taiwan si85xx-is yywwrttttt tw e3
si85xx 34 preliminary rev. 0.4 d ocument c hange l ist revision 0.1 to revision 0.2 ? updated table 1, ?electrica l specifications,? on page 4. ? added 20-pin wide-body soic package option. ? updated "6. ordering guide" on page 26. ?? all devices are now specified to 5% initial accuracy. ?? all devices are now specified for operation over ?40 to +125 c temperature range. all ordering part numbers have been updated to reflect this (i.e. previous ?-gm? and ?-gs? part number suffixes have been replaced with ?-im? and ?-is? suffixes). ? added sections ?8. recommended pcb land pattern (12-pin qfn)? and ?10. recommended pcb land pattern (20-pin soic)?. revision 0.2 to revision 0.21 ? added reference to iec61010, iec60601 on page 1. ? updated "6. ordering guide" on page 26. ? added top marking sections. revision 0.21 to revision 0.3 ? updated table 2 on page 5. ?? production test voltage is > 6.0 kv rms . ? added ?2.5. effect of switching frequency on accuracy? on page 11. ? added figure 6, ?full-scal e output accuracy vs. frequency,? on page 11. ? updated "3.2. layout requirements" on page 13. ?? added layout recommendations for qfn. ? added figure 10, ?qfn layout requirements,? on page 13. revision 0.3 to revision 0.4 ? updated table 8 on page 8. ?? added junction temperature spec. ? removed figure 6, ?full-scale output accuracy vs. frequency,? on page 11. ? updated figures 9 and 10 on page 13. ? updated table 11 on page 16. ?? updated notes. ? updated top marks. ?? added revision description.
si85xx preliminary rev. 0.4 35 n otes :
si85xx 36 preliminary rev. 0.4 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclai ms responsibility for any consequences resu lting from the use of information included herein. additionally, silicon labor atories assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and sp ecifically discla ims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the si licon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.
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