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| 1. general description meets jedec specification 42.4 tse2002b 1, 3 jun 2009. the nxp semiconductors se97b measures temperature from ? 40 c to +125 c with jedec grade b 1 c maximum accura cy between +75 c and +95 c critical zone and also provide 256 bytes of eeprom memory commu nicating via the i 2 c-bus/smbus. it is typically mounted on a ddr3 dual in-line memory module (dimm) measuring the dram temperature in accordance with the new jedec (jc-42.4) mobile platform memory module temperature sensor component specification and also replacing the serial presence detect (spd) which is used to store memory module and vendor information. the se97b thermal sensor an d eeprom operates over the v dd range of 3.0 v to 3.6 v. the ts consists of a ? analog to digital converter (adc) that monitors and updates its own temperature readings 10 times per second, converts the reading to a digital data, and latches them into the data temperature register. user-programmable registers, the specification of upper/lower alarm and cr itical temperature trip points, event output control, and temperature sh utdown, provide flexibility fo r dimm temperature-sensing applications. when the temperature changes beyond the s pecified boundary limits, the se97b outputs an event signal using an open-drain output that can be pulled up between 0.9 v and 3.6 v. the user has the option of setting the event output signal polarity as either an active low or active high comparator outp ut for thermostat operation, or as a temperature event in terrupt output for microprocessor -based systems. the event output can also be configured as only a critical temperature output. the eeprom is designed specifically for dram dimms spd. the lower 128 bytes (address 00h to 7fh) can be permanent wr ite protected (pwp) or reversible write protected (rwp) by software. this allows dram vendor and product information to be stored and write protected. the upper 128 bytes (address 80h to ffh) are not write protected and can be used for general purpose data storage. the se97b has a single die for both the te mp sensor and eeprom for higher reliability and supports the industry-standard 2-wire i 2 c-bus/smbus serial interface. the smbus timeout function is supported to prevent s ystem lock-ups. manufacturer and device id registers provide the ability to confirm the identity of the device. three address pins allow up to eight devices to be controlled on a single bus. the se98b is available as the se97b thermal sensor only. se97b ddr memory module temp se nsor with integrated spd rev. 01 ? 27 january 2010 product data sheet
se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 2 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 2. features 2.1 general features ? jedec (jc-42.4) dimm temperature sensor plus 256-byte serial eeprom for serial presence detect (spd) ? sda open-drain output design for best operat ion in distributed mu lti-point applications ? shutdown current: 0.1 a (typ.) and 5.0 a (max.) ? power-on reset: 1.8 v (typ.) ? 2-wire interface: i 2 c-bus/smbus compatib le, 0 hz to 400 khz ? smbus alert response address and timeout 25 ms to 35 ms (programmable) ? esd protection exceeds 2500 v hbm per jesd22-a114, 250 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? available in hwson8 package 2.2 temperature sensor features ? 11-bit adc temperature-to-digital converter with 0.125 c resolution ? voltage range: 3.0 v to 3.6 v ? operating current: 250 a (typ.) and 400 a (max.) table 1. comparison of se97 versus se97b features feature se97 se97b jedec specification old jedec spec ification new jedec specification bit 8 ?1? thermal sensor shutdown no smbus timeout smbus timeout 25 ms to 35 ms bit 8 ?0? thermal sensor active smbus timeout 25 ms to 35 ms i 2 c-bus maximum frequency 400 khz i 2 c scl and sda v il /v ih voltage levels v il(max) =0.3 v dd ; v ih(min) =0.7 v dd capabilities bit 6 smbus timeout set to 0 set to 1 event pin operation frozen de-assert capabilities bit 7 event pin set to 0 set to 1 a0 pin is 10 v tolerant yes capabilities bit 5 vhv set to 0 set to 1 i 2 c spike suppression 50 ns i 2 c input hysteresis - 0.05 v dd se97 device id register 1010 0010 revision id register 0000 0001 0000 0011 temperature sensor accuracy grade b improved grade b power-on reset (por) 0.6 v 1.8 v temperature sensor volt age range 3.0 v to 3.6 v eeprom write voltage range 3.0 v to 3.6 v eeprom read voltage range 1.7 v to 3.6 v 3.0 v to 3.6 v 2mm 3mm 0.8 mm package assembly plant hong kong assembly plant bangkok (thicker die and leadframe) se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 3 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd ? programmable hysteresis threshold: off, 0 c, 1.5 c, 3 c, 6 c ? over/under/critica l temperature event output ? b-grade accuracy: ? 0.5 c/ 1 c (typ./max.) +75 c to +95 c ? 1.0 c/ 2 c (typ./max.) +40 c to +125 c ? 2.0 c/ 3 c (typ./max.) ? 40 c to +125 c 2.3 serial eeprom features ? read and write voltage range: 3.0 v to 3.6 v ? operating current: ? write 0.6 ma (typ.) for 3.5 ms (typ.) ? read 100 a (typ.) ? organized as 1 block of 256 bytes (256 8) ? 100,000 write/erase cycles an d 10 years of data retention ? permanent and reversible software write protect ? software write protection for the lower 128 bytes 3. applications ? ddr2 and ddr3 memory modules ? laptops, personal computers and servers ? enterprise networking ? hard disk drives and other pc peripherals 4. ordering information [1] industry standard 2 mm 3mm 0.8 mm package to jedec wce-3, pson8 in 8 mm 4 mm pitch tape 4 k quantity reels. table 2. ordering information type number topside mark package name description version SE97BTP [1] 97b hwson8 plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 3 0.8 mm sot1069-2 se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 4 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 5. block diagram fig 1. block diagram of se97b 002aae309 scl sda event 2-kbit eeprom no write protect software write protect se97b v ss smbus/i 2 c-bus interface v dd ffh 7fh 00h temperature register critical alarm trip upper alarm trip lower alarm trip capability manufacturing id device/rev id smbus timeout/alert configuration ? hysteresis ? shutdown temp sensor ? lock protection ? event output on/off ? event output polarity ? event output status ? clear event output status pointer register band gap temperature sensor 11-bit ? adc por 10 v overvoltage filter a0 a1 a2 r 30 k to 800 k r 30 k to 800 k r 30 k to 800 k 80h se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 5 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration for hwson8 terminal 1 index area 1 a0 SE97BTP 002aae311 transparent top view 2 a1 3 a2 4 8 7 6 5 v ss v dd event scl sda table 3. pin description symbol pin type description a0 1 i i 2 c-bus/smbus slave address bit 0 with internal pull-down. this input is overvoltage tolerant to support software write protection. a1 2 i i 2 c-bus/smbus slave address bit 1 with internal pull-down a2 3 i i 2 c-bus/smbus slave address bit 2 with internal pull-down v ss 4 ground device ground sda 5 i/o smbus/i 2 c-bus serial data input/output (open-drain). must have external pull-up resistor. scl 6 i smbus/i 2 c-bus serial clock input/out put (open-drain). must have external pull-up resistor. event 7 o thermal alarm output for high/low and critical temperature limit (open-drain). must have external pull-up resistor. v dd 8 power device power supply (3.0 v to 3.6 v) se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 6 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7. functional description 7.1 serial bus interface the se97b communicates with a host controller by means of the 2-wire serial bus (i 2 c-bus/smbus) that consists of a serial cloc k (scl) and serial data (sda) signals. the device supports smbus, i 2 c-bus standard-mode and fast-mode. the i 2 c-bus standard speed is defined to have bus speeds from 0 hz to 100 khz, i 2 c-bus fast speed from 0 hz to 400 khz, and the smbus is from 10 khz to 100 khz. the host or bus master generates the scl signal, and the se97b uses the scl signal to receive or send data on the sda line. data transfer is serial, bidi rectional, and is one byte at a time with the most significant bit (msb) transferred first. since scl and sda are open-drain, pull-up resistors must be installed on these pins. 7.2 slave address the se97b uses a 4-bit fixed and 3-bit progra mmable (a0, a1 and a2) 7-bit slave address that allows a total of eight devices to coexist on the same bus. the a0, a1 and a2 pins are pulled low internally. the a0 pin is also overvoltage tolerant supporting 10 v software write protect. when it is driven higher than 7.0 v, writing a special command would put the eeprom in reversible wr ite protect mode (see section 7.10.2 ? memory protection ? ). each pin is sampled at the start of each i 2 c-bus/smbus access. the temperature sensor?s fixed address is ?0011b?. the e eprom?s fixed address for the normal eeprom read/write is ?1010b?, and fo r eeprom software protection co mmand is ?0110b?. refer to figure 3 . a. temperature sensor b. eeprom (nor mal read/write) c. eeprom (software protection command) fig 3. slave address r/w 002aab30 4 0 0 1 1 a2 a1 a0 fixed hardware selectable slave address msb lsb x r/w 002aab35 1 1 0 1 0 a2 a1 a0 fixed hardware selectable slave address msb lsb x r/w 002aab35 2 0 1 1 0 a2 a1 a0 fixed hardware selectable slave address msb lsb x se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 7 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.3 event output condition the event output indicates conditions such as the temperature crossing a predefined boundary. the event modes are very configurable and selected using the configuration register (config). the interrupt mode or co mparator mode is selected using config[0], using either tcrit/upper/lower or tcrit only temperature bands (config[2]) as modified by hysteresis (c onfig[10:9]) . the upper/lower (config[6]) and tcrit (config[7]) bands can be locked. figure 4 shows an example of the measured temperature versus time, with the co rresponding behavior of the event output in each of these modes. upon device power-up , the default condition for the event output is high-impedance to prevent spurious or unwanted alarms, but ca n be later enabled (config[3]). config[3] does not have to be cleared (e.g., set back to (0)) before changing config[2] or config[0]. event output polarity can be set to active high or active low (config[1]). event status can be read (config[ 4]) and cleared (config[5]). if the event output is enabled (config[3] = 1) an d the part is switched between interrupt mode and co mparator mode or vice versa, the event output may glitch during the change. if the device enters sh utdown mode (config[8] ) with asserted event output, the output either de-asserts (default) or remains asserted (frozen) depending on smbus[4]. 7.3.1 event pin output voltage levels and resistor sizing the event open-drain output is typically pulled up to a voltage level from 0.9 v to 3.6 v with an external pull-up resistor, but there is no real lower limit on the pull-up voltage for the event pin since it is simply an open-drain nmos pull-down output. it could be pulled up to 0.1 v and would not af fect the output. from the syst em perspective, there will be a practical limit. that limit will be the voltage necessary for the device m onitoring the interrupt pin to detect a high on its input. a possible practical lim it for a cmos input would be 0.4 v. another thing to consider is the value of the pull-up resistor. when a low supply voltage is applied to the drain (through the pull-up resistor) it is important to use a higher value pull-up resistor, to allow a larger maximum signal swing on the event pin. se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 8 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd [1] between t amb t th(crit) and t amb < t th(crit) ? t hys the event output is in comparator mode and bit 0 of config (event output mode) is ignored. refer to table 4 for figure note information. fig 4. event output condition 002aae763 time temperature ( c) critical event in interrupt mode event in comparator mode software interrupt clear lower boundary alarm upper boundary alarm event in ?critical temp only? mode (1) (2) (1) (3) (4) (3) (5) (7) (6) (4) (2) t amb t trip(l) ? t hys t trip(u) ? t hys t th(crit) ? t hys t trip(u) ? t hys t trip(l) ? t hys table 4. event output condition figure note event output boundary conditions event output temperature register status bits comparator mode interrupt mode critical temp only mode bit 15 above critical trip bit 14 above alarm window bit 13 below alarm window (1) t amb t trip(l) hlh000 (2) t amb < t trip(l) ? t hys llh001 (3) t amb > t trip(u) llh010 (4) t amb t trip(u) ? t hys hlh000 (5) t amb t th(crit) lll110 (6) t amb < t th(crit) ? t hys lhh010 (7) table note [1] se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 9 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.3.2 event thresholds 7.3.2.1 alarm window the device provides a compar ison window with an upper tr ip point and a lower trip point, programmed through the upper boundary alarm trip register (02h), and lower boundary alarm trip register (03h). the upper boundary alarm trip register holds the upper temperature trip point, while the lower boundary alarm trip register holds the lower temperature trip point as modified by hyst eresis as programmed in the configuration register. when en abled, the event output triggers whenever en tering or exiting (crossing above or below) the alarm window. ? advisory note: ? nxp device: the event output can be cleared thro ugh the clear event bit or smbus alert response address (ara). ? competitor device: the event output can be cleared only through the clear event bit. ? work-around: on ly clear event output using the event bit if both nxp and competitor devices are used. the upper boundary alarm trip should always be set above the lower boundary alarm trip. the alarm window limit is imme diately compared with the temperature register even if it has not been recently update d (e.g., device has been in standby) when the event is turned on (config[3]). consider waiting one conversion cycle (125 ms) after setting the alarm window limit before enab ling the event output/comparing the alarm windo w limit with the temperature register to ensure that there is correct data in the temperature register. if smbus[2] is set, then the alarm window limit will only be compared to the temperature register after it has been updated when event is turned on. 7.3.2.2 critical trip the t th(crit) temperature setting is programmed in the critical alarm trip register (04h) as modified by hysteresis as programmed in the configuration register. when the temperature re aches the critical temp erature value in this register (and event is enabled), the event output asserts and cannot be de-asserted until the temperature drops below the critical temperature threshold. the event cannot be cleared through the clear event bit or smbus alert. the critical alarm trip should always be set above the upper boundary alarm trip. the critical trip limit is immediately compared with the temperature register even if it has not been recently update d (e.g., device ha s been in standb y) when the event is turned on (config[3]). consider waiting one conversion cycle (125 ms) after setting the critical trip limit before enabling the event output/comparing the critical trip limit with the temperature register to ensure that there is correct data in the temperature register. if smbus[2] is set, then the alarm window limit will only be compared to the temperature register after it has been updated when event is turned on. se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 10 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.3.3 event operation modes 7.3.3.1 comparator mode in comparator mode, the event output behaves like a window-comparator output that asserts when the temperature is outside the window (e.g., above the value programmed in the upper boundary alarm trip register or below the value programmed in the lower boundary alarm trip register or above the critical alarm tr ip register if t th(crit) only is selected). re ads/writes on these register s do not affect the event output in comparator mode. the event signal remains asserted until the temperature goes inside the alarm window or the window thresholds are reprogrammed so that the current temperature is within the alarm window. the comparator mode is useful for thermost at-type applications, such as turning on a cooling fan or triggering a system shutdown when the temperature exceeds a safe operating range. 7.3.3.2 interrupt mode in interrupt mode, event asserts whenever the temperature crosses an alarm window threshold. after such an event occurs, writing a 1 to the clear event bit in the configuration register de-asserts the event output until the next trigger condition occurs. in interrupt mode, event asserts when the temperature crosses the alarm upper boundary. if the event output is cleared and the temper ature continues to increase until it crosses the critical te mperature threshold, event asserts again. because the temperature is greater than the critical temperature threshold, a clear event command does not clear the event output. once the temperature drops below the critical temperature, event de-asserts immediately. if the event output is not cleared before or when the temperature is in the critical temperature threshold, event will remain asserted after the temperature drops below the critical temperature unt il a clear event command. 7.3.3.3 switching between comparator mode and interrupt mode when the part is in comparator mode and th e temperature windows are set such that the baw bit is set and the event pin asserted (eventoutputcontrol = 1) and the part is switched to interr upt mode, the event is de-asserted. se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 11 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.4 conversion rate the conversion time is the amount of ti me required for the adc to complete a temperature measurement for the local temperature sensor. the conversion rate is the inverse of the conversion peri od which describes the number of cycles the temperature measurement completes in one second?the faster the conversion rate, the faster the temperature reading is updated. the se97b?s conversion rate is at least 8 hz or 125 ms. 7.4.1 what temperature is read when conversion is in progress the se97b has been designed to ensure a valid temperature is always available. when a read to the temperature register is initiated through the smbus, the device checks to see if the temperature conversion process (analog-to-digital conversion) is complete and a new temperature is available: ? if the temperature conversion process is complete, then the new temperature value is sent out on the smbus. ? if the temperature conversion process in not complete, then the previous temperature value is sent out on the smbus. it is possible that while smbus master is reading the temperature register, a new temperature conver sion completes. however, this will not affect the data (msb or lsb) that is being shifted out. on the next read of the temperature register, the new temperature value will be shifted out. 7.5 power-up default condition after power-on, the se97b is initialized to the fo llowing default condition: ? starts monitoring local sensor ? event register is cleared; event output is pulled high by external pull-ups ? event hysteresis is defaulted to 0 c ? command pointer is defaulted to ?00h? ? critical temp, alarm temperature upper and lower boundary trip register are defaulted to 0 c ? capability register is defaulted to ?00f 7h? for the b-grade and vhv capability, event de-asserted and smbus timeout between 25 ms and 35 ms enabled. ? operational mode: comparator ? smbus register is defaulted to ?21h? 7.6 device initialization se97b temperature sensors have programmable registers, which, upon power-up, default to zero. the open-drain event output is default to being disabled, comparator mode and active low. the alarm trigger registers defaul t to being unprotected. the configuration registers, upper and lower alarm boundary re gisters and critical temperature window are defaulted to zero and need to be programmed to the desired values. smbus timeout feature defaults to being enabled and can be programmed to disable. these registers are required to be initialized bef ore the device can properly function. except for the spd, which does not have any programmable regist ers, and does not need to be initialized. se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 12 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd ta b l e 5 shows the default values and the example value to be programmed to these registers. 7.7 smbus timeout the se97b supports smbus timeout feature. if the host holds scl low more than 35 ms, the se97b would reset its internal state machine to the bus idle state to prevent a system bus hang-up. this feature is turned on by default and release sda. the smbus timeout can be disabled by writing a ?1? to smbus[7]. remark: when smbus timeout is enabled, the i 2 c-bus minimum bus speed is limited by the smbus timeout spec ification limit of 10 khz. the se97b has no scl driver, so it cannot hold the scl line low. 7.8 smbus alert response address (ara) the se97b supports smbus alert when it is programmed for the interrupt mode and when the event polarity bit is set to ?0?. in comparator mode or when the event polarity bit is set to ?1?, the smbus alert address is not ack nowledged. the event pin can be anded with other event or interrupt signals from other slave devices to signal their intention to communicate with the host co ntroller. when the host detects event or other interrupt signal low, it issues an ara to which a slave device would respond with its address. when there are multiple slave devices generating an alert the se97b performs bus arbitration with the other slaves. if it wins the bus, it responds to the ara and then clears the event pin. this feature is turned off by default and can be enabled by writing a ?0? to smbus[0]. remark: either in comparator mode or when the se97b crosses the critical temperature, the host must also read the event status bit and provide remedy to the situation by bringing the temperature to within the alarm window or below the critical temperature if that bit is set. ot herwise, the event pin will not get de-asserted. table 5. registers to be initialized register default value example value description 01h 0000h 0209h configuration register ? hysteresis = 1.5 c ? event output = interrupt mode ? event output is enabled 02h 0000h 0550h upper boundary alarm trip register = 85 c 03h 0000h 1f40h lower boundary alarm trip register = ? 20 c 04h 0000h 05f0h critical alarm trip register = 95 c 22h 21h 21h smbus register = no change se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 13 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.9 smbus/i 2 c-bus interface the data registers in this device are selected by the pointer register. at power-up, the pointer register is set to ?00h?, the locati on for the capability register. the pointer register latches the last locati on to which it was set. each data register falls into one of three types of user accessibility: ? read only ? write only ? write/read same address a ?write? to this device will always include th e address byte an d the pointer byte. a write to any register other than the pointer register requires two data bytes. reading this device can take place either of two ways: ? if the location latched in the pointer register is correct (most of the time it is expected that the pointer regist er will point to one of the temperature register (as it will be the data most frequently read), then the read can simply consist of an address byte, followed by retrieving the two data bytes. ? if the pointer register needs to be set, then an address byte, pointer byte, repeat start, and ano ther address byte will accomplish a read. the data byte has the most significant bit first. at the end of a read, th is device can accept either acknowledge (ack) or no acknowledg e (nack) from the master (no acknowledge is typically used as a signal for the slave that the master has read its last byte). it takes this device 125 ms to measure the temp erature. refer to timing diagrams figure 6 to figure 9 for how to program the device. fig 5. how se97b responds to smbus alert response address 0 0 0 1 1 a2 alert response address 1 1 0 0 s 0 0 0 start bit read acknowledge 002aac685 a1 a0 0 1 p device address no acknowledge stop bit host nack and sends a stop bit slave acknowledges and sends its slave address. the last bit of slave address is hard coded '0'. master sends a start bit, ara and a read command host detects smbus alert 1 a = ack = acknowledge bit. w = write bit = 0. r = read bit = 1. fig 6. smbus/i 2 c-bus write to the pointer register 123456789123456789 scl a6 a5 a4 a3 a2 a1 a0 sda d7 d6 d5 d4 d3 d2 d1 d0 device address and write register address wa s start ack by device p stop a ack by device 002aab30 8 se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 14 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd a = ack = acknowledge bit. w = write bit = 0. r = read bit = 1. fig 7. smbus/i 2 c-bus write to the pointer register followed by a write data word 123456789123456789 scl a6 a5 a4 a3 a2 a1 a0 sda d7 d6 d5 d4 d3 d2 d1 d0 device address and write write register address wa s start by host ack by device a ack by device (cont.) (cont.) 002aab412 123456789123456789 scl d15 d14 d13 d12 d11 d10 d9 sda d7 d6 d5 d4 d3 d2 d1 d0 most significant byte data least significant byte data a by host ack by device p stop by host d8 a ack by device a = ack = acknowledge bit. a = nack = no acknowledge bit. w = write bit = 0. r = read bit = 1. fig 8. smbus/i 2 c-bus write to pointer register followed by a repeated start and an immediate data word read 123456789123456789 scl a6 a5 a4 a3 a2 a1 a0 sda d7 d6 d5 d4 d3 d2 d1 d0 device address and write read register address wa s start by host ack by device a ack by device (cont.) (cont.) 123456789 d15 d14 d13 d12 d11 d10 d9 d8 returned most significant byte data a ack by host scl sda 123456789 scl a6 a5 a4 a3 a2 a1 a0 sda device address and read ra sr repeated start by host ack by device (cont.) (cont.) 002aac686 123456789 d7 d6 d5 d4 d3 d2 d1 d0 returned least significant byte data p stop by host a nack by host se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 15 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.10 eeprom operation the 2-kbit eeprom is organized as either 256 bytes of 8 bits each (byte mode), or 16 pages of 16 bytes each (page mode). a ccessing the eeprom in byte mode or page mode is automatic; partial page write of 2 byt es, 4 bytes, or 8 bytes is also supported. communication with the eeprom is via the 2-wire serial i 2 c-bus or smbus. figure 10 provides an overview of the eeprom partitioning. a = ack = acknowledge bit. a = nack = no acknowledge bit. w = write bit = 0. r = read bit = 1. fig 9. smbus/i 2 c-bus word read from register with a pre-set pointer 123456789 d15 d14 d13 d12 d11 d10 d9 d8 returned most significant byte data a ack by host scl sda 123456789 scl a6 a5 a4 a3 a2 a1 a0 sda device address and read ra ack by device (cont.) (cont.) 002aac68 7 123456789 d7 d6 d5 d4 d3 d2 d1 d0 returned least significant byte data p stop nack by host s start by host a fig 10. eeprom partitioning ffh 80h 7fh 0fh 00h 00h 01h 07h 1 page or 16 bytes 8 pages or 128 bytes 16 pages or 256 bytes no write protect write protect by software 002aac81 2 se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 16 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.10.1 write operations 7.10.1.1 byte write in byte write mode the master creates a start condition and then broadcasts the slave address, byte address, and data to be writ ten. the slave acknowledges all 3 bytes by pulling down the sda line during the ninth clock cycle following each byte. the master creates a stop condition after the last ack from the slave, which then starts the internal write operation (see figure 11 ). during internal write, the slave will ignore any read/write request from the master. 7.10.1.2 page write the se97b contains 256 bytes of data, arranged in 16 pages of 16 bytes each. the page is selected by the four most significant bits (msb) of the address byte presented to the device after the slave address, while the four least significant bits (lsb) point to the byte within the page. by loading more than one data byte into the device, up to an entire page can be written in one write cycle (see figure 12 ). the internal byte address counter will increment automatically after each data byte. if the master transmits more than 16 data bytes, then earlier bytes will be over written by later bytes in a wrap-around fashion within the selected page. the internal write cycle is started following the stop condition created by the master. fig 11. byte write timing 002aab246 0 1 0 a2 a1 a0 0 a s 1 a p slave address (memory) start condition r/w acknowledge from slave acknowledge from slave word address sda stop condition; write to the memory is performed data data a acknowledge from slave fig 12. page write timing 0 1 0 a2 a1 a0 0 a s 1 a slave address (memory) start condition r/w acknowledge from slave acknowledge from slave word address sda data to memory data n a acknowledge from slave 002aab247 p stop condition; write to the memory is performed data to memory data n + 15 a acknowledge from slave se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 17 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.10.1.3 acknowledge polling acknowledge polling can be used to determine if the se97b is busy writing or is ready to accept commands. polling is implemented by se nding a ?selective read? command (described in section 7.10.3 ? read operations ? ) to the device. the se97b will not acknowledge the slave address as long as internal write is in progress. 7.10.2 memory protection the lower half (the first 128 bytes) of the memory can be write protected by special eeprom commands without an exte rnal control pin. the se97b features three types of memory write protection instructions, and th ree respective read protection instructions. the level of write-protection (set or clear) that has been defined us ing these instructions remained defined even after power cycle. the memory protection commands are: ? permanent write protection (pwp) ? reversible write protection (rwp) ? clear write protection (cwp) ? read permanent write protection (rpwp) ? read reversible write protection (rrwp) ? read clear write protection (rcwp) ta b l e 6 is the summary for normal and memory protection instructions. [1] the most significant bi t, bit 7, is sent first. [2] v i(ov) ranges from 7.0 v to 10 v. [3] a0, a1, and a2 are compared against the respec tive external pins on the se97b. do not apply v i(ov) to the a0 pin during normal eeprom read/write, permanent write protection (pwp) and read pwp. this special eeprom command consists of a unique 4-bit fi xed address (0110b) and the voltage level applied on the 3-bit hardware address. normally, to address the memory array, the 4-bit fixed address is ?1010b?. to access the memory protection settings, the 4-bit fixed address is ?0110b?. figure 13 and figure 14 show the write and read protection sequence, respectively. table 6. eeprom commands summary command fixed address hardware selectable address r/w bit 7 [1] bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 normal eeprom read/write 1010a2a1a0r/w reversible write protection (rwp) 0110v ss v ss v i(ov) [2] 0 clear reversible write protection (crwp)0110v ss v dd v i(ov) [2] 0 permanent write protection (pwp) [3] 0110a2a1a00 read rwp 0110v ss v ss v i(ov) [2] 1 read crwp 0110v ss v dd v i(ov) [2] 1 read pwp 0110a2a1a01 se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 18 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd up to eight memory devices can be connected on a single i 2 c-bus. each one is given a 3-bit on the hardware selectable address (a2, a1, a0) inputs. the device only responds when the 4-bit fixed and hardware selectable bits are matched. the 8th bit is the read/write bit. this bit is set to 1 or 0 for read and write protection, respectively. the corresponding device acknowledges during the ninth bit time when there is a match on the 7-bit address. the device does not acknowledge when there is no match on the 7-bit address or when the device is already in permanent write protection mode and is programmed with any write protection instructions (i.e., pwp, rwp, cwp). 7.10.2.1 permanent write protection (pwp) if the software write-protection has been set with the pwp instruction, the first 128 bytes of the memory are permanently write-protected. this write-protection cannot be cleared by any instruction, or by power-cycling the device. also, once the pwp instruction has been successfully executed, the device no lon ger acknowledges any instruction (with 4-bit fixed address of 0110b) to access the write-protection settings. x = don?t care (1) refer to table 7 regarding the exact state of the acknowledge bit. fig 13. software write protect (write) 1 1 0 a2 a1 a0 0 a s 0 a slave address (memory) start condition r/w acknowledge (1) from slave acknowledge (1) from slave dummy byte address sda dummy data a acknowledge (1) from slave 002aab356 p stop condition xxxxxxxx xxxxxxxx x = don?t care (1) refer to table 8 regarding the exact state of the acknowledge bit. fig 14. software write protect (read) 1 1 0 a2 a1 a0 1 a s 0 a slave address (memory) start condition r/w acknowledge (1) from slave no acknowledge (1) from slave dummy byte address sda dummy data a no acknowledge (1) from slave 002aac644 p stop condition xxxxxxxx xxxxxxxx se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 19 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.10.2.2 reversible write protection (rwp) and clear reversible write protection (crwp) if the software write-protection has been set with the rwp instruction, it can be cleared again with a crwp instruction. the two instructions, rwp and crwp have the same format as a byte write instruction, but with a different setting for the ha rdware address pins (as shown in ta b l e 6 ). like the byte write instruction, it is followed by an address byte and a data byte, but in this case the contents are all ?don?t care? ( figure 13 ). another difference is that the voltage, v i(ov) , must be applied on the a0 pin, and specific lo gical levels must be applied on the other two (a1 and a2), as shown in ta b l e 6 . 7.10.2.3 read permanent write protection (rpwp), read reversible write protection (rrwp), and read clear reversible write protection (rcrwp) read pwp, rwp, and crwp allow the se97b to be read in write protection mode. the instruction format is the same as that of the write protection except that the 8 th bit, r/w , is set to 1. figure 14 shows the instruction format, while ta b l e 8 shows the responses when the instructions are issued. table 7. acknowledge when writing data or defining write protection instructions with r/w bit = 0. status instruction ack address ack data byte ack write cycle (t w ) permanently protected pwp, rwp or crwp nack not significant nack not significant nack no page or byte write in lower 128 bytes ack address ack data nack no protected with rwp rwp nack not significant nack not significant nack no crwp ack not significant ack not significant ack yes pwp ack not significant ack not significant ack yes page or byte write in lower 128 bytes ack address ack data nack no not protected pwp or rwp ack not significant ack not significant ack yes crwp ack not significant ack not significant ack no page or byte write ack address ack data ack yes table 8. acknowledge when reading the write protection instructions with r/w bit = 1. status instruction ack address ack data byte ack permanently protected rpwp, rrwp or rcrwp nack not significant nack not significant nack protected with rwp rrwp nack not significant nack not significant nack rcrwp ack not significant nack not significant nack rpwp ack not significant nack not significant nack not protected rpwp, rrwp or rcrwp ack not significant nack not significant nack se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 20 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.10.3 read operations 7.10.3.1 current address read in standby mode, the se97b internal address counter points to the data byte immediately following the last byte accessed by a previous op eration. if the ?previous? byte was the last byte in memory, then the address counter will po int to the first memory byte, and so on. if the se97b decodes a slave address with a ?1? in the r/w bit position ( figure 15 ), it will issue an acknowledge in the ninth clock cycle and will then transmit the data byte being pointed at by the address counter. the master can then stop further transmission by issuing a no acknowledge on the ninth bit then followed by a stop condition. 7.10.3.2 selective read the read operation can also be started at an address different from the one stored in the address counter. the address counter can be ?initialized? by performing a ?dummy? write operation ( figure 16 ). the start condition is followe d by the slave address (with the r/w bit set to ?0?) and the desired byte address. instead of following-up with data, the master then issues a second start, followed by the ?current address read? sequence, as described in section 7.10.3.1 . fig 15. current address read timing 0 1 0 a2 a1 a0 1 a s 1 slave address (memory) start condition r/w acknowledge from slave data from memory sda 002aab251 p stop condition no acknowledge from master a fig 16. selective read timing 0 1 0 a2 a1 a0 0 a s 1 a slave address (memory) start condition r/w acknowledge from slave acknowledge from slave word address sda 002aac901 p stop condition data from memory a no acknowledge from master 0 1 0 a2 a1 a0 s 1 slave address (memory) start condition 1 a r/w acknowledge from slave se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 21 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 7.10.3.3 sequential read if the master acknowle dges the first data byte transmitt ed by the se97b, then the device will continue transmitting as long as each data byte is acknowledged by the master ( figure 17 ). if the end of memory is reached during sequential read, the address counter will ?wrap around? to the beginning of memo ry, and so on. sequential read works with either ?immediate address read? or ?selective read?, the only difference being the starting byte address. fig 17. sequential read timing 0 1 0 a2 a1 a0 1 a s 1 a slave address (memory) start condition r/w acknowledge from slave acknowledge from master data from memory sda data from memory data n + 1 a acknowledge from master 002aab253 p stop condition data from memory data n + x a no acknowledge from master data n se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 22 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 8. register descriptions 8.1 register overview this section describes all the registers used in the se97b. the registers are used for latching the temperature reading, storing the low and high temperature limits, configuring, the hysteresis threshold of the adc, as we ll as reporting status. the device uses the pointer register to access these registers. r ead registers, as the name implies, are used for read only, and the write registers are for write only. any attempt to read from a write-only register will result in reading ?0?s. writing to a read-only register will have no effect on the read even though the write command is acknowledged. the pointer register is an 8-bit register. all other registers are 16-bit. a write to reserved registers my cause unexpec ted results which may re sult in requiring a reset by removing and re-applying its power. table 9. register summary address (hex) default state (hex) register name short name jedec name n/a n/a pointer register 00h f7h capability register cap capabilities 01h 0000h configuration register config configuration 02h 0000h upper boundary alarm trip register upper high limit 03h 0000h lower boundary alarm trip register lower low limit 04h 0000h critical alarm trip register critical tcrit limit 05h n/a temperature register temp ambient temperature 06h 1131h manufacturer id register manid manufacturer id 07h a203h device id/revision register deviceid device/revision 08h to 21h 0000h reserved registers 22h 21h smbus register smbus 23h to ffh 0000h reserved vendor-defined se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 23 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 8.2 cap ? capability regist er (00h, 16-bit read-only) table 10. cap - capability register (address 00h) bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu default 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol evsd tmout vhv tres tres wrng hacc bcap default 11110111 access rrrrrrrr table 11. capability register (address 00h) bit description bit symbol description 15:8 rfu reserved for future use; must be zero. 7 evsd event with shutdown action. 0 ? the event output freezes in its current state when entering shutdown. upon exiting shutdown, the event output remains in the previous state until the next thermal sample is taken. 1 (default) ? the event output is de-asserted (not driven) when entering shutdown, and remains de-asserted upon exit from shutdown until the next thermal sample is taken. remark: bit 7 follows the state of smbus[4] which can change event output to freeze. 6 tmout bus time-out pe riod for thermal sensor access during normal operation. note that bus time-out support is operational in shutdown mode, or for access to the eeprom portion of the device. 1 ? parameter t to(smbus) is supported within t he range of 25 ms to 35 ms (smbus compatible). 5 vhv high voltage standoff for pin a0. 1 ? supports a voltage up to 10 v on the a0 pin. 4:3 tres temperature resolution. 10 ? 0.125 c lsb (11-bit) 2 wrng wider range. 1 ? can read temperatures below 0 c and set sign bit accordingly 1 hacc higher accuracy (set during manufacture). 1 ? b grade accuracy 0 bcap basic capability. 1 ? has alarm and critical trips interrupt capability se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 24 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 8.3 config ? configuration regi ster (01h, 16-bit read/write) table 12. config - configuration register (address 01h) bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu hen shmd default 00000000 access rrrrrr/wr/wr/w bit 7 6 5 4 3 2 1 0 symbol ctlb awlb cevnt estat eoctl cvo ep emd default 00000000 access r/w r/w w r r/w r/w r/w r/w table 13. configuration register (address 01h) bit description bit symbol description 15:11 rfu reserved for future use; must be ?0?. 10:9 hen hysteresis enable. 00 ? disable hysteresis (default) 01 ? enable hysteresis at 1.5 c 10 ? enable hysteresis at 3 c 11 ? enable hysteresis at 6 c when enabled, hysteresis is applied to temperature movement around trigger points. for example, consider the behavior of the ?above alarm window? bit (bit 14 of the temperature regi ster) when the hysteresis is set to 3 c. as the temperature rises, bit 14 wi ll be set to ?1? (temperature is above the alarm window) when the temperature register contains a value that is greater than the value in the alarm te mperature upper boundary register. if the temperature decrease s, bit 14 will remain set until the measured temperature is less than or equal to the value in the alarm temperature upper boundary register minus 3 c. (refer to figure 4 and table 14 ). similarly, the ?below alarm window? bit (bit 13 of the temperature register) will be set to ?0? (temperature is equal to or above the alarm window lower boundary trip register) when the value in the temperature register is equal to or greater than the value in the alarm temperature lower boundary register. as the temperature decreases , bit 13 will be set to ?1? when the value in the temperature register is equal to or less than the value in the alarm temperature lower boundary register minus 3 c. note that hysteresis is also applied to event pin functionality. when either of the critical trip or alarm window lock bits is set, these bits cannot be altered until unlocked. se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 25 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 8 shmd shutdown mode. 0 ? temperature sensor is ac tive and converting (default). 1 ? disabled temperature sensor will not generate interrupts or update the temperature data. when shut down, the thermal sensor diode and adc are disabled to save power, no events will be generated. when ei ther of the critical trip or alarm window lock bits is set, this bit cannot be set until unlocked. however, it can be cleared at any time. when in shutdo wn mode, the se97b will still respond to commands normally. when coming out of shutdown, the event output remains de-asserted as a new temperature conversion is done. hyst eresis is subtracted from the alarm thresholds if the temperature is falli ng but not used if the temperature is rising. the temperature trend will not be determined until at least two temperature conversions are done. si nce all the alarm threshold flags (temp bits 13, 14, 15) are cleared with coming out of shutdown, it was decided to only apply hysteresis to the lower alarm threshold calculations when determining after the initial temperature conversion if the event should assert. after the second temp erature conversion the direction of temperature is known and temp bits 13, 14 or 15 are changed as required and the event is asserted as required. 7 ctlb critical trip lock bit. 0 ? critical alarm trip register is not locked and can be altered (default) 1 ? critical alarm trip register settings cannot be altered this bit is initially cleared. when set, this bit will return a ?1?, and remains locked until cleared by internal power- on reset. this bit can be written with a single write and does not require double writes. 6 awlb alarm window lock bit. 0 ? upper and lower alarm trip registers are not locked and can be altered (default) 1 ? upper and lower alarm trip registers setting cannot be altered this bit is initially cleared. when set, this bit will return a ?1? and remains locked until cleared by internal power-on reset. this bit can be written with a single write and does not require double writes. 5 cevnt clear event (write only). 0 ? no effect (default) 1 ? clears active event in interrupt mode. writing to this register has no effect in comparator mode. if smbus[0] is a logic 0, the smbus alert response address (ara) command can be sent to also clear the event output. when read, this register always returns zero. 4 estat event status (read only). 0 ? event output condition is not being asserted by this device (default) 1 ? event output pin is being asserted by this device due to alarm window or critical trip condition the actual event causing the event can be determined from the read temperature register. interrupt events ca n be cleared by writing to the ?clear event ? bit (cevnt) or smbus alert response. writing to this bit will have no effect. table 13. configuration register (address 01h) bit description ?continued bit symbol description se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 26 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 3 eoctl event output control. 0 ? event output disabled (default) 1 ? event output enabled when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. 2 cvo critical event only. 0 ? event output on alarm or critic al temperature event (default) 1 ? event only if temperature is above the value in the critical temperature register when the alarm window lock bit is set, this bit cannot be altered until unlocked. 1 ep event polarity. 0 ? active low (default) 1 ? active high. when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. when the ep (event polarity) bit is changed, the event output would immediately change state on the se97b. a new shutdown mode has been added on the se97b with two states defined by the smbus register eventsleepstate = 0. fr eeze state of event output and eventsleepstate = 1: de-as serted state of event output. so now if the ep bit changes, the event output state will change immediately even during shutdown. it will not wait for the part to do a new temperature conversion after coming out of shutdown. changes to all other bits in the config register and the smbus register take effect after a new temperature conversion happens when the part comes out of shutdown. the ep bit is not related to temperature conversion or readin gs or if the part is in shutdown or active. remark: in shutdown mode, when disabletimeout = 1 or if disabletimeout = 0 and enable sdio = 0, the event polarity bit will not take effect immediately, but will updated after it comes out of shutdown. 0 emd event mode. 0 ? comparator output mode (default) 1 ? interrupt mode when either of the critical trip or alarm window lock bits is set, this bit cannot be altered until unlocked. table 13. configuration register (address 01h) bit description ?continued bit symbol description se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 27 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd table 14. hysteresis enable action below alarm window bit (bit 13) above alarm window bit (bit 14) above critical trip bit (bit 15) temperature slope threshold temperature temperature slope threshold temperature temperature slope threshold temperature sets falling t trip(l) ? t hys rising t trip(u) rising t th(crit) clears rising t trip(l) falling t trip(u) ? t hys falling t th(crit) ? t hys fig 18. hysteresis: how it works 002aac799 current temperature time temperature set clear clear set clear clear set clear below alarm window (register 05h; bit 13 = baw bit) above alarm window (register 05h; bit 14 = aaw bit) above critical trip (register 05h; bit 15 = act bit) lower alarm threshold upper alarm threshold critical alarm threshold hysteresis hysteresis hysteresis se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 28 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 8.4 temperature format the temperature data from the temperature read back register is an 11-bit 2?s complement word with the least significan t bit (lsb) equal to 0.125 c (resolution). ? a value of 019ch will represent 25.75 c ? a value of 07c0h will represent 124 c ? a value of 1e64h will represent ? 25.75 c. the unused lsb (bit 0) is set to ?0?. bit 11 will have a resolution of 128 c. the upper 3 bits of the temperature register indicate trip status based on the current temperature, and are not affect ed by the status of the event output. one of the ways to calculate the temper ature, upper boundary, lower boundary, and critical alarm trip values in c from the 12-bit temp data is: ? if the sign bit = 0, then the temperature is positive, ( c) = +(temp data) 0.125 c (0.250 c for alarm registers). ? if the sign bit = 1, then the temperature is negative, ( c) = ? (2?s complement of temp data) 0.125 c (0.250 c for alarm registers). ta b l e 1 5 lists the examples of the content of the temperature data register for positive and negative temperature for two scenarios of status bits: status bits = 000b and status bits = 111b. table 15. degree celsius and temperature data register temperature content of temperature data register status bits = 000b status bits = 111b binary hex binary hex +125 c 000 0 01111101 000 0 07d0h 111 0 01111101 000 0 e7d0h +25 c 000 0 00011001 000 0 0190h 111 0 00011001 000 0 e190h +1 c 000 0 00000001 000 0 0010h 111 0 00000001 000 0 e010h +0.25 c 000 0 00000000 010 0 0004h 111 0 00000000 010 0 e004h +0.125 c 000 0 00000000 001 0 0002h 111 0 00000000 001 0 e002h 0 c 000 0 00000000 000 0 0000h 111 0 00000000 000 0 e000h ? 0.125 c 000 1 11111111 111 0 1ffeh 111 1 11111111 111 0 fffeh ? 0.25 c 000 1 11111111 110 0 1ffch 111 1 11111111 110 0 fffch ? 1 c 000 1 11111111 000 0 1ff0h 111 1 11111111 000 0 fff0h ? 20 c 000 1 11110100 000 0 1f40h 111 1 11110100 000 0 ff40h ? 25 c 000 1 11100111 000 0 1e70h 111 1 11100111 000 0 fe70h ? 55 c 000 1 11001001 000 0 1c90h 111 1 11001001 000 0 fc90h se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 29 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 8.5 temperature trip point registers while writing to the 16-bit upper, lower, or critical boundary alarm trip registers, please ensure that both bytes get written before doing a new start or stop to ensure that a valid temperature value gets written into the registers. 8.5.1 upper ? upper boundary alarm trip register (02h, 16-bit read/write) the value is the upper threshold temperature value for alarm mode. the data format is 2?s complement with bit 2 = 0.25 c. ?rfu? bits will always re port zero. interrupts will respond to the presently programmed boundary values. if boundary values are being altered in-system, it is advised to turn off in terrupts until a known state can be obtained to avoid superfluous interrupt activity. table 16. upper - upper boundary al arm trip register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu rfu rfu sign 128 c64 c32 c16 c default 00000000 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol 8 c4 c2 c1 c0.5 c0.25 crfu rfu default 00000000 access r/w r/w r/w r/w r/w r/w r r table 17. upper boundary alarm trip register bit description bit symbol description 15:13 rfu reserved; always ?0? 12 sign sign (msb) 11:2 - upper boundary alarm trip temperature (lsb = 0.25 c) 1:0 rfu reserved; always ?0? se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 30 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 8.5.2 lower ? lower boundary alarm trip register (03h, 16-bit read/write) the value is the lower threshold temperature value for alarm mode. the data format is 2?s complement with bit 2 = 0.25 c. rfu bits will always re port zero. interrupts will respond to the presently programmed boundary values. if boundary values are being altered in-system, it is advised to turn off in terrupts until a known state can be obtained to avoid superfluous interrupt activity. 8.5.3 critical ? critical alarm trip register (04h, 16-bit read/write) the value is the critical temperature. the data format is 2?s complement with bit 2 = 0.25 c. rfu bits will always report zero. table 18. lower - lower boundary alarm trip register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu rfu rfu sign 128 c64 c32 c16 c default 00000000 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol 8 c4 c2 c1 c0.5 c0.25 crfu rfu default 00000000 access r/w r/w r/w r/w r/w r/w r r table 19. lower boundary alarm trip register bit description bit symbol description 15:13 rfu reserved; always ?0? 12 sign sign (msb) 11:2 - lower boundary alarm trip temperature (lsb = 0.25 c) 1:0 rfu reserved; always ?0? table 20. critical - crit ical alarm trip register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu rfu rfu sign 128 c64 c32 c16 c default 00000000 access r r r r/w r/w r/w r/w r/w bit 7 6 5 4 3 2 1 0 symbol 8 c4 c2 c1 c0.5 c0.25 crfu rfu default 00000000 access r/w r/w r/w r/w r/w r/w r r table 21. critical alarm trip register bit description bit symbol description 15:13 rfu reserved; always ?0? 12 sign sign (msb) 11:2 - critical alarm trip temperature (lsb = 0.25 c) 1:0 rfu reserved; always ?0? se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 31 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 8.6 temp ? temperature regist er (05h, 16-bit read-only) table 22. temp - temperatur e register bit allocation bit 15 14 13 12 11 10 9 8 symbol act aaw baw sign 128 c64 c32 c16 c default 00000000 access rrrrrrrr bit 7 6 5 4 3 2 1 0 symbol 8 c4 c2 c1 c0.5 c0.25 c 0.125 crfu default 00000000 access rrrrrrrr table 23. temperature register bit description bit symbol description 15 act above critical trip. increasing t amb : 0 ? t amb se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 33 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 8.9 smbus ? smbus register (22h, 8-bit read/write) table 26. smbus - smbus time-out register bit allocation bit 15 14 13 12 11 10 9 8 symbol rfu default 0 0000000 access r rrrrrrr bit 7 6 5 4 3 2 1 0 symbol disable timeout rfu enable sdto event sleep state intrclear mode flag update mode rfu disable ara default 0 0110001 access r/w r r/w r/w r/w r/w r r/w table 27. smbus time-out register bit description bit symbol description 15:8 rfu reserved; always ?0? 7 disabletimeout disable smbus time-out. 0 ? smbus time-out is enabled (default) 1 ? smbus time-out is disabled when either of the critical trip or al arm window lock bits is set, this bit cannot be altered until unlocked. 6 rfu reserved; always ?0? 5 enablesdto smbus time-out du ring shutdown (config[8]). 0 ? disable smbus time-out 1 ? enable smbus time-out (default) remark: disabletimeout bit must be a logic 0 to enable this feature. when either critical trip or alarm window lock bits are set, this bit cannot be altered until unlocked. 4 eventsleep state [1] state of event output when shmd bit is set. 0 ? event pin state is frozen 1 ? event pin is de-asserted, state based on polarity bit (default) when either critical trip or alarm window lock bits are set, this bit cannot be altered until unlocked. 3 intrclear mode [2] interrupt flop clearing mode. 0 ? allow clearing interrupt flop whil e in comparator mode (default) 1 ? disable clearing interrupt flow while in comparator mode when either critical trip or alarm window lock bits are set, this bit cannot be altered until unlocked. 2 flagupdate mode update aaw, baw and act flags after each new temperature conversion. 0 ? update aaw, baw and act flags continuously (default) 1 ? update flags with new temperature conversion when either critical trip or alarm window lock bits are set, this bit cannot be altered until unlocked. se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 34 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd [1] when the part comes out of shutdown, the state of the event pin will not change until after the first temperature conversion. when the part enters shutdown, the act (temp[15]), aaw (temp[14]) and baw (temp[13]) bits (flip-flops) will be cleared. [2] the stts424e02 allows clearing the interrupt when in comparator mode, but the other competitors do not. [1] smbus time-out. 0 ? enabled (default) 1 ? disabled [2] shutdown time-out. 0 ? smbus time-out disabled when shmd = 1 1 ? smbus time-out enabled when shmd = 1 (default) [3] thermal sensor shutdown mode. 0 ? active (default) 1 ? shutdown 1 rfu reserved; always ?0? 0 disableara disable smbus alert response address (ara). 0 ? smbus ara is enabled 1 ? disable smbus ara (default) when either of the critical trip or al arm window lock bits is set, this bit cannot be altered until unlocked. table 27. smbus time-out register bit description ?continued bit symbol description table 28. smbus register setting guide disable timeout [1] enable sdto [2] shmd [3] thermal sensor behavior spd behavior power mode use 0 x 0 ts is active and smbus to is on spd read/write and smbus to is on full power, oscillator is running jedec - smbus for ts and spd (like se97 if ts is on) 1 x 0 ts is active and smbus to is off spd read/write and smbus to is off full power, oscillator is running i 2 c-bus - no smbus to 0 1 1 ts is disabled and smbus to is on spd read/write and smbus to is on lower power, oscillator is off unless bus active or write to spd jedec - smbus for ts and spd 1 1 1 ts is disabled and smbus to is off spd low power read/write and smbus to is off lower power, oscillator is off unless write to the spd i 2 c-bus - no smbus to x 0 1 ts is disabled and smbus to is off spd low power read-only and smbus to is off lowest power, oscillator is off all the time i 2 c-bus - no smbus to (like se97 if ts is off) se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 35 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 9. application design-in information in a typical application, the se97b behaves as a slave device and interfaces to a bus master (or host) via the scl and sda lines. the event output is monitored by the host, and asserts when the temperature reading ex ceeds the programmed values in the alarm registers. the a0, a1 and a2 pins are directly connected to v dd or v ss without any pull-up resistors. the sda and scl serial interface pi ns are open-drain i/os that require pull-up resistors, and are able to sink a maximum of 3 ma with a voltage drop less than 0.4 v. typical pull-up values for scl and sda are 10 k , but the resistor values can be changed in order to meet the rise time requirement if the capacitance load is too large due to routing, connectors, or multiple components sharing the same bus. fig 19. typical application showing se97b interfacing with 3.3 v host 002aae31 3 host controller se97b a0 a1 a2 scl sda event v dd 10 k (3 ) v ss slave master 3.3 v fig 20. se97b interfacing with 1.0 v host controller 002aae31 4 host controller se97b a0 a1 a2 scl sda event v dd 10 k v ss 3.3 v 0.1 f 10 k pca9509 mother board 0.1 f v cc(b) b2 b1 en v cc(a) a2 a1 10 k 10 k scl sda event 0.1 f 1.0 v 5 % se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 36 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 9.1 se97b in memory module application figure 21 shows the se97b being placed in the memory module application. the se97b is centered in the memory module to monito r the temperature of the dram and also to provide a 2-kbit eeprom as the serial presence detect (spd). in the event of overheating, the se97b triggers the event output and the memory controller throttles the memory bus to slow the dram. the memory controller can also read the se97b and watch the dram thermal behavior, taking preventive measures when necessary. 9.2 layout consideration the se97b does not require any additional co mponents other than the host controller to read its temperature. it is recommended that a 0.1 f bypass capacitor between the v dd and v ss pins is located as close as possible to the power and ground pins for noise protection. 9.3 thermal considerations in general, self-heating is the result of po wer consumption and not a concern, especially with the se97b, which consum es very low power. in the event the sda and event pins are heavily loaded with small pull-up resistor values, self-heating affects temperature accuracy by approximately 0.5 c. equation 1 is the formula to calculate the effect of self-heating: (1) where: t = t j ? t amb t j = junction temperature t amb = ambient temperature r th(j-a) = package thermal resistance v dd = supply voltage i dd(av) = average supply current fig 21. system application 002aae31 5 se97b event dimm dram dram dram dram memory controller smbus cpu tr th j - a () v dd i dd av () () v ol sda () i ol k sin () sda () () v ol event () i ol k sin () event () ++ [ ] = se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 37 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd v ol(sda) = low-level output voltage on pin sda v ol(event) = low-level output voltage on pin event i ol(sink)(sda) = sda output current low i ol(sink)event = event output current low calculation example: t amb (typical temperature inside the notebook) = 50 c i dd(av) = 400 a v dd = 3.6 v maximum v ol(sda) = 0.4 v i ol(sink)(sda) = 1 ma v ol(event) = 0.4 v i ol(sink)event = 3 ma r th(j-a) = 56 c/w self heating due to power dissipation is: (2) 9.4 hot plugging the se97b can be used in hot plugging applic ations. internal circuitry prevents damaging current backflow through the device when it is powered down, but with the i 2 c-bus, event or address pins still connected . the open-drain sda and event pins (scl and address pins are input only) effectively places the outputs in a high-impedance state during power-up and power-down, which prevents driver conflict and bus contention. the 50 ns noise filter will filter out any insertion glitches from the state machine, which is very robust and not prone to false operation. the device needs a proper power-up sequence to reset itself, not only for the device i 2 c-bus and i/o initial states, but also to load specific pre-defined data or calibration data into its operational registers. the power-up sequence should occur correctly with a fast ramp rate and the i 2 c-bus active. the se97b might not respond immediately after power-up, but it should not damage the part if the power-up sequence is abnormal. if the scl line is held low, the part will not exit th e power-on rese t mode since the part is held in reset until scl is released. t56 3.60.4 () 0.4 3 () 0.4 1 () ++ [] 56 c w 3.04 mw 0.17 c = ? = = se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 38 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 10. limiting values 11. characteristics table 29. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +4.3 v v n voltage on any other pin sda, scl, a1, a2, event pins ? 0.5 +4.3 v v a0 voltage on pin a0 overvoltage input; a0 pin ? 0.5 +12.5 v i sink sink current sda, event pins ? 1+10ma t j(max) maximum junction temperature - 150 c t stg storage temperature ? 65 +165 c table 30. thermal sensor characteristics v dd = 3.0 v to 3.6 v; t amb = ? 40 c to +125 c; unless otherwise specified. symbol parameter conditions min typ max unit t lim(acc) temperature limit accuracy b-grade; v dd = 3.0 v to 3.6 v t amb =75 cto95 c ? 1.0 < 0.5 +1.0 c t amb =40 cto125 c ? 2.0 < 1.0 +2.0 c t amb = ? 40 cto+125 c ? 3.0 < 2+3.0 c t res temperature resolution - 0.125 - c t conv conversion period - 100 120 ms e f(conv) conversion rate error percentage error in programmed data ? 30 - 30 % se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 39 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd [1] if the temperature sensor is not needed it s hould be placed in standby, which will reduce i dd(av) to 0.1 a typical at room temperature or 3.0 a typical at 125 c. [2] high-voltage input voltage applied to pin a0 during rwp and crwp operations. the jedec specification is 7 v (min.) and 10 v (ma x.). when v dd is 3.6 v, then i i(ov) >4.8v +v dd or > 4.8 v + 3.6 v then the minimum voltage is 8.4 v. table 31. dc characteristics v dd = 3.0 v to 3.6 v; t amb = ? 40 c to +125 c; unless otherwise specif ied. these specifications are guaranteed by design. symbol parameter conditions min typ max unit v dd supply voltage 3.0 - 3.6 v i dd(av) average supply current smbus inactive [1] - 210 320 a i dd supply current f scl = 400 khz - 250 400 a i sd(vdd) supply voltage shutdown mode current smbus inactive - 0.1 10 a v ih high-level input voltage scl, sda 0.7 v dd -v dd +1 v v il low-level input voltage scl, sda ? 0.5 - +0.3 v dd v v i(ov) overvoltage input voltage pin a0; v i(ov) ? v dd >4.8v [2] 7.0 - 10 v v ol low-level output voltage sda, event i ol =0.7ma - - 0.2 v i ol =2.1ma - - 0.4 v i ol =3.0ma - - 0.5 v v i(hys) hysteresis of input voltage v dd 2.2 v 0.05 v dd -- v v dd 2.2 v 0.10 v dd -- v v th(por)h high-level power-on reset threshold voltage device operation voltage increase - - 2.9 v v th(rec)por power-on reset recovery threshold voltage device reset voltage decrease 1.2 1.8 - v i loh high-level output leakage current event ; v oh =v dd ? 1.0 - +1.0 a i lih high-level input leakage current sda, scl; v i =v dd ? 1.0 - +1.0 a i lil low-level input leakage current sda, scl; v i =v ss ? 1.0 - +1.0 a a0, a1, a2; v i =v ss ? 1.0 - +1.0 a c i(scl/sda) scl and sda input capacitance -58pf c i(addr) address input capacitance - 5 10 pf i pd pull-down current internal; a0, a1, a2 pins; v i =0.3v dd to v dd --4.0 a z il low-level input impedance pins a0, a1, a2; v i <0.3v dd 30 - - k z ih high-level input impedance pins a0, a1, a2; v i 0.3v dd 800 - - k se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 40 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd i 2 c-bus inactive. f scl = 400 khz. fig 22. average supply current fig 23. average supply current fig 24. shutdown supply current fig 25. sda output v ol at i ol =0.7ma fig 26. sda output v ol at i ol = 2.1 ma fig 27. sda output v ol at i ol =3.0ma t amb ( c) ? 40 120 80 040 002aaf180 320 i dd(av) ( a) 20 120 220 v dd = 3.6 v 3.0 v t amb ( c) ? 40 120 80 040 002aaf181 350 i dd(av) ( a) 50 150 250 v dd = 3.6 v 3.0 v 1 3 5 i sd(vdd) ( a) ? 1 t amb ( c) ? 40 120 80 040 002aaf182 v dd = 3.6 v 3.0 v t amb ( c) ? 40 120 80 040 002aaf183 0.08 0.12 0.04 0.16 0.20 0 v ol (v) v dd = 3.6 v 3.0 v 0 0.3 0.2 0.1 0.4 v ol (v) 002aaf184 t amb ( c) ? 40 120 80 040 v dd = 3.6 v 3.0 v 0 0.3 0.2 0.1 0.4 v ol (v) 002aaf185 t amb ( c) ? 40 120 80 040 v dd = 3.6 v 3.0 v se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 41 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd fig 28. event output v ol at i ol = 0.7 ma fig 29. event output v ol at i ol =2.1ma fig 30. event output v ol at i ol = 3.0 ma fig 31. conversion rate fig 32. conversion period fi g 33. eeprom write cycle time t amb ( c) ? 40 120 80 040 002aaf186 0.08 0.12 0.04 0.16 0.20 0 v ol (v) v dd = 3.6 v 3.0 v t amb ( c) ? 40 120 80 040 002aaf187 0.08 0.12 0.04 0.16 0.20 0 v ol (v) v dd = 3.6 v 3.0 v t amb ( c) ? 40 120 80 040 002aaf188 0.08 0.12 0.04 0.16 0.20 0 v ol (v) v dd = 3.6 v 3.0 v t amb ( c) ? 40 120 80 040 002aad886 9 11 7 13 15 5 conversion rate (conv/s) 60 120 100 80 140 t conv (ms) 002aad887 t amb ( c) ? 40 120 80 040 3 4 5 t cy(w) (ms) 2 t amb ( c) ? 40 120 80 040 002aad888 se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 42 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd for temp sensor conversion. for eeprom read operation. fig 34. average power-on threshold voltage fig 35. average power-on threshold voltage for eeprom write operation. v dd = 3.3 v + 150 mv (p-p); 0.1 f ac coupling capacitor; no decoupling capacitor; t amb =25 c. fig 36. average power-on threshold voltage fig 37. temperature error versus power supply noise frequency 2.0 1.5 2.5 3.0 v th (v) 1.0 t amb ( c) ? 40 120 80 040 002aad889 1.0 0.5 1.5 2.0 v th (v) 0 t amb ( c) ? 40 120 80 040 002aad890 2.0 1.5 2.5 3.0 v th (v) 1.0 t amb ( c) ? 40 120 80 040 002aae107 noise frequency (hz) 10 2 10 8 10 7 10 6 10 3 10 5 10 4 002aad892 1 3 5 temp error (?c) ? 1 se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 43 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd from 25 c (air) to 120 c (oil bath) at 3.3 v. fig 38. se97b temperature accuracy fig 39. package thermal response 3.0 t lim(acc) ( c) ? 3.0 t amb ( c) ? 40 120 80 040 002aaf189 0 ? 1.5 1.5 40 80 120 thermal response (%) 0 time (s) 05 4 23 1 002aaf178 se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 44 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd [1] minimum clock frequency is 0 khz if smbus timeout is disabled. [2] delay from sda stop to sda start. [3] a device must internally provide a hold time of at least 200 ns for sda signal (referenced to the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. [4] delay from scl high-to-low transition to sda edges. [5] delay from scl low-to-high transition to restart sda. [6] delay from sda start to first scl high-to-low transition. [7] these parameters tested initially and after a design or process change that affects the parameter. [8] t pu(r) and t pu(w) are the delays required from the time v dd is stable until the specified operation can be initiated. table 32. smbus ac characteristics v dd = 3.0 v to 3.6 v; t amb = ? 40 c to +125 c; unless otherwise specif ied. these specifications are guaranteed by design. the ac specifications fully meet or exceed smbus 2.0 specifications, but allow the bus to interface with the i 2 c-bus from dc to 400 khz. symbol parameter conditions standard mode fast mode unit min max min max f scl scl clock frequency 10 [1] 100 10 [1] 400 khz t high high period of the scl clock 70 % to 70 % 4000 - 600 - ns t low low period of the scl clock 30 % to 30 % 4700 - 1300 - ns t to(smbus) smbus time-out time low period to reset smbus 25 35 25 35 ms t r rise time of both sda and scl signals - 1000 20 300 ns t f fall time of both sda and scl signals - 300 - 300 ns t su;dat data set-up time 250 - 100 - ns t h(i)(d) data input hold time [2] [3] 0-0-ns t hd;dat data hold time [4] 200 3450 200 900 ns t su;sta set-up time for a repeated start condition [5] 4700 - 600 - ns t hd;sta hold time (repeated) start condition 30 % of sda to 70 % of scl [6] 4000 - 600 - ns t su;sto set-up time for stop condition 4000 - 600 - ns t buf bus free time between a stop and start condition [2] 4700 - 1300 - ns t sp pulse width of spikes that must be suppressed by the input filter -50-50ns t vd;dat data valid time from clock 200 - 200 - ns t f(o) output fall time - - - 250 ns t por power-on reset pulse time power supply falling 0.5 - 0.5 - s eeprom power-up timing [7] t pu(r) read power-up time [8] -1-1ms t pu(w) write power-up time [8] -1-1ms write cycle limits t cy(w) write cycle time [9] -10-10ms se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 45 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd [9] the write cycle time is the time elapsed between the stop co mmand (following the write instruction) and the completion of th e internal write cycle. during the internal write cycle, sda is released by the slave and the device does not acknowledge external command s. s = start condition p = stop condition fig 40. ac waveforms 002aae750 t low sda p s t buf t hd;sta t r t hd;dat t high t su;dat t su;sta t hd;dat s p t su;sto v ih v il v ih v il scl sda scl t su;sto v ih v il v ih v il t w stop condition start condition t su;sta write cycle t f se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 46 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 12. package outline fig 41. package outline sot1069-2 (hwson8) references outline version european projection issue date iec jedec jeita sot1069-2 - - - mo-229 - - - sot1069-2_po 09-10-22 09-11-18 unit mm max nom min 0.80 0.75 0.70 0.05 0.02 0.00 2.1 2.0 1.9 1.6 1.5 1.4 3.1 3.0 2.9 0.5 1.5 0.45 0.40 0.35 0.05 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. h wson8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.8 mm sot1069- 2 a 1 0.65 0.55 0.45 a 2 0.2 a 3 b 0.30 0.25 0.18 d (1) d 2 e (1) e 2 1.6 1.5 1.4 ee 1 k 0.40 0.35 0.30 lv 0.1 w 0.05 y 0.05 y 1 0 1 2 mm scale x c y c y 1 terminal 1 index area b a d e detail x a a 3 a 1 a 2 terminal 1 index area b e 1 e a c b v c w e 2 l k d 2 1 4 5 8 se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 47 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 48 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 42 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 3 3 and 34 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 42 . table 33. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 34. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 49 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 14. abbreviations msl: moisture sensitivity level fig 42. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 35. abbreviations acronym description adc a-to-d converter ara alert response address cdm charged device model cpu central processing unit ddr double data rate dimm dual in-line memory module dram dynamic random access memory eeprom electrically erasable programmable read-only memory esd electrostatic discharge hbm human body model i 2 c-bus inter-integrated circuit bus lsb least significant bit mm machine model msb most significant bit pc personal computer pcb printed-circuit board por power-on reset se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 50 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 15. revision history smbus system management bus so-dimm small outline dual in-line memory module spd serial presence detect table 35. abbreviations ?continued acronym description table 36. revision history document id release date data sheet status change notice supersedes se97b_1 20100127 product data sheet - - se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 51 of 53 nxp semiconductors se97b ddr memory module temp sensor with integrated spd 16. legal information 16.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 16.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 disclaimers general ? information in this document is believed to be accurate and reliable. however, nxp semiconductors d oes not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale ? nxp semiconductors products are sold subject to the general terms and condit ions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writ ing by nxp semiconductors. in case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 16.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 17. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification. se97b_1 ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 27 january 2010 52 of 53 continued >> nxp semiconductors se97b ddr memory module temp sensor with integrated spd 18. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 general features . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 temperature sensor features . . . . . . . . . . . . . . 2 2.3 serial eeprom features . . . . . . . . . . . . . . . . . 3 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 serial bus interface . . . . . . . . . . . . . . . . . . . . . . 6 7.2 slave address . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.3 event output condition . . . . . . . . . . . . . . . . . . 7 7.3.1 event pin output voltage levels and resistor sizing. . . . . . . . . . . . . . . . . . . . . . . 7 7.3.2 event thresholds . . . . . . . . . . . . . . . . . . . . . . 9 7.3.2.1 alarm window . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3.2.2 critical trip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3.3 event operation modes . . . . . . . . . . . . . . . . 10 7.3.3.1 comparator mode. . . . . . . . . . . . . . . . . . . . . . 10 7.3.3.2 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.3.3 switching between comparator mode and interrupt mode . . . . . . . . . . . . . . . . . . . . . 10 7.4 conversion rate . . . . . . . . . . . . . . . . . . . . . . . 11 7.4.1 what temperature is read when conversion is in progress . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.5 power-up default condition . . . . . . . . . . . . . . . 11 7.6 device initialization . . . . . . . . . . . . . . . . . . . . . 11 7.7 smbus timeout . . . . . . . . . . . . . . . . . . . . . . 12 7.8 smbus alert response address (ara) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.9 smbus/i 2 c-bus interface . . . . . . . . . . . . . . . . 13 7.10 eeprom operation . . . . . . . . . . . . . . . . . . . . 15 7.10.1 write operations . . . . . . . . . . . . . . . . . . . . . . . 16 7.10.1.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10.1.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10.1.3 acknowledge polling . . . . . . . . . . . . . . . . . . . . 17 7.10.2 memory protection . . . . . . . . . . . . . . . . . . . . . 17 7.10.2.1 permanent write protec tion (pwp) . . . . . . . . 18 7.10.2.2 reversible write protection (rwp) and clear reversible write protection (crwp) . . 19 7.10.2.3 read permanent write protection (rpwp), read reversible write protection (rrwp), and read clear reversible write protection (rcrwp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.10.3 read operations. . . . . . . . . . . . . . . . . . . . . . . 20 7.10.3.1 current address read . . . . . . . . . . . . . . . . . . . 20 7.10.3.2 selective read . . . . . . . . . . . . . . . . . . . . . . . . 20 7.10.3.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . 21 8 register descriptions . . . . . . . . . . . . . . . . . . . 22 8.1 register overview . . . . . . . . . . . . . . . . . . . . . 22 8.2 cap ? capability register (00h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 23 8.3 config ? configuration register (01h, 16-bit read/write). . . . . . . . . . . . . . . . . . 24 8.4 temperature format . . . . . . . . . . . . . . . . . . . . 28 8.5 temperature trip point regi sters . . . . . . . . . . 29 8.5.1 upper ? upper boundary alarm trip register (02h, 16-bit read/write) . . . . . . . . . . . 29 8.5.2 lower ? lower boundary alarm trip register (03h, 16-bit read/write) . . . . . . . . . . . 30 8.5.3 critical ? critical alarm trip register (04h, 16-bit read/write). . . . . . . . . . . . . . . . . . 30 8.6 temp ? temperature register (05h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 31 8.7 manid ? manufacturer?s id register (06h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 32 8.8 deviceid ? device id register (07h, 16-bit read-only) . . . . . . . . . . . . . . . . . . 32 8.9 smbus ? smbus register (22h, 8-bit read/write). . . . . . . . . . . . . . . . . . . 33 9 application design-in information. . . . . . . . . 35 9.1 se97b in memory module application . . . . . . 36 9.2 layout consideration . . . . . . . . . . . . . . . . . . . 36 9.3 thermal considerations . . . . . . . . . . . . . . . . . 36 9.4 hot plugging. . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 46 13 soldering of smd packages . . . . . . . . . . . . . . 47 13.1 introduction to soldering. . . . . . . . . . . . . . . . . 47 13.2 wave and reflow soldering. . . . . . . . . . . . . . . 47 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 47 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 48 14 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 49 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 50 16 legal information . . . . . . . . . . . . . . . . . . . . . . 51 16.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 51 16.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 16.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 51 16.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 51 nxp semiconductors se97b ddr memory module temp sensor with integrated spd ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 27 january 2010 document identifier: se97b_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17 contact information. . . . . . . . . . . . . . . . . . . . . 51 18 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 |
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