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mr0a08b 128k x 8 mram features ? 3.3 volt power supply ? fast 35 ns read/write cycle ? sram compatible timing ? native non-volatility ? unlimited read & write endurance ? data always non-volatile for >20-years at temperature ? commercial and industrial temperatures ? rohs-compliant tsopii, bga and soic packages benefits ? one memory replaces flash, sram, eeprom and bbsram in system for simpler, more efcient design ? improves reliability by replacing battery-backed sram introduction the mr0a08b is a 1,048,576-bit magnetoresistive random access memory (mram) device organized as 131,072 words of 8 bits. the mr0a08b ofers sram compatible 35 ns read/write timing with unlimited endurance. data is always non-volatile for greater than 20-years. data is auto - matically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specifcation. the mr0a08b is the ideal memory solution for applica- tions that must permanently store and retrieve critical data and programs quickly. the mr0a08b is available in small footprint 400-mil, 44-lead plastic small-outline tsop type-ii package, 8 mm x 8 mm, 48-pin ball grid array (bga) package with 0.75 mm ball centers or a 32-lead soic package. these packages are compatible with similar low-power sram products and other non-volatile ram prod- ucts. the mr0a08b provides highly reliable data storage over a wide range of temperatures. the product is of- fered with commercial temperature (0 to +70 c) and industrial temperature (-40 to +85 c). document number: mr0a08b rev. 4, 8/2011 1 rohs contents 1. device pin assignment......................................................................... 2 2. electrical specifications................................................................. 4 3. timing specifications.......................................................................... 7 4. ordering information....................................................................... 12 5. mechanical drawing.......................................................................... 13 6. revision history...................................................................................... 16 how to reach us.......................................................................................... 16 everspin technologies ? 2011
document number: mr0a08b rev. 4, 8/2011 2 chip enable buffer output enable buffer address buffer write enable buffer g e 17 output enable 128k x 8 bit memory array row decoder column decoder sense amps output buffer write driver final write drivers write enable w a[16:0] 10 7 8 8 8 8 8 8 dq[7:0] 1. device pin assignment figure 1.1 block diagram table 1.1 pin functions signal name function a address input e chip enable w write enable g output enable dq data i/o v dd power supply v ss ground dc do not connect nc no connection everspin technologies ? 2011
a a a a dq0 dq1 v dd e v ss dq2 dq3 w a a a dc a dc 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 dc nc nc nc dc a g dq7 dq6 v ss a v dd dq5 dq4 dc a a a a a dc dc a a dc nc 1 2 3 4 5 6 g a 0 a 1 a 2 a a 3 a 5 a 4 e b a 6 c v dd v dd d dc nc a 14 v ss v ss e a 12 a 13 dq 7 dq 2 dq 3 dq 1 dq 0 dq 4 dq 5 dq 6 f nc nc a 10 a 11 w g nc nc a 7 a 9 nc h nc nc nc nc nc dc dc dc dc a 16 a 15 a 8 document number: mr0a08b rev. 4, 8/2011 figure 1.2 pin diagrams for available packages (top view) 44 pin tsop ii 32 pin soic 48 pin fbga table 1.2 operating modes e 1 g 1 w 1 mode v dd current dq[7:0] 2 h not selected i sb1 , i sb2 hi-z l h h output disabled i hi-z l l h byte read i out l l byte write i ddw in 1 h = high, l = low, x = dont care 2 hi-z = high impedance device pin assignment mr0a08b everspin technologies ? 2011 1 dc 2 a 16 3 a 14 4 a 12 5 a 7 6 a 6 7 a 5 8 a 4 9 a 3 10 a 2 11 a 1 12 a 0 13 dq 0 14 dq 1 v dd a 15 a 13 a 8 a 9 a 11 nc a 10 e dq 7 dq 6 dq 5 dq 4 dq 3 15 dq 2 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 v ss w g
2. electrical specifications absolute maximum ratings this device contains circuitry to protect the inputs against damage caused by high static voltages or electric felds; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (hi-z) circuits. the device also contains protection against external magnetic felds. precautions should be taken to avoid application of any magnetic feld more intense than the maximum feld intensity specifed in the maximum ratings. document number: mr0a08b rev. 4, 8/2011 4 parameter symbol value unit supply voltage 2 v dd -0.5 to 4.0 v voltage on any pin 2 v in -0.5 to v dd + 0.5 v output current per pin i out 20 ma package power dissipation p d 0.600 w temperature under bias mr0a08b (commercial) mr0a08bc (industrial) t bias -10 to 85 -45 to 95 c storage temperature t stg -55 to 150 c lead temperature during solder (3 minute max) t lead 260 c maximum magnetic feld during write mr0a08b (all temperatures) h max_write 2000 a/m maximum magnetic feld during read or standby h max_read 8000 a/m 1 permanent device damage may occur if absolute maximum ratings are exceeded. functional opera- tion should be restricted to recommended operating conditions. exposure to excessive voltages or magnetic felds could afect device reliability. 2 all voltages are referenced to v ss . 3 power dissipation capability depends on package characteristics and use environment. table 2.1 absolute maximum ratings 1 mr0a08b everspin technologies ? 2011
document number: mr0a08b rev. 4, 8/2011 5 parameter symbol min typical max unit power supply voltage v dd 3.0 i 3.3 3.6 v write inhibit voltage v wi 2.5 2.7 3.0 i v input high voltage v ih 2.2 - v dd + 0.3 ii v input low voltage v il -0.5 iii - 0.8 v temperature under bias mr0a08b (commercial) mr0a08bc (industrial) t a 0 -40 70 85 c i there is a 2 ms startup time once v dd exceeds v dd, (max). see below. ii v ih (max) = v dd + 0.3 v dc ; v ih (max) = v dd + 2.0 v ac (pulse width 10 ns) for i 20.0 ma. iii v il (min) = -0.5 v dc ; v il (min) = -2.0 v ac (pulse width 10 ns) for i 20.0 ma. table 2.2 operating conditions power up and power down sequencing mram is protected from write operations whenever v dd is less than v wi . as soon as v dd exceeds v dd (min), there is a startup time of 2 ms before read or write operations can start. this time allows memory power supplies to stabilize. the e and w control signals should track v dd on power up to v dd - 0.2 v or v ih (whichever is lower) and remain high for the startup time. in most systems, this means that these signals should be pulled up with a resis- tor so that signal remains high if the driving signal is hi-z during power up. any logic that drives e and w should hold the signals high with a power-on reset signal for longer than the startup time. during power loss or brownout where v dd goes below v wi , writes are protected and a startup time must be observed when power returns above v dd (min). brownout or power loss normal operation normal operation startup time startup time v dd v dd writes inhibited w e v dd,min v wi figure 2.1 power up and power down diagram mr0a08b electrical specifcations everspin technologies ? 2011
document number: mr0a08b rev. 4, 8/2011 6 parameter symbol min typical max unit input leakage current i lkg(i) - - 1 a output leakage current i lkg(o) - - 1 a output low voltage (i ol = +4 ma) (i ol = +100 a) v ol - - 0.4 v ss + 0.2 v output high voltage (i ol = -4 ma) (i ol = -100 a) v oh 2.4 v dd - 0.2 - - v table 2.3 dc characteristics table 2.4 power supply characteristics parameter symbol typical max unit ac active supply current - read modes 1 (i out = 0 ma, v dd = max) i ddr 25 30 ma ac active supply current - write modes 1 (v dd = max) mr0a08b (commercial) mr0a08bc (industrial) i ddw 55 55 65 70 ma ac standby current (v dd = max, e = v ih ) i sb1 6 7 ma cmos standby current (e v dd - 0.2 v and v in v ss + 0.2 v or v dd - 0.2 v) (v dd = max, f = 0 mhz) i sb2 5 6 ma 1 all active current measurements are measured with one address transition per cycle and at minimum cycle time. mr0a08b electrical specifcations everspin technologies ? 2011
document number: mr0a08brev. 4, 8/2011 7 mr0a08b 3. timing specifications table 3.1 capacitance 1 parameter symbol typical max unit address input capacitance c in - 6 pf control input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf 1 f = 1.0 mhz, dv = 3.0 v, t a = 25 c, periodically sampled rather than 100% tested. table 3.2 ac measurement conditions figure 3.1 output load test low and high figure 3.2 output load test all others parameter value unit logic input timing measurement reference level 1.5 v logic output timing measurement reference level 1.5 v logic input pulse levels 0 or 3.0 v input rise/fall time 2 ns output load for low and high impedance parameters see figure 3.1 output load for all other timing parameters see figure 3.2 v output l = 1.5 v r l = 50 z d = 50 output 435 590 5 pf 3.3 v everspin technologies ? 2011
mr0a08b timing specifcations document number: mr0a08b rev. 4, 8/2011 8 parameter symbol min max unit read cycle time t avav 35 - ns address access time t avqv - 35 ns enable access time 2 t elqv - 35 ns output enable access time t glqv - 15 ns output hold from address change t axqx 3 - ns enable low to output active 3 t elqx 3 - ns output enable low to output active 3 t glqx 0 - ns enable high to output hi-z 3 t ehqz 0 15 ns output enable high to output hi-z 3 t ghqz 0 10 ns 1 w is high for read cycle. power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. 2 addresses valid before or at the same time e goes low. 3 this parameter is sampled and not 100% tested. transition is measured 200 mv from the steady-state voltage. table 3.3 read cycle timing 1 read mode figure 3.3a read cycle 1 figure 3.3b read cycle 2 a (address) q (data out) t avav t axqx t avqv previous data valid note: device is continuously selected (ev il , gv il ). data valid a (address) e (chip enable) g (output enable) q (data out) data valid t avav t avqv t elqv t elqx t ghqz t ehqz t glqv t glqx everspin technologies ? 2011
mr0a08b timing specifcations document number: mr0a08b rev. 4, 8/2011 9 table 3.4 write cycle timing 1 ( w controlled) 1 parameter symbol min max unit write cycle time 2 t avav 35 - ns address set-up time t avwl 0 - ns address valid to end of write ( g high) t avwh 18 - ns address valid to end of write ( g low) t avwh 20 - ns write pulse width ( g high) t wlwh t wleh 15 - ns write pulse width ( g low) t wlwh t wleh 15 - ns data valid to end of write t dvwh 10 - ns data hold time t whdx 0 - ns write low to data hi-z 3 t wlqz 0 12 ns write high to output active 3 t whqx 3 - ns write recovery time t whax 12 - ns 1 all write occurs during the overlap of e low and w low. power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. if g goes low at the same time or after w goes low, the output will remain in a high impedance state. after w or e has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. the minimum time between e being asserted low in one cycle to e being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 all write cycle timings are referenced from the last valid address to the frst transition address. 3 this parameter is sampled and not 100% tested. transition is measured 200 mv from the steady-state voltage. at any given voltage or temperate, t wlqz (max) < t whqx (min) w ( w r i te e n ab l e ) a ( addr e s s ) e (ch i p e n ab l e ) t a v a v t a v w h t w ha x t a v w l t w l e h t w l w h d a t a val i d t d v w h t w hd x q ( d at a out ) d ( d at a in) t w l qz t w hqx h i - z h i - z figure 3.4 write cycle timing 1 ( w controlled) everspin technologies ? 2011
mr0a08b timing specifcations everspin technologies ? 2011 document number: mr0a08b rev. 4, 8/2011 10 table 3.5 write cycle timing 2 ( e controlled) 1 figure 3.5 write cycle timing 2 ( e controlled) parameter symbol min max unit write cycle time 2 t avav 35 - ns address set-up time t avel 0 - ns address valid to end of write ( g high) t aveh 18 - ns address valid to end of write ( g low) t aveh 20 - ns enable to end of write ( g high) t eleh t elwh 15 - ns enable to end of write ( g low) 3 t eleh t elwh 15 - ns data valid to end of write t dveh 10 - ns data hold time t ehdx 0 - ns write recovery time t ehax 12 - ns 1 all write occurs during the overlap of e low and w low. power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. if g goes low at the same time or after w goes low, the output will remain in a high impedance state. after w or e has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. the minimum time between e being asserted low in one cycle to e being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 all write cycle timings are referenced from the last valid address to the frst transition address. 3 if e goes low at the same time or after w goes low, the output will remain in a high-impedance state. if e goes high at the same time or before w goes high, the output will remain in a high-impedance state. a (address) e (chip enable) w (write enable) q (data out) d (data in) t avav t aveh t avel t ehax t ehdx t dveh hi-z data valid t eleh t elwh
mr0a08b timing specifcations document number: mr0a08b rev. 4, 8/2011 11 table 3.6 write cycle timing 3 (shortened t whax , w and e controlled) 1 table 3.6 write cycle timing 3 (shortened t whax , w and e controlled) parameter symbol min max unit write cycle time 2 t avav 35 - ns address set-up time t avwl 0 - ns address valid to end of write ( g high) t avwh 18 - ns address valid to end of write ( g low) t avwh 20 - ns write pulse width t wlwh t wleh 15 - ns data valid to end of write t dvwh 10 - ns data hold time t whdx 0 - ns enable recovery time t ehax -2 - ns write recovery time 3 t whax 6 - ns write to enable recovery time 3 t whel 12 - ns 1 all write occurs during the overlap of e low and w low. power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. if g goes low at the same time or after w goes low, the output will remain in a high impedance state. after w , or e has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. the minimum time between e being asserted low in one cycle to e being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. 2 all write cycle timings are referenced from the last valid address to the frst transition address. 3 if e goes low at the same time or after w goes low the output will remain in a high impedance state. if e goes high at the same time or before w goes high the output will remain in a high impedance state. e must be brought high each cycle. t a v w l t a v a v t a v w h t w l w h t w l e h t d v w h t w h d x t w h a x t t e h a x w h e l w (write enable) a (address) e (chip enable) d (data in) everspin technologies ? 2011
document number: mr0a08b rev. 4, 8/2011 12 mr0a08b 4. ordering information figure 4.1 part numbering system part number description temperature mr0a08bys35 3.3 v 128kx8 mram 44-tsop commercial mr0a08bcys35 3.3 v 128kx8 mram 44-tsop industrial MR0A08BYS35R 3.3 v 128kx8 mram 44-tsop t&r commercial mr0a08bcys35r 3.3 v 128kx8 mram 44-tsop t&r industrial mr0a08bma35 3.3 v 128kx8 mram 48-bga commercial mr0a08bcma35 3.3 v 128kx8 mram 48-bga industrial mr0a08bma35r 3.3 v 128kx8 mram 48-bga t&r commercial mr0a08bcma35r 3.3 v 128kx8 mram 48-bga t&r industrial mr0a08bso35 3.3 v 128kx8 mram 32-soic commercial mr0a08bso35r 3.3 v 128kx8 mram 32-soic t&r commercial table 4.1 available parts everspin technologies ? 2011 carrier blank = tray, r = tape & reel speed 35 ns package ys = tsopii, ma = fbga, so=soic temperature range blank= 0 to +70 c, c= -40 to +85 c revision data width 08 = 8-bit type a = asynchronous density 0 = 1mb magnetoresistive ram mr mr 0 a 08 b c ys 35 r
document number: mr0a08b rev. 4, 8/2011 13 figure 5.1 tsop-ii mr0a08b 5. mechanical drawing print version not to scale 1. dimensions and tolerances per asme y14.5m - 1994. 2. dimensions in millimeters. 3. dimensions do not include mold protrusion. 4. dimension does not include dam bar protrusions. dam bar protrusion shall not cause the lead width to exceed 0.58. everspin technologies ? 2011
document number: mr0a08b rev. 4, 8/2011 14 top view bottom view side view figure 5.2 fbga print version not to scale 1. dimensions in millimeters. 2. dimensions and tolerances per asme y14.5m - 1994. 3. maximum solder ball diameter measured parallel to datum a 4. datum a, the seating plane is determined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any efect of mark on top surface of package. mr0a08b mechanical drawings everspin technologies ? 2009
document number: mr0a08b rev. 4, 8/2011 15 mr0a08b mechanical drawings everspin technologies ? 2011 figure 5.3 soic unit a b c d e f g h i j k mm - min - max 20.574 20.878 1.00 1.50 0.355 0.508 0.66 0.81 0.101 0.254 2.286 2.540 radius 0.101 0.533 1.041 0.152 0.304 7.416 7.594 10.287 10.642 inch - min - max 0.810 0.822 0.04 0.06 0.14 0.02 0.026 0.032 0.004 0.010 0.09 0.10 radius 0.0040 0.021 0.041 0.006 0.012 0.292 0.299 0.405 0.419 1 16 32 17 pin 1 id a b c d e f g h j k i reference jedec mo-119 print version not to scale
mr0a08b document number: mr0a08b rev. 4, 8/2011 16 revision date description of change 0 sep 12, 2008 initial advance information release 1 may 8, 2009 revised format; add table 3.6 write timing cycle 3; add figure 3.6 write tim - ing cycle 3; add tsopii lead width info; changed to preliminary from prod- uct concept. 2 june 18, 2009 changed from datasheet from preliminary to production except where noted. 3 apr 12, 2011 added soic package option. 4 august 15, 2011 corrected soic pin 1 to read dc. updated contact information. revised copyright year. 6. revision history information in this document is provided solely to enable system and sof tware implementers to use everspin technologies products. there are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. everspin technolo - gies reserves the right to make changes without further notice to any products herein. everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does everspin technologies assume any liability arising out of the application or use of any product or circuit, and specifcally disclaims any and all liability, including without limitation consequential or inci - dental damages. typical parameters, which may be provided in everspin technologies data sheets and/ or specifcations can and do vary in diferent applications and actual performance may vary over time. all operating parameters including typicals must be validated for each customer application by customers technical experts. everspin technologies does not convey any license under its patent rights nor the rights of others. everspin technologies products are not designed, intended, or authorized for use as compo - nents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the everspin technologies product could create a situation where personal injury or death may occur. should buyer purchase or use everspin technologies products for any such unintended or unauthorized application, buyer shall indemnify and hold everspin technologies and its ofcers, employees, subsidiaries, afliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that everspin technologies was negligent regarding the design or manufacture of the part. everspin? and the everspin logo are trademarks of everspin technologies, inc. all other product or service names are the property of their respective owners. ?everspin technologies, inc. 2009 unless otherwise noted, this is a production product - this product conforms to specifcations per the terms of the everspin standard warranty. the product has completed everspin internal qualifcation testing and has reached production status. how to reach us: home page: www.everspin.com e-mail: support@everspin.com orders@everspin.com sales@everspin.com usa/canada/south and central america everspin technologies 1347 n. alma school road, suite 220 chandler, arizona 85224 +1-877-347-mram (6726) +1-480-347-1111 europe, middle east and africa support.europe@everspin.com japan support.japan@everspin.com asia pacifc support.asia@everspin.com document control number: est00183 file name: mr0a08b_datasheet_est183_rev4.pdf everspin technologies ? 2011

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