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key features ? variable input clock frequency ? two 16c550 uart interfaces ? up to 10 bits general purpose io ? i 2 c interface ? usb 2.0 full-speed compliant interface ? jtag debug & test interface ? capability for embedded solutions ? external fexible flash sizes, 2C16 mbit ? point to multipoint, 7 slaves ? power management, park, sniff & hold ? qualifed for bluetooth spec. 1.1 description the bluetooth baseband pbm 990 90 from ericsson microelectronics is a generic baseband controller designed to be suitable for both host and embedded applications. the baseband controller will together with a radio module and a flash memory form a complete bluetooth system. as the pbm 990 90 is a generic product, it can be used for many different types of applications that require bluetooth capability such as: ? data and voice access points ? cable replacement ? ad hoc networking the pbm 990 90 is based on the scalable ericsson bluetooth core (ebc) architecture. the system controller is an embedded arm7 tdmi? microprocessor communicating with the ebc and peripheral interfaces over an amba? system bus. this confguration allows for embedded stand-alone bluetooth applications where your target application is embedded within the baseband controller, in addition to traditional host-based applications. this possibility is especially useful in accessory type applications like cordless headsets, industrial sensor and actuator devices. providing a wide range of external interfaces like usb, i 2 c, gpio, pcm and a pair of uarts, the pbm 990 90 is ideally suited for access applications in desktop and mobile computing environments, home base stations, and hot spot network access points. pbm 990 90 bluetooth? baseband controller
pbm 990 90 2 block diagram figure 1. block diagram. xi n s y st em c o nt ro ll er , ti m e rs , w a tc hdog n r e set ne x t cs 0 ne x t cs 1 ne x t cs 2 ne x t w r ne x t rd e x t a d d r 0 .. 19 e x t d a t a 0 .. 15 ua rt1 lp o x in testen ntrs t tck tm s tdi tdo n s y s w a k u p txo n txc lk txd a t a r x o n r x d a t a sy n t o n px o n ph do f f cdc lk cm s cdi cdo pc mc lk pc ms yn c pc ma pc mb e x te r nal b u s i/ f u s b u a r t 1 r t s ua rt1 d t r ua rt1 d s r u a r t 1 ct s ua rt1 r x u a r t 1 t x ua rt2 r x u a r t 2 t x a r m 7 tdm i p l l 64kb yt e s r a m 4kb yt e ro m ua rt2 c l oc k di vi de rs st ar t de te ct & a u t oba ud in te rru pt c o nt ro ll er d ebu g & t e st i/ f mi sc. c o nt ro l u a r t 1r i_ u s b d m ua r t 1d cd _ u s b d p s e r i a l c l k s e r i a l d a t a e r i css on bl uet oot h c o re ph y g p io (i 2 c) u s b v t _ e b c w a k u p s y s c l k r e q
pbm 990 90 3 absolute maximum ratings parameter condition symbol min typ max unit i/o supply range, all groups v ddio -0.3 +3.6 v core supply range v ddcore -0.3 +2.8 v input voltage range v i -0.3 v ddio +0.3 v output voltage range v o -0.3 v ddio +0.3 v input clamp current v o < v ssio or v i > v ddio i ic -20 +20 ma output clamp current v o < v ssio or v i > v ddio i oc -20 +20 ma operating ambient temperature range t amb -40 +85 c storage temperature t stg -40 +125 c characteristic data static data unless otherwise stated: v ddcore & v ddio = 2.5v ;v ss = 0 v ; t amb = -40..+85c parameter condition symbol min typ max unit supply voltage core & pll 1) v ddcore 2.3 2.5 2.7 v supply voltage io group 1 v ddio1 v ddcore 1) 2.5 3.6 v supply voltage io group 2 v ddio2 v ddcore 1) 3.3 3.6 v supply voltage io group 3 v ddio3 v ddcore 1) 2.5 3.6 v supply voltage io group 4 v ddio4 v ddcore 1) 2.5 3.6 v supply current i dd tbd ma low level input voltage, digital input guaranteed input low v il v ssio C 0.3 0.3 v ddio v high level input voltage, digital input guaranteed input high v ih 0.7 v ddio v ddio +0.3 v schmitt trigger input min hysteresis = 0.49 v t + 1.42 1.45 1.46 v schmitt trigger input min hysteresis = 0.49 v t - 0.92 0.94 0.97 v input leakage current v i = v ssio i li -1 +1 a v i = v ddio low level output voltage i ol =800 a v ol 0 v ssio +0.1 v high level output voltage i oh =-800 a v oh v ddio -0.1 v ddio v output leakage current, tri-state v o = v ssio i ot -10 +10 a v o = v ddio notes on static data: 1) if the core voltage is greater than either of the i/o voltages by about 0.5 v or more, then pbm 990 90 will not work. this is because the inputs to the core from the pads will not be suffciently high level to drive the core gates. the level shifter between core and i/o is only designed to shift from low core to a high i/o. 2) if the core voltage is off, but the the i/o voltage is left on, then this will cause pbm 990 90 to drive out a logic low on all output pins. for example nextwr, nextrd, extdata and all three nextcs signals will be driven low which will result in a bidirectional clash on the databus if several external units are driving the bus. 3) all pbm 990 90 i/o pins can be connected to any external driving bus of max 3.6 v before turning on the supply, without the chip being damaged. however it cannot be guaranteed that pbm 990 90 does not load the external bus in this case, unless the core supply voltage is completely discharged prior to this event.
pbm 990 90 4 dynamic data requirements on all input pins conditions: rise and fall times are measured between 10% to 90% of the vddio level. type symbol parameter min max unit all input pins tr rise time 10 ns tr fall time 10 ns requirements on xin pin input frequency symbol parameter min max unit without using the pll:12.40 mhz facc frequency accuracy -20 +20 ppm tj jitter tbd tbd ns tdc duty cycle tbd tbd % using the pll: facc frequency accuracy -20 +20 ppm example frequencies: tj jitter tbd tbd ns 12.60, 12.80, 13.00, 14.40, 16.80, 19.20, or tdc duty cycle tbd tbd % 19.44 mhz requirements on lpoxin pin input frequency symbol parameter min max unit 3.200 khz facc frequency accuracy 250 ppm tj jitter tbd tdb s tdc duty cycle tbd tbd % 32.000 khz facc frequency accuracy 250 ppm tj jitter tbd tbd s tdc duty cycle tbd tbd % 32.768 khz facc frequency accuracy 50 ppm tj jitter tbd tbd s tdc duty cycle tbd tbd % digital output pins characteristics conditions: t amb = -40 .. +85 c, c load = 25 pf, v ddcore = 2.3 v .. 2.7v, v ddio = 2.3 .. 3.3 v rise and fall times are measured between 10 % to 90 % of the vddio level. type symbol parameter min max unit all digital output and bi-directional output tr rise time 3.5 10.0 ns pins (3x drive, 6 ma) tf fall time 3.5 10.0 ns usb transceiver pins characteristics conditions: t amb = -40 .. +85 c, c load = 50 pf, v ddcore = 2.3 v .. 2.7 v, v ddio2 = 3.3 v symbol parameter min typ max unit tr, tf transition rise or fall time 4 10 20 ns tr/tf transition rise/fall time ratio 0.9 1.0 1.1 v cr cross-over voltage 1.3 2.0 v z drv driver output resistance (see note) 16 28 ? note: excluding external resistor. in order to comply with usb specifcation, external resistors of 14 ? 5 % on each of the d+ and d- branches are recommended.
pbm 990 90 5 pll characteristics to generate higher internal clock frequencies from the input clock xin an on-chip pll is included in pbm 990 90. the pll can be adapted to different input frequencies by programmable registers. register values for the following common crystal frequencies have been defned: 12.60, 12.80, 13.00, 14.40, 16.80, 19.20 and 19.44 mhz. the pll is fed by an internal current reference block, iref, which can be disabled when the pll is not used in order to save power. the start-up time of the pll is dependent on whether the iref is enabled prior to start of the pll or not. symbol parameter min typ max unit f in input frequency 13.00 mhz t st1 start-up time, iref enabled before start 100 s t st2 start-up time, iref disabled before start 140 s connection figure 2. pin confguration (top view, balls face down). 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 a ext da ta 1 ext da ta 0 n ext rd ext a ddr 0 n ext cs 0 ext da ta 6 ext a ddr 16 v ddi o1 vd d co re ua rt 2 rx nre se t pc ma pc mb pc m clk b ext data 10 ext da ta 9 ext da ta 8 ext da ta 3 ext da ta 11 vssi o3 xi n vss co re ua rt 2 tx vssi o1 u sbvt _ ebc waku p pc m syn c ua rt 1 rts ua rt 1 dtr c ext data 4 ext da ta 2 ua rt 1 ds r ua rt 1 cts d v ddi o 3 vssi o3 vssi o2 v ddi o2 e ext da ta 13 ext data 12 ua rt 1 rx ua rt 1 tx f ext da ta 7 ext data 15 ua rt 1 ri _ u sbd m ua rt 1 dc d_ u sbd p g ext a ddr 15 ext a ddr 9 h ext a ddr 14 ext da ta 14 j ext a ddr 13 ext a ddr 17 k v ddi o3 vssi o3 l ext a ddr 11 ext a ddr 6 m ext a ddr 8 ext a ddr 3 n ne xt wr ext a ddr 1 ext a ddr 2 ext a ddr 5 ext da ta 5 ext a ddr 12 n ext cs 1 vss co re p ext a ddr 19 ext a ddr 7 ext a ddr 4 ext a ddr 18 ext a ddr 10 vd d co re n ext cs 2 core suppl y pins i/ o gr oup 1 pins i/ o gr oup 2 pins i/ o gr oup 3 pins i/ o gr oup 4 pins
pbm 990 90 6 pin description pin no. pin name io pad type reset io functional description direction state group input clock interface (1 pin) b7 xin i di 1 system input clock (square wave) system controller interface (4 pins) a11 nreset i dis 1 system reset (active low) k14 lpoxin ai ana 4 low power operation clock (square wave) p8 nsyswakup i di 4 system external wakeup (active low) l14 sysclkreq o do3t h 4 system clock request (tri-stateable) usb vterm & ebc wakeup interface (1 pin) b11 usbvt_ebcwakup i/o bd3 z 2 usb vterm or ebc wakeup external bus interface (41 pins) a5 nextcs0 o do3 h 3 external bus chip select 0 n7 nextcs1 o do3 h 3 external bus chip select 1 p7 nextcs2 o do3 h 3 external bus chip select 2 a3 nextrd o do3 h 3 external bus read strobe n1 nextwr o do3 h 3 external bus write strobe a4 extaddr0 i/o bd3 l 3 external bus address line 0 n2 extaddr1 i/o bd3 l 3 external bus address line 1 n3 extaddr2 i/o bd3 l 3 external bus address line 2 m2 extaddr3 i/o bd3 l 3 external bus address line 3 p3 extaddr4 i/o bd3 l 3 external bus address line 4 n4 extaddr5 i/o bd3 l 3 external bus address line 5 l2 extaddr6 i/o bd3 l 3 external bus address line 6 p2 extaddr7 i/o bd3 l 3 external bus address line 7 m1 extaddr8 i/o bd3 l 3 external bus address line 8 g2 extaddr9 i/o bd3 l 3 external bus address line 9 p5 extaddr10 i/o bd3 l 3 external bus address line 10 l1 extaddr11 i/o bd3 l 3 external bus address line 11 n6 extaddr12 i/o bd3 l 3 external bus address line 12 j1 extaddr13 i/o bd3 l 3 external bus address line 13 h1 extaddr14 i/o bd3 l 3 external bus address line 14 g1 extaddr15 i/o bd3 l 3 external bus address line 15 a7 extaddr16 i/o bd3 l 3 external bus address line 16 j2 extaddr17 i/o bd3 l 3 external bus address line 17 p4 extaddr18 o do3 l 3 external bus address line 18 p1 extaddr19 o do3 l 3 external bus address line 19 a2 extdata0 i/o bd3 l 3 external bus data line 0 a1 extdata1 i/o bd3 l 3 external bus data line 1 c2 extdata2 i/o bd3 l 3 external bus data line 2 b4 extdata3 i/o bd3 l 3 external bus data line 3 c1 extdata4 i/o bd3 l 3 external bus data line 4 n5 extdata5 i/o bd3 l 3 external bus data line 5 a6 extdata6 i/o bd3 l 3 external bus data line 6 f1 extdata7 i/o bd3 l 3 external bus data line 7 b3 extdata8 i/o bd3 l 3 external bus data line 8 or gpiob0 b2 extdata9 i/o bd3 l 3 external bus data line 9 or gpiob1
pbm 990 90 7 pin no. pin name io pad type reset io functional description direction state group b1 extdata10 i/o bd3 l 3 external bus data line 10 or gpioa2 b5 extdata11 i/o bd3 l 3 external bus data line 11 or gpioa3 e2 extdata12 i/o bd3 l 3 external bus data line 12 or gpioa4 e1 extdata13 i/o bd3 l 3 external bus data line 13 or gpioa5 h2 extdata14 i/o bd3 l 3 external bus data line 14 or gpioa6 f2 extdata15 i/o bd3 l 3 external bus data line 15 or gpioa7 i 2 c interface (2 pins) n9 serialclk i/o bd3 i 4 i2c serial clock (gpioa0) p9 serialdata i/o bd3 i 4 i2c serial data (gpioa1) pcm interface (4 pins) a12 pcma i/o bd3 i 2 pcm digital serial audio channel a a13 pcmb i/o bd3 i 2 pcm digital serial audio channel b a14 pcmclk i/o bd3 i 2 pcm digital serial audio clock b12 pcmsync i/o bd3 i 2 pcm digital serial audio sync pulse radio interface (12 pins) m13 txclk i di 4 radio transmit data clock, 1 mhz g14 txdata o do3 x 4 radio transmit data m14 txon o do3 l 4 radio transmitter on g13 phdoff o do3 l 4 radio phase detector loop off l13 pxon o do3 l 4 radio packet on h13 synton o do3 l 4 radio synthesizer on n13 rxdata i di 4 radio receive data n14 rxon o do3 l 4 radio receiver on h14 cdclk o do3 h 4 radio serial control clock k13 cdi i di 4 radio serial control data input j14 cdo o do3 l 4 radio serial control data output j13 cms o do3 l 4 radio serial control mode select uart1 & usb interface (8 pins) c14 uart1cts i di 2 uart1 clear to send c13 uart1dsr i di 2 uart1 data set ready b14 uart1dtr o do3 h 2 uart1 data terminal ready b13 uart1rts o do3 h 2 uart1 request to send e13 uart1rx i di 2 uart1 receive data e14 uart1tx o do3 h 2 uart1 transmit data f14 uart1dcd_usb i/o bd3, phy i 2 uart1dcd or usbdp dp f13 uart1ri_usbdm i/o bd3, phy i 2 uart1ri or usbdm uart2 interface (2 pins) a10 uart2rx i di 1 uart2 receive data b9 uart2tx o do3 h 1 uart2 transmit data
pbm 990 90 8 pin no. pin name io pad type reset io functional description direction state group debug & test interface (6 pins) n11 testen i did 4 test enable (pull-down, active high) n12 tck i diu 4 jtag clock (pull-up) p13 tdi i diu 4 jtag data in (pull-up) p14 tdo o do3t z 4 jtag data out p12 tms i diu 4 jtag mode select (pull-up) p11 ntrst i did 4 jtag reset (pull-down) power (15 pins) a9 vddcore cp, ana core & pll vdd supply p6 vddcore cp core vdd supply a8 vddio1 iop 1 io1 group vdd supply d14 vddio2 iop 2 io2 group vdd supply k1 vddio3 iop 3 io3 group vdd supply d1 vddio3 iop 3 io3 group vdd supply p10 vddio4 iop 4 io4 group vdd supply b8 vsscore gnd, ana core & pll ground n8 vsscore gnd core ground b10 vssio1 gnd 1 io1 group ground d13 vssio2 gnd 2 io2 group ground k2 vssio3 gnd 3 io3 group ground d2 vssio3 gnd 3 io3 group ground b6 vssio3 gnd 3 io3 group ground n10 vssio4 gnd 4 io4 group ground notes on the pin description: io direction: i = input, o = output, i/o = bi-directional, ai = analog input reset state: h = high, l = low, z = tri-state, x = high or low pad types: di = input pad diu = input pad with pull-up (resistor: min 30 k ? , typ 50 k ? , max 80 k ? ) did = input pad with pull-down (resistor: min 10 k ? , typ 20 k ? , max 30 k ? ) dis = schmitt trigger input pad ana = analog pad do3 = 3x drive, 6 ma output pad do3t = tri-stateable 3x drive, 6 ma output pad bd3 = 3x drive, 6 ma bi-directional output pad cp = core vdd power supply pad iop = i/o vdd power supply pad gnd = vss power supply pad phy = usb transceiver pad shared with uart1 ri and dcd pins. other information: all pins which are defned as inputs in the application and are not connected to any driving external circuit must be pulled to either vddio or vss i.e. must not be foating. the only pins that have on-chip pull resistors are the debug & test interface input pins. all pin names that start with an n are active low.
pbm 990 90 9 mechanical description, 96 pin bga package figure 3. mechanical drawing. 0. 50 ty p 0. 75 ty p 0. 85 0. 10 ball pad a1 corner indicator (no solder ball) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 bot to m vi ew p n m l k j h g f e d c b a to p v i ew a1 ba ll pa d co rn er 0. 75 ty p 8. 00 0. 05 8. 00 0. 05 se a tin g plan e 0. 22 0. 06 0. 08 5 ? 1. 0 ba ll a1 in di ca to r 7 0. 50 ty p y x z 0. 65 0. 04 5 ? 0. 3 20 0. 05 0 0. 08 (4 x ) 0. 12 z 0. 10 z sea ti ng pl an e 96 pin bga mechanical drawing no te s 1. the maximum allowable number of solder balls is 96. 2 the maximum solder ball matrix size is 14 x 14. . 3. the basic solder ball grid pitch is 0.50mm. 4. all dimensions & tolerances conform to asme y14.5m-1994. unless otherwise stated. . 7 6 5 dimension is measured at the maximum solder ball diameter, parallel to primary datum z. primary datum z & seating plane are defined by the spherical crowns of the solder balls. a1 ball pad corner i.d. to be marked by laser. m ? 0. 15 ? 0. 08 z z x y 6 m
pbm 990 90 10 functional description overview the purpose of this section is to give a brief description of the features and functions in the pbm 990 90 product and how it can work in a system. see fgure 4. pbm 990 90 is a one-chip solution, packaged into a 96 pin bga package, 8 8 mm footprint with 0.50 mm pin pitch and 0.85 mm building height. pbm 990 90 handles the baseband functionality in a bluetooth radio link, i.e. the digital controller logic. the baseband functionality is partitioned in one hardware and one software part. the software part is executed by an on-chip microprocessor arm7 tdmi. to increase the ease of use, standard interfaces like usb 2.0 full-speed, uarts, pcm and i 2 c are integrated on the chip. the pbm 990 90 philosophy is to provide a scalable solution with a high level of fexibility. the goal is to offer a solution that can be easily added to an existing system thus enabling bluetooth capabilities. the solution offers designers: ? power versus performance trade-offs ? reduced need for external components (oscs, usb phy etc) to save power, all interfaces can individually be turned off and the processor speed can be adapted to produce a suitable capacity depending on what application is running. the radio part requires a crystal or a clock frequency with 20 ppm accuracy. the pbm 990 90 is designed to be fexible in this matter and can re-use a square clock signal for a wide spectrum of frequencies depending on the kind of reference signal used by the radio. the pbm 990 90 software is also able to offer fexibility in the choice of brand and size for the flash memory. architecture the bluetooth functionality is based on both hardware and software, forming an embedded system design targeting both fexibility and scalability. the system architecture is based around an arm7 tdmi processor, executing the bluetooth stack drivers, and a hardware block: ericsson bluetooth core supporting bluetooth standard 1.1. the supported interfaces: usb 2.0 full-speed and uarts are used to access the chip from a host system. peripheral components such as flash, ram, rom, etc. can be connected through the external bus interface. the external bus interface is confgurable to ft a variety of peripheral components. the pbm 990 90 together with a bluetooth radio and a flash holding the frmware, forms a bluetooth radio link, see fgure 5. ericsson bluetooth core (ebc) ebc is the name of the bluetooth dedicated hardware designed to offoad the processor by taking care of heavy calculation tasks such as whitening, crc check, ciphering of data, forward error correction and bluetooth packet segmentation & reassemble. ebc is compliant with the bluetooth specifcation revision 1.1 and includes the following key features: ? acl link support giving data rates up to 721 kbit/s over the air interface. ? sco link with support for up to three voice channels over the air interface. ? hw support for all packet types. ? support for one pcm-channel. ? architecture designed for low power consumption. ? hold, sniff, parked modes ? ciphering keys up to 128 bits ? high quality fltering of voice packets enables excellent audio quality. ? flexible voice formats to host and over air (cvsd, pcm, 16/8 bit 1st and 2nd complement, signed, a-law, -law). ? point to multipoint with support for up to 7 slaves. ? master/slave switch capability ? radio interface is compliant with bluerf interface v0.9, unidirectional mode, rxmode2. figure 4. example system using pbm 990 90. codec base band chi p pbm 990 90 flash bluetoot h radi o data addr ctrl hci pcm & i 2 c uart (max 921 kb/s) usb 2.0 (12 mb/s ) inte l am d sst st toshiba host system blue rf i/f ericsson pba 313 01 pba 313 02 pba 313 05 other s
pbm 990 90 11 host interfaces to enable a host system to access the bluetooth radio link, a host controller interface (hci) has been defned. the host system controls and distributes data to and from the bluetooth link manager with a set of commands. these commands are carried physically on either the usb or uart interface. usb 2.0 full-speed usb is a serial interface supporting a 12 mbit/s. the interface is plug and play C to its nature and is therefore easy to use for equipment that is constantly moved around. the usb interface implemented in pbm 990 90 is based on the 2.0 full-speed version of the usb standard and is confgured for 6 endpoints: ? control endpoint with 8 bytes buffer. ? 2 isochronous endpoints (rx/tx) C double buffered with 64 bytes in each buffer. ? 2 bulk transfer endpoints (rx/tx) C double buffered with 64 bytes in each buffer. ? interrupt endpoint with 16 bytes buffer. the usb is divided into three parts, usb phy, usb core, and usb driver software integrated in the frmware. pbm 990 90 has an integrated phy, the necessary analog line driver for usb signalling, thus avoiding an external component. the simplifed usb pin confguration where only d+ and d- are used, means that the interface does not require to be fed power from the usb host. the usb core is the digital hardware part handling packet transmission and reception. it also handles low level control. the usb software driver is integrated in the frmware delivered with the chip. measured throughput (usb-airlink-usb) packet type full duplex half duplex dh5 420/420 kbit/s 705 kbit/s uarts there are two on-chip uart 16c550 compatible interfaces, uart1 and uart2. uart1 has 128 byte fifos and full modem control support and is used for data transmission at bit rates up to 921 kbit/s. uart1 is setup to a dte confguration as default. it can be changed to a dce confguration by software. ri and dcd then become outputs, cts is swapped with rts and dsr is swapped with dtr externally. pin name dte confguration dce confguration uart1cts clear to send input request to send input uart1dsr data set ready input data terminal ready input uart1dcd data carrier detect input data carrier detect output uart1ri ring indicator input ring indicator output uart1rts request to send output clear to send output uart1dtr data terminal ready output data set ready output the other uart, uart2 has 16 byte fifos and is used for control and/or boot. uart2 has only the tx and rx pins available and can support bit rates up to 230 kbit/s. start-detect and auto-baud functionality is available for both uarts. default settings uart1, uart2 speed 57600 bit/s data bit 8 bit stop bit one parity none flow cts/rts (not applicable for uart2) note: these settings can be changed from the hci level using ericsson specifc commands. figure 5. architecture. am ba tm ericsson bluetoot h core 64 kb sr am arm7 td mi usb uart 1 uart 2 gp io te st interface bl ue rf i/f pc m ho st i/f gp io / i 2 c de bug & te st i/ f external bu s interface rom o t h e r bluetooth radi o pba 313 01 pba 313 02 pba 313 05 f l a s h
pbm 990 90 12 confguration type options access type no retry, retry after every access or retry after every four memory accesses memory width 8- or 16-bit burst mode non-burst devices or burst rom write protect on / off write protect error status fag error, no error or clear fag bus transfer error status fag error, no error or clear fag wait state for write accesses 1..32 internal system clock cycles wait state(s) (sram) or 0..31 clock cycles wait state(s) (burst rom) wait state for read accesses 1..32 internal system clock cycles wait state(s) bus turnaround cycles 1..16 internal system clock between read & write cycles wait state(s) access other interfaces external bus interface the external bus interface allows the designer to add peripheral circuits included in the pbm 990 90 memory map. it has support for three memory banks each offering an address range of 1024 k positions and individually confgurable by memory mapped registers as described below. memory bank 0 is used by the flash memory holding the frmware executing on the processor. bank 1 and 2 can be used to expand the ram or to add other components. each memory bank can be confgured according to the table to the right: figure 6. external bus interface. figure 7. example of an external bus one wait state read access. address data nextr d nextw r nextcs0 nextcs1 nextcs2 pbm 990 90 external bus interface flash valid extdata[15:0] 0x00000000 extaddr[19:0] int. addr. bus [31:0] int. data bus [31:0] 1 wait state nextcs[x] nextrd valid valid valid
pbm 990 90 13 gpio / i 2 c pbm 990 90 supports up to 10 bit general purpose i/os. 2 bits gpio are available by default and these are also used as the i 2 c interface. 8 bits extra gpio can be obtained by using the 8 most signifcant bits of the 16 bit data bus. the i 2 c interface function is based on software using two gpios. the interface has a capacity of handling approximately 100 kbit/s. the different confgurations of gpio is controlled by the memory mapped registers described below. gpio register name function gpioaccen select between 16 bit external data bus or 8 bit external data bus + 8 extra gpio. gpiopaddr data direction register for gpioa bits. each gpioa bit can be setup to either an input or output. gpiopbddr data direction register for gpiob bits. each gpiob bit can be setup to either an input or output. gpiopadr data register for gpioa bits. this register is used to apply or read data from the gpioa bits. gpiopbdr data register for gpiob bits. this register is used to apply or read data from the gpiob bits. gpiointc1 interrupt control register 1. this register selects one of the available gpio bits to be connected to gpio interrupt 1. it also sets up the polarity and edge properties, enable and clear for the interrupt. gpiointc2 interrupt control register 2. this register selects one of the available gpio bits to be connected to gpio interrupt 2. it also sets up the polarity and edge properties, enable and clear for the interrupt. pcm the pcm interface (pif) in the ebc block provides an interface between the serial pcm transfer lines and the receive and transmit voice blocks inside the ebc. this interfacing task involves: ? synchronization between two asynchronous clock domains ? direction switching of the bi-directional pcm data and control signals ? synchronous serial data to parallel data conversion. the ebc supports one pcm channel on the pcm interface. the pcm line interface can act either as slave or master. when the pcm line interface is slave the frequency range of pcmclk (in) is 200 khz to 2 mhz. when the pcm line interface is master pcmclk (out) is always 2 mhz. each pcm symbol received on the pcma or pcmb in line is organized as an 8 or 16-bit sequence of bits, arriving synchronous to pcmclk in (if the pcm line interface is slave) or pcmclk out (if the pcm line interface is master). the symbol starts with its most signifcant bit arriving after a positive edge on the pcmclk in (or out), one clock cycle after a pcmsync in (or out) positive transition. the symbol is then transferred by one bit each pcmclk in (or out) clock cycle until the least signifcant bit is transferred. the ebc then samples the arriving bit at falling edges of pcmclk in (or out). the pcm symbols are transmitted bit by bit starting with the msb, one clock cycle after a positive edge on the pcmclk in (if the pcm line interface is slave) or pcmclk out (if the pcm line interface is master), one clock cycle after an pcmsync (in or out) positive transition. the rest of the bits are then transferred by one bit each pcmclk (in or out) cycle, and are synchronized with the rising edge of this clock. figure 9. pcm interface transmit timing diagram. figure 8. pcm interface receive timing diagram. pcmclkx p cmsyncx pcmxi n 0,1,or z msb msb-1 msb-2 msb-3 msb-4 d1 d0 0,1,or z not required for receive . pcmclkx p cmsyncx pcmxout 0,1,or z msb msb-1 msb-2 msb-3 msb-4 d1 d0 0,1,or z this pulse overlaps with the first pulse when the symbols are aligned. this is necessary to disable the output .
pbm 990 90 14 debug interface to support development of smaller applications, pbm 990 90 has a jtag based debug interface. the debug interface opens the possibility to access the processor system via multi-ice tm using a debug environment such as the ads 1.1? from arm ltd. arm7 tdmi processor this system is based around an arm7 tdmi microprocessor. the arm, together with rom, ram, system controller, external bus interface and an external flash forms the processor system, which executes the bluetooth frmware. the system offers some fexibility in terms of system performance, power management and scalability. the confguration of pbm 990 90 is done by writing to memory mapped registers. system controller & miscellaneous control these functions handle all system confguration and power management. they confgure the built-in pll, deactivate blocks that are not used, adjust the system frequency to match the performance needed for the application, etc. this fexibility is important for power management. figure 10 below illustrates how the clock generation is built up from the input clock. pll feedback divider this block controls the feedback divider for the phase locked loop. in combining an input clock, the pll and the programmable divider, pbm 990 90 is able to operate with a wide variety of input clock frequencies. the aim is that a designer will be able to re-use an existing system clock and is not constrained by frequency requirements, thus reducing the need for additional discrete components (such as an oscillator). the following formula can be used to derive the input frequencies that can be supported by pbm 990 90: 1 m 31; 80 n 137; p = 0, 1, 2 f xin ( n- p ) = 96 mhz m 3 writing to a memory mapped register sets the value of n, p, and m. system clock x/y divider the system clock defnes the speed for the arm processor. it is important to have enough capacity when using usb or the uart at 921 kb/s. the frequency can be changed from hci level by writing to a memory mapped register to change the value of the divider parameters (sysclkxdiv, sysclkydiv), which have the following relation: sysclk = clkmain ( sysclkxdiv ) sysclkydiv note: x and y can be set to values between 1 and 255. the x-value must be less than or equal to the y-value. uart clock x/y divider the frequency of the uart clock depends on what bit rate is required. for 921.6 kbit/s a frequency of 14.7456 mhz is required. the relation between uartclk and clkmain is programmed by setting the x/y divider parameter values (uartxdiv, uartydiv) according to the expression below: clkbaud = clkmain ( uartxdiv ) uartydiv note: x and y can be set to values between 1 and 255. the x-value must be less than or equal to the y-value. bluetooth clock, clk4m, x/y divider the bluetooth part of the chip, ebc, needs a 4 mhz clock frequency. this clock has to be trimmed using the x/y divider to suit the frequency available as sysclk. it is important to notice that clk4m is a function of sysclk and therefore a function of sysclk x and y parameter values. clk4m = sysclk ( clk4mxdiv ) clk4mydiv clk4m = clkmain ( sysclkxdiv ) ( clk4mxdiv ) sysclkydiv clk4mydiv note: x and y can be set to values between 1 and 255. the x-value must be less than or equal to the y-value. figure 10. clock generation. 1/ 3 pl l pll feedback divider cl km ai n uartclk sysclk clk4m x/ y x/ y 96 mh z 32 mh z programmable control : 1/ 2 usbclk x/ y programmable divider s programmable divider xi n
pbm 990 90 15 low power operation (lpo) clock support this function is essential for the wake up function. when the radio link is unused, the circuit will go in to a power saving mode inactivating all other blocks including the pll. at this time the lpo clock and a small number of gates are the only active logic in the circuit. the lpo associated logic activates the processor periodically for page- and inquiry- scan. the lpo clock input, lpoxin requires an external 3.2 or 32 or 32.768 khz square wave. usb vterm & ebc wakeup support these functions are shared on the same usbvt_ebcwakup pin and are selected by a memory mapped register. only one of the functions can be used for a given system confguration. usbvt functionality: the default state after reset is a usb vterm output pin. the usb vterm output is used to either connect or disconnect an external 1.5 k ? termination resistor between usb_dp and vddio2 (3.3 v in this case). a connect indicates that a high speed usb unit is attached to the usb line. a disconnect indicates that the usb unit is detached from the line. the default state after reset is disconnect, i.e. usbvt is tri- stated. ebcwakup functionality: the alternative function is an active high ebc wakeup input pin. this can be used by an external unit to order the ebc to start a bluetooth scan procedure. system wakeup in low power operation nsyswakup is an active low unconditional system wakeup input pin. it has to be connected to vddio4 if this functiona- lity is not to be used. software the bluetooth link is partitioned into a hardware part and a software part. the software relates to the bluetooth protocol stack. depending on the level of integration, there will be two different frmware models available, including hardware specifc drivers for the bluetooth core, usb, uarts, gpio and i 2 c. the level of integration follows the two scenarios: ? lm & hci frmware ? embedded bluetooth stack frmware lm & hci frmware in this confguration the customer will access the lm through a host controller interface (hci) protocol distributed over usb or uart. see fgure 11. embedded bluetooth stack frmware this confguration opens up the possibility for the customer to build small applications based on the pbm 990 90 chip, using the arm processor in pbm 990 90 as the main processor. see fgure 12. figure 11. lm & hci frmware. figure 12. embedded bluetooth stack frmware. pbm 990 90 running ?l m ?hci os: ose host system controlle r running: ?host stac k ?applicatio n os: customer uart/usb lm hci uart usb pbm 990 90 pbm 990 90 lm p api l2cap api rfcomm sdp api applicatio n pbm 990 90 running: ?applicatio n ?rfcom m ?sdp ?l2cap ?lm p ?other os: ose uart s pcm gpi o usb
ericsson microelectronics se-164 81 kista, sweden +46 8 757 50 00 www.ericsson.com/microelectronics for local sales contacts, please refer to our website or call: int + 46 8 757 47 00, fax: +46 8 757 47 76 preliminary data sheet en/lzt 146 128 r1a ? ericsson microelectronics ab, december 2001 information given in this data sheet is believed to be accurate and reliable. no responsibility is assumed for the consequences of its use nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of ericsson microelectronics. these products are sold only according to ericsson microelectronics general conditions of sale, unless otherwise confrmed in writing. specifcations subject to change without notice.

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