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this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change without notice. august 2014 docid026783 rev 2 1/58 STCH01 advanced multi-mode power management controller for zero no-load power consumption datasheet - preliminary data features ? cv/cc regulation with or without optocoupler (opto or optoless version respectively) ? burst mode operation at no load, with wake-up from secondary side (optoless version) ? zero power consumption in no load condition (optoless version) with excellent dynamic load transient ? internal high voltage startup ? ovp dedicated pin with sensing from auxiliary winding of transformer ? dedicated pin for protection purpose (prot pin with latched or autorestart option) ? second level ocp (transformer saturation or output rectifier short-circuit) ? online digital trimming for the highest end product accuracy ? intelligent frequency jitter for emi suppression ? low v dd supply voltage operation ? two avalanche rated internal power mosfets applications ? adapter/plug-in charger: mobile phone, tablet, camcorder, shaver, emergency light, etc. description the STCH01device is a high voltage primary switcher intended for operating directly from the rectified mains with minimum external parts. housed in a compact so16n package,STCH01 embeds controller and two dedicated power sections in a unique full integrated solution. the device allows to implement power supplies with extremely low consumption during no-load assuring excellent dynamic load transition response without optocoupler. the converter utilizes two operating modes: forced commutation mode: performed by a high- performance qr pwm controller and a low-side (ls) power mosfet, to serve the purpose of power storage and power control. self commutation mode: performed by an integrated proprietary scheme and a high-side (hs) mosfet, to serve the purpose of resonant power release to the load. : so16n table 1. device summary tube tape and reel version STCH01 STCH01tr optoless and autorestart STCH01l STCH01ltr optoless and latched STCH01nw STCH01nwtr optoless and autorestart STCH01lnw STCH01lnwtr optoless and latched www.st.com
contents STCH01 2/58 docid026783 rev 2 contents 1 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 pin functions and typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 typical application - optoless version . . . . . . . . . . . . . . . . . . . . . . . 16 7 typical application - opto version . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 low-side power section and gate driver . . . . . . . . . . . . . . . . . . . . . 19 8.2 high-side power section and resonant frequency control . . . . . . . . 20 8.3 high voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.4 zero current detection circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.5 constant voltage regulation (optoless version) . . . . . . . . . . . . . . . . . 24 8.6 constant voltage regulation (opto version) . . . . . . . . . . . . . . . . . . . . . . 25 8.7 constant current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.8 voltage feed-forward block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.9 burst mode operation (optoless version) . . . . . . . . . . . . . . . . . . . . . . 30 8.10 burst mode operation (opto version) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.11 frequency jitter for emi reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.12 ovp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.13 hiccup mode ocp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.14 generic protection pin (prot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.15 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 online trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 docid026783 rev 2 3/58 STCH01 contents 58 9.2 device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 9.3 device commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 data strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.4 emulation commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.5 emulate v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.6 emulate g i * v cref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9.7 emulate r ff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.8 emulate ipk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.9 read commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.9.1 read v ref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.9.2 read g i * v cref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.9.3 read r ff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.9.4 read ipk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.10 reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.11 reset volatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.12 write nvm (otp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.13 multiplexed scl and sda inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 device description STCH01 4/58 docid026783 rev 2 1 device description the device implements a current-mode control specifically designed for quasi-resonant flyback converters operating with valley switching , available in two versions: optoloess and opto. the optoless version is capable of providing constant output voltage (cv) regulation and constant output current (cc) regulation, using primary-sensing feedback. this eliminates the need for the optocoupler, the secondary voltage reference as well as the current sensor, still maintaining quite accurate regulation. the opto version uses a standard secondary side cv regulation with an optocoupler, while cc regulation is still performed with the primary side sensing. quasi-resonant operation is achieved by means of a transformer demagnetization sensing input that triggers the ls mosfet turn-on. the same input is dedicated also to output voltage monitoring, to perform cv regulation, and input voltage monitoring, to achieve mains independent cc regulation (line voltage feed-forward). a blanking time after the turn-on is inserted to allow for valley-skipping operation at a medium-light load, assuring in this way high-efficiency over wide range of the output load. at a very light load, the device enters a controlled burst mode operation that, along with the built-in high voltage start-up circuit and the low operating current of the device, helps minimize the residual input consumption. with the optoless version, in no load, light load conditions, the controller stops operating (entering a very low consumption state) and remains waiting for a wake-up signal pulse (on zcd pin) from the secondary side. during cc regulation, where the flyback voltage generated by the auxiliary winding drops and may be not enough to supply the internal circuits, the chip is able to power itself directly from the rectified mains through the high voltage start-up circuit. during the burst mode operation the self-supply feature is disabled (due to very stringent no load consumption requirement), and the v dd supply voltage has to be guaranteed by proper application design. to reduce the emi noise filtering, the device embeds a proprietary frequency jittering technique. STCH01 allows to achieve zero power consumption consumption in no load operation thanks to the following features: ? low operating v dd voltage ? low operating quiescent current ? intelligent burst mode operation, with wake-up from secondary side (optoless version) ? built-in high voltage active start-up circuit, based on depletion mosfet in addition to these functions that optimize power handling under different operating conditions, the device offers protection features with autorestart functionality that considerably increase end product's safety and reliability: ? thermal shutdown with hysteresis ? feedback disconnection feature ? second level ocp against transformer saturation or secondary diode short-circuit docid026783 rev 2 5/58 STCH01 device description 58 the device allows a system level trimming that improves application performance and manufacturing process. the parameters that can be adjusted by on line digital trimming are: ? output voltage accuracy setting ? output current accuracy setting ? voltage feed-forward accuracy setting ? frequency jitter amplitude an ovp pin is also provided, with sensing from the auxiliary winding and latched functionality. furthermore, the device is equipped with a pin prot, for a generic user defined protection circuit (like ovp or otp): this can be the latched type or autorestart, according to the selected bit option. an embedded soft-start procedure and leading edge blanking on the current sense input for greater noise immunity complete the equipment of this device. block diagram STCH01 6/58 docid026783 rev 2 2 block diagram figure 1. block diagram docid026783 rev 2 7/58 STCH01 pin functions and typical power 58 3 pin functions and typical power table 2. pin functions name function vin input bus voltage (from the rectified mains) connected to the drain of the internal high-side mosfet. pins connected to the internal metal frame to facilitate heat dissipation. drain drain connection of the internal low-side power mosfet. the internal high voltage start-up generator sinks current from these pins as well. pins connected to the internal metal frame to facilitate heat dissipation. cres a capacitor connected between this pin and the drain pin sets the resonant frequency occurring after the low-side mosfet turn-off (during transformer demagnetization). cdrv a capacitor connected between this pin and the drain pin allows high-side mosfet self-driving: this mosfet is turned-on when drain voltage is higher than vin voltage and is turned-off when drain voltage is lower than vin voltage. src source connection of the internal low-side mosfet and input to the pwm and 2 nd -ocp comparators. the current flowing in the low-side mosfet is sensed through a resistor connected between the src pin and gnd. the resulting voltage is sent to internal comparators to determine the mosfet's turn- off. gnd circuit ground reference and current return for both the signal part of the ic and the gate drive. all ground connections of the bias components should be tied to a trace going to this pin and kept separated from any pulsed current return (sense resistor between the src pin and gnd). vdd supply voltage of the device. an electrolytic capacitor, connected between this pin and ground, is initially charged by the internal high voltage start-up generator; when the device is running the same generator will keep it charged in case the voltage suppl ied by the auxiliary winding is not sufficient (for example this may happen during cc regulation). this feature is disabled in case of protection tripping. sometimes a small bypass capacitor (0.1 f typ.) to gnd might be useful to get a clean bias voltage for the signal part of the ic. iref cc regulation loop reference voltage. an external capacitor connected between this pin and gnd is charged by an internal circuit to an appropriate voltage level that is used as the reference for the mosfet's peak drain current during cc regulation. the voltage is automatically adjusted to keep constant the average output current. pin functions and typical power STCH01 8/58 docid026783 rev 2 zcd the following functions are performed by this pin: ? transformer demagnetization sensing for quasi-resonant operation. a negative going edge falling below the v zcdt threshold triggers the mosfet turn-on, provided the internal circuit has been previously armed by a positive going edge exceeding the v zcda threshold. ? input voltage feed-forward compensation. by connecting the zcd pin to the auxiliary winding through a resistor, the current sourced by the pin during the mosfet on-time is monitored to get an image of the input voltage to the converter. this information is used by the internal circuitry to achieve a cc regulation independent of the mains voltage. ? output voltage sense through a resistive divider connected to the auxiliary winding. the voltage on the low-side resistor of the divider (connected to this pin) is sampled and held right at the end of transformer's demagnetization to get an accurate image of the output voltage to be fed to the inverting input of the internal transconductance type error amplifier. ? sensing of wake-up signal coming from the secondary side during the burst mode, through the transformer auxiliary winding (optoless version). ? feedback disconnection. if the current sourced by the pin during the low-side mosfet turn-on does not exceed 50 a, either a floating pin or an abnormally low input voltage is assumed, the device is stopped and restarted after v dd voltage has dropped below v dd_restart . ? please note that the maximum i zcd sunk/sourced current has to not exceed the values indicated in the amr section table 4: absolute maximum ratings in all the vin range conditions (88 - 265 vac). no capacitor is allowed between this pin and the transformer auxiliary winding. comp ? optoless version: output of the internal transconductance error amplifier. the compensation network will be placed between this pin and gnd to achieve stability and good dynamic performance of the voltage control loop. ? opto version: control input for duty cycle control. an internal current generator provides a bias current for voltage loop regulation (implemented through secondary side sensing and optocoupler), while the internal transconductance error amplifier is disabled and internally disconnected from the pin. a voltage below the threshold v compbm activates the burst mode operation. ovp/scl a multiplexed pin for the overvoltage protection input during the normal operation and online trimming clock input. ? output voltage sense through a resistive divider connected to the auxiliary winding for overvoltage protection purpose: the voltage sensed on this pin is compared with an internal reference v ovp at the time instant when the transformer is demagnetized (and the auxiliary winding voltage is a representative value of the output voltage through the turn ratio); if the internal threshold v ovp is surpassed, then an overvoltage condition is assumed and the circuit enters a latched protection mode. after protection tripping, a mains recycle is necessary for a new restart attempt. ? in case ovp function is not used, the pin has to be connected to gnd through a resistor (5 k to 30 k ). ? clock (scl) logic input for i 2 c serial communication protocol. this pin will be externally pull-up to 3.6 v max. a small internal pull-up is present to prevent false signal detection (the pin is floating during normal operation). prot/sda a multiplexed pin for a generic protection input during normal operation and online trimming data input. ? generic protection input pin (active low): when the voltage on this pin is lower than the v prot threshold, the protection detection circuit stops device operation (latch type or autorestart mode according to the selected option). if this pin is not used, keep it open (not connected). ? data (sda) logic input/output for i 2 c serial communication protocol. this pin will be externally pull- up to 3.6 v max. a small internal pull-up is present to prevent false signal detection (the pin is floating during normal operation). table 2. pin functions (continued) name function docid026783 rev 2 9/58 STCH01 pin functions and typical power 58 table 3. typical power part number 230 v ac 85-265 v ac adapter (1) 1. typical continuous power in non-ventilat ed enclosed adapter measured at 50 c ambient open frame (2) 2. maximum continuous power in an open frame design at 50c ambient with adequate heat sinking adapter (1) open frame (2) STCH01 12.5w 18w 10w 12.5w maximum ratings STCH01 10/58 docid026783 rev 2 4 maximum ratings stressing the device above the rating listed in table 4: absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions may affect device reliability. table 4. absolute maximum ratings symbol parameter value unit v ds_ls_mos low-side mosfet drain-to-source voltage 650 v v ds_hs_mos high-side mosfet drain-to-source voltage 500 v e av-ls-mos single pulse avalanche energy, starting t j = 25 c, i d = i as = 0.7 a (single pulse avalanche current) (1) 1. pulse width limited by t j = 150 c. 20 mj e av-hs-mos single pulse avalanche energy, starting t j = 25 c, i d = i as = 0.7 a (single pulse avalanche current) (1) 20 mj i drain (ls-mos) low-side mosfet drain current (pulsed) 1.5 a i drain (hs-mos) high-side mosfet drain current (pulsed) 1.5 a v d-rrm diode (d) for high-side mosfet drive repetitive peak reverse voltage 300 v i fd diode (d) for high-side mosfet drive forward current (pulsed, 200 ns) 0.2 a i fzd1,2 internal diodes (zd1, zd2) forward current (pulsed, 200 ns) 0.2 a v dd device supply voltage (i dd < 25 ma) -0.3 to self-limited v v zcd zcd pin voltage (-3 ma i zcd +3 ma) -0.3 to self-limited v v ovp ovp pin voltage (-3 ma i zcd +3 ma) -0.3 to self-limited v v prot protection pin voltage -0.3 to 3 v - analog/digital pin voltages -0.3 to 3.6 v table 5. thermal data symbol parameter value unit r th-amb thermal resistance junction ambient (1) 1. mounted on a standard single side fr4 board with 50 mm 2 of cu (35 m thick) under drain and vin pins. 120 c/w p tot max. power dissipation at t amb = 50 c 0.8 w t j junction temperature range -40 to 150 (2) 2. max t j = 150 c refers to the embedded mosfet. c t stg storage temperature -55 to 150 c docid026783 rev 2 11/58 STCH01 maximum ratings 58 figure 2. device pinout (top view) 1. the copper area for heat dissipation has to be designed under the highlighted pins, connected respectively to drain and vin signals. vin comp zcd iref n.c. src gnd vdd drain drain ovp/scl n.c. n.c. prot/sda cre cdrv STCH01 am03702 electrical characteristics STCH01 12/58 docid026783 rev 2 5 electrical characteristics table 6. electrical characteristics (t j = -25 c to 125 c, v dd = 8 v; unless otherwise specified) symbol parameter test condition min. typ. max. unit low-side mosfet v (br)dss drain-source breakdown voltage i drain < 100 a; t j = 25 c 650 v i off off state drain leakage current v ds = 650 v; t j = 125 c, v dd = 8 v, v comp < v compbm , v zcd connected to gnd 4a r ds(on) static drain-source on- resistance i d = 1 a; t j = 25 c 4 i d = 1 a; t j = 125 c 8.8 c osseq. equivalent output capacitance v ds = 0 to 480 v; t j = 25 c 30 pf high-side mosfet v (br)dss drain-source breakdown voltage i drain < 100 a; t j = 25 c 500 v i off off state drain leakage current v ds = 500 v; t j = 125 c 1 a r ds(on) static drain-source on- resistance v cdrv - v cres = 10 v; i d = 1 a; t j = 25 c 8 v cdrv - v cres = 10 v; i d = 1 a; t j = 125 c 17.6 c osseq. equivalent output capacitance v ds = 0 to 480 v; t j = 25 c 25 pf internal diode (d) for high-side mosfet drive v r reverse voltage i r < 1 a 300 v v f forward drop i f = 20 ma; t j = 25 c 1 v internal zener diodes (zd1, zd2) for high-side mosfet drive v zd1,2 zd1, 2 zener voltage i r = 5 ma; t j = 25 c 10 15 20 v v fzd1,2 zener diode forward drop i f = 2 ma; t j = 25 c 1.7 1.9 v r d1,2 dynamic resistance i f = 2 to 10 ma; t j = 25 c 300 supply section v ds_start drain-source start voltage 55 62 67 v docid026783 rev 2 13/58 STCH01 electrical characteristics 58 i dd_ch start-up charging current v drain > v ds_start ; v dd = 4 v -3.5 -5.5 -8 ma v drain > v ds_start ; v dd < 0.6 v (v dd shorted or after protection tripping) -0.7 -1.1 -1.72 ma v dd operating voltage range after turn-on 5.75 23.5 v v dd_clamp v dd clamp voltage i dd = 5 ma 23.5 v v dd_on v dd turn-on threshold v drain = 120 v 10 11 (1) 12 v v dd_off v dd shutdown threshold 4.75 5.25 (1) 5.75 v v dd_restart v dd (falling) restart voltage normal operation 5 5.5 (1) 6v after autorestart or latch protection 4.5 5 (1) 5.5 v i dd_st-up before start-up current v drain > v ds_start ;250a i ddo quiescent current (not switching between bursts) v comp = v compl (no opto) v dd = v dd_on - 0.2 v 50 a v comp = v compl , (with opto) 350 a i dd operating supply current v ds = 120 v; f sw = 100 khz 1.3 ma i dd_fault operating supply current with protection tripping prot open 350 a prot shorted 550 a controller section zero current detection i zcd_bias input bias current v zcd = 0.1 to 3 v 1 a v zcd_h upper clamp voltage i zcd = 1 ma 3.3 v v zcd_l lower clamp voltage i zcd = -1 ma -60 mv v zcd_a_th arming voltage threshold positive going edge 110 mv v zcd_t_th trigger voltage threshold negative going edge 60 mv i zcd_on minimum source current during mosfet on-time -25 -50 -75 a t blank blanking time after turn-on v comp > 1.3 v 6 s v comp < 0.9 v 30 s t d_zcd fixed turn-on delay after zcd triggering 450 ns wake-up pulse detection (optoless version) v zcdwupth wake-up threshold on zcd pin (for burst-mode exiting) positive going edge 0.6 0.7 0.8 v t wup_min min wake-up pulse width above wake-up threshold 1.2 s table 6. electrical characteristics (t j = -25 c to 125 c, v dd = 8 v; unless otherwise specified) (continued) symbol parameter test condition min. typ. max. unit electrical characteristics STCH01 14/58 docid026783 rev 2 t wup_mask wake-up masking time after burst-mode entering 46 50 54 s transconductance error amplifier v ref voltage reference (1) v dd within supply range 2.45 2.5 2.55 v gm transconductance i comp = 10 a v comp = 1.65 v 1 ms gv voltage gain open loop 70 db gb gain-bandwidth product 0.5 mhz i comp source current v zcd = 2.3 v, v comp = 1.65 v 70 100 a opto bit option 70 100 130 a sink current v zcd = 2.7 v, v comp = 1.65 v 550 750 a v comph upper comp voltage v zcd = 2.3 v 2.7 v v compl lower comp voltage v zcd = 2.7 v 0.7 v v compbm burst mode threshold voltage falling 0.95 v hys burst mode hysteresis voltage rising 50 mv current reference v irefx maximum value (1) v comp = v compl 1.5 1.6 1.7 v g i current loop gain (2) v comp = v comph 0.5 v cref current reference voltage 0.4 v g i * v cref 190 200 210 mv current sense v csx max. clamp value (1) dvcs/dt = 200 mv/s 0.7 0.75 0.8 v v csdis hiccup mode ocp level 0.92 1 1.08 v t d propagation delay 250 ns t leb leading edge blanking 250 ns t on_min minimum on-time 500 ns input voltage feed-forward r ff equivalent ff resistor i zcd = -1 ma 54 60 66 frequency jittering f m modulation frequency 10 11 12 khz duty modulation duty cycle 50 % ipk peak current change (default bit option) 5 % starter t starter starter period zcd not armed 180 s table 6. electrical characteristics (t j = -25 c to 125 c, v dd = 8 v; unless otherwise specified) (continued) symbol parameter test condition min. typ. max. unit docid026783 rev 2 15/58 STCH01 electrical characteristics 58 ovp function v ovp overvoltage threshold (1) v dd within supply range 1.204 1.254 1.304 v v ovp_h upper clamp voltage i zcd = 1 ma 3.3 v v ovp_l lower clamp voltage i zcd = -1 ma -60 mv protection pin v prot_sd shutdown threshold 1.204 1.254 1.304 v i s source current v prot = 1.24 v -165 -200 -225 a i s_fault source current v prot = 0 v, v dd rising from v dd _ restart to 11 v autorestart option -125 -150 -175 a v prot = 0 v, v dd rising from v dd_restart to 11 v latch option -20 a v prot-clp clamp voltage pin open 3 v c max max external capacitance 13 pf trimming functions v scl_low scl input low level 0.8 v v scl_hi (2) scl input high level 2 3.45 v c scl scl input capacitance 5 pf f scl scl frequency 100 khz v sda_low sda input low level 0.8 v v sda_hi (2) sda input high level 2 3.45 v c sda sda input capacitance 5 pf v ddzap prom zapping voltage 17 20 v i zap prom zapping current v dd = 19 v 50 90 ma t zap prom zapping time v dd = 19 v 34 45 ms v ref trimming range (5 bits) referred to 0% trimming -9 9 % v ref trimming step 0.6 % g i * v cref trimming range (4 bits) referred to 0% trimming -10.5 10.5 % g i * v cref trimming step 1.5 % r ff trimming range (3 bits) referred to 0% trimming -17.5 17.5 % r ff trimming step 2.5 % ipk frequency jitter amplitude levels:% of peak current change no jitter 0 % default value. for the other values, refer to table 19 . 5% 1. all voltages in tracking. 2. sda and scl inputs are connected to an internal bus at 3.3 v even if they are protected to v dd as amr. table 6. electrical characteristics (t j = -25 c to 125 c, v dd = 8 v; unless otherwise specified) (continued) symbol parameter test condition min. typ. max. unit typical application - optoless version STCH01 16/58 docid026783 rev 2 6 typical application - optoless version figure 3. typical +5 v -8 w charger application electrical diagram 1 2 j1 con2 1 2 j2 con2 + - ~ ~ d1 df06s c1 10uf-400v out 1 gnd 2 nc3 3 vsns 4 nc5 5 vdd 6 u2 stwk01 c4 47pf-500v c11 4.7nf c3 220pf-500v r5 60.4k c2 4.7uf-400v r6 68k r8 47k r3 12k c10 150nf prot-sda l2 330uh c7 res +5v l1 2x10mh c9 1nf ovp-scl c8 100nf r9 2r2 d3 bav103 c12 10uf-50v +5v d2 sbr10u45 c5 270uf-6.3v r1 fuse-4r7 r2 0.75r 1 2 3 4 j3 con4_0 prot/sda ovp/scl vdd vdd c6 560uf-6.3v 4 8 6 5 2 1 7 9 t1 e20-1.5mh vin 1 nc2 2 src 3 vdd 4 gnd 5 iref 6 zcd 7 prot/sda 10 nc11 11 drain 12 drain 13 nc14 14 cdrv 15 cres 16 comp 8 ovp/scl 9 u1 STCH01 r7 res r10 360k r11 33k c13 470pf-y 1 r4 14.3k am03703 docid026783 rev 2 17/58 STCH01 typical application - opto version 58 7 typical application - opto version figure 4. typical +5 v -8 w charger application electrical diagram 1 2 j1 co n2 1 2 j2 con2 r14 68k r15 21.5k + - ~ ~ d1 df06s c1 10uf-400v c4 47pf-500v c11 4.7nf c3 220pf-500v r5 60.4k c2 4.7uf-400v u4 ts431 prot-sda l2 330uh c7 res l1 2x10mh c9 470pf ovp-scl c8 100nf r9 2r2 c10 100nf d3 bav103 r13 15k c14 10n r3 22k c12 10uf-50v +5v u3a sfh617a-2 d2 sbr10u45 c5 270uf-6.3v u3b sfh617a-2 r6 res r1 fuse-4r7 r12 470 +5v r2 0.75r 1 2 3 4 j3 con4_0 prot/sda ovp/scl vdd vdd c6 560uf-6.3v 4 8 6 5 2 1 7 9 t1 e20-1.5mh vin 1 nc2 2 src 3 vdd 4 gnd 5 iref 6 zcd 7 prot/sda 10 nc11 11 drain 12 drain 13 nc14 14 cdrv 15 cres 16 comp 8 ovp/scl 9 u1 STCH01 r10 360k r11 33k c13 470pf-y 1 r4 14.3k am03704 operation description STCH01 18/58 docid026783 rev 2 8 operation description the STCH01device is a high-performance switching regulator, specific for off-line qr flyback topology; it combines a low-voltage pwm controller with two avalanche rugged power mosfets in the same package: the low-side one is the main switch of the topology, the high-side one is used for controlling the resonant frequencies. in the optoless version, the controller includes the current mode pwm logic and the zcd circuit for qr operation, and regulates the output voltage and current, basing on primary-sensing feedback. the auxiliary winding voltage is sampled by a sample and hold circuit just at the end of transformer demagnetization, when its voltage is proportional to the output voltage through the transformer turn ratio, triggered by the demagnetization sensing circuit. the sensed voltage is then sent to the error amplifier and its output to the constant voltage pwm comparator. the demagnetization circuit also allows obtaining a reference voltage (proportional to the output current) for the constant current pwm comparator. in the opto version, the internal error amplifier is disabled and a current generator provides to the comp pin the required feedback current, allowing to regulate the output voltage (sensed at the secondary side) through the optocoupler connected to the comp pin. the device provides protection features with autorestart functionality that increases the end product safety and reliability, like the feedback disconnection protection, the second level ocp circuit (suitable for detection of transformer saturation or output diode short-circuit) and the thermal shutdown with hysteresis. a dedicated protection pin (prot) is also available for a generic user defined protection (like otp or ovp), that can be autorestart or latched, according to the selected device version. other features, like an embedded soft-start, frequency jitter for emi reduction and leading edge blanking on the current sense input, complete the device equipment, giving the user flexibility and ease of use in designing an end product very robust and performing, with high-efficiency and extremely low no load consumption as well and, above all, with a very low component count. the pwm logic works in the qr mode at the nominal load, in the valley-skipping mode at a lighter load and in the burst mode with a very low load or no load. in the qr mode the controller turns on the low-side power mosfet at the end of the transformer demagnetization, by detecting the resulting negative going edge of the voltage across the auxiliary winding of the transformer. the mosfet turn-off is instead decided by the pwm comparator when the drain current reaches the peak value needed for the output voltage or the output current regulation; therefore the operating switching frequency will be different for different line and load conditions. at lower load levels, the valley-skipping mode is activated. in fact, depending on the comp pin voltage, a blanking time from the turn-on instant (increasing with decreasing comp voltage) is internally set, limiting the maximum operating frequency. as a consequence, the mosfet turn-on will not any more occur on the first valley but on the second one, the third one and so on. in this way a ?frequency clamp? effect is achieved (see figure 5 ). docid026783 rev 2 19/58 STCH01 operation description 58 figure 5. frequency mode operation versus load while reducing the load, the comp pin voltage progressively reduces: at no load or a very light load, it goes below the threshold v compbm and consequently the controller stops operation and reduces its consumption. with the opto version, the operation restarts as soon as the comp pin, due to feedback reaction at the operation stop, increases above the v compbm level plus the burst mode hysteresis (hys). in case of the optoless version, instead, once stopped the operation, the controller remains in a very low consumption state waiting for a wake-up signal pulse (on zcd pin). a dedicated ic at the secondary side (stwk01 companion of the primary controller optoless version) detects the primary side operation stop and starts monitoring the output voltage: when this decreases (due to the residual output consumption) below a user defined voltage threshold, the stwk01 ic releases a wake-up pulse via the transformer windings, that is sensed by the zcd pin through the resistive divider connected to the auxiliary transformer winding; consequently the STCH01controller resumes operation (see section 8.9: burst mode operation (optoless version) on page 30 . 8.1 low-side power section and gate driver the low-side power section guarantees safe avalanche operation within the specified energy rating as well as high dv/dt capability. the power mosfet gate driver is designed to supply a controlled gate current during both turn-on and turn-off in order to minimize the common mode emi. under uvlo conditions, an internal pull-down circuit holds the gate low in order to ensure that the power mosfet cannot be turned on accidentally. the driver is also provided with a voltage clamp to limit the gate charge to the mosfet in case of higher v dd supply. % x u v w p r g h 9 d o o h \ v n l s s l q j p r g h 4 5 p r g h ) p d [ ) 6 : 3 r x w , q f u h d v l q j 9 , 1 $ 0 operation description STCH01 20/58 docid026783 rev 2 8.2 high-side power section and resonant frequency control the device integrates also a high-side power section to control resonant frequencies. the high-side mosfet connects and disconnects a capacitor cr (placed between cres and drain pins) in parallel to the primary winding of the power transformer. in this way the converter operates at two different resonant frequencies: a high resonant frequency when cr is disconnected and a lower resonant frequency when cr is connected to the transformer primary inductance. the energy stored in the circuit during the two portions of resonant cycles in principle may provide zvs (?zero voltage switching?) operation for both low and high-side power mosfets, thus increasing the overall converter efficiency. the mosfet is automatically driven on and off depending on the external circuit operation; only a capacitor (47 - 100 pf) is needed, connected between the cdrv and drain pins. in particular the high-side mosfet is on when the drain voltage across the low-side mosfet is higher than the input voltage and is off when the drain voltage is lower than vin. 8.3 high voltage startup generator based on a depletion mosfet embedded into the low-side mosfet structure, the hv current generator is supplied through the drain pin and is enabled only if the input bulk capacitor voltage is higher than the v ds_start threshold. when the hv current generator is on, the i dd_ch current is delivered to the capacitor on the v dd pin. as the voltage across the v dd capacitor reaches the start-up threshold v dd_on , the uvlo signal is asserted high and enables the low-side mosfet switching, while the hv current generator is turned off. the ic is powered by the energy stored in the v dd capacitor until the self-supply circuit (from an auxiliary winding of the transformer) develops a voltage high enough to sustain the operation. the chip is able to power itself directly from the rectified mains through the hv start-up circuit: when the voltage on the v dd pin falls below v dd_restart, during each mosfet's off- time, the hv current generator is turned on and charges the supply capacitor until it reaches the v dd_on threshold again. in this way, the self-supply circuit develops a voltage high enough to sustain the operation of the device. this feature is useful especially during cc regulation, when the flyback voltage generated by the auxiliary winding alone may be not enough to keep v dd above v dd_restart . after an autorestart type protection tripping, the v dd_restart value is reduced (below v dd_off ) and the hv generator provides only about 20% of i dd_ch full value, allowing for a lower repetition rate of restart attempts (reduced input power consumption and depletion mosfet stress). when at no load or a very light load the controller stops operating and remains waiting for the wake-up signal, the vdd is not controlled and the hv start-up generator is not restarted in case the v dd_restart is reached. therefore, during the burst mode operation the vdd voltage has to be always higher than v dd_off by a proper design of the transformer auxiliary winding turns and of the capacitor value on the v dd pin. figure 6 shows the time diagram during the various operating conditions, from power-on to power-off, with the typical restart during cc regulation, when the transformer auxiliary winding is not enough to sustain the device supply voltage. at converter power-down the system will lose regulation as soon as the input voltage falls below v ds_start . this prevents docid026783 rev 2 21/58 STCH01 operation description 58 converter's restart attempts and ensures monotonic output voltage decay at system power- down. in order to avoid overheating of the hv current generator in case of a short-circuit on v dd , the full current i dd_ch is delivered only if the v dd voltage is detected higher than a v be threshold, otherwise it is reduced to about 20% of i dd_ch full value. figure 6. timing diagram from power-on to power-off 9 ' ' w w w w 9 ' 6 b 6 7 $ 5 7 w w 3 r z h u r q 3 r z h u r i i 1 r u p d o r s h u d w l r q & |