AN1322/0405 1/9 AN1322 application note migrating an application from st7263 rev.b to st7263b introduction this application note provides information on migrating existing st7263 rev. b based appli - cations to the new st7263b. this document: ? describes the different steps required to upgr ade your design environment so as to support the st7263b, ? lists the device differences that must be taken into account when porting device firmware. 1 devices involved ? st72631l4m1/xxx ? st72t631l4m1 ? st72631k4b1/xxx ? st72t631k4b1 ? st72632l2m1/xxx ? st72t632l2m1 ? st72632k2b1/xxx ? st72t632k2b1 ? st72633l1m1/xxx ? st72t633l1m1 ? st72633k1b1/xxx ? st72t633k1b1 ? st72e631k4d1 note : xxx is the name of the rom code. 2 development tools table 1. development tool or dering information if you already have the st7263-emu2 emulator, you do not need to order the new emulator. simply contact our sale office for further information. device emulator eprom programming board (epb) st7263 rev. b st7263-emu2 st7263-epb st7263b st7mdtu3-emu3 st7mdtu3-epb 1
2/9 migrating an application from st7263 rev.b to st7263b 3 hardware changes for a summary of hardware modifications, please refer to table 2. 3.1 pull up value in reset pin the value of the weak pull-up resistor for the reset pin changes from 30 k ? for the st7263 rev. b to 100 k ? for the st7263b. 3.2 power supply in st7263 rev.b, the operating power supply can lie between 3.0 v to 5.5 v without usb and 4.0 v to 5.5v with usb, while for the st7263b, the operating supply is fixed at 4.0 v to 5.5 v (with or without usb ). 3.3 low voltage detector (lvd) the lvd generates a reset when v dd is: ? below 4.00 v for st7263b (4.00v for st7263 rev. b) when v dd is rising, ? below 3.80v for st7263b (3.70 v for st7263 rev.b) when v dd is falling. table 2. hardware comparison chart please refer to the corresponding datasheet for all electrical characteristics. st7263 rev. b st7263b reset pull-up value 30k ? 100k ? power supply 3.0 to 5.5v (when usb is disabled) 4.0 to 5.5 (when usb is enabled) 4.0 to 5.5 v (with or without usb) lvd reset generation 4.00 v when v dd is rising 4.00 v when v dd is rising 3.70 v when v dd is falling 3.80 v when v dd is falling 2
3/9 migrating an application from st7263 rev.b to st7263b 4 software porting 4.1 device configuration the st7263b device features an option byte that provides two new optional functions: ? watchdog hardware selection, ? read out protection. this option byte allows the device to be configured independently of the application software. the option byte is also used to control cer tain functions that were previously managed in the miscellaneous register (miscr) in the st7263 rev.b: ? 24 or 12 mhz oscillator selection function th at provides an internal frequency of either 2, 4 or 8 mhz while maintaining a 6 mhz frequency for the usb ? lvd reset function that allows the mcu to reset other devices. moreover, a new bit, the slow mode select (sms) bit, is added in the miscr register and en - ables an internal divide-by-2 clock divider used to halve the cpu frequency for power saving reasons. consequently, the miscr register of the st7263 rev.b and st7263b are not directly upward compatible and require some software adjustments. 4.1.1 option byte description five new configuration options are available as described below. bit 5 = wdgsw hardware or software watchdog this option bit selects the watchdog type. 0: hardware (watchdog always enabled) 1: software (watchdog to be enabled by software) bit 4 = wdhalt watchdog and halt mode this option bit determines if a reset is generated when entering halt mode while the watchdog is active. 0: no reset generation when entering halt mode 1: reset generation when entering halt mode. bit 3 = lvd low voltage detector selection this option bit enables the lvd. 0: lvd reset enabled 1: lvd reset disabled 7 0 - - wdgsw wdhalt lvd - osc24/12 fmp_r
4/9 migrating an application from st7263 rev.b to st7263b bit 1 = osc24/12 quartz crystal selection this option bit ensures that the usb peripheral is clocked at 6 mhz regardless of the quartz crystal used. the cpu frequency also depends on the context of the miscr register. 0: 24 mhz oscillator 1: 12 mhz oscillator bit 0 = fmp_r memory read-out protection this option indicates if the user memory is prote cted against read-out. this protection is based on the read and write protection of the memory in test modes and during in-application pro - gramming (iap). if the option bytes are erased when the fmp_r option is selected, the entire user flash memory will be erased first. as a rom option, this will be a mask option and not software. 0: read-out protection enabled 1: read-out protection disabled 4.1.2 miscr register description st7263 rev. b st7263b the lvd bit has been removed from the miscr register and added to the option byte. its be - haviour remains unchanged. the clkdiv bit, which selects either a 12 or 24 mh z quartz crystal, has been removed from the miscellaneous register and added to the option byte of the st7263b. for further informa - tion, refer to section 4.1.1 option byte description . the clken and mco bits still have the same function (pa0 outputs the internal cpu clock signal). only the name has been changed. the sms bit used for slow mode selection is now available in the miscellaneous register. if the sms bit is equal to 1, the cpu frequency is divided by 2. the following section provides two different ta bles summarizing how the option byte and mis - cellaneous register must be programmed in order to be compatible with existing applications based on the st7263 rev.b. 7 0 - - - - lvd clkdiv usboe clken 7 0 - - - - - sms usboe mco
5/9 migrating an application from st7263 rev.b to st7263b 4.1.3 option byte and miscellaneous register programming table 3. st7263b configuration for st7263 rev.b upward compatibility table 4. internal frequency configuration 4.2 peripherals the i2c and usb peripherals are fully software compatible as long as the application software has been recompiled with an updated register map. 4.2.1 serial communications inte rface (sci) (not upward compatible) certain new features such as the power down and parity generation/check functions have been added and are controlled by bits that were unused on the st7263 rev. b. as long as the following 5 bits are set to 0 on the st7263 rev.b software, they are directly upward compat - ible when recompiled with an updated register map. the new parity management feature in the st7263b requires the following configuration in both transmission and reception modes: in the scicr1 register, ? bit 5 = scid sci disabled when this bit is set, the sci cell is disabled and power consumption is reduced. ? bit 2 = pce parity control enable select the hardware parity control. in transmissi on, parity is inserted at the msb position, and parity is checked in reception mode. ? bit 1 = ps parity selection even (0) or odd (1) ? bit 0 = pie parity interrupt enable generates an interrupt when a parity error is detected. st7263 rev. b configuration equivalent st7263b configuration lvd (miscr) clkdiv (miscr) sms (miscr) option byte wdgsw lvd osc24/12 wdhalt fmp_r 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 quartz osc24/12 option byte (bit 1) slow mode miscr (bit 2) f cpu f usb 24 mhz 0 0 8 mhz 6 mhz 24 mhz 0 1 4 mhz 6 mhz 12 mhz 1 0 4 mhz 6 mhz 12 mhz 1 1 2 mhz 6 mhz
6/9 migrating an application from st7263 rev.b to st7263b in the scisr register, ? bit 0 = pe parity error detection this flag is set when a parity error is detected in reception mode. the baud rate value selection has also been changed. in the new version, all transmission and reception rates are multiplied by two. consequently, the contents of the baud rate (scibrr) register for the st7263b must be up - dated to match certain st7263 rev.b rates. for example, to obtain the same baud rate (1200 baud), the scp[1:0] and sct[2:0] bits in the scibrr register must be configured as follows: table 5. baud rate register comparison chart 4.2.2 timer (upward compatible) the 16-bit timer of the st7263b has been modified to solve certain issues related to pwm and one pulse modes. 4.2.2.1 pwm mode to prevent uncontrolled states from being output in pwm mode, a double buffering on the output compare registers (2x16 bits) is implemented in the st7263b. any new values written in the four oc1r and oc2r registers are taken into account only at the end of the pwm period (oc2 event) to prevent spikes from occurring on the pwm output. 4.2.2.2 one pulse mode one pulse mode has been improved in the st7263b version to increase efficiency. when the icap1 event is detected (on the falling or rising edge), the ic1r register is loaded with the value of the counter, which is then reset to fffch. the rest of the sequence remains un - changed. st7263 rev. b st7263b scp[1:0] sct[2:0] scp[1:0] sct[2:0] 11 100 11 101
7/9 migrating an application from st7263 rev.b to st7263b 4.3 register map a new line must be inserted in the register map corresponding to the flash control and status register (fcsr). address: 0037h read / write reset value: 0000 0000 (00h) this register is reserved for use by the pr ogramming tool software. it controls the flash pro - gramming and erasing operations. for details on customizing flash programming methods and in-circuit testing, refer to the st7 flash programming and icc reference manual. table 6. interrupt vector addresses 4.3.1 ram in the st7263 rev. b, the data ram is up to 512 bytes with 64-byte stacks. in the st7263b version, the data ram is 512 bytes with 128-byte stacks. therefore, the stack address is also changed: ? in st7263 rev.b, the stack is from 0100h to 013fh ? in st7263b, the stack is from 0100h to 017fh in the same way, 16-bit addressing ram size is reduced: ? in st7263 rev.b, the 16-bit addressing ram is from 0140h to 023fh ? in st7263b, the 16-bit addressing ram is from 0180h to 023fh 7 0 0 0 0 0 0 0 0 0 vector address st7263 rev.b st7263b ffee - ffef -- usb interrupt vector fff0 - fff1 usb interrupt vector sci interrupt vector fff2 - fff3 sci interrupt vector i2c interrupt vector fff4 - fff5 i2c interrupt vector timer interrupt vector fff6 - fff7 timer interrupt vector it1 to it8 interrupt vector fff8 - fff9 it1 to it8 interrupt vector usb end suspend mode interrupt vector fffa - fffb usb end suspend mode interrupt vector flash start programming interrupt vector fffc - fffd trap interrupt trap interrupt fffe - ffff reset vector reset vector
8/9 migrating an application from st7263 rev.b to st7263b figure 1. ram memory map * program memory and ram sizes are product dependen t. see specific datasheet for more information. 5 feature comparison chart for more detailed information, please refer to the st7263b datasheet. st7263 rev.b st7263b package csdip32w, psdip32, so34 sdip32, so34,so24,tqfp48(7x7) program memory 4k, 8k or16k (otp or rom) 4k, 8 k (flash or rom) or 16k (flash or rom), 32k (flash) ram 256 bytes for 4k and 8k 512 bytes for 16k with 64-byte stack 384 bytes for 4k and 8k 512 bytes for 16k 1024 bytes for 32k with 128-byte stack register map 64 bytes 64 bytes (minor changes) i/os 19 pins 19 pins (unchanged) 12/24 mhz oscillator selected in miscellaneous register selected in option byte miscr register yes not upward compatibility watchdog yes yes (unchanged) 16-bit timer yes yes (minor change in pwm and one shot modes) i2c yes yes (unchanged) sci yes new features, not upward compatible adc yes yes (unchanged) lvd selected in miscellaneous register selected in option byte usb yes yes (unchanged) power supply 3.0 v to 5.5 v 4.0 v to 5.5 v reset reset pad pull-up is 30 k ? reset pad pull-up is 100 k ? interrupt vector map fff0 - ffff ffee - fffe (due to flash it insertion) 0100h 017fh 00ffh 0040h 0180h 01bf/023f/043fh short addressing stack (64 bytes) 0100h 0140h 023fh 0040h 00ffh 013fh 16-bit ram (192 bytes) (256 bytes) addressing ram short addressing stack (128 bytes) 16-bit ram (192 bytes) addressing ram st7263 rev. b st7263b
9/9 migrating an application from st7263 rev.b to st7263b ?the present note which is for guidance only aims at providing cus - tomers with information regarding their products in order for them to save time. as a result, stmicroelectronics shall not be held liable for any direct, indirect or conseq uential damages with respect to any claims arising from the content of su ch a note and/or the use made by customers of the information contained herein in connexion with their products.? information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com
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