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preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 1 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 figure: mechanical dimensions 1 4g b ddr3 l C sdram ecc so - u dimm 204 pin ecc so - u dimm sl n0 4 g72f1b a 1 hy - xx r t 4 gbyte in fbga techn ology rohs compliant *) the refresh rate has to be doubled when 85c preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 3 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 event# temperature event: the event# pin is asserted by the temperature sensor when critical v dd supply voltage ( 1.35v - 0.067v/+0.1v and 1.5v 0.075v) v ref dq referen ce voltage: dq, dm (v dd /2) v ref ca reference voltage: control, command, and address (v dd /2) v ss ground v tt termination voltage: used for control, command, and address (v dd /2). v ddspd serial eeprom positive power supply scl serial clock for presence det ect sda serial data out for presence detect sa0 C sa1 presence detect address inputs odt0 on - die termination nc no connection pin configuration frontside pin symbol pin symbol pin symbol pin symbol 1 v refdq 53 v ss 103 a3 155 v ss 3 v ss 55 dq24 105 a1 157 dm5 5 dq0 57 dq25 107 a0 159 dq42 7 dq1 59 dm3 109 v dd 161 dq43 9 v ss 61 v ss 111 ck0 163 v ss 11 dm0 63 dq26 113 ck0# 165 dq48 13 dq2 65 dq27 115 v dd 167 dq49 15 dq3 67 v ss 117 a10/ap 169 v ss 17 v ss 69 cb0 119 ba0 171 dqs6# 19 dq8 71 cb1 121 we# 173 dqs6 21 dq9 key 123 v dd 175 v ss 23 v ss 73 v ss 125 cas# 177 dq50 25 dqs1# 75 dqs8# 127 s0# 179 dq51 27 dqs1 77 dqs8 129 nc( s1# ) 181 v ss 29 v ss 79 v ss 131 v dd 183 dq56 31 dq10 81 cb2 133 dq32 185 dq57 33 dq11 83 cb3 135 dq33 187 v ss 35 v ss 8 5 v dd 137 v ss 189 dm7 37 dq16 87 cke0 139 dqs4# 191 dq58 39 dq17 89 nc( cke1 ) 141 dqs4 193 dq59 41 v ss 91 ba2 143 v ss 195 v ss 43 dqs2# 93 v dd 145 dq34 197 sa0 45 dqs2 95 a12/bc# 147 dq35 199 v ddspd 47 v ss 97 a8 149 v ss 201 sa1 49 dq18 99 a5 151 dq40 203 v tt 51 dq19 101 v dd 153 dq41 (sig): signal in brackets may be routed to the socket connector, but is not used on the module preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 4 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 backside pin symbol pin symbol pin symbol pin symbol 2 v ss 54 dq28 104 a4 156 dqs5 4 dq4 56 dq29 106 a2 158 v ss 6 dq5 58 v ss 108 ba1 160 dq46 8 v ss 60 dqs3# 110 v dd 162 dq47 10 dqs0# 62 dqs3 112 nc( ck1 ) 164 v ss 12 dqs0 64 v ss 114 nc( ck1 #) 166 dq52 14 v ss 66 dq30 116 v dd 168 dq53 16 dq6 68 dq31 118 nc( s3# ) 170 v ss 18 dq7 70 v ss 120 nc( s2# ) 172 dm6 20 v ss 72 cb4 122 ras# 174 dq54 22 dq12 key 124 v dd 176 dq55 24 dq13 74 cb5 126 odt0 178 v ss 26 v ss 76 dm8 128 nc( odt1 ) 180 dq60 28 dm1 78 v ss 130 a13 182 dq61 30 reset# 80 cb6 132 v dd 184 v ss 32 v ss 82 cb7 134 dq36 186 dqs7# 34 dq14 84 v refca 136 dq37 188 dqs7 36 d q15 86 v dd 138 v ss 190 v ss 38 v ss 88 a15 140 dm4 192 dq62 40 dq20 90 a14 142 dq38 194 dq63 42 dq21 92 a9 144 dq39 196 v ss 44 dm2 94 v dd 146 v ss 198 event# 46 v ss 96 a11 148 dq44 200 sda 48 dq22 98 a7 150 dq45 202 scl 50 dq23 100 a6 152 v ss 204 v tt 52 v ss 102 v dd 154 dqs5# (sig): signal in brackets may be routed to the socket connector, but is not used on the module preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 5 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 functional block diagramm 4096 mb ddr3 sdram so - u dimm, 1 rank and 9 components i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 0 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 1 dqs cs dq 0 dq 1 dq 2 dq 3 dq 5 dq 4 dq 6 dq 7 s 0 dqs 0 dqs 0 dm 0 dqs 1 dqs 1 dm 1 dq 8 dq 9 dq 10 dq 11 dq 13 dq 12 dq 14 dq 15 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 2 dqs cs dqs 2 dqs 2 dm 2 dq 16 dq 17 dq 18 dq 19 dq 21 dq 20 dq 22 dq 23 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 3 dqs cs dqs 3 dqs 3 dm 3 dq 24 dq 25 dq 26 dq 27 dq 29 dq 28 dq 30 dq 31 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 4 dqs cs i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 5 dqs cs dq 32 dq 33 dq 34 dq 35 dq 37 dq 36 dq 38 dq 39 dqs 4 dqs 4 dm 4 dqs 5 dqs 5 dm 5 dq 40 dq 41 dq 42 dq 43 dq 45 dq 44 dq 46 dq 47 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 6 dqs cs dqs 6 dqs 6 dm 6 dq 48 dq 49 dq 50 dq 51 dq 53 dq 52 dq 54 dq 55 i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 7 dqs cs dqs 7 dqs 7 dm 7 dq 56 dq 57 dq 58 dq 59 dq 61 dq 60 dq 62 dq 63 v ddspd spd v dd / v ddq d 0 - d 8 v refdq v refca d 0 - d 8 d 0 - d 8 d 0 - d 8 v ss notes : 1 . dq - to - i / o wiring is shown as recommended but may be changed . 2 . dq / dqs / dqs / odt / dm / cke / s relationship must be maintained as shown . 3 . dq , dm , dqs / dqs resistors : refer to associated topology diagram . 4 . refer to the appropriate clock wiring topology under the dimm wiring details section of the jeded document . 5 . for each dram , a unique zq resistor is connected to gnd . the zq resistor is 240 o 1 %. 6 . refer to associated figure for spd details . i / o 0 i / o 1 i / o 2 i / o 3 i / o 5 i / o 4 i / o 6 i / o 7 dm dqs zq d 8 dqs cs dqs 8 dqs 8 dm 8 cb 0 cb 1 cb 2 cb 3 cb 5 cb 4 cb 6 cb 7 ba 0 - ba 2 ba 0 - ba 2 : sdram d 0 - d 8 a 0 - a 14 a 0 - a 14 : sdram d 0 - d 8 ras ras : sdram d 0 - d 8 cas cas : sdram d 0 - d 8 we we : sdram d 0 - d 8 odt 0 odt : sdram d 0 - d 8 cke 0 cke : sdram d 0 - d 8 ck 0 ck : sdram d 0 - d 8 ck 0 ck : sdram d 0 - d 8 reset reset : sdram d 0 - d 8 preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 6 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 maximum electrical dc characteristics parameter/ condition symbol min max units supply voltage v dd - 0.4 1.975 v i/o supply voltage v dd q - 0.4 1.975 v voltage on any pin relative to v ss v in , v out - 0.4 1.975 v input leakage current any input 0v v in v dd, v ref pin 0v v in 0.95v (all other pins not under test = 0v) i i a command/address ras#, cas#, we#, s#, cke - 16 16 ck, ck# - 16 16 dm - 2 2 output leakage current (dqs and odt are disabled; 0v v out v dd q ) i oz - 5 5 a dq, dqs, dqs# v ref leakage current ; v ref is on a valid level i vref - 8 8 a dc operating conditions parameter/ condition symbol min nom max units supply voltage v dd 1.283 1.35 1.450 v i/o supply voltage v dd q 1.283 1.35 1.450 v i/o refe rence voltage v ref 0.49 x v dd q 0.50 x v dd q 0.51x v dd q v i/o termination voltage (system) v tt 0.49 x v dd q - 20mv 0.50 x v dd q 0.51x v dd q +20mv v input high (logic 1) voltage v ih (dc 90 ) v ref + 90mv v dd q + 0.3 v input low (logic 0) voltage v il (dc 90 ) - 0.3 v ref C under 1.5v operation this ddr3l device operates in accordance to the following specification: sgn04g72f1b a 1 hy - xxrt ac input operating conditions parameter/ condition symbol min max units input high (logic 1) voltage v ih (ac 135 ) v ref + 0.1 35mv - v input low (logic 0) voltage v il (ac 135 ) - v ref C 0 .135mv v capacitance at ddr3 data rates, it is recommended to simulate the performance of the module to achieve optimum values. when inductance and delay parameters associated with trace l engths are used in simulations, they are significantly more accurate and realistic than a gross estimation of module capacitance. simulations can then render a considerably more accurate result. jedec modules are now designed by using simulations to close timing budgets. preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 7 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 i dd specifications and conditions (0c t case + 85c; v dd q , v dd = +1. 283 v C 1.45v ) parameter & test condition max. symbol 12800 - cl11 10600 - cl9 unit operating current *) : one device bank active - precharge; t rc = t rc (i dd ); t ck = t ck (i dd ); cke is high, cs# is high between valid commands; dq inputs changing once per clock cycle; address and control inputs changing once every two clock cycles i dd0 264 256 ma operating current *) : one device bank; active - read - precharge; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address inputs changing once every two clock cycles; data pattern is same as i dd4w i dd1 320 312 ma precharge power - down current: all device banks idle; powe r - down mode; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref fast exit i dd2p 80 80 ma slow exit 64 64 precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high , cs# is high; all control and address bus inputs are not changing; dqs are floating at v ref i dd2q 136 136 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, cs# is high; all other control and address bus inputs are ch anging once every two clock cycles; dq inputs changing once per clock cycle i dd2n 136 128 ma active power - down current: all device banks open; t ck = t ck (i dd ); cke is low; all control and address bus inputs are not changing; dqs are floating at v ref (a lways fast exit) i dd3p 144 136 ma active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; all other control and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd3n 208 200 ma operating read current: all device banks open, continuous burst reads; one module rank active; i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4r 680 600 ma preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 8 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 parameter & test condition max. symbol 1 2800 - cl11 10600 - cl9 unit operating write current: all device banks open, continuous burst writes; one module rank active; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, cs# is high between valid commands; address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd4w 720 640 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval, cke is high, cs# is high between valid commands; all other cont rol and address bus inputs are changing once every two clock cycles; dq inputs changing once per clock cycle i dd5 1600 1600 ma self refresh current: ck and ck# at 0v; cke 0.2v; all other control and address bus inputs are floating at v ref ; dqs are fl oating at v ref i dd6 96 96 ma operating current *) : four device bank interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) C 1 x t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, cs# is high between valid commands; address bus inputs are not changing during deselect; dq inputs changing once per clock cycle i dd7 1080 1040 ma *) value calculated as one module rank in this operating condition, and all other module ranks in idd2p (cke low) mode. timing values used for i dd measurement i dd measurement conditions symbol 12800 - cl11 10600 - cl9 unit cl (i dd ) 11 9 t ck t rcd (i dd ) 13. 75 13. 5 ns t rc (i dd ) 48.75 49.5 ns t rrd (i dd ) 6 6 ns t ck (i dd ) 1.25 1.5 ns t ras min (i dd ) 35 36 ns t ras max (i dd ) 70 200 70 200 ns t rp (i dd ) 13.75 13.5 ns t rfc (i dd ) 260 260 ns preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 9 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical characteristics and recommended ac operating conditions (0c t case + 85c; v dd q , v dd = +1. 283 v C 1.45v ) ac characteristics 12800 - cl11 10600 - cl9 parameter symbol min max min max unit clock cycle time cl = 11 t ck (11) 1.25 - - - ns cl = 10 t ck (10) 1.5 <1.875 1.5 <1.875 cl = 9 t ck (9) 1.5 <1.87 5 1.5 <1.875 cl = 8 t ck (8) 1.875 <2.5 1.875 <2.5 cl = 7 t ck (7) 1.875 <2.5 1.875 <2.5 cl = 6 t ck (6) 2.5 3.3 2.5 3.3 cl = 5 t ck (5) 3.0 3.3 3.0 3.3 in t ernal read command to first data t aa 13.75 - 13.5 - ck high - level width t ch ( avg ) 0.47 0 .53 0.47 0.53 t ck ck low - level width t cl ( avg ) 0.47 0.53 0.47 0.53 t ck data - out high - impedance window from ck/ck# t hz - 2 25 - 250 ps data - out low - impedance window from ck/ck# t lz - 450 225 - 500 250 ps dq and dm input setup time relative to dqs v ref =1v/n s t ds1v 1 60 - 180 - ps dq and dm input hold time relative to dqs v ref =1v/ns t dh1v 145 - 165 - ps dq and dm input pulse width ( for each input ) t dipw 360 - 400 - ps dqs, dqs# to dq skew, per access t dqsq - 100 - 125 ps dq - dqs hold, dqs to first dq to g o non - valid, per access t qh 0.38 - 0.38 - t ck (avg) dqs input high pulse width t dqsh 0.45 0.55 0.45 0.55 t ck dqs input low pulse width t dqsl 0.45 0.55 0.45 0.55 t ck dqs, dqs# rising to/from ck, ck# t dqsck - 2 25 2 25 - 250 250 ps dqs, dqs# rising to/from c k, ck# when dll disabled t dqsck dll_dis 1 10 1 10 ns dqs falling edge to ck rising - setup time t dss 0. 18 - 0.2 - t ck dqs falling edge from ck rising - hold time t dsh 0. 18 - 0.2 - t ck dqs read preamble t rpre 0.9 note 1 0.9 note 1 t ck dqs read postamble t rpst 0.3 note 2 0.3 note 2 t ck dqs write preamble t wpre 0.9 - 0.9 - t ck dqs write postamble t wpst 0.3 - 0.3 - t ck positive dqs latching edge to associated clock edge t dqss - 0.2 7 + 0.2 7 - 0.25 + 0.25 t ck address and control input pulse width ( for each input ) t ipw 560 - 620 - ps ctrl, cmd, addr setup to ck, ck# t is(base) 45 - 65 - ps ctrl, cmd, addr setup to ck, ck# v ref @ 1v/ns t is(1v) 2 20 - 240 - ps 1 the maximum preamble is bound by t lzdqs (max) 2 the maximum postamble is bound by t hzdqs (max) preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 10 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q , v dd = +1. 283v C 1.45v ) ac characteristics 1 28 00 - cl11 10600 - cl9 parameter symbol min max min max unit ctrl, cmd, addr hold to ck, ck# t ih(base) 1 20 - 140 - ps ctrl, cmd, addr hold to ck, ck# v ref @ 1v/ns t ih(1v) 220 - 24 0 - ps cas# to cas# command delay t ccd 4 - 4 - t ck active to active (same bank) command period t rc 48.75 - 49.5 - ns active to active minimum command period t rrd max 4nck,6ns max 4nck,6ns ns active to read or write delay t rcd 13. 7 5 - 13.5 - ns four ba nk activate period 1k page size t faw 30 - 30 - ns 2k page size 4 0 - 45 - active to precharge command t ras 3 5 70 t rtp max 4nck,7.5ns - max 4nck,7.5ns - ns write recovery time t wr 15 - 15 - ns auto precharge write recovery + precharge time t dal t wr + t rp /t ck - t wr + t rp /t ck - ns internal write to read command delay t wtr max 4nck,7.5ns - max 4nck,7.5ns - ns precharge command period t rp 13.75 - 13.5 - ns load mode command cycle time t mrd 4 - 4 - t ck refresh to active or refresh to refresh command interval t rfc 260 70 0 c t case 85 c t refi - 7.8 - 7.8 s 85 c < t case 95 c t refi (it) - 3.9 - 3.9 rtt turn - on from odtl on reference t aon - 2 25 2 25 - 250 250 ps rtt turn - on from odtl off reference t aof 0.3 0.7 0.3 0.7 t ck asynchronous rtt turn - on delay (power down with d ll off) t aonpd 2 8,5 2 8,5 ns asynchronous rtt turn - off delay (power down with dll off) t aofpd 2 8,5 2 8,5 ns rtt dynamic change skew t adc 0.3 0.7 0.3 0.7 t ck exit self refresh to commands not requiring a locked dll t xs max 5nck,tr fc + 10ns - max 5nck, tr fc + 10ns - ns write levelling setup from rising ck, ck# crossing to rising dqs, dqs# crossing t wls 1 65 - 195 - ps write levelling setup from rising dqs, dqs# crossing to rising ck, ck# crossing t wlh 1 65 - 195 - ps first dqs, dqs# rising edge t wlmrd 40 - 40 - t ck dqs, dqs# delay t wldqsen 25 - 25 - t ck preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 11 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 ddr3 sdram component electrical characteristics and recommended ac operating conditions (continued) (0c t case + 85c; v dd q , v dd = +1. 283v C 1.45v ) ac characteristics 128 00 - cl11 10600 - cl9 pa rameter symbol min max min max unit exit reset from cke high to a valid command t xpr max 5nck, t rfc + 10ns - max 5nck, t rfc + 10ns - t ck begin power supply ramp to power supplies stable t v ddpr - 200 - 200 ms reset# low to power supplies stable t rps 0 20 0 0 200 ms reset# low to i/o and rtt high - z t ioz - 20 - 20 ns exit precharge power - down to any non - read command t xp max 3nck,6ns - max 3nck, 6 ns - t ck cke minimum high/low time t cke max 3nck, 5 ns - max 3nck, 5.625ns - t ck temperature sensor with seri al presence - detect eeprom temperature sensor with serial presence - detect eeprom operating conditions parameter / condition symbol min max unit supply voltage v ddspd +3 +3.6 v supply current: v dd = 3.3v i dd +2.0 ma input high voltage: logic 1; scl, sda v ih +1.45 v ddspd +1 v input low voltage: logic 0; scl, sda v il - 550 mv output low voltage: i out = 2.1ma v ol - 400 mv input current i in - 5.0 5.0 a temperature sensing range t . b . d t . b . d c temperature sensor accuracy t . b . d t . b . d c s c l s d a e v e n t s a 2 s a 1 s a 1 s a 0 s a 0 e v e n t w p / r 1 0 preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 12 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 a.c. characteristics of temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c symbol parameter / condition min max unit f scl scl clock frequency 10 400 khz t buf bus free time between stop and start 1300 ns t f sda fall time 300 ns t r sda rise time 300 ns t hd:dat data hold time (accepted for input data) 0 ns data hold time (guaranteed for output data) 300 900 ns t h:sta start condition hold time 600 ns t high high period of scl 600 ns t low low period of scl 1300 ns t su: dat data setup time 100 ns t su:sta start condition setup time 600 ns t su:sto stop condition setup time 600 ns t timeout smbus scl clock low timeout 25 35 ms t i noise pulse filtered at scl and sda inputs 100 ns t wr write cycle time 5 ms t pu power - up delay to valid temperature recording 100 ms temperature characteristics of temperature sensor v cc = 3.3 v 10%, t a = ?40c to +125c parameter test conditions/comments max unit temperature reading error class b, jc42.4 compliant +75c t a +95c +40c t a +125c, monitor range 40c t a +125c, sensing range 1 ja junction - to - ambient (still air) 9 2 c/w 1 power dissipation is defined as p j = (t j ? t a )/ ja , where tj is the junction temperature and ta is the ambient temperature. the thermal resistance value refers to the case of a package being used on a standard 2 - layer pcb. slave address bits of temperature sensor device device type identifier select address signals r/w# b7 1 b6 b5 b4 b3 b2 b1 b0 eeprom 1 0 1 0 a 2 a 1 a 0 r/w# temp. sensor 0 0 1 1 a 2 a 1 a 0 r/w# 1 the most significant bit, b7, is sent first. preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 13 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 serial presence - detect matrix byte byte description 12800 - cl11 10600 - cl9 0 crc range, eeprom bytes, bytes used 0x92 1 spd revison 0x1 1 2 dram device type 0x0b 3 module type (form factor) 0x0 8 4 sdram device density & banks 0x0 4 5 sdram device row & column count 0x 21 6 module nominal voltage, v dd 0x0 2 7 module ranks & device dq count 0x01 8 ecc tag & module memory bus width 0x0 b 9 fine timebase dividend/divisor 0x 11 10 medium timebase dividend 0x01 11 medium timebase divisor 0x08 12 min sdram cyc le time (t ck min ) 0x0a 0x0c 13 by te 13 reserved 0x00 14 cas latencies supported (cl4 => cl11) 0xfe 0x 3 e 15 cas latencies supported (cl12 => cl18) 0x00 16 min cas latency time ( t aa min ) 0x69 17 min write recovery time ( t wr min ) 0x78 18 min ras# to cas# delay ( t rcd min ) 0x69 19 min ro w active to row active delay ( t rrd min ) 0x30 20 min row precharge delay ( t rp min ) 0x69 21 upper nibble for t ras & t rc 0x11 22 min active to precharge delay ( t ras min ) 0x18 0x20 23 min active to active/refresh delay ( t rc min ) 0x81 0x89 24 min refresh r ecovery delay ( t rfc min ) lsb 0x 20 25 min refresh recovery delay ( t rfc min ) msb 0x 08 26 min internal write to read cmd delay ( t wtr min ) 0x3c 27 min internal read to precharge cmd delay ( t rtp min ) 0x3c 28 min four active window delay ( t faw min ) msb 0x00 29 min four active window delay ( t faw min ) lsb 0xf0 30 sdram device output drivers supported 0x8 3 31 sdram device thermal & refresh options 0x0 1 preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 14 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 byte byte description 12800 - cl11 10600 - cl9 32 module thermal sensor 0x80 3 3 - 59 bytes 32 - 59 reserved 0x 00 60 module height (nominal) 0x0f 61 module thickness (max) 0x11 62 reference raw card id 0x 0 2 63 address mapping edge conector to dram 0x00 64 - 116 bytes 64 - 116 reseved 0x00 117 module mfr id (lsb) 0x83 118 module mfr id (msb) 0 xda 119 module mfr location id 0x01 (swi t zerland) 0x02 (germany) 0x03 (usa) 120 module mfr year x 121 module mfr week x 122 - 125 module serial number x 126 - 127 crc 0 x 5d0e 0x 5 d09 128 - 145 module part number " sln 0 4 g72f1b a 1 hy - xx" 146 module die rev x 147 module pcb rev x 148 dram device mfr id (lsb) 0x80 149 dram device mfr (msb) 0x ad 150 - 175 mfr reserved bytes 150 - 175 0x00 176 - 255 customer reserved bytes 176 - 255 0 xff part number code s l n 0 4 g 72 f1 b a 1 hy - d c * r ** 1 2 3 4 5 6 7 8 9 10 11 12 13 14 *rohs compl. swissbit ag ddr3 - 1 600 mt/s sdram d dr 3 l 204 pin so - dimm chip vendor ( hynix ) capacity ( 4 g b yte ) 1 module rank width (72bit) chip rev. a pcb - type (b83s 781 1 . 0 0) chip orga nisation x8 * optional / additional information ** t=thermal sensor preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 15 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 revision history revision changes date 0.9 preliminary version 11 . 06 .20 1 3 preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 16 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 locations swissbit ag industriestrasse 4 ch C 9552 bronschhofen switzerland phone: +41 (0)71 913 03 03 fax: +41 (0)71 913 03 15 _____________________________ swissbit germany gmbh wolfener strasse 36 d C 12681 berlin germany phone: +49 (0)30 93 69 54 C 0 fax: +49 (0)30 93 69 54 C 55 ________ _____________________ swissbit na, inc. 1117 e plaza drive unit e suites 105/205 eagle, id 83616 usa phone: +1 208 258 - 6254 fax: +1 208 938 - 4525 _____________________________ swissbit japan, inc. 3f core koenji, 2 - 1 - 24 koenji - kita, suginami - ku, tokyo 1 66 - 0002 japan phone: +81 3 5356 3511 fax: +81 3 5356 3512 ________________________________ preliminary data sheet rev.0.9 11.06.2013 swissbit ag indu striestrasse 4 fon: +41 (0) 71 913 03 03 www.swissbit.com page 17 ch C 9552 bronschhofen fax: +41 (0) 71 913 03 15 email: info@swissbit.com of 17 declaration of conformity we manufacturer: swissbit ag industriestrasse 4 ch - 9552 bronschhofen switzerland declare under our sole re sponsibility that the product product type: 4 gb ddr3 l so - u dimm brand name: swissmemory? product series: ddr3 l so - udimm part number: s ln0 4 g72f1b a 1 hy - xxxr t to which this declaration relates is in conformity with the following directives: 2002/96/ec category 3 (weee) following the provisions of directive rest riction of the use of certain hazardous substances 2011/65/eu swissbit ag, juni 2013 manuela k?gel head of quality management |
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