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rev. 1.2 12/00 copyright ? 2000 by silicon laboratories si3036-ds12 si3036 fcc/jate mc?97 s ilicon daa features complete daa includes the following: applications description the si3036 is an integrated direct access arrangement (daa) chipset that provides a digital, programmable interface to a telephone line. available in two 16-pin small outline packages (ac?97 interface on si3024 and phone-line interface on si3012), the chipset eliminates the need for an analog front end (afe), an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. the si3036 dramatically reduces the number of discrete components and cost required to achieve compliance with fcc part 68 and jate. the si3024 complies with the ac?97 2.1 specification. functional block diagram ! ac?97 2.1 compliant ! primary or secondary codec ! phone line interface compliant with fcc part 68 and jate ! 86 db dynamic range tx/rx paths ! 3.3 or 5 v power supply ! 3000 v isolation ! integrated ring detector ! wake-up on ring ! caller id support ! integrated analog front end ! 2- to 4-wire hybrid ! low-power standby mode ! low profile soic packages ! patented isocap? technology ! software modems ! audio/telephony sub-systems ! audio/modem riser cards (amr) ! mobile daughter cards (mdc) ! mini-pci cards si3024 si3012 clock control interface isolation interface hybrid isolation interface dc termination out in xout mclk/xin bit_clk sync gpio_a gpio_b reset sdata_in ac'97 digital interface sdata_out ido id1 tx rx hybd vreg2 vreg dct rext ignd rng1 rng2 qb qe ring detect off-hook us patent # 5,870,046 us patent # 6,061,009 other patents pending ordering information see page 50. pin assignments si3024 (soic) si3024 (tssop) si3012 (soic or tssop) 9 10 11 12 13 16 15 14 gpio_a gpio_b id1 v a gnd c1a id0 aout mclk/xin xout bit_clk v d sdata_in sdata_out sync reset 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 v d bit_clk xout mclk/xin gpio_a gpio_b id1 v a sdata_in sdata_out sync reset aout id0 c1a gnd 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 tsta tstb ignd c1b rng1 rng2 qb qe tx nc rx rext dct hybd vreg2 vreg
si3036 2 rev. 1.2
si3036 rev. 1.2 3 t able of c ontents section page electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 si3036 schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ac-link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 jate support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 isolation barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 off-hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ring detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 wake-up on ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 pulse dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 on-hook line monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 caller id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 loop current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 analog output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 filter selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 in-circuit testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 lightning test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 safety and isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 si3024 as secondary device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 si3024 as primary mc?97 codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 si3024 connection to the digital ac?97 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 resetting si3036 chipset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 ac-link digital serial interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 codec register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ac-link low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 appendix?ul1950 3rd edition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 pin descriptions: si3024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 pin descriptions: si3012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 soic outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 tssop outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4
si3036 4 rev. 1.2 electrical specifications table 1: recommended operating conditions parameter 1 symbol test condition min 2 typ max 2 unit ambient temperature 3 t a k-grade 0 25 70 c si3024 supply voltage, analog v a 4.75 5.0 5.25 v si3024 supply voltage, digital 4 v d v a = 5 v 4.75 5.0 5.25 v si3024 supply voltage, digital 4 v d v a = charge pump 3.0 3.3 3.6 v notes: 1. the si3036 specifications are guaranteed when the typical application circuit (including component tolerances) of figure 19 and any si3024 and si3012 are used. 2. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25c unless otherwise stated. 3. the temperature specifications are guaranteed when using the typical application circuit on a 4 sq. in. minimum fr4 pcb. for other materials and smaller form factors, heat dissipation factors may apply. contact silicon laboratories for more details. 4. the digital supply, v d, can operate from either 3.3 v or 5.0 v. the si3024 supports interface to 3.3 v logic when operating from 3.3 v. 3.3 v operation applies to both the ac?97 digital interface and the digital signals reset , id0 , and id1 . table 2: loop characteristics (v d = 3.0 to 3.6 v, v a = charge pump, t a = 0 to 70c, see figure 1) parameter symbol test condition min typ max unit dc termination voltage v tr i l = 20 ma ? ? 7.7 v dc termination voltage v tr i l = 105 ma 12 ? ? v dc ring current i rdc w/ caller id ? ? 1 ma dc ring current i rdc w/o caller id ? ? 20 a ac termination impedance z act ?600 ? ? operating loop current i lp 20 ? 120 ma loop current sense bits lcs lcs = fh 180 155 ? ma ring detect voltage v rd 13 18 26 v rms ring frequency f r 15 ? 68 hz on-hook leakage current i lk v tr = ?48 v ? ? 1 a ringer equivalence number ren w/ caller id ? 1.0 1.67 ringer equivalence number ren w/o caller id ? 0.2 ?
si3036 rev. 1.2 5 figure 1. test circuit for loop characteristics table 3: dc characteristics, v d = + 5 v (v a = 4.75 to 5.25 v, v d = 4.75 to 5.25 v, t a = 0c to 70c) parameter symbol test condition min typ max unit high level input voltage v ih 3.5 ? ? v low level input voltage v il ??0.8 v high level output voltage v oh i o = ?2 ma 2.4 ? ? v low level output voltage v ol i o = 2 ma ? ? 0.4 v input leakage current i l ?10 ? 10 a power supply current, analog i a v a pin ? 0.1 2 ma power supply current, digital i d v d pin ? 14 17 ma total supply current, sleep mode i a + i d ??1.5ma table 4: dc characteristics, v d = + 3.3 v (v d = 3.0 to 3.6 v, v a = charge pump, t a = 0 to 70c) parameter symbol test condition min typ max unit high level input voltage v ih 2.4 ? ? v low level input voltage v il ??0.8 v high level output voltage v oh i o = ?2 ma 2.4 ? ? v low level output voltage v ol i o = 2 ma ? ? 0.35 v input leakage current i l ?10 ? 10 a power supply current, digital i d v d pin ? 12 14.5 ma total supply current, sleep mode i a + i d ?1.53.0ma note: the remainder of the circuit is identical to the one shown in figure 19 on page 15. tip ring + ? si3012 v tr 600 ? 10 f i l
si3036 6 rev. 1.2 table 5: ac characteristics (v d = 3.0 to 5.25 v, v a = charge pump, t a = 0 to 70c) parameter symbol test condition min typ max unit freq response, transmit 1 f rt low ?3 db corner ? 16 ? hz transmit full scale level 2 (0 db gain) v tx ?0.98 ?v peak freq response, receive 1 f rr low ?3 db corner ? 16 ? hz receive full scale level 2,3 (0 db gain) v rx ?0.98 ?v peak dynamic range 4 dr vin = 1 khz, ?3 dbfs 80 86 ? db dynamic range 5 dr vin = 1 khz, ?3 dbfs ? 84 ? db total harmonic distortion 6 thd vin = 1 khz, ?3 dbfs ? ?84 ? db dynamic range (call progress aout) dr ao vin = 1 khz 60 ? ? db thd (call progress aout) thd ao vin = 1 khz ? 1.0 ? % aout full scale level ? 0.75v a ?v pp aout output impedance ? 10 ? k ? mute level (call progress aout) ?90 ? ? dbfs dynamic range (caller id mode) dr cid vin = 1 khz, ?13 dbfs ? 60 ? db caller id full scale level (0 db gain) 2 v cid ?0.8 ?v peak notes: 1. these characteristics are determined by external components. see figure 19 on page 15. 2. parameter measured at tip and ring of figure 19 on page 15. 3. receive full scale level will produce ?0.9 dbfs at sdata_in. 4. dr = 3 db + 20log (rms signal/rms noise). applies to both transmit and receive paths. measurement bandwidth is 300 to 3400 hz. sample rate = 9.6 khz, loop current = 40 ma. 5. dr = 3 db + 20log (rms signal/rms noise). applies to both transmit and receive paths. measurement bandwidth is 15 to 3400 hz. sample rate = 9.6 khz, loop current = 40 ma. 6. thd = 20log (rms distortion/rms signal). this applies to both the transmit and receive paths. sample rate = 9.6 khz, loop current = 40 ma. table 6: absolute maximum ratings parameter symbol value unit dc supply voltage v d , v a ?0.5 to 6.0 v input current, si3024 digital input pins i in 10 ma digital input voltage v ind ?0.3 to (v d + 0.3) v operating temperature range t a ?40 to 100 c storage temperature range t stg ?65 to 150 c note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
si3036 rev. 1.2 7 figure 2. cold reset timing diagram figure 3. warm reset timing diagram table 7: ac link timing characteristics?cold reset (v d = 3.0 to 3.6 v, v a = charge pump, t a = 25c, c l = 50 pf) parameter symbol min typ max unit reset active low pulse width t rst_low 1.0 ? ? s reset inactive to bit_clk startup delay t rst2clk 162.8 ? ? ns table 8. ac link timing characteristics?warm reset (v d = 3.0 to 3.6 v, v a = charge pump, t a = 25c, c l = 50 pf) parameter symbol min typ max unit sync active high pulse width t sync_high 1.0 ? ? s sync inactive to bit_clk startup delay t sync2clk 162.8 ? ? ns t rst_low t rst2clk reset bit_clk sync bit_clk t sync_high t sync2clk
si3036 8 rev. 1.2 figure 4. clocks timing diagram table 9. ac link timing characteristics?clocks (v d = 3.0 to 3.6 v, v a = charge pump, t a = 25c, c l = 50 pf) parameter symbol min typ max unit bit_clk frequency ? 12.288 ? mhz bit_clk period t clk_period ? 81.4 ? ns bit_clk output jitter ? ? 750 ps bit_clk high pulse width* t clk_high 36 40.7 45 ns bit_clk low pulse width* t clk_low 36 40.7 45 ns sync frequency ? 48.0 ? khz sync period t sync_period ? 20.8 ? s sync high pulse width t sync_high ?1.3? s sync low pulse width t sync_low ? 19.5 ? s *note: worst case duty cycle restricted to 45/55. sync bit_clk t clk_high t clk_low t sync_low t sync_period t sync_high t clk_period
si3036 rev. 1.2 9 figure 5. data setup and hold timing diagram figure 6. signal rise and fall timing diagram table 10. ac link timing characteristics?data setup and hold (v d = 3.0 to 3.6 v, v a = charge pump, t a = 25c, c l = 50 pf) parameter symbol min typ max unit setup to falling edge of bit_clk t setup 15.0 ? ? ns hold from falling edge of bit_clk t hold 5.0 ? ? ns table 11. ac link rise and fall times (v d = 3.0 to 3.6 v, v a = charge pump, t a = 25c, c l = 50 pf) parameter symbol min typ max unit bit_clk rise time trise clk 2?6ns bit_clk fall time tfall clk 2?6ns sync rise time trise sync 2?6ns sync fall time tfall sync 2?6ns sdata_in rise time trise din 2?6ns sdata_in fall time tfall din 2?6ns sdata_out rise time trise dout 2?6ns sdata_out fall time tfall dout 2?6ns sync bit_clk t setup t hold sdata_out sdata_in sync bit_clk sdata_out sdata_in trise clk tfall clk trise sync tfall sync trise din tfall din trise dout tfall dout
si3036 10 rev. 1.2 figure 7. ac-link low power mode timing diagram figure 8. ate test mode timing diagram table 12. ac link timing characteristics? low power mode timing (v d = 3.0 to 3.6 v, v a = charge pump, t a = 25c, c l = 50 pf) parameter symbol min typ max unit end of slot 2 to bit_clk, sdata_in low t s2_pdown ??1.0s table 13. ate test mode (v d = 3.0 to 3.6 v, v a = charge pump, t a = 25c, c l = 50 pf) parameter 1,2 symbol min typ max unit setup to falling edge of reset (also applies to sync) t setup2rst 15.0 ? ? ns rising edge of reset to hi-z delay t off ? ? 25.0 ns notes: 1. all ac link signals are normally low through the trailing edge of reset . bringing sdata_out high for the trailing edge of reset causes ac?97 ac-link outputs to go high impedance, which is suitable for ate in circuit testing. 2. when the test mode has been entered, ac?97 must be issued another reset with all ac-link signals low to return to the normal operating mode. sync bit_clk data_out sdata_in slot 1 slot 2 write to 0x56 data mlnk don't care t s2_pdown note: bit_clk not to scale reset sdata_out sdata_in, bit_clk t setup2rst hi-z t off
si3036 rev. 1.2 11 table 14: digital fir filter characteristics?transmit and receive (v d = 3.0 to 3.6 v, v a = charge pump, sample rate = 8 khz, t a = 70c) parameter symbol min typ max unit passband (0.1 db) f (0.1 db) 0?3.3khz passband (3 db) f (3 db) 0?3.6khz passband ripple peak-to-peak ?0.1 ? 0.1 db stopband ? 4.4 ? khz stopband attenuation ?74 ? ? db group delay t gd ? 12/fs ? sec note: typical fir filter characteristics for fs = 8000 hz are shown in figures 9, 10, 11, and 12. table 15: digital iir filter characteristics?transmit and receive (v d = 3.0 to 3.6 v, v a = charge pump, sample rate = 8 khz, t a = 70c) parameter symbol min typ max unit passband (3 db) f (3 db) 0?3.6khz passband ripple peak-to-peak ?0.2 ? 0.2 db stopband ? 4.4 ? khz stopband attenuation ?40 ? ? db group delay t gd ? 1.6/fs ? sec note: typical iir filter characteristics for fs = 8000 hz are shown in figures 13, 14, 15, and 16. figures 17 and 18 show group delay versus input frequency.
si3036 12 rev. 1.2 figure 9. fir receive filter response figure 10. fir receive filter passband ripple figure 11. fir transmit filter response figure 12. fir transmit filter passband ripple for figures 9?12, all filter plots apply to a sample rate of fs = 8 khz. the filters scale with the sample rate as follows: f (0.1 db) = 0.4125 fs f (?3 db) = 0.45 fs where fs is the sample frequency. input frequency?hz attenuation?db input frequency?hz attenuation?db attenuation?db input frequency?hz input frequency?hz attenuation?db
si3036 rev. 1.2 13 figure 13. iir receive filter response figure 14. iir receive filter passband ripple figure 15. iir transmit filter response figure 16. iir transmit filter passband ripple for figures 13?16, all filter plots apply to a sample rate of fs = 8 khz. the filters scale with the sample rate as follows: f (?3 db) = 0.45 fs where fs is the sample frequency. input frequency?hz attenuation?db input frequency?hz attenuation?db input frequency?hz attenuation?db input frequency?hz attenuation?db
si3036 14 rev. 1.2 figure 17. iir receive group delay figure 18. iir transmit group delay input frequency?hz delay?s input frequency?hz delay?s
si3036 rev. 1.2 15 typical application circuit sync fb1 q2 r21 j1 rj-11 1 2 3 4 5 6 aout + c5 r23 z4 r22 c6 c24 c8 c3 c4 reset# u1 si3024 2 1 3 4 5 6 7 89 10 11 12 13 14 15 16 xout mclk/xin bit_clk vd sdata_in sdata_out sync reset aout id0 c1a gnd va id1 gpio_b gpio_a +3.3vd c12 z5 d4 bav99 r6 c35 c34 z1 r1 d3 bav99 r18 sdata_in id1# q1 d2 c25 c2 rv1 r27 c20 bitclk rv2 c7 y1 24.576 mhz c16 c31 no ground plane in daa section c11 c1 c10 id0# r4 note1: if jate support is not required, r21, c12 and c23 may be removed and the following modifications implemented: r21 should be replaced wit h a 0 ohm resistor or shorted, and r4 should be changed to a 604 ohm, 1/ 4 w, +- 1%. note 2: see appendix for applications requiring ul 1950 3rd edition compliance. r5 c30 r28 r10 fb2 sdata_out r2 d1 + c23 c9 c32 u2 si3012 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 tsta tstb ignd c1b rng1 rng2 qb qe vreg vreg2 hybd dct rext rx nc tx q3 r9 figure 19. typical application circuit for the si3036
si3036 16 rev. 1.2 bill of materials table 16. fcc component values?si3036 chipset component 1 value supplier(s) c1,c4 150 pf, 3 kv, x7r, 20% novacap, venkel, johanson, murata, panasonic c2 not installed c3 0.22 f, 16 v, x7r, 20% c5 1 f, 16 v, tant/elec, 20% c6,c10,c16 0.1 f, 16 v, x7r, 20% c7,c8,c9 15 nf, 250 v, x7r, 20% novacap, johanson, murata, panasonic c11 39 nf, 16 v, x7r, 20% c12 2 2.7 nf, 16 v, x7r, 20% c23 2 0.1 f, 16 v, tant/elec/x7r, 20% c24,c25,c31,c32 3 1000 pf, 3 kv, x7r, 10% novacap, venkel, johanson, murata, panasonic c30 4 not installed c34,c35 5 33 pf,16 v, npo, 5% novacap, venkel, johanson, murata, panasonic d1,d2 6 dual diode, 300 v, 225 ma central semiconductor d3,d4 bav99 dual diode, 70 v, 350 mw diodes inc., onsemiconductor, fairchild fb1,fb2 ferrite bead murata q1,q3 a42, npn, 300 v onsemiconductor, fairchild q2 a92, pnp, 300 v onsemiconductor, fairchild rv1 sidactor, 275 v, 100 a teccor, st microelectronics, microsemi, ti rv2 mov, 240 v panasonic r1 51 ? , 1/2 w 5% r2 15 ? , 1/4 w 5% r4 2 ,r18,r21 2 301 ? , 1/10 w, 1% r5,r6 36 k ? , 1/10 w 5% r9,r10 2 k ? , 1/10 w 5% r22,r23 20 k ? , 1/10 w 5% r27,r28 10 ? , 1/10 w 5% u1 si3024 silicon labs u2 si3012 silicon labs y1 4 24.576 mhz, 18 pf, 50 ppm z1 zener diode, 18 v vishay, rohm, onsemi z4,z5 zener diode, 5.6 v, 1/2 w diodes inc., onsemiconductor, fairchild notes: 1. the following reference designators were intentionally omitted: c13?c15, c17?c22, c26?c29, c31?c33, r3, r7, r8, r11?r17, r19, and r20. 2. if jate support is not required, r21, c12, and c23 may be removed and the following modifications implemented: r21 should be replaced with a 0 ? resistor or shorted, and r4 should be changed to a 604 ? , 1/4 w, 1%. 3. alternate population option is c24, c25 (2200 pf, 3 kv, x7r, 10% and c31, c32 not installed). 4. install only if needed for improved radiated emissions performance (10 pf, 16 v, npo, 10%). 5. y1, c34, and c35 should be installed if the si3024 is configured as a primary device. 6. several diode bridge configurations are acceptable (suppliers include general semi, diodes inc.)
si3036 rev. 1.2 17 analog output figure 20 illustrates an optional application circuit to support the analog output capability of the si3036 for call progress monitoring purposes. the aout level can be set to 0 db, ?6 db, ?12 db, and mute for both transmit and receive paths through the atm/arm bits in register 5ch. u1 provides a gain of 26 db. additional gain adjustments may be made by varying the voltage divider created by r1 and r3. figure 20. optional connection to aout for a call progress speaker ? table 17. component values?optional connection to aout symbol value c1 2200 pf, 16 v, 20% c2, c3, c5 0.1 f, 16 v, 20% c4 100 f, 16 v, elec. 20% c6 820 pf, 16 v, 20% r1 10 k ? , 1/10 w, 5% r2 10 ? , 1/10 w, 5% r3 47 k ? , 1/10 w, 5% u1 lm386 aout c5 r2 c4 speaker +5 v 3 2 6 4 + + ? 5 c2 r3 c3 r1 c6 c1 u1
si3036 18 rev. 1.2 functional description the si3036 is an integrated chipset that provides a low- cost, isolated, silicon-based mc97-compliant interface to the telephone line. the chipset reduces cost and board area by eliminating the need for a modem afe or serial codec. it also eliminates the need for an isolation transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. the si3036 complies with the ac?97 2.1 specification and requires only a few low-cost discrete components to achieve full compliance with fcc part 68 and jate out-of-band noise requirements. see figure 19 on page 15 for a typical application circuit. see the pin-compatible si3038 data sheet for designs requiring global compliance. initialization when the si3036 is initially powered up, the reset pin should be asserted. when the reset pin is deasserted, the registers will have default values. this reset condition guarantees the line-side chip (si3012) is powered down with no possibility of loading the line (i.e., off-hook). an example initialization procedure is outlined below: 1. execute a register reset by writing (any value) to register 3ch. 2. program the desired sample rate with register 40h (42h). see register 40h (42h) description on page 33 for allowable sample rates. 3. write 0x0000 to register 3ch to power up the si3036. 4. wait for the si3036 to complete power up. the lower 8 bits indicate that the si3036 is ready. if the si3036 is configured as line #1 codec, 3eh[7:0] = 0x0f indicates readiness. if the codec is configured as line #2, 3eh[7:0] = 0x33 indicates readiness. 5. program gpio registers to desired modes (registers 4ch? 54h). 6. program dac/adc levels with register 46h (48h). after this procedure is complete, the si3036 is ready for ring detection and off-hook operation. ac-link ac-link is a bidirectional, fixed rate, serial pcm digital stream. it handles multiple input and output audio streams and control register accesses employing a time division multiplexed (tdm) scheme. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. the ac-link serial interconnect defines a digital data and control pipe between the controller and the codec. the ac-link supports 12 20-bit slots at 48 khz on sdata_in and sdata_out. the tdm ?slot-based? architecture supports a per-slot valid tag infrastructure that is the source of each slot?s data sets or clears to indicate the validity of the slot data within the current frame. for modem afe, data streams at a variety of required sample rates can be supported. jate support capacitor c23 adds the necessary transmit out-of-band filtering required to meet jate out-of-band noise specifications. the addition of c23 alters the transmit path frequency response which must be balanced with capacitor c12 to obtain maximum hybrid cancellation. products using the si3036 which have been submitted for jate approval should document a waiver for the jate dc termination specification. this specification is met in the si3038 global daa device. isolation barrier the si3036 achieves an isolation barrier through low- cost, high-voltage capacitors in conjunction with silicon laboratories? patented isocap signal processing techniques. these techniques eliminate any signal degradation due to capacitor mismatches, common mode interference, or noise coupling. as shown in figure 19 on page 15, the c1, c2, c4, c24, and c25 capacitors isolate the si3024 (system-side) from the si3012 (line-side). all transmit, receive, control, ring detect, and caller id data are communicated through this barrier. the isocap communications link is disabled by default. the pr bits in register 3eh must be cleared, and the sample rate must be set in register 40h/42h. no communication between the si3024 and si3012 can occur until these conditions are set. off-hook the communication system generates an off-hook command by writing a logic 1 to gpio0 (line 1) or gpio10 (line 2) of slot 12. the off-hook state is used to seize the line for an incoming/outgoing call and can also be used for pulse dialing. when in the on-hook state, negligible dc current flows through the hookswitch. in the off-hook state, the hookswitch transistor pair, q1 & q2, turn on. the net effect of the off-hook signal is the application of a termination impedance across tip and ring and the flow of dc loop current. the termination impedance has both an ac and dc component. the ac termination impedance is a 604- ? resistor, which is connected to the tx pin. the dc termination is a 51- ? resistor, which is connected to the dct pin. when executing an off-hook sequence, the si3036
si3036 rev. 1.2 19 requires 1548/fs seconds to complete the off-hook and provide phone line data on the ac link. this includes the 12/fs filter group delay. if necessary, for the shortest delay, a higher fs may be established prior to executing the off-hook. the delay allows line transients to settle prior to normal use. ring detect the ring signal enters the si3036 through low-value capacitors (c7 and c8) connected to tip and ring. the integrated ring detect of the si3036 chipset allows it to present the ring signal to the ac?97 controller through the ac-link with no additional signaling required. the signal sent to the ac?97 controller is a clipped version of the original ring signal. in addition, the si3036 passes through the caller id data unaltered. the system can detect a ring occurring by the status of the gpio1 (gpio11) bit of slot 12. this bit is set when the line-side device detects a ring signal at rng1 and rng2. when this state occurs, the line-side chip draws a small amount of dc current from the line to provide the digitized line data to the ac?97 controller. the gpio1 (gpio11) bit clears when the system either goes off-hook or 4.5 to 9 seconds after the last ring is detected. the ring information is passed to the ac?97 controller via the sdata_in pin. sdata_in will be ?32768 (8000h) while the rng1-rng2 voltage is between the ring thresholds. when a ring is detected, sdata_in will transition rather quickly to +32767 while the ring signal is positive, then go back to ?32768 while the ring is near zero and negative. thus a near square wave is presented on sdata_in that swings from ?32768 to +32767 in cadence with the ring signal. wake-up on ring ring is an example of an event that might need to wake- up a pc that has suspended into a low-power state. power management (or wake) event support for a modem is a key feature of the current pc industry standards. the si3036 provides wake-up on ring through the ac- link as defined by the ac?97 ver 2.1 specification. in an implementation designed for wake-on ring where the si3036 and ac-link are both completely powered by vaux, a ring detected at the rng1 and rng2 pins of the si3036 causes the assertion of the power management signal to the system. the power management signal is the rising edge of the sdata_in signal when the si3036 is in low-power mode. the power management event signal assertion causes the system to resume so that the modem event (ring) can be serviced. the first thing that the device driver must do to reestablish communications with the si3036 is to command the ac?97 digital controller to execute a warm reset to the ac-link. figure 21 illustrates the entire sequence. the rising edge of sdata_in causes the ac?97 digital controller to assert its power management signal to the system?s acpi controller. the si3036 will keep sdata_in high until it has sampled sync having gone high, and then low (warm reset). the power management event is cleared out in the ac?97 digital controller by system software, asynchronous to ac-link activity. the ac?97 digital controller should always monitor the si3036?s ready bit before sending data to it. the modem driver should read the gpio pin status register to determine if the wake event was due to the ring signal before executing a register reset. before entering the low-power mode, the si3036 must be enabled to cause the wake signal when receiving a ring. this is done by programming the gpio pin sticky (50h) and gpio wake up mask (52h) registers and clearing previous sticky gpio events. before setting the mlnk bit the driver should do the following: 1. set the gs1 bit in register 50h (gs11 if using line #2). 2. set the gw1 bit in register 52h (gw11 for line #2). 3. clear a possible old sticky event by writing a 0 to the gi1 (gi11 for line #2) bit in the read-only register?gpio pin status register (54h). figure 21. ac-link power-down/up sequence sync bit_clk sdata_out power down frame sleep state wake event new audio frame slot 12 prev. frame tag write to 56th data mlnk tag slot 1 slot 2 sdata_in tag tag slot 1 slot 2 slot 12 prev. frame
si3036 20 rev. 1.2 if the ac?97 digital controller allows the reset signal to go low during the low-power mode of the si3036, the wake event will be a cold reset (rising edge of reset ), and the modem driver should reprogram the gpio pin sticky register to set the gs1 (or gs11) bit. this will allow the modem driver to read the sticky value of the gpio pin status register. the si3036 can also be programmed to wake up on events due to gpio_a and gpio_b. pulse dialing pulse dialing is accomplished by going off and on hook to generate make and break pulses. the nominal rate is 10 pulses per second. the si3036 dc holding circuit has active control of the on-hook and off-hook transients to maintain pulse dialing fidelity. on-hook line monitor the si3036 allows the user to receive line activity when in an on-hook state. the line1_cid/line2_cid bit in slot 12 enables a low-power adc which digitizes the signal passed across the rng1/2 pins. this signal is passed across the ac-link to the ac?97 controller. a current of approximately 450 a is drawn from the line when this bit is activated. this mode is typically used to detect caller id data (see the ?caller id? section). the on-hook line monitor can also be used to detect whether a phone line is physically connected to the si3012 and associated circuitry. if a line is present and the line1_cid/line2_cid bit is set, sdata_in will have a near zero value and the lcs[3:0] bits will read 1111b. due to the nature of the low-power adc, the data presented on sdata_in could have up to a 10% dc offset. if no line is connected, the output of sdata_in will move towards a negative full scale value (?32768). the value is guaranteed to be at least 89% of negative full scale. in addition, the lcs[3:0] bits will be zero. caller id using the on-hook line monitor feature, the si3036 provides the designer with the ability to pass caller id data from the phone line to the ac-link interface. in countries where the caller id data is passed on the phone line between the first and second rings, the following method should be utilized to capture the caller id data. the line1_cid/line2_cid bit (gpio2/12 in slot 12) should be set upon completion of the first ring signal. this bit enables a low-power adc (approximately 450 a is drawn from the line) which digitizes the signal passed across the rng1/2 pins. this signal is passed across the isocap to the ac-link interface. the line1_cid/line2_cid bit should be cleared after the caller id data is received and prior to the second ring. due to the nature of the low-power adc, the data presented on sdata_in will have up to a 10% dc offset. the caller id decoder must use either a high pass or band pass filter to accurately retrieve the caller id data. loop current monitor it may be desirable to have a measurement of the loop current being drawn from the line. this measurements can be used to tell whether a telephone line is connected, whether a parallel handset has been picked up, or if excessive loop current is present. when the system is in an off-hook state, the lcs bits of register 5eh indicate the approximate amount of dc loop current. the lcs is a 4-bit value ranging from zero to fifteen. each unit represents approximately 6 ma of loop current from lcs codes 1?14. the typical lcs transfer function is shown in figure 22: figure 22. typical lcs transfer function an lcs value of zero means the loop current is less than required for normal operation and the system should be on-hook. typically, an lcs value of 15 means the loop current is greater than 155 ma. the lcs detector has a built-in hysteresis of 2 ma. this allows for a stable lcs value when the loop current is near a transition level. the lcs value is a rough approximation of the loop current, and the designer is advised to use this value in a relative means rather than an absolute value. this feature enables the modem to determine if an additional line has ?picked up? while the modem is transferring information. in the case of a second phone going off-hook, the loop current falls approximately 50% and is reflected in the value of the lcs bits. 0 5 10 15 lcs bit 0 6 12 18 24 30 36 42 48 54 60 66 72 155 78 84 90 96 loop current (ma)
si3036 rev. 1.2 21 analog output the si3036 supports an analog output (aout) for driving the call progress speaker. aout is an analog signal comprised of a mix of the transmit and receive signals. the aout level can be adjusted via the atm and arm bits in control register 5ch. the transmit portion of aout can be set to ?20 db, ?26 db, ?32 db, or mute. the receive portion of aout can be set to 0 db, ?6 db, ?12 db, or mute. figure 20 on page 17 illustrates a recommended application circuit. note that in the configuration shown, the lm386 provides a gain of 26 db. additional gain adjustments may be made by varying the voltage divider created by r1 and r3. gain control the si3036 supports multiple gain and attenuation settings in register 46h/48h for the receive and transmit paths, respectively. the receive path can support gains of 0, 3, 6, 9, and 12 db, as selected by adc[3:1] bits. the receive path can also be muted by setting bit 7. the transmit path can support attenuations of 0, 3, 6, 9, and 12 db, as selected by dac[3:1] bits. the transmit path can also be muted by setting bit 15. filter selection the si3036 supports additional filter selections for the receive and transmit signals. the iire bit of register 5ch, when set, enables the iir filters. this filter provides a much lower, however non-linear, group delay than the default fir filters. in-circuit testing t he si3036?s advanced design provides the modem manufacturer with increased ability to determine system functionality during production line tests, as well as user diagnostics. several loopback modes exist allowing increased coverage of system components. the loopback mode allows the data pump to provide a digital input test pattern on sdata_in and receive a corresponding digital test pattern back on sdata_out. to enable this mode, set l1b[2:0] (l2b[2:0])=101 in register 56h. in this mode, the isolation barrier is actually being tested. the digital stream is delivered across the isolation capacitors, c1 and c2 of figure 19 on page 15, to the line-side device and returned across the same barrier. the digital dac loopback mode allows data to be sent on the digital path from sdata_in to the digital section of dac to adc to sdata_out. this loopback mode is used when the line-side chip is in power-down mode. to enable this mode, set l1b[2:0] (l2b[2:0])=011 in register 56h. the remote analog loopback mode allows an external device to drive the receive pins of the line-side chip and receive the signal from the transmit pins. this mode allows testing of external components connecting the rj-11 jack (tip and ring) to the line side of the si3012. to enable this mode, set l1b[2:0] (l2b[2:0]) = 100 in register 56h. the adc loopback mode allows an external device to drive the receive pins of the si3012. the signal is then digitized on the si3012 and sent to the si3024, which sends the data back to the si3012. the signal is then converted back to analog. the external device receives the signal on the transmit pins. this mode allows testing of the si3036s converters and external devices between the si3012 and rj-11 jack. to enable this mode, set the l1b[2:0] (l2b[2:0]) = 001. the final two testing modes, local analog loopback and external analog loopback, allow the system to test the basic operation of the converters on the line side and the functionality of the external components. in local analog loopback mode, the ac?97 controller provides a digital test waveform on sdata_out. this data is passed across the isolation barrier, converted to analog, internally looped to the receive path, converted to digital, passed back across the isolation barrier, and presented to the ac?97 controller. to enable local and analog loopback, set l1b[2:0] (l2b[2:0]) = 010. external analog loopback mode allows the system to test external components by passing converted data (from sdata_in) to the transmit pin, which is looped externally to the receive pin. to enable external analog loopback, set l1b[2:0] (l2b[2:0]) = 110. both analog loopback modes require power, which is typically supplied by the loop current from tip and ring. lightning test the si3036 chipset meets the lightning test requirements of fcc part 68. safety and isolation the si3036 chipset meets the requirements of fcc part 68 and ul1950 3rd edition.
si3036 22 rev. 1.2 digital interface the id pins configure the si3024 as a primary or secondary ac?97 device as shown in table 18. the following sections describe si3024 operation. si3024 as secondary device the si3024 can operate as a secondary device, which allows up to two si3024s to exist on the ac-link along with a primary device. the primary device can be an ac?97 rev. 2.1-compatible codec or an si3024 configured as the primary device. when configured as a secondary device, the si3024?s bit_clk becomes an input and is used as the master clock. si3024 as primary mc?97 codec the si3024 can operate as a primary ac?97 rev 2.1 compatible codec. however, when there is an audio ac?97 codec present on the ac link, the si3024 should be configured as a secondary codec, and the audio ac?97 codec should be configured as the primary. when the si3024 is configured as a primary device, clocking is derived from a 24.576 mhz crystal across the xin and xout pins. an external 24.576 mhz master clock can also be applied to xin. si3024 connection to the digital ac?97 controller the si3024 communicates with its companion ac?97 controller through a digital serial link called the ac-link. all digital audio streams, optional modem line codec streams, and command/status information is communicated over this point to point serial interconnect. figure 23 illustrates the breakout of the connecting signals. clocking the si3024 derives its internal clock, when primary, from the 24.576 mhz clock and drives a buffered and divided down (1/2) clock to its digital companion controller over ac-link through the bit_clk signal. clock jitter at the dacs and adcs is a fundamental impediment to high quality output, and the internally generated clock provides the si3024 with a clean clock that is independent of the physical proximity of the si3024?s companion ac?97 controller. the beginning of all audio sample packets, or audio frames, transferred over ac-link is synchronized to the rising edge of the sync signal. sync is driven by the ac?97 controller. the ac?97 controller takes bit_clk as an input and generates sync by dividing bit_clk by 256 and applying some conditioning to tailor its duty cycle. this yields a 48-khz sync signal whose period defines an audio frame. data is transitioned on ac-link on each rising edge of bit_clk and subsequently sampled on the receiving side of ac-link on each immediately following falling edge of bit_clk. figure 23. si3024 connection to ac?97 controller (primary device configuration) table 18. device id configuration id1 id0 device 1 1 primary device 1 0 secondary device #1 0 1 secondary device #2 0 0 factory test digital ac'97 controller si3024 sync bit_clk sdata_out sdata_in reset
si3036 rev. 1.2 23 resetting si3036 chipset there are three types of reset: ! cold reset ?initializes all si3036 logic (registers included) to its default state. initiated by bringing reset low at least 1 s during a time when bit_clk is inactive. ! warm reset ?leaves the register contents unaltered. initiated by bringing sync high for at least 1 s in the absence of bit_clk. ! register reset ?initializes only the registers to their default states. initiated by a write to register 3ch. after signaling a reset to the si3036 chipset, the ac?97 controller should not attempt to play or capture modem data until it has sampled a codec ready indication from the si3036 chipset. see "ac-link audio input frame (sdata_in)?" on page 26. ac-link digital serial interface protocol the si3024 incorporates a 5-pin digital serial interface that links it to the ac?97 controller. ac-link is a bi- directional, fixed rate, serial pcm digital stream. it handles multiple input and output audio streams (including modems), as well as control register accesses employing a tdm scheme. the ac-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. the si3024 data streams are as follows: ! control ?control register write port; two output slots ! status ?control register read port; two input slots ! modem line codec output ?modem line codec dac input stream; one output slot per line ! modem line codec input ?modem line codec adc output stream; one input slot per line ! i/o control ?daa control and gpio; one output slot ! i/o status ?daa status and gpio; one input slot synchronization of all ac-link data transactions is signaled by the ac?97 controller. the si3024 drives the serial bit clock onto ac-link, which the ac?97 controller then qualifies with a synchronization signal to construct audio frames. the sync signal, fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk). buckle, fixed at 12.288 mhz, provides the necessary clocking granularity to support 12 20-bit outgoing and incoming time slots. ac-link serial data is transitioned on each rising edge of bit_clk. the receiver of ac-link data, the si3024 for outgoing data and the ac?97 controller for incoming data, samples each serial bit on the falling edges of bit_clk. the ac-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream and contains valid data. if a slot is tagged invalid, it is the responsibility of the data source (the si3024 for the input stream, the ac?97 controller for the output stream) to populate all bit positions with 0s during that slot?s active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is called the tag phase. the remainder of the audio frame where sync is low is called the data phase. see figure 24. additionally, for power savings, all clock, sync, and data signals can be halted. the si3036 chipset maintains its register contents intact when entering a power-savings mode. ac-link audio output frame (sdata_out) the audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting the si3036?s dac inputs and control registers. each audio output frame supports up to 12 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16 bits used for ac-link protocol infrastructure. within slot 0, the first bit is a global bit (sdata_out slot 0, bit 15) which flags the validity for the entire audio frame. if the valid frame bit is a 1, the current audio frame contains at least one slot time of valid data. the next 12 bit positions sampled by the si3024 indicate which of the corresponding 12 time slots contain valid data. in this way, data streams of differing sample rates can be transmitted across ac-link at its fixed 48-khz audio frame rate. figure 25 illustrates the time slot- based ac-link protocol.
si3036 24 rev. 1.2 figure 24. standard bidirectional audio frame figure 25. ac-link audio output frame a new audio output frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the si3024 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the ac?97 controller transitions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit position is presented to ac-link on a rising edge of bit_clk, and subsequently sampled by the si3024 on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. see figure 26. figure 26. start of an audio output frame sdata_out?s composite stream is msb justified (msb first) with all non-valid slots? bit positions padded with 0s by the ac?97 controller. in the event that there are less than 20 valid bits within an assigned and valid time slot, the ac?97 controller always pads all trailing non-valid bit positions of the 20- bit slot with 0s. variable sample rate signaling protocol for variable sample rate output, the codec examines its sample rate control registers, the state of its fifos, and the incoming sdata_out tag bits at the beginning of each audio output frame to determine which slotreq bits (bit 4 or 9 in sdata_in slot 1) to set active (low). slotreq bits asserted during the current audio input frame signal which active output slots require data from the ac?97 digital controller in the next audio output frame. an active output slot is defined as any slot supported by the codec that is not in a power-down state. the slotreq signal is dependent on the current power state. below is a list of conditions in which the slotreq for slot 5 is active and conditions in which it is inhibited: ! slotreq is active every frame when the prd/prf is set (reg 3e, bit 11/13). (dac is powered down.) this is required by the ac?97 specification for compatibility with 48 khz ac?97 rev. 1.03 codecs. slot # sdata_out sync 0123456789101112 sdata_in tag status addr status data pcm l pcm r line 1 adc mic adc rsrvd line 2 adc hset adc io status rsrvd rsrvd pcm l (n+1) pcm r (n+1) pcm c (n+1) tag cmd addr cmd data pcm l pcm r line 1 dac pcm center pcm l surr pcm r surr pcm lfe line 2 dac hset dac io ctrl codec id slotreq 3?12 tag phase data phase 20.8 s (48 khz) sync sdata_out bit_clk valid frame slot(1) slot(2) "0" "0" "0" 19 0 19 0 19 0 19 0 slot(12) end of previous audio frame time slot "valid" bits ("1" = time slot contains valid pcm data) slot 1 slot 2 slot 3 slot 12 12.228 mhz 81.4 ns sync sdata_out bit_clk valid frame slot (1) slot (2) ac '97 samples snyc assertion here ac '97 samples sdata_out bit of frame here end of previous audio frame
si3036 rev. 1.2 25 ! slotreq is inhibited (high) if the mlnk bit is set (register 56, bit 12), and ac-link halt is impending. slot 1: command address port the command address port controls features and monitors status (see audio input frame slots 1 and 2) for si3036 chipset functions including, but not limited to, sample rate, afe configuration, and power management. the control interface architecture supports up to 64 16-bit read/write registers addressable on even-byte boundaries. only the even registers (00h, 02h, etc.) are valid; odd register (01h, 03h, etc.) writes are ignored and reads return 0. note that shadowing of the control register file on the ac?97 controller is an option left open to the implementation of the ac?97 controller. the si3036?s control register file is readable as well as writable to provide more robust testability. audio output frame slot 1 communicates control register address and write/read command information to the si3036 chipset. command address port bit assignments: ! bit(19)?read/write command (1 = read, 0 = write) ! bit(18:12)?control register index (64 16-bit locations, addressed on even byte boundaries) ! bit(11:0)?reserved (padded with 0s) the first bit (msb) sampled by the si3024 indicates whether the current control transaction is a read or a write operation. the following seven bit positions communicate the targeted control register address. the trailing 12 bit positions within the slot are reserved and must be padded with 0s by the ac?97 controller. slot 2: command data port the command data port delivers 16-bit control register write data in the event that the current command port operation is a write cycle as indicated by slot 1, bit 19. command data port bit assignments: ! bit(19:4)?control register write data (padded with 0s if the current operation is a read) ! bit(3:0)?reserved (padded with 0s) slot 5: modem line 1 dac audio output frame slot 5 contains msb-justified modem dac output data for phone line #1 (id = 0 or 1). the modem dac output resolution is 16 bits. the si3036 receives its dac data msb first. slot 5 data is sent by the controller at a rate below the 48 khz rate of the ac-link. therefore, ?tags? are used to mark when there is valid data in slot 5. the tag for slot 5 is bit 10 in slot 0. tag bits are sent by the controller in response to a slotreq on sdata_in. table 19. slot 12 gpio name sense description gpio15 line2_gpio_b in/out gpio pin b, line 2 gpio14 line2_gpio_a in/out gpio pin a, line 2 gpio13 line2_dlcs in delta loop current sense, line 2 gpio12 line2_cid out caller id path enable, line 2 gpio11 line2_ri in ring detect, line 2 gpio10 line2_oh out off hook, line 2 gpio9:6 reserved gpio5 line1_gpio_b in/out gpio pin b, line 1 gpio4 line1_gpio_a in/out gpio pin a, line 1 gpio3 line1_dlcs in delta loop current sense, line 1 gpio2 line1_cid out caller id path enable, line 1 gpio1 line1_ri in ring detect, line 1 gpio0 line1_oh out off hook, line 1 vendor optional bit 3 reserved bit 2 line2_fdt in frame detect, line 2 bit 1 line1_fdt in frame detect, line 1 bit 0 gpio_int in gpio state change
si3036 26 rev. 1.2 slot 10: modem line 2 dac line 2 is assigned to slot 10. the leading 16-bits of each slot must contain valid sample data (msb bit 19, lsb 4). slot 12: modem gpio control slot 12 contains latency critical signals for the si3012 and the gpio of the si3024. see table 19. slots 3, 4, 6?9, 11: not used the si3036 always pads audio output frame slots 3, 4, 6?9, and 11 with 0s. ac-link audio input frame (sdata_in) the audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the ac?97 controller. this is the case with the audio output frame; each ac-link audio input frame consists of 12 20-bit time slots. slot 0 is a special reserved time slot containing 16 bits that are used by the ac-link protocol infrastructure. within slot 0, the first bit is a global bit (sdata_in slot 0, bit 15) that flags whether the si3024 is in the codec ready state or not. if the codec ready bit is a 0, the si3024 is not ready for normal operation. this condition is normal following the deassertion of reset (e.g., while the si3024?s voltage references settle). when the ac- link codec ready indicator bit is a 1, the ac-link and si3024 control and status registers are in a fully operational state. the ac?97 controller must further probe the powerdown control/status register to determine exactly which subsections, if any, are ready. before any attempts to put the si3036 chipset into operation, the ac?97 controller should poll the first bit in the audio input frame (sdata_in slot 0, bit 15) for an indication that the si3024 is codec ready. when the si3024 is sampled codec ready, then the next 12 bit positions sampled by the ac?97 controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. figure 27 illustrates the time slot-based ac-link protocol. a new audio input frame begins with a low to high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the si3024 samples the assertion of sync. this falling edge marks the time when both sides of ac-link are aware of the start of a new audio frame. on the next rising of bit_clk, the si3024 transitions sdata_in into the first bit position of slot 0 (codec ready bit). each new bit position is presented to ac-link on a rising edge of bit_clk and subsequently sampled by the ac?97 controller on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. sdata_in?s composite stream is msb justified (msb first) with all non-valid bit positions (for assigned and unassigned time slots) padded with 0s by the si3024. sdata_in data is sampled on the falling edges of bit_clk by the ac?97 controller. slot 1: status address port the status address port monitors status for si3024 functions including, but not limited to, line-side configuration. audio input frame slot 1?s stream echoes the control register index (for historical reference) for the data to be returned in slot 2 (assuming that slots 1 and 2 had been tagged ?valid? by the si3024 during slot 0). status address port bit assignments: ! bit(19)?reserved (padded with 0s) ! bit(18:12)?control register index (echo of register index for which data is being returned) ! bit(11:2)?slotreq bits, bit 9 for line 1 and bit 4 for line 2. (see "variable sample rate signaling protocol?" on page 24 for more details.) ! bit(1,0)?reserved (padded with 0s) the first bit (msb) generated by the si3024 is always padded with a 0. the following seven bit positions communicate the associated control register address and the trailing 12 bit positions are padded with 0s by the si3024. figure 27. ac-link audio input frame tag phase data phase 20.8 s (48 khz) sync sdata_in bit_clk codec ready slot(1) slot(2) "0" "0" "0" 19 0 19 0 19 0 19 0 slot(12) end of previous audio frame time slot "valid" bits ("1" = time slot contains valid pcm data) slot 1 slot 2 slot 3 slot 12 12.228 mhz 81.4 ns
si3036 rev. 1.2 27 slot 2: status data port the status data port delivers 16-bit control register read data. status data port bit assignments: ! bit(19:4)?control register read data (padded with 0s if tagged invalid by the si3024) ! bit(3:0)?reserved (padded with 0s) if slot 2 is tagged invalid by the si3024, then the entire slot is padded with 0s by the si3024. slot 5: modem line 1 adc audio input frame slot 5 contains msb-justified modem adc output data for phone line #1 (id = 0 or 1). the modem adc output resolution is 16 bits. the si3036 transmits adc output data msb first and pads any trailing non-valid bit positions with 0s to fill out its 20-bit time slot. slot 5 data is sent by the controller at a rate below the 48 khz rate of the ac-link. therefore, ?tags? are used to mark when there is valid data in slot 5. the tag for slot 5 is bit 10 in slot 0. the tag for slot 5 (and slot 10) is dependent on the current power state. slot 5 is inhibited by the following: ! prc/pre bit is set (register 3e, bit 10/12); adc is powered down. ! mlnk bit is set (register 56, bit 12); ac-link halt is impending. note that slot 5 is active when the daa is on-hook in order to pass ringer and caller-id data. slot 10: modem line 2 adc audio input frame for line 2. slot 12: modem gpio status slot 12 contains latency critical signals for si3012 and the gpio of the si3024. slot 12 also reflects the status of the link between the si3024 and si3012. see ta b l e 1 9 . codec register access whenever the ac?97 digital controller addresses the si3024 as a primary codec or the codec responds to a read command, slot 0 tag bits should always be set to indicate actual valid data in slot 1 and slot 2. see ta b l e 2 0 . when the ac?97 digital controller addresses the si3024 as a secondary codec, the slot 0 tag bits for address and data must be 0. a non-zero, 2-bit codec id in the lsbs of slot 0 indicates a valid read or write address in slot 1, and the slot 1 r/w bit indicates presence or absence of valid data in slot 2. see ta b l e 2 1 . in order for the ac?97 digital controller to independently access primary and secondary codec registers, a 2-bit codec id field (chip select) is used in the lsbs of output slot 0. for secondary codec access, the ac?97 digital controller must invalidate the tag bits for slot 1 and 2 command address and data (slot 0, bits 14 and 13) and place a non-zero value (01 or 10) into the codec id field (slot 0, bits 1 and 0). when configured as a secondary codec, the si3024 disregards the command address and command data (slot 0, bits 14 and 13) tag bits when a 2-bit codec id value (slot 0, bits 1 and 0) is sent that matches the id configuration. in a sense, the secondary codec id field functions as an alternative valid command address (for secondary reads and writes) and command data (for secondary writes) tag indicator. the si3024 monitors the frame valid bit and ignores the frame (regardless of the state of the secondary codec id bits) if it is not valid. the ac?97 digital controllers should set the frame valid bit for a frame with a secondary register access, even if no other bits in the output tag slot except the secondary codec id bits are set. see table 22.
si3036 28 rev. 1.2 table 20. primary codec addressing: slot 0 tag bits function slot 0, bit 15 (valid frame) slot 0, bit 14 (valid slot 1 address) slot 0, bit 13 (valid slot 2 data) slot 0, bits 1?0 (codec id) ac?97 digital controller primary read frame n, sdata_out 11 000 ac?97 digital controller primary write frame n, sdata_out 11 100 si3024 status frame n + 1, sdata_in 11 100 table 21. secondary codec addressing: slot 0 tag bits function slot 0, bit 15 (valid frame) slot 0, bit 14 (valid slot 1 address) slot 0, bit 13 (valid slot 2 data) slot 0, bits 1?0 (codec id) ac?97 digital controller secondary read frame n, sdata_out 1 0 0 01 or 10 ac?97 digital controller secondary write frame n, sdata_out 1 0 0 01 or 10 si3024 status frame n + 1, sdata_in 11100 table 22. secondary codec register access slot 0 bit definitions output tag slot (16-bits) bit description 15 frame valid 14 slot 1: valid command address bit (primary codec only) 13 slot 2: valid command data bit (primary codec only) 12?3 slot 3: 12 valid bits as defined by ac?97 2 reserved (set to 0) 1?0 2-bit codec id field (00 reserved for primary; 01, 10 indicate secondary)
si3036 rev. 1.2 29 ac-link low power mode the ac-link signals can be placed in a low-power mode. when ac?97?s powerdown register is programmed to the appropriate value, both bit_clk and sdata_in will be brought to, and held, at a logic low-voltage level. figure 28. ac-link powerdown timing bit_clk and sdata_in are transitioned low immediately following the decode of the write to the register 56h with mlnk. when the ac?97 controller driver is at the point where it is ready to program the ac-link into its low-power mode, slots 1 and 2 are assumed to be the only valid stream in the audio output frame. the ac?97 controller should also drive sync and sdata_out low after programming the si3036 to this low- power mode. when the si3036 has been instructed to halt bit_clk, a special wake up protocol must be used to bring the ac-link to the active mode because normal audio output and input frames cannot be communicated in the absence of bit_clk. note: the si3036?s pll must be initialized before being placed in sleep mode. pll is initialized by writing a sample rate in register 40h (42h). waking up the ac-link there are two methods for bringing the ac-link out of a low- power, halted mode. regardless of the method, the ac?97 controller performs the wake-up task. ac-link protocol provides for a cold reset and a warm reset. the current power down state ultimately dictates which form of reset is appropriate. unless a cold or register reset (a write to the reset register) is performed, wherein the registers are initialized to their default values, registers are required to keep state during all power-down modes. when powered down, reactivation of the ac-link through reassertion of the sync signal must not occur for a minimum of four audio frame times following the frame in which the power down was triggered. when ac-link powers up, the si3036 indicates readiness through the codec ready bit (input slot 0, bit 15). the si3036 can be enabled to indicate a power management event has occurred (e.g., ring detection) while in low-power mode. see "52h gpio pin wake up mask?" on page 37 for more details. si3036 cold reset a cold reset is achieved by asserting reset for the minimum specified time. by driving reset low, bit_clk and sdata_out are activated, or reactivated as the case may be, and all si3036 control registers are initialized to their default power on reset values. it should be noted that while reset is low, the si3036 will remain active. upon the rising edge of reset the si3036 will perform a cold reset. reset is an asynchronous si3036 input. si3036 warm reset a warm reset reactivates the ac-link without altering the current si3036 register values. a warm reset is signaled by driving sync high for a minimum of 1 s in the absence of bit_clk. within normal audio frames, sync is a synchronous si3036 input. however, in the absence of bit_clk, sync is treated as an asynchronous input used in the generation of a warm reset to the si3036. the primary ac?97 codec will not respond with the activation of bit_clk until sync has been sampled low again by ac?97. this will preclude the false detection of a new audio frame. sync sdata_out bit_clk sdata_in tag tag write to 56h data mlnk slot 12 prev. frame slot 12 prev. frame
si3036 30 rev. 1.2 control registers note: any register not listed here is reserved and should not be written. undefined/unimplemented registers return 0. table 23. register summary register name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 3ch extended modem id id1 id0 lin2 lin1 3eh extended modem sta- tus & control prf pre prd prc prb pra dac2 adc2 dac1 adc1 mref gpio 40h line 1 dac/ adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 42h line 2 dac/ adc rate sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 46h line 1 dac/ adc level mute dac3 dac2 dac1 mute adc3 adc2 adc1 48h line 2 dac/ adc level mute dac3 dac2 dac1 mute adc3 adc2 adc1 4ch gpio pin configura- tion gc15 gc14 gc13 gc12 gc11 gc10 gc5 gc4 gc3 gc2 gc1 gc0 4eh gpio pin polarity & type gp15 gp14 gp13 gp12 gp11 gp10 gp5 gp4 gp3 gp2 gp1 gp0 50h gpio pin sticky gs15 gs14 gs13 gs11 gs5 gs4 gs3 gs1 52h gpio pin wake up mask gw15 gw14 gw13 gw11 gw5 gw4 gw3 gw1 54h gpio pin status gi15 gi14 gi13 gi12 gi11 gi10 gi5 gi4 gi3 gi2 gi1 gi0 56h miscella- neous modem afe status & control mlnk l2b2 l2b1 l2b0 l1b2 l1b1 l1b0 5ah chip id & revision cbid revb3 revb2 revb1 revb0 reva3 reva2 reva1 reva0 5ch line side configura- tion 1 arm1 arm0 atm1 atm0 iire sqlch rfwe ohs bte act dct1 dct0 rz rt 5eh line side status pdc rov btd cle fdt lcs3 lcs2 lcs1 lcs0 rdtp rdtn 62h line side configura- tion 2 dial fjm vol1 vol0 lim1 lim0 64h line side configura- tion 3 ctro btm 7ch vendor id register f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 7eh vendor id register t7 t6 t5 t4 t3 t2 t1 t0 pid2 pid1 pid0
si3036 rev. 1.2 31 reset settings (dependent on pins id1 and id0 ) = 0001 8002 4001 cxxx register 3ch extended modem id d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 id1 id0 lin2 lin1 bit name function 15 id1 id1, id0 is a 2-bit field which indicates the codec configuration: primary is 00; secondary is 01 and 10; factory test is 11 14 id0 13:2 reserved read returns zero. 1 lin2 lin2 = 1 indicates 2nd line is supported, id1:0 = 10. codec data is transferred in slot 10. 0 lin1 lin1 = 1 indicates 1st line is supported, id1:0 = 01. codec data is transferred in slot 5.
si3036 32 rev. 1.2 reset settings = 0xff00 bits 7?0 are read only, 1 indicates modem afe subsystem readiness. bits 13?8 are read/write and control modem afe subsystem power-down. note: when bits 13?8 are all set to 1, the si3012 is powered down. register 3eh extended modem status and control d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 prf pre prd prc prb pra dac2 adc2 dac1 adc1 mref gpio bit name function 15:14 reserved read returns zero. 13 prf prf = 1 indicates modem line 2 dac off. 12 pre pre = 1 indicates modem line 2 adc off. 11 prd prd = 1 indicates modem line 1 dac off. 10 prc prc = 1 indicates modem line 1 adc off. 9 prb reserved for future use. 8 pra pra = 1 indicates gpio power-down. 7:6 reserved read returns zero. 5 dac2 dac2 = 1 indicates modem line 2 dac ready. 4 adc2 adc2 = 1 indicates modem line 2 adc ready. 3 dac1 dac1 = 1 indicates modem line 1 dac ready. 2 adc1 adc1 = 1 indicates modem line 1 adc ready. 1 mref mref = 1 indicates modem vref?s up to nominal level. 0 gpio gpio = 1 indicates gpio ready.
si3036 rev. 1.2 33 reset settings = 0x0000 each dac/adc pair is governed by a read/write modem sample rate control register that contains a 16-bit unsigned value between 0 and 65535, representing the rate of operation in hz. a number written over 0x3592 will cause the sample rate to be 13.714 khz. for all rates, if the value written to the register is supported, that value will be echoed back when read, otherwise the closest rate supported is returned. when set to zero, the internal pll is disabled. the pll should be programmed before the line side (si3012) is activated via clearing any pr bit in register 3eh. furthermore, sleep mode is not supported when the pll is disabled. reset settings = 0000h (rates same as for line 1, refer to above table) register 40h line 1 dac/adc rate d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0 sample rates for line 1 and line 2 sample rate d15?d0 7200 1c20 8000 1f40 8228.57 (57600/7) 2024 8400 20d0 9000 2328 9600 2580 10285.71 (72000/7) 282d 12000 2ee0 13714.28 (96000/7) 3592 register 42h line 2 dac/adc rate d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 sr15 sr14 sr13 sr12 sr11 sr10 sr9 sr8 sr7 sr6 sr5 sr4 sr3 sr2 sr1 sr0
si3036 34 rev. 1.2 reset setting for line 1 device = 0x8080 reset setting for line 2 device = 0x0000 this read/write register controls the modem afe dac and adc levels. the default value after cold register reset for this register (0x8080) corresponds to 0 db dac attenuation with mute on and 0 db adc gain with mute on. register 46h line 1 dac/adc level d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute dac3 dac2 dac1 mute adc3 adc2 adc1 bit name function 15 mute transmit mute. 0 = mute off. 1 = mute on. 14:12 reserved read returns zero. 11:9 dac[3:1] analog transmit attenuation. 000 = 0 db attenuation 001 = 3 db attenuation 010 = 6 db attenuation 011 = 9 db attenuation 1xx = 12 db attenuation 8 reserved read returns zero. 7mute receive mute. 0 = mute off. 1 = mute on. 6:4 reserved read returns zero. 3:1 adc[3:1] analog receive gain. 000 = 0 db gain 001 = 3 db gain 010 = 6 db gain 011 = 9 db gain 1xx = 12 db gain 0 reserved read returns zero.
si3036 rev. 1.2 35 reset setting for line 1 device = 0x0000 reset setting for line 2 device = 0x8080 this read/write register controls the modem afe dac and adc levels. the default value after cold register reset for this register (0x8080) corresponds to 0 db dac attenuation with mute on and 0 db adc gain with mute on. register 48h line 2 dac/adc level d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mute dac3 dac2 dac1 mute adc3 adc2 adc1 bit name function 15 mute transmit mute. 0 = mute off. 1 = mute on. 14:12 reserved read returns zero. 11:9 dac[3:1] analog transmit attenuation. 000 = 0 db attenuation 001 = 3 db attenuation 010 = 6 db attenuation 011 = 9 db attenuation 1xx = 12 db attenuation 8 reserved read returns zero. 7mute receive mute. 0 = mute off. 1 = mute on. 6:4 reserved read returns zero. 3:1 adc[3:1] analog receive gain. 000 = 0 db gain 001 = 3 db gain 010 = 6 db gain 011 = 9 db gain 1xx = 12 db gain 0 reserved read returns zero.
si3036 36 rev. 1.2 reset setting for line 1 device = 0x003f reset setting for line 2 device = 0xfc00 the gpio pin configuration register is read/write for configuring slot 12 i/o. these pins are digital commands (virtual pins). this register specifies whether a gpio pin is configured for input (1) or output (0). the digital controller sends the desired gpio pin value over output slot 12 in the outgoing stream of the ac-link before configuring any of these bits for output. reset settings = 0xffff the gpio pin polarity/type register is read/write for selecting the polarity and type for slot 12 i/o. this register defines gpio input polarity (0 = low, 1 = high active) when a gpio pin is configured as an input. it defines gpio output type (0 = cmos, 1 = open-drain) when a gpio pin is configured as an output. the default value after soft reset (0xffff) is all pins active high. non-implemented gpio pins always return 1s. note: register 4eh is not effected by a cold or warm reset. (this is to avoid corrupting sticky bits.) reset settings = 0x0000 the gpio pin sticky is a read/write register. it defines the gpio input type (0 = non-sticky, 1 = sticky) when a gpio pin (defined in slot 12 i/o) is configured as an input. applies to ring detect, delta loop current sense, gpio_a, and gpio_b bits. gpio inputs configured as sticky are cleared by writing a 0 to the corresponding bit of the gpio pin status register (54h). the default value after cold register reset (0x0000) is all pins non-sticky. unimplemented gpio pins always return 0s. sticky is defined as edge sensitive, non-sticky as level sensitive. register 4ch gpio pin configuration d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gc15 gc14 gc13 gc12 gc11 gc10 gc5 gc4 gc3 gc2 gc1 gc0 register 4eh gpio pin polarity and type d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gp15 gp14 gp13 gp12 gp11 gp10 gp5 gp4 gp3 gp2 gp1 gp0 register 50h gpio pin sticky d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gs15 gs14 gs13 gs11 gs5 gs4 gs3 gs1
si3036 rev. 1.2 37 reset settings = 0x0000 the gpio pin wake-up is a read/write register that provides a mask for determining if an input gpio change will generate a wake-up or gpio_int (0 = no, 1 = yes). when the ac-link is powered down, a wake-up event will trigger the assertion of sdata_in. when ac-link is powered up, a wake-up event will appear as gpio_int = 1 on bit 0 of input slot 12. ring-detection wake-up can be enabled or disabled. an ac-link wake-up interrupt is defined as a 0 to 1 transition on sdata_in when the ac-link is powered down. gpio bits that have been programmed as inputs, sticky, and pin wake-up, upon transition (either high-to-low or low-to-high) depending on pin polarity, will cause an ac-link wake-up event, if the ac-link was powered down. the default value after cold register reset (0x0000) defaults to all 0s specifying no wake-up event. applies to ring detect, gpio_a, and gpio_b bits. non-implemented gpio pins always return 0s. reset settings = 0xxxxx gpio status is a read/write register that reflects the state of all gpio pins (inputs and outputs) on slot 12. the value of all gpio pin inputs and outputs comes from each frame on slot 12, but is also available for reading as gpio pin status via the standard slot 1 and 2 command address/data protocols. gpio inputs configured as sticky are cleared by writing a 0 to the corresponding bit of this register. (this should be the last event before setting the ac?97 mlnk bit.) bits corresponding to unimplemented gpio pins should be forced to zero in this register and input slot 12. gpio bits that have been programmed as inputs and sticky, upon transition (high-to-low or low-to-high), will cause the individual gi bit to go asserted 1, and remain asserted until a write of 0 to that bit. the only way to set the desired value of a gpio output pin is to set the control bit in output slot 12. if configured as an input, the default value after register reset is always the state of the gpio pin. register 52h gpio pin wake up mask d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gw15 gw14 gw13 gw11 gw5 gw4 gw3 gw1 register 54h gpio pin status d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gi15 gi14 gi13 gi12 gi11 gi10 gi5 gi4 gi3 gi2 gi1 gi0
si3036 38 rev. 1.2 reset settings = 0x0000 this read/write register defines the loopback modes available for the modem line adcs/dacs. the default value after cold register reset (0x0000) is all loopbacks disabled. ? figure 29. loopback points register 56h miscellaneous modem afe status and control d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mlnk l2b2 l2b1 l2b0 l1b2 l1b1 l1b0 bit name function 15:13 reserved read returns zero. 12 mlnk controls an mc?97?s ac-link status. 1 sets the mc?97?s ac-link to off (sleep), 0 sets the link on (active). 11:7 reserved read returns zero. 6:4 l2b[2:0] line 2 loopback modes. 000 = disabled (default) 001 = adc loopback (i b) 010 = local analog loopback (f m) 011 = digital dac loopback (c j) 100 = remote analog loopback (m f) 101 = isocap loopback (d k) 110 = external analog loopback (g n) 111 = reserved 3 reserved read returns zero. 2:0 l1b[2:0] line 1 loopback modes. 000 = disabled (default) 001 = adc loopback (i b) 010 = local analog loopback (f m) 011 = digital dac loopback (c j) 100 = remote analog loopback (m f) 101 = isocap loopback (d k) 110 = external analog loopback (g n) 111 = reserved ac link analog dac analog adc i/o pad i/o pad a 3024 3012 bdefg hi k lm n dac output adc input note: for all loopback modes except 011, the line-side must be powered on and off-hook. c j digital filter digital filter
si3036 rev. 1.2 39 reset settings = n/a note: line-side must be activated via pr bits before valid read. register 5ah chip id and revision d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cbid revb3 revb2 revb1 revb0 reva3 reva2 reva1 reva0 bit name function 15:9 reserved read returns zero. 8 cbid chip b (line-side) id. 0 = line-side is domestic. 1 = line-side has international support. 7:4 revb[3:0] chip revision. four-bit value indicating the revision of the si3012 (line side) silicon. 0100 = si3012 rev d 0101 = si3012 rev e 0111 = si3012 rev g 3:0 reva[3:0] chip revision. four-bit value indicating the revision of the si3024 (system side) silicon. 0010 = si3024 rev b 0011 = si3024 rev c
si3036 40 rev. 1.2 reset settings = 0xf010 note: light gray boxed bit descriptions are for international line-side support (si3014) only. register 5ch line side configuration 1 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 arm1 arm0 atm1 atm0 iire sqlch rfwe ohs bte act dct1 dct0 rz rt bit name function 15:14 arm[1:0] analog (call progress) receive path mute. 00 = 0 db 01 = ?6 db 10 = ?12 db 11 = mute 13:12 atm[1:0] analog (call progress) transmit path mute. 00 = ?20 db 01 = ?26 db 10 = ?32 db 11 = mute 11 iire iir filter enable. 0 = fir filter enabled for transmit and receive filters. (see figures 9?12 on page 12.) 1 = iir filter enabled for transmit and receive filters. (see figures 13?18 on page 13.) 10 sqlch ring detect network squelch. this bit must be set, then cleared, following a polarity reversal detection. used to quickly recover the offset on the rng1/2 pins after a polarity reversal. 0 = normal. 1 = squelch. 9 rfwe ring detector full wave rectifier enable. when set, the ring detection circuitry provides full wave rectification. this will effect the data stream presented on sdata_in during ring detection. 0 = half wave. 1 = full wave.
si3036 rev. 1.2 41 reset settings = 0xf010 note: light gray boxed bit descriptions are for international line-side support (si3014) only. register 5ch line side configuration 1 (continued) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 arm1 arm0 atm1 atm0 iire sqlch rfwe ohs bte act dct1 dct0 rz rt bit name function 8 reserved read returns zero. 7 ohs on-hook speed. sets speed of execution of an on-hook. 0 = fast. 1 = slow. 6 bte billing tone detector enable. when set, a billing tone signal is detected on the line and off-hook is maintained through the billing tone. if a billing tone is detected, the btd bit of register 5eh will be set to indi- cate the event. 5 act ac termination select. 0 = selects the real impedance. 1 = selects the complex impedance. 4:3 dct[1:0] dc termination select. 00 = reserved. 01 = japan mode. low voltage mode. (transmit level = ?3 dbm). 10 = fcc mode. standard voltage mode. (transmit level = ?1 dbm). 11 = ctr21. current limiting mode. (transmit level = ?1 dbm). 2 rz ringer impedance. 0 = maximum (high) ringer impedance. 1 = synthesize ringer impedance. c15, r14, z2, and z3 must not be installed when set- ting this bit. 1 reserved read returns zero. 0 rt ringer threshold select. used to satisfy country requirements on ring detection. signals below the lower level will not generate a ring detection. signals above the upper level are guaranteed to generate a ring detection. 0 = 11 to 22 v rms . 1 = 17 to 33 v rms .
si3036 42 rev. 1.2 reset setting = 0x0000 note: light gray boxed bit descriptions are for international line-side support (si3014) only. note: line side must be activated via pr bits before valid read/write. register 5eh line side status d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 pdc rov btd cle fdt lcs3 lcs2 lcs1 lcs0 rdtp rdtn bit name function 15:11 reserved read returns zero. 10 pdc charge pump disable. this bit disables the internal charge pump when set. 9 rov receive overload. this bit is set when the receive input detects an excessive input level. a write of zero is required to clear this bit. (this bit is disabled when bte = 0 in register 5ch.) 8 btd billing tone detected. this bit will be set if bte bit of register 5ch is enabled and a billing tone is detected. a write of zero is required to clear this bit. (this bit is only active when bte = 1 in register 5ch.) 7cle communications (isocap) error. 1 = indicates a communication problem between the si3024 and si3012. when it goes high, it remains high until a logic 0 is written to it. 6 fdt frame detect. 0 = indicates isocap communication has not established frame lock. 1 = indicates isocap frame lock has been established. 5:2 lcs[3:0] loop current sense. four-bit value returning the loop current in 6 ma increments. 0 = loop current < 0.4 ma typical. 1111 = loop current > 155 ma typical. see "loop current monitor?" on page 20. 1 rdtp ring detect signal positive. 1 = positive ring signal is occurring. 0 rdtn ring detect signal negative. 1 = negative ring signal is occurring.
si3036 rev. 1.2 43 reset setting = 0x0000 note: light gray boxed bit descriptions are for international line-side support (si3014) only. register 62h line side configuration 2 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dial fjm vol1 vol0 lim1 lim0 bit name function 15:9 reserved read returns zero. 8 dial dtmf dialing mode. this bit should be set during dtmf dialing in ctr21 mode if lcs[3:0] < 6. 0 = normal operation. 1 = increase headroom for dtmf dialing. 7 fjm force japan dc termination mode. 0 = normal gain. 1 = when register 16, dct[1:0], is set to 10b (fcc mode), setting this bit will force japan dc termination mode while allowing for a transmit level of ?1dbm. 6:5 vol[1:0] line voltage adjust. when set, this bit will adjust the tip-ring line voltage. lowering this voltage will improve margin in low voltage countries. raising this voltage may improve distortion performance. 00 = normal 01 = ?0.125 v 10 = 0.25 v 11 = 0.125 v 4:3 lim[1:0] current limit. 00 = all other modes. 11 = ctr21 mode. 2:0 reserved read returns zero.
si3036 44 rev. 1.2 reset setting = 0x0000 note: light gray boxed bit descriptions are for international line-side support (si3014) only. reset settings f[7:0] = 53h s[7:0] = 49h t[7:0] = 4ch pid[2:0] = 001b remaining bits = reserved these registers are for specific vendor identification. the id method is microsoft?s plug and play vendor id code with f7..0 being the first character of that id, s7..0 being the second character, and t7..0 the third character. these three characters are ascii encoded. silicon laboratories vendor id is ?sil? or ?53h 49h 4ch?. the pid[2:0] field contains the silicon laboratories part id (?001b?). register 64h line side configuration 3 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 ctro btm bit name function 15:8 reserved read returns zero. 7 ctro ctr overload detected. 0 = overload detected. loop current is excessive. 1 = normal. 6:3 reserved read returns zero. 2 btm overload detected. this bit has the same function as rov in register 5e, but will clear itself after the overload has been removed. 1:0 reserved test bits. register 7ch and 7eh vendor id registers d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 7ch f7 f6 f5 f4 f3 f2 f1 f0 s7 s6 s5 s4 s3 s2 s1 s0 7eh t7 t6 t5 t4 t3 t2 t1 t0 pid2 pid1 pid0
si3036 rev. 1.2 45 a ppendix ?ul1950 3 rd e dition designs using the si3036 pass all overcurrent and overvoltage tests for ul1950 3rd edition compliance with a couple of considerations. figure 30 shows the designs that can pass the ul1950 overvoltage tests, as well as electromagnetic emissions. the top schematic of figure 30 shows the configuration in which the ferrite beads (fb1, fb2) are on the unprotected side of the sidactor (rv1). for this configuration, the current rating of the ferrite beads needs to be 6 a. however, the higher current ferrite beads are less effective in reducing electromagnetic emissions. the bottom schematic of figure 30 shows the configuration in which the ferrite beads (fb1, fb2) are on the protected side of the sidactor (rv1). for this design, the ferrite beads can be rated at 200 ma. in a cost optimized design, it is important to remember that compliance to ul1950 does not always require overvoltage tests. it is best to plan ahead and know which overvoltage tests will apply to your system. system-level elements in the construction, such as fire enclosure and spacing requirements, need to be considered during the design stages. consult with your professional testing agency during the design of the product to determine which tests apply to your system. figure 30. circuits that pass all ul1950 overvoltage tests c24 1.25 a fb1 75 ? @ 100 mhz, 6 a tip fb2 ring c25 75 ? @ 100 mhz, 6 a rv1 c24 1.25 a tip ring c25 600 ? @ 100 mhz, 200 ma fb1 fb2 rv1 600 ? @ 100 mhz, 200 ma
si3036 46 rev. 1.2 pin descriptions: si3024 table 24. 3024 pin descriptions soic pin # tssop pin # pin name description 113mclk/xin master clock input/crystal in. 214 xout crystal output. 315 bit_clk serial port bit clock output/input. controls the serial data on sdata_in and latches the data on sdata_out. output when configured as primary device. input when configured as second- ary device. 416 v d digital power supply. provides the digital supply voltage to the si3024. nominally either 5 v or 3.3 v. 5 1 sdata_in ac-link serial data in. serial communication and status data that is provided by the si3024 to the digital ac?97 controller. 62sdata_out ac-link serial data out. serial communication and control data that is generated by the digital ac?97 controller and presented as an input to the si3024. 73 sync frame sync input. data framing signal that is used to indicate the start and stop of a communi- cation data frame. 84 reset reset input. an active low input that is used to reset all control registers to a defined, ini- tialized state. also used to bring the si3036 out of sleep mode. 95 aout analog speaker output. provides an analog output signal for driving a call progress speaker. 10 6 id0 device id bit 0. bit 0 of the device configuration. internal pull-up to v dd . 11 7 c1a isolation capacitor 1a. connects to one side of the isolation capacitor c1. 12 8 gnd ground. connects to the system digital ground. also connects to capacitor c2. 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 gpio_a gpio_b id1 v a gnd c1a id0 aout mclk/xin xout bit_clk v d sdata_in sdata_out sync reset 9 10 11 12 13 16 15 14 v d bit_clk xout mclk/xin gpio_a gpio_b id1 v a sdata_in sdata_out sync reset aout id0 c1a gnd 1 2 3 4 5 6 7 8 si3024 (soic) si3024 (tssop)
si3036 rev. 1.2 47 13 9 v a analog supply voltage. provides the analog supply voltage for the si3024. nominally 5 v. 14 10 id1 device id bit 1. bit 1 of the device configuration. internal pull-up to v dd . 15 11 gpio_b general purpose i/o b. programmable via registers 4ch?54h. default input. 16 12 gpio_a general purpose i/o a. programmable via registers 4ch?54h. default input. table 24. 3024 pin descriptions (continued) soic pin # tssop pin # pin name description
si3036 48 rev. 1.2 pin descriptions: si3012 table 25. 3012 pin descriptions pin # pin name description 1tsta test input a. allows access to test modes, which are reserved for factory use. this pin has an inter- nal pull-up and should be left as a no connect for normal operation. 2tstb test input b. allows access to test modes, which are reserved for factory use. this pin has an inter- nal pull-up and should be left as a no connect for normal operation. 3ignd isolated ground. connects to ground on the line-side interface. 4c1b isolation capacitor 1b. connects to one side of isolation capacitor c1. 5 rng1 ring 1. connects through a capacitor to the tip lead of the telephone line. provides the ring and caller id signals to the si3036. 6 rng2 ring 2. connects through a capacitor to the ring lead of the telephone line. provides the ring and caller id signals to the si3036. 7qb transistor base. connects to the base of transistor q3. 8qe transistor emitter. connects to the emitter of transistor q3. 9vreg voltage regulator. connects to an external capacitor to provide bypassing for an internal voltage regulator. 10 vreg2 voltage regulator 2. connects to an external capacitor to provide bypassing for an internal voltage regulator. 11 hybd hybrid node output. balancing capacitor connection used for jate out-of-band noise support. 12 dct dc termination. provides dc termination to the telephone network. 1 2 3 4 5 6 7 8 9 10 11 12 13 16 15 14 tsta tstb ignd c1b rng1 rng2 qb qe tx nc rx rext dct hybd vreg2 vreg si3012 (soic or tssop)
si3036 rev. 1.2 49 13 rext external resistor. connects to an external resistor. 14 rx receive input. serves as the receive side input from the telephone network. 15 nc no connect. 16 tx transmit output. provides the output, through an ac termination impedance, to the telephone network. table 25. 3012 pin descriptions (continued) pin # pin name description
si3036 50 rev. 1.2 ordering guide table 26. ordering guide chipset region interface digital (soic) line (soic) digital (tssop) line (tssop) temperature si3034 global dsp serial i/f si3021-ks si3014-ks si3021-kt si3014-kt 0c to 70c si3035 fcc/japan dsp serial i/f si3021-ks si3012-ks si3021-kt si3012-kt 0c to 70c si3036 fcc/japan ac link SI3024-KS si3012-ks si3024-kt si3012-kt 0c to 70c si3038 global ac link SI3024-KS si3014-ks si3024-kt si3014-kt 0c to 70c si3044 enhanced global dsp serial i/f si3021-ks si3015-ks 0c to 70c si3044 enhanced global dsp serial i/f si3021-bs si3015-bs ?40c to 85c si3046 fcc/jate ac link si3025-ks si3012-ks 0c to 70c si3048 global ac link si3025-ks si3014-ks 0c to 70c
si3036 rev. 1.2 51 soic outline figure 31 illustrates the package details for the si3024 and si3012. table 27 lists the values for the dimensions shown in the illustration. figure 31. 16-pin small outline plastic package (soic) table 27. package diagram dimensions controlling dimension: mm symbol inches millimeters min max min max a 0.053 0.069 1.35 1.75 a1 0.004 0.010 0.10 0.25 a2 0.051 0.059 1.30 1.50 b 0.013 0.020 0.330 0.51 c 0.007 0.010 0.19 0.25 d 0.386 0.394 9.80 10.01 e 0.150 0.157 3.80 4.00 e 0.050 bsc ? 1.27 bsc ? h 0.228 0.244 5.80 6.20 l 0.016 0.050 0.40 1.27 l1 0.042 bsc ? 1.07 bsc ? ? 0.004 ? 0.10 0 8 0 8
si3036 52 rev. 1.2 tssop outline figure 32 illustrates the package details for the si3024 and si3012. table 28 lists the values for the dimensions shown in the illustration. figure 32. 16-pin thin small shrink outline package (tssop) table 28. package diagram dimensions symbol millimeters min nom max a ? 1.10 1.20 a1 0.05 ? 0.15 a2 0.80 1.00 1.05 b0.19 ?0.30 c0.09?0.20 d 4.85 5.00 5.15 e0.65 bsc e6.40 bsc e1 4.30 4.40 4.50 l 0.45 0.60 0.75 l1 1.00 ref r0.09 ? ? r1 0.09 ? ? s0.20 ? ? 10 ?8 2 12 ref 3 12 ref l 1 l1 s r1 r 2 3 c d a1 a a2 b e1 e e
si3036 rev. 1.2 53 data sheet changes from version 1.0 to version 1.1 ! typical application circuit updated. ! c24, c25 value changed from 470 pf to 1000 pf and c31, c32 were added in table 16. data sheet changes from version 1.1 to version 1.2 ! tssop information added. ! revision g values added to register 5ah. ! figure 19, ?typical application circuit for the si3036,? on page 15 updated. ! table 16, ?fcc component values?si3036 chipset,? on page 16 updated.
si3036 54 rev. 1.2 contact information silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and isocap are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resu lting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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