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1. general description the pca9616 is a fast-mode plus (fm+) smbus/i 2 c-bus buffer that extends the normal single-ended smbus/i 2 c-bus through electrically noisy environments using a differential smbus/i 2 c-bus (di 2 c) physical layer, which is transparent to the smbus/i 2 c-bus protocol layer. it consists of three single-ended to di fferential driver channels for the scl (serial clock), sda (serial data), and a third channel useful for int or other signaling. remark: if the third channel is not used, the int pin (pin 7 of the tssop16 package) should not be left disconnected or ?floating? (it may generate incorrect bus signals due to system noise entering this high-impedance node). tie it to v ss . the use of differential transmission lines between identical di 2 c bus buffers removes electrical noise and common-mode offsets that are present when signal lines must pass between different voltage domains, are bundled with hostile signals, or run adjacent to electrical noise sources, such as high energy power supplies and electric motors. the smbus/i 2 c-bus was conceived as a simple slow speed digital link for short runs, typically on a single pcb or between adja cent pcbs with a commo n ground connection. applications that extend the bus length or run long cables require careful design to preserve noise margin and reject interference. the di 2 c-bus buffers were designed to solve these problems and are ideally suited for rugged high noise environments and/or longer cable applications, allow multiple slaves, and operate at bus speeds up to 1 mhz clo ck rate. cables can be extended to at least three meters (3 m), or longer cable runs at lower clock speeds. the di 2 c-bus buffers are compatible with existing smbus/i 2 c-bus devices and can drive standard, fast-mode, and fast-mode plus devices on the single-ended side. signal direction is automatic, and requires no external control. to prevent bus latch up, the standard smbus/i 2 c-bus side of the bus buffer, the pca9616 employs static offset, care should be taken when connecting these to other smbus/i 2 c-bus buffers that may not operate with offset. this device is a bridge between the normal 2-wire single-ended wired-or smbus/i 2 c-bus and the 4-wire di 2 c-bus. additional circuitry allows the pca9616 to be used for ?hot swap? applications, where systems are always on, but require insertion or removal of modules or cards without disruption to existing signals. the pca9616 has two supply voltages, v dd(a) and v dd(b) . v dd(a) , the card side supply, only serves as a reference and ranges from 0.8 v to 5.5 v. v dd(b) , the line side supply, serves as the majority supply for circuitry and ranges from 3.0 v to 5.5 v. pca9616 3-channel multipoint fas t-mode plus differential i 2 c-bus buffer with hot-swap logic rev. 2 ? 10 march 2014 product data sheet
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 2 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 2. features and benefits ? new di 2 c-bus buffers offer improved resistance to system noise and ground offset up to 1 2 of supply voltage ? hot swap (allows insertion or removal of modules or card without disruption to bus data) ? ready signal (pca9616 output) indicates device is ready from a cold start ? en signal (pca9616 input) controls pca9616 hot swap sequence ? bus idle detect (pca9616 internal functi on) waits for a bus id le condition before connection is made ? 3 channel di 2 c (differential i 2 c-bus) to fm+ single-ended buffer operating up to 1 mhz with 30 ma sda/scl > 2.2 v, or 3 ma sda/scl < 2.4 v ? compatible with i 2 c-bus standard/fast-mode and smbus, fast-mode plus up to 1mhz ? active high (internal pull-up resistor) enabl e disables the device to high-impedance state ? single-ended i 2 c-bus on card side up to 540 pf >2.2 v and 400 pf <2.4 v ? differential i 2 c-bus on cable side supporting multi-drop bus ? maximum cable length: 3 m (approximately 10 feet) (longer at lower frequency) ? di 2 c output: 1.5 v differential output with nominal terminals ? differential line impedance (user defined): 100 ? nominal suggested ? receive input sensitivity: ? 200 mv ? hysteresis: ? 30 mv typical ? input impedance: high-impedance (200 k ? typical) ? receive input voltage range: ? 0.5 v to +5.5 v ? lock-up free operation ? supports arbitration and clock stretching across the di 2 c-bus buffers ? powered-off and powering-up high-impedance i 2 c-bus pins ? operating supply voltage (v dd(a) ) range of 0.8 v to 5.5 v with single-ended side 5.5 v tolerant fig 1. smbus/i 2 c-bus translation to di 2 c-bus and back to smbus/i 2 c-bus v dd(a)1 scl sda pca9616 aaa-009537 di 2 c-bus (differential i 2 c-bus, 1 of 3 lines shown) twisted-pair cable single-ended i 2 c-bus pca9616 scl sda gnd1 gnd2 v dd(a)2 single-ended i 2 c-bus v dd(b) v dd(b) int int v dd(b) v dd(b) pidet pidet ready ready en en
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 3 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic ? differential i 2 c-bus operating supply voltage (v dd(b) ) range of 3.0 v to 5.5 v with 5.5 v tolerant. best operation is at 5 v. ? esd protection exceeds 2000 v hbm per jesd22-a114 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? package offering: tssop16 3. applications ? any application with multiple power supplies and the potential for ground offsets up to 2.5 v ? any application that requires long i 2 c-bus runs in electrically noisy environments ? monitor remote temperature/leak detectors in harsh environment with interrupt back to master ? control of power supplies in high noise environment ? transmission of i 2 c-bus between equipment cabinets ? commercial lighting and industr ial heating/cooling control 4. ordering information 4.1 ordering options table 1. ordering information type number topside marking package name description version PCA9616PW pca9616 tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 table 2. ordering options type number orderable part number package packing method minimum order quantity temperature range PCA9616PW PCA9616PW,118 tssop16 reel 13? q1/t1 *standard mark smd 2500 t amb = ? 40 ? c to +85 ?c
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 4 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 5. block diagram fig 2. block diagram (level 0) fig 3. differential output driver simplified circuit dsclp dsclm scl dsdap dsdam sda dintp dintm int pca9616 v dd(a) v dd(b) 002aah589 connect i 2 c-bus hot swap logic en ready en power-on reset, plug-in detection and debouncing pidet connect vdda_se l connect connect v ss connect v dd(a) dsclp, dsdap, dintp 002aag405 v dd dsclm, dsdam, dintm
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 5 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 6. pinning information 6.1 pinning 6.2 pin description fig 4. pin configuration for tssop16 PCA9616PW v dd(a) v dd(b) sda dsdam en dsdap scl dsclp pidet dsclm ready dintm int dintp v ss vdda_sel 002aah588 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 table 3. pin description symbol pin description v dd(a) 1i 2 c-bus side power supply (0.8 v to 5.5 v) sda 2 card side open-drain serial data input/output en 3 enable input (active high); internal pull-up resistor to v dd(a) scl 4 card side open-drain serial clock input/output pidet 5 plug-in detection, open-dr ain output low to indicate that all hot-swap pins have been steady and reliably plugged into the backplane ready 6 open-drain output that goes high when sda and scl are disconnected from dsda and dscl, and pulls low when two sides are connected int 7 card side open-drain interrupt input/output v ss 8 ground supply voltage (0 v) vdda_sel 9 v dd(a) supply pin option input. floating automatically selects threshold based on v dd(a) magnitude. recommend to be high when v dd(a) >2.2v and be low when v dd(a) < 2.4 v through a resistor. dintp 10 line side differential open-drain interrupt plus input/output dintm 11 line side differential open- drain interrupt minus input/output dsclm 12 line side differential open-drain clock minus input/output dsclp 13 line side differential open-drain clock plus input/output dsdap 14 line side differential open-drain data plus input/output dsdam 15 line side differential open-drain data minus input/output v dd(b) 16 differential side power supply (3.0 v to 5.5 v)
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 6 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 7. functional description refer to figure 2 . the pca9616 is used at each node of the di 2 c-bus signal path, to provide conversion from the di 2 c-bus signal format to conventional i 2 c-bus/smbus, allowing the connection of existing i 2 c-bus/smbus devices as slaves or the bus master. because the signal voltages on the i 2 c-bus/smbus bus side may be different from the di 2 c-bus side, there are two power supply pins and a common grou nd. static offset is employed by the i 2 c-bus/smbus side to prevent bus latch up. signal direction is determined by the i 2 c-bus/smbus bus protocol, and does not requir e a direction signal, as these bus buffers automatically set signal flow direction. an e nable pin (en) is provided to disable the bus buffer, and is useful for fault finding, power- up sequencing, or reconfiguration of a large bus system by isolating sections not needed at all times. construction of the differential transmissi on line is not device dependent. pcb traces, open wiring, twisted pair cables or a comb ination of these may be used. twisted pair cables offer the best performance. a typica l twisted pair transmis sion line cable has a characteristic impedance of ?about 100 ? ? and must be terminated at both ends in 100 ? to prevent unwanted signal reflection s. multiple nodes (each using a di 2 c-bus buffer) may be connected at any point along this transmission line, however, the stub length will degrade the bus performance, and should therefore be minimized. 7.1 i 2 c-bus/smbus side the i 2 c-bus/smbus side of the pca9616 differential bus buffer is connected to other i 2 c-bus/smbus devices and requires pull-up resistors on each of the scl and sda signals. the value of the resistor should be chosen based on the bus capacitance and desired data speed, being careful not to overload the driver current rating of 3 ma for standard and fast modes, 30 ma for fast-mode plus (fm+). note that at lower supply voltages the driver will not deliv er the higher current (see table 5 ? static characteristics ? ). the i 2 c-bus/smbus side of the pca9616 is powered from the v dd(a) supply pin. 7.2 di 2 c-bus side differential pair in previous i 2 c-bus/smbus designs the nodes (master and one or more slaves) are connected by wired-or in combination with a single pull-up resistor. this simple arrangement is not suited for long distances more than one meter (1 m) or about three feet (3 ft), due to ringing and reflections on the un-terminated bus. the use of a transmission line with correct te rmination eliminates this problem, and is further improved by differential signaling used in the di 2 c-bus scheme. each node acts as both a driver and a receiver to allow bidirectional signal flow , but not at the same time. switching from transmit to receive is done automatically. the di 2 c-bus side of the pca9616 is powered from the v dd(b) supply pin. the di 2 c-bus is also biased to an idle state (d+ more positive than d ? ) to be compatible with the i 2 c-bus/smbus wired-or scheme, when not transmitting traffic (data). this allows every node to receive broadcast mess ages from the master, and return ack/nack and data in response. biasing is done with additional resistors, connected to v dd(b) and v ss (the local ground), as shown in figure 5 . the transmission line is terminated in the characteristic impedance of the cable, typically 100 ? . this is the value defined by three resistors, the other two resistors providing th e idle condition bias to the twisted pair.
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 7 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 7.2.1 noise rejection impulse noise coupled into the i 2 c-bus/smbus signals can prevent the i 2 c-bus/smbus bus from operating reliably. the hostile signals may appear on the scl line, sda line, or both. impulse noise may also enter the co mmon ground connection, or be caused by current in the ground path caused by dc power supplies, or other signals sharing the common ground return path. this problem is removed by using a differential transmission line, in place of the i 2 c-bus/smbus signal path. the di 2 c-bus receiver (at each di 2 c-bus node) subtracts the signals on the two differential lines (d+ and d ? ), and eliminates any common-mode noise that is coupled into the di 2 c-bus. the receiver amplifies the signals which are also attenuated by the bulk re sistance of the transmission line cable connection, and does not rely on a common ground connection at each node. 7.2.2 rejection of ground offset voltage hostile signals interfere with the i 2 c-bus/smbus bus through the common ground connection between each node. current in this ground path will caus e an offset that may cause false data or push the i 2 c-bus/smbus signals outside of an acceptable range. unwanted ground offset can be caused by heavy dc current in the ground path, or injection of ground current from ac signals, ei ther of which may show up as false signals. because the di 2 c-bus node?s receiver responds only to the difference between the two di 2 c-bus transmission lines, common-mode signals are ignored. there is no need to have a ground connection between each of the nodes, which may be powered locally. nodes may also be powered by extra conductors (for v dd and ground) run with the di 2 c-bus signals. voltage offsets caused by dc current in these additional wires will be ignored by the di 2 c-bus receiver, which subtracts the two differential signals (d+ and d ? ). 7.2.3 interrupt channel the pca9616 has a third channel identical to the scl or sda channel that can be used as a side band for interrupt or reset. if unused, the int pin should be held low and the dintm and dintp are left ?not connected?. fig 5. di 2 c-bus terminations dxxxp dxxxm aaa-011061 twisted-pair cable dxxxp dxxxm
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 8 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 7.3 en pin enable input to connect the device into bus. when this pin is low, the device will never connect to the bus, and disconnect the scl/ sda from differential scl/sda, and ready pin set high. when en is driven high, and v dd(a) and v dd(b) are stable and di 2 c-bus side are with appropriate loads (indicated by pidet goes low), the en pin connects sda/scl to differential sda/scl after a st op bit or bus idle has been detected on differential line bus. en pin should never change state during an i 2 c-bus/smbus operation because disabling during a bus ope ration will hang the bu s and enabling part way through a bus cycle could confuse the i 2 c-bus/smbus parts being enabled. the en pin should only change state when the global bus and the buffer port are in an idle state to prevent system failures. 7.4 pidet pin plug-in status output. this open-drain n-channel mosfet output pulls low when the hot-swapped pins (differential sda and scl) have been steady and reliably plugged into the bus when v dd(a) and v dd(b) are powered. connect a pull-up resistor, typically 10 k ? , from this pin to v dd(a) . leave open or tie to v ss if unused. 7.5 ready pin connection ready status output. this open-d rain n-channel mosfet output goes high when the input and output sides are disconnected. ready is pulled low when en is high, pidet is low, and a connection has been established between the input and differential output. connect a pull-up resistor, typically 10 k ? , from this pin to v dd(a) . leave open or tie to v ss if unused. 7.6 vdda_sel pin enable input to select v dd(a) range. tie to v dd(b) if v dd(a) is greater than 2.2 v and constant v ol on scl/sda (0.52 v) is desired, and tie to v ss if v dd(a) is less than 2.4 v and the ratio v ol (0.2 ? v dd(a) ) is desired. or leave open to let the device automatically switch based on v dd(a) magnitude. 7.7 hot swap and power-on reset during a power-on sequence, an initialization circuit holds the pca9616 in a disconnected state, meaning all outputs ? sda, scl an d the differential pins dsclp/dsclm and dsdap/dsdam ? are in a high-impedance stat e. as the power supply rises (either power-up or live insertion), th e initialization circuit enters a state where the internal references are stabilized and an internal timer is tr iggered. after 1 ms, power is applied to the rest of the circuitry and the pca961 6 detects the status on the differential dsclp/dsclm and dsdap/dsdam lines. when th e differential lines are detected as connected to a bus with valid terminat ion, that is, both dsclm/dsdam < 0.9 ? v dd(b) and dsclp/dsdap > 0.1 ? v dd(b) , another timer is triggered. at the end of 10 ms, hot-swap logic ( figure 2 ) is enabled and the en pin can detect a stop bit and bus idle condition. however, there is still no connection betw een sda and dsdap/dsdam or between scl and dsclp/dsclm. a successful en pin seq uence must occur for actual connection. when the en pin is set high and the dsd ap and dsclp pins have been high for the bus idle time or when both the scl and sda pins are high and a stop condition has been seen on the differential bus (dsdap/dsdam and dsclp/dsclm pins), a
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 9 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic connection is established between the differen tial and the single-ended buses. whenever disconnected status is detect ed or the device is un-powered, the pca9616 will disconnect the single-ended to differential buses, and the hot swap sequ ence will repeat again before the pca9616 connects sda to dsda p/dsdam and scl to dsclp/dsclm. remark: start-up process is the same for both PCA9616PW and pca9615dp, except that pidet and ready signals are only available in 16-pin package. for pca9616, the ready time is at least 11 ms (1 ms for power ready, 10 ms for plug-in debouncing delay), which means the devic e can only be in operation after 11 ms with v dd(a) ,v dd(b) on and a bus idle/stop detected. fig 6. hot swap related timings ~11 ms ~1 ms t en for power-on and stabilization v dd(a) , v dd(b) pwon ~10 ms pidet en only when en goes high and pidet inputs go low will the bus idle/stop detector start functioning t idle scl/sda, dscl/dsda t stop ready = pwon && pidet && en && 002aah591 (set by bus idle or stop) plug-in debouncing time
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 10 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 8. application design-in information 8.1 i 2 c-bus as with the standard i 2 c-bus system, pull-up re sistors are required to provide the logic high levels on the single-ended buffered bu s (standard open-drain configuration of the i 2 c-bus). the size of these pull-up resistor s depends on the system. the device is designed to work with standard-mode, fast-mode and fast-mode plus i 2 c-bus devices in addition to smbus devices. standard-mode and fast-mode i 2 c-bus and smbus devices only specify 3 ma output drive; this limits the termination current to 3 ma in a generic i 2 c-bus system where standard-mode device s and multiple masters are possible. when only fast-mode plus devices are used, then higher termination currents can be used due to their 30 ma sink capability. the sink capability varies from 3 ma at 0.8 v to 30 ma at 5.5 v with the cut-off between 30 ma and 3 ma at 2.3 v. 8.2 differential i 2 c-bus application see figure 7 through figure 9 . the simple application ( figure 7 ) shows an existing smbus/i 2 c-bus being extended over a section of di 2 c-bus transmission line, containing a dedicated twisted pair for scl and sda. at one end of the transmission line a resistor network (r1-r2-r1) terminates the twisted pair cable and biases d+ positive with respect to d ? . an identical resistor network at the other end of the transmission line term inates the twisted pair cable. dc power for each end of the transmission line and the v dd(b) of each pca9616 bus buffer can be from separate and isolated power supplies, or use the same supply and ground run in separate wires along the same path as the di 2 c-bus signal twisted pairs. telecom category 5 (?cat 5?) data cable is we ll suited for this task , but loose wires may also be used, with a reduction in performance. assuming v dd(b) is 5 v, and using cat 5 cable, r2 is 120 ? , and r1 is 600 ? . the parallel combination yields a termination of 100 ? at each end of the twisted pairs. either side of the di 2 c-bus buffer pair is connected to standard smbus/i 2 c buses, which require their own pull-up resistors to v dd(a) of the pca9616 bus buffers. v dd(a) and v dd(b) can be the same supply, however, making them different voltages enables the pca9616 bus buffers to level translate between the smbus/i 2 c-bus and di 2 c-bus sections of the bus, or to have different supply voltages and level translate at either end of the di 2 c-bus and smbus/i 2 c-bus system. for example, the left-hand bus master (and local slave) may operate on a 3.3 v supply and smbus/i 2 c-bus while the di 2 c-bus transmission lines are at 5 v, and the right-hand slave is operated from a different 3.3 v supply and smbus/i 2 c-bus, or even a different bus voltage other than 3.3 v. depending upon the timing from the system master, clock toggle ra tes can vary from 10 khz for the smbus (or less for smbus/i 2 c-bus protocol) up to 100 khz (standard mode), 400 khz (fast mode), or up to 1 mhz (fast-mode plus). the bus path is bidirectional. assume that the left side smbus/i 2 c-bus becomes active. a start condition (sda goes low while sda is high) is sent. this upsets the idle condition on the di 2 c-bus section of the bus, because d+ was more positive than d ? and
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 11 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic now they are reversed. the right side bus buffer sees the differential lines change polarity and in turn pulls sda low on the smbus/i 2 c-bus side of the bus buffer, transmitting the start condition to the slave on that section of the smbus/i 2 c-bus. if the data clocked out by the left side master contains a valid address of the right side slave, that slave responds by pulling sda lo w on the ninth clock. this condition is transmitted across the di 2 c-bus section that has now changed flow direction, and received by the left side bus buffer (again, d+ was more positive than d ? and now they are reversed). this sequence continues until the master sends the stop condition (scl high while sda goes high), placing the active slave (on the right side) back to idle. when idle, the normal smbus/i 2 c-bus (both left and right sections) are pulled up by their respective pull-ups. in turn, the di 2 c-bus section of the bus rests with d+ more positive than d ? . the idle condition can be changed by any node on either smbus/i 2 c-bus section or an additional di 2 c-bus node, if present, on the di 2 c-bus section of the system. this allows the existing smbus/i 2 c-bus protocol to operate transpa rently over a mix of smbus/i 2 c and di 2 c bus segments. due to the smbus/i 2 c-bus handshake protocol (ack/nac k on the ninth clock pulse), the direction of the smbus/i 2 c-bus is reversed often. the ?time of flight? for the signals to pass through each bus buffer and for the target slave to respond defines the maximum speed of the bus, regardless of how fast the clock toggles. the di 2 c-bus section of the bus requires two additional pca9616 bus buffers, further delaying the smbus/i 2 c-bus traffic. if the di 2 c-bus transmission line section is made lo nger, the bus will operate much slower, regardless of the clock toggle speed. it is not necessary to have a ground connection between each end of the di 2 c section of the bus. the di 2 c-bus receiver responds to reversal of the polarity of the d+ and d ? signals, and ignores the common-mode voltage that may be present. ideally, the common-mode voltage is the same at each end of the twisted pairs, and no current flows along the twisted pair when the bus is idle, because the d+ and d ? di 2 c-bus drivers are both high-impedance, the bus is biased by r1-r2-r1 at each end. if the common-mode voltage is not 0 v, current will flow along the twisted pa ir, returni ng through the common ground or common power supply connection if present. if both ends of the twisted pair are powered by the same v dd(b) supply and one end is remote, there will be a common- mode offset between them. this is ignored by the di 2 c-bus receivers, which only respond to the difference between d+ and d ? . however, a large common-mode offset voltage will force the d+ and d ? signals out of the range of the rece iver, and data will be lost. the pc a9616 bus buffers use standard esd protection networks to protect the external pins, and therefore should not be biased above or below the v dd(b) and v ss pins respectively. this limits the common-mode range to approximately 0.5 ? v dd(b) . dc resistance of the transmissi on line will attenuate the signals, more so over longer distances. the loss of signal amplitude is made up by the gain of the di 2 c-bus receiver. there is a limit to how long the di 2 c-bus section can be made, as it is necessary for the driver to overcome the bias on the transmission line, in order to signal a polarity change (d+ and d ? reversal) at the receiver end.
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 12 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic remark: for clarity, dsdap and dsdam are flipped from actual device pinout. fig 7. typical application for pca9616 v dd(b)1 pca9616 r1 r2 r1 r1 r2 r1 scl sda slave master dsclp dsclm dsdap dsdam v ss1 r1 r2 r1 r1 r2 r1 scl sda master slave r1 r2 r1 int dintp dintm r1 r2 r1 pca9616 002aag411 card card int v dd(a)1 v dd(a)2 (optional) (optional) v ss2 v dd(b)2
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 13 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic remark: for clarity, dsdap and dsdam are flipped from actual device pinout. fig 8. pca9616 application diagram; v dd and v ss are routed through the cable v dd(b) pca9616 r1 r2 r1 r1 r2 r1 scl sda slave master dsclp dsclm dsdap dsdam v ss r1 r2 r1 int dintp dintm 002aag412 card pca9616 slave master card v dd(b) v dd(b) termination v dd(b) pca9616 slave master card v ss v dd pca9616 card v ss v dd v dd(b) optional slave master r1 r2 r1 r1 r2 r1 r1 r2 r1 v dd(a) v dd(a) v dd(a) v dd(a)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 14 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic remark: for clarity, dsdap and dsdam are flipped from actual device pinout. fig 9. pca9616 application diagram; v dd and v ss are not routed through the cable v dd(b) pca9616 scl sda slave master dsclp dsclm dsdap dsdam v ss int dintp dintm card pca9616 slave master card pca9616 slave master card v dd(b) pca9616 slave master card pca9616 slave master card pca9616 slave master card 002aag413 v dd(a) v dd(a) v dd(a) v dd(a) v dd(a) v dd(a)
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 15 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic fig 10. hot swap application 002aah590 v dd(a) v dd(b) dscl dsda v ss pidet en ready scl sda master card with master. the master can issue the en after pidet goes low. v dd(a) v dd(b) dscl dsda v ss pidet en ready scl sda slave card without master. backplane connector differential terminations are always on backplane. 3.3 v 5 v
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 16 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic fig 11. differential bus waveform aaa-009538 fig 12. single-ended bus waveform (master side of bus) 002aah616 9th clock pulse acknowledge scl sda v ol of master v ol of pca9616 (from slave)
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 17 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 9. limiting values table 4. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd(b) supply voltage port b differential bus; 3.0 v to 5.5 v ? 0.5 +6 v v dd(a) supply voltage port a single-ended bus; 0.8 v to 5.5 v ? 0.5 +6 v v o(dif) differential output voltage ? 0.5 +6 v v bus bus voltage voltage on i 2 c-bus a side, or enable (en) ? 0.5 +6 v i i/o input/output current sda, scl, int, dxxxx pins - 80 ma pidet , ready pins - 20 ma i dd(b) supply current port b - 160 ma p tot total power dissipation - 100 mw t stg storage temperature ? 55 +125 ?c t amb ambient temperature operating in free air ? 40 +85 ?c t j junction temperature - 125 ?c
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 18 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 10. static characteristics table 5. static characteristics v dd(b) = 3.0 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd(b) supply voltage port b differential bus 3.0 - 5.5 v v dd(a) supply voltage port a single-ended bus [1] 0.8 - 5.5 v i dd(vdda) supply current on pin v dd(a) -- 16 ? a i ddh(b) port b high-level supply current 3-channel; both channels high; v dd(b) =5.5v; int = sdan = scln = v dd(a) =5.5v -1.22.0ma i ddl(b) port b low-level supply current 3-channel; both channels low; v dd(b) = 5.5 v; sda and scl = v ss ; differential i/os open -1.22.0ma driving termination; 3 channels - 95 136 ma input and output sda and scl and int v ih high-level input voltage 0.7v dd(a) -5 . 5v v il low-level input voltage vdda_sel = 1 and v dd(a) >2.2v ? 0.5 - +0.4 v vdda_sel = 0 and v dd(a) <2.4v ? 0.5 - +0.1v dd(a) v v ik input clamping voltage i i = ? 18 ma ? 1.5 - 0 v i li input leakage current v i =v dd(a) -- ? 2 ? a i il low-level input current v i = 0.2 v for v dd(a) >1.8v; v i = 0.1 v for v dd(a) <1.8v -- 12 ? a v ol low-level output voltage i ol =200 ? a or 30 ma (v dd(a) > 2.2 v and vdda_sel = 1) 0.47 0.52 0.6 v i ol =200 ? a or 3 ma (v dd(a) < 2.4 v and vdda_sel = 0) -0.2v dd(a) 0.3v dd(a) v ol ? v il difference between low-level output and low-level input voltage guaranteed by design i ol =200 ? a or 30 ma (v dd(a) > 2.2 v and vdda_sel = 1) -- 90mv i ol =200 ? a or 3 ma (v dd(a) < 2.4 v and vdda_sel = 0) - 0.05v dd(a) 0.1v dd(a) i loh high-level output leakage current v o =v dd(a) -- 2 ? a c io input/output capacitance v i =v dd(a) or 0 v; disabled or v dd(a) =0v - 7 10 pf
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 19 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic [1] single-ended bus supply voltage. recommend vdda_sel = 0 for v dd(a) = 0.8 v to 2.4 v, and vdda_sel = 1 for v dd(a) = 2.2 v to 5.5 v. if left floating, the best selection is automatically picked based on magnitude of v dd(a) . input and output dsdap/dsdam an d dsclp/dsclm and dintp/dintm v cm common-mode voltage 0 - v dd(b) v i li input leakage current v i =v dd(b) dsclp, dsclm, dsdap, dsdam pins -- ? 40 ? a dintp, dintm pins - - ? 1 ? a i il low-level input current v i =0.2v dsclp, dsclm, dsdap, dsdam pins -- ? 40 ? a dintp, dintm pins - - ? 1 ? a r pu pull-up resistance internal pull-up resistor on dsclm and dsdam connected to v dd(b) rail - 200 - k ? r pd pull-down resistance internal pull-down resistor on dsclp and dsdap connected to v ss rail - 200 - k ? v th(dif) differential receiver threshold voltage 0v ? v cm ? v dd(b) ? 200 - +200 mv v i(hys) hysteresis of input voltage receiver; 0 v ? v cm ? v dd(b) -30- mv v o(dif)(p-p) peak-to-peak differential output voltage single-ended input low no load ? v dd(b) --v r l = 54 ? at v dd(b) =5v ? 5.0 ? 1.5 ? 1.0 v c io input/output capacitance v i =v dd(b) or 0 v; disabled or v dd(b) =0v - 7 10 pf input en v ih high-level input voltage 0.7v dd(a) -5 . 5v v il low-level input voltage ? 0.5 - +0.3v dd(a) v i li input leakage current v i =v dd(b) ? 1- +1 ? a i il(en) low-level input current on pin en v i = 0.2 v, en; v dd(a) =5.5v - ? 20 ? 54 ? a c i input capacitance v i =v dd(a) - 6 10 pf r pu pull-up resistance internal pull-up resistor connected to v dd(a) rail - 300 - k ? output pidet and ready v ol low-level output voltage i ol =3ma; v dd(b) =3.0v ? 0.5 - +0.4 v i l leakage current ready and pidet off; v dd(a) =v pidet /v ready =5.5v -- ? 2 ? a input vdda_sel v ih high-level input voltage 0.7v dd(b) -5 . 5v v il low-level input voltage ? 0.5 - +0.3v dd(b) v i li input leakage current v dd(b) =5.5v; v i =0v for v dd(a) = 1.8 v, or v i =v dd(b) for v dd(a) =5.5v -- ? 1 ? a table 5. static characteristics ?continued v dd(b) = 3.0 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 20 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 11. dynamic characteristics [1] times are specified with loads of 1.35 k ? pull-up resistance and 50 pf load capacitance on the a side, and 50 ? termination network resistance and 50 pf load capacitance on the b side. different l oad resistance and capacitance will alter the rc time constant, t hereby changing the propagation delay and transition times. [2] pull-up voltages are v dd(a) on the a side and termination network on the b side. [3] typical values were measured with v dd(a) = 3.3 v at t amb =25 ? c, unless otherwise noted. [4] the t plh delay data from b side to a side is measured at 0 v differential on the b side to 0.5v dd(a) on the a side. [5] typical value measured with v dd(a) =3.3v at t amb =25 ? c. [6] the proportional delay data from a side to b side is measured at 0.5v dd(a) on the a side to 0 v on the b side. [7] the enable pin (en) should only change state when the global bus and the repeater port are in an idle state. table 6. dynamic characteristics v dd = 2.7 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; unless otherwise specified. [1] [2] symbol parameter conditions min typ [3] max unit t plh low to high propagation delay single-ended side to differential side; figure 15 [4] ? 140 ? 120 - ns t plh2 low to high propagation delay 2 single-ended side to differential side; figure 15 --100ns t phl high to low propagation delay single-ended side to differential side; figure 13 [5] --120ns sr r rising slew rate differential side; figure 13 --1v/ns sr f falling slew rate differential side; figure 13 [5] --1v/ns t plh low to high propagation delay differential side to single-ended side; figure 14 [6] --150ns t phl high to low propagation delay differential side to single-ended side; figure 14 [6] --150ns sr f falling slew rate single-ended side; figure 14 --0.1v/ns t dis disable time en low to disable [7] --200ns t idle idle time ready active after bus idle - 100 - ? s t stop stop time ready active after bus stop - - 1 ? s t deb(bus) bus debounce time 5 - 15 ms
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 21 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 11.1 ac waveforms v dd(a) =3.0v. sr f =0.6 ? (v high ? v low ) / t thl sr r =0.6 ? (v high ? v low ) / t tlh v dd(a) =3.0v. sr f =0.6v dd(a) / t thl fig 13. propagation delay and transition times; single-ended side to differential side fig 14. propagation delay and transition times; differential side to single-ended side fig 15. propagation delay 002aag416 v dd(a) 0.3 v t plh t thl 0.5v dd(a) 0.5v dd(a) input output 20 % 0 v 0 v 80 % 20 % 80 % t phl t tlh ?2.5 v 0.1 v differential voltage input output 80 % 80 % 0.5v dd(a) 0.5v dd(a) 20 % 20 % 0 v 0 v t phl t plh 0.3 v ?0.3 v v dd(a) t thl t tlh 002aag417 differential voltage 0.5 v input sda, scl output dsclp/dsclm, dsdap/dsdam t plh2 0 v 002aag418 0.3 v ?2.5 v 0.5v dd(a) t plh
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 22 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 12. test information r l = load resistor; 1.35 k ? on single-ended side. r t = termination resistance should be equal to z o of pulse generators. fig 16. test circuit for differential outputs r l = load resistor; 1.35 k ? on single-ended side. c l = load capacitance includes ji g and probe capacitance; 50 pf. r t = termination resistance should be equal to z o of pulse generators. fig 17. test circuit for open-drain output i 2 c-bus level shifter v o 60 002aag419 r t v i v dd(b) dut v dd(a) pulse generator 300 v dd(a) p m 300 v dd(b) differential probe differential v o c l r l 002aag420 r t v dd(a) v dd(a) dut v dd(b) p m
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 23 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 13. package outline fig 18. package outline sot403-1 (tssop16) 81,7 $ $ $ e s f ' ( h + ( / / s 4 = \ z y 5()(5(1&(6 287/,1( 9(56,21 (8523($1 352-(&7,21 ,668('$7( ,(& -('(& -(,7$ pp r r ',0(16,216ppduhwkhruljlqdoglphqvlrqv 1rwhv 3odvwlfruphwdosurwuxvlrqvripppd[lpxpshuvlghduh qrwlqfoxghg 3odvwlflqwhuohdgsurwuxvlrqvripppd[lpxpshuvlghdu hqrwlqfoxghg 627 02 z 0 e s ' = h $ $ $ / s 4 ghwdlo; / $ + ( ( f y 0 $ ; $ \ pp vfdoh 76623sodvwlfwklqvkulqnvpdoorxwolqhsdfndjhohdgve rg\zlgwkpp 627 $ pd[ slqlqgh[
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 24 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 25 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 19 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 7 and 8 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 19 . table 7. snpb eutectic process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 8. lead-free process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 26 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 19. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 27 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 15. soldering: pcb footprints fig 20. pcb footprint for sot403-1 (tssop16); reflow soldering ',0(16,216lqpp $\ %\ ' ' *\ +\ 3 & *[ vrwbiu +[ 627 vroghuodqg rffxslhgduhd )rrwsulqwlqirupdwlrqiruuhiorzvroghulqjri76623sdfndjh $\ %\ *\ & +\ +[ *[ 3 *hqhulfirrwsulqwsdwwhuq 5hihuwrwkhsdfndjhrxwolqhgudzlqjirudfwxdood\rxw 3 ' '[ 3
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 28 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 16. abbreviations 17. revision history table 9. abbreviations acronym description cdm charged-device model di 2 c-bus differential inter-integrated circuit bus esd electrostatic discharge hbm human body model i 2 c-bus inter-integrated circuit bus i/o input/output led light emitting diode smbus system management bus table 10. revision history document id release date data sheet status change notice supersedes pca9616 v.2 20140310 product data sheet - pca9616 v.1 modifications: ? inserted the word ?multipoint? in descriptive title of this data sheet ? section 1 ? general description ? : ? added ?remark? paragraph ? eighth paragraph re-written ? figure 1 ? smbus/i 2 c-bus translation to di 2 c-bus and back to smbus/i 2 c-bus ? updated: added en, pidet and reset pins ? section 2 ? features and benefits ? : ? added (new) first bullet item ? seventh bullet item changed from ?and fast-m ode plus at 1 mhz? to ?and smbus, fast-mode plus up to 1 mhz? ? section 2 ? features and benefits ? , tenth bullet item: ? second sub-bullet changed from ?3 v differenti al output (unloaded: ~5 v, loaded: ~1.5 v)? to ?1.5 v differential output with nominal terminals? ? sixth sub-bullet changed from ?(1 m ? typical)? to ?(200 k ? typical)? ? figure 2 ? block diagram (level 0) ? updated (added transistor on signal pidet ) ? figure 3 ? differential output driver simplified circuit ? updated (corrected transistor types) ? table 3 ? pin description ? : ? updated description for v dd(a) (pin 1) ? updated description for en (pin 3) ? description for vdda_sel (pin 9) changed from ?floating is not information of v dd(a) range. recommend to be high when v dd(a) > 2.3 v and be low when v dd(a) < 2.3 v through a resistor.? to ?floati ng automatically selects threshold based on v dd(a) magnitude. recommend to be high when v dd(a) > 2.2 v and be low when v dd(a) < 2.4 v through a resistor.? ? figure 5 ? di 2 c-bus terminations ? corrected: from ?dxxxn? to ?dxxxm? (2 places) ? added (new) section 7.2.3 ? interrupt channel ? ? section 7.3 ? en pin ? : first paragraph re-written
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 29 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic modifications: (continued) ? section 8.2 ? differential i 2 c-bus application ? : ? second paragraph, second sentence changed from ?(r1, r2, r3)? to ?(r1-r2-r1)? ? third paragraph, second sentence ch anged from ?r1 and r3 are 600 ? ? to ?and r1 is 600 ? ? ? 13th paragraph, first sentence changed from ?r1, r2 and r3? to ?r1-r2-r1? ? figure 7 ? typical application for pca9616 ? : corrected pin names; added ?remark?; ?r3? changed to ?r1?; added dashed line to indicate optional connection ? figure 8 ? pca9616 application diagram; v dd and v ss are routed through the cable ? : corrected pin names; corrected resistor label from ?r3? to ?r1?; added ?remark? ? figure 9 ? pca9616 application diagram; v dd and v ss are not routed through the cable ? : corrected pin names; added ?remark? ? table 4 ? limiting values ? : ? v dd(a) : combined voltage ranges to one condition ? deleted characteristic ?i dd , supply current? ? added characteristic ?i i/o , input/output current? ? table 5 ? static characteristics ? , sub-section ?supplies?: ? i ddh(b) typ value changed from ?0.9 ma? to ?1.2 ma? ? i ddl(b) (condition ?3-channel; both channels low; v dd(b) = 5.5 v; sda and scl = v ss ; differential i/os open?), typ value changed from ?1.5 ma? to ?1.2 ma? ? i ddl(b) (condition ?3-channel; both channels low; v dd(b) = 5.5 v; sda and scl = v ss ; differential i/os open?), max value changed from ?3.0 ma? to ?2.0 ma? ? i ddl(b) (condition ?driving termination; 3 channels?), typ value changed from ?105 ma? to ?95 ma? ? table 5 ? static characteristics ? , sub-section ?input and output sda and scl and int?: ? deleted characteristic ?c l , load capacitance? ? i li condition changed from ?v i = 5.5 v? to ?v i =v dd(a) ? ? i loh : condition changed from ?v o = 5.5 v? to ?v o = v dd(a) ?; max value changed from ?2 ? a? to ? ? 2 ? a? ? c io : merged conditions; max value changed from ?-? to ?10 pf? ? table 5 ? static characteristics ? , sub-section ?input and output dsdap/dsdam and dsclp/dsclm and dintp/dintm?: ? v cm max value changed from ?5.5 v? to ?v dd(b) ? ? i li : condition changed from ?v i = 5.5 v? to ?v i =v dd(b) ? ? i il : condition changed from ?sda, scl; v i =0.2v? to ?v i = 0.2 v for v dd(a) >1.8v; v i = 0.1 v for v dd(a) <1.8v? ? v th(dif) : condition changed from ?0 v ? v cm ? 5.5 v? to ?0 v ? v cm ? v dd(b) ? ? v i(hys) : condition changed from ?receiver; 0 v ? v cm ? 5.5 v? to ?receiver; 0 v ? v cm ? v dd(b) ?; min value changed from ?? to ?-?; typ value changed from ?? to ?30 mv?; max value changed from ?? to ?-? ? c io , merged conditions; max value changed from ?-? to ?10 pf? ? table 5 ? static characteristics ? , sub-section ?input en?: ? i il(en) typ value changed from ? ? 10 ? a? to ? ? 20 ? a? ? c io : max value changed from ?-? to ?10 pf? ? table 5 ? static characteristics ? , sub-section ?input vdda_sel?: i li conditions changed from ?v dd(b) =5.5v; v i =0v for v dd(a) < 1.8 v, or v i =v dd(b) for v dd(a) >2.5v? to ?v dd(b) =5.5v; v i =0v for v dd(a) =1.8v, or v i =v dd(b) for v dd(a) =5.5v? ? table 5 ? static characteristics ? , table note [1] re-written pca9616 v.1 20131002 preliminary data sheet - - table 10. revision history ?continued document id release date data sheet status change notice supersedes
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 30 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pca9616 all information provided in this document is subject to legal disclaimers. ? nxp semiconductors n.v. 2014. all rights res erved. product data sheet rev. 2 ? 10 march 2014 31 of 32 nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp semiconductors n.v. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pca9616 3-channel multipoint fm+ di 2 c-bus buffer with hot-swap logic ? nxp semiconductors n.v. 2014. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 10 march 2014 document identifier: pca9616 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 functional description . . . . . . . . . . . . . . . . . . . 6 7.1 i 2 c-bus/smbus side . . . . . . . . . . . . . . . . . . . . . 6 7.2 di 2 c-bus side differential pair . . . . . . . . . . . . . . 6 7.2.1 noise rejection . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2.2 rejection of ground offset voltage . . . . . . . . . . 7 7.2.3 interrupt channel. . . . . . . . . . . . . . . . . . . . . . . . 7 7.3 en pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.4 pidet pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.5 ready pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.6 vdda_sel pin . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.7 hot swap and power-on reset. . . . . . . . . . . . . . 8 8 application design-in information . . . . . . . . . 10 8.1 i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8.2 differential i 2 c-bus application . . . . . . . . . . . . 10 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 10 static characteristics. . . . . . . . . . . . . . . . . . . . 18 11 dynamic characteristics . . . . . . . . . . . . . . . . . 20 11.1 ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . 21 12 test information . . . . . . . . . . . . . . . . . . . . . . . . 22 13 package outline . . . . . . . . . . . . . . . . . . . . . . . . 23 14 soldering of smd packages . . . . . . . . . . . . . . 24 14.1 introduction to soldering . . . . . . . . . . . . . . . . . 24 14.2 wave and reflow soldering . . . . . . . . . . . . . . . 24 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 24 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 25 15 soldering: pcb footprints. . . . . . . . . . . . . . . . 27 16 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17 revision history . . . . . . . . . . . . . . . . . . . . . . . . 28 18 legal information. . . . . . . . . . . . . . . . . . . . . . . 30 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31 19 contact information. . . . . . . . . . . . . . . . . . . . . 31 20 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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