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november 2011 doc id 15187 rev 8 1/23 23 vni2140j dual high side smart power solid state relay features nominal current: 0.5 a per channel shorted load protections junction overtemperature protection case overtemperature protection for thermal independence of the channels thermal case shutdown restart not simultaneous for the various channels protection against loss of ground current limitation 1 a per channel undervoltage shutdown open load in off-state and short to v cc detection open-drain diagnostic outputs 3.3 v cmos/ttl compatible inputs fast demagnetization of inductive loads conforms to iec 61131-2 description the vni2140j is a monolithic device designed using stmicroelectronics' vipower technology. the device drives two independent resistive or inductive loads with one side connected to ground. active current limitation prevents a drop in system power supply in cases of shorted-load, and built-in thermal shutdown protects the chip from damage due to over-temperature and short- circuit. in overload conditions, channel turns off and on automatically to maintain the junction temperature between ttsd and tr. if the case temperature reaches tcsd, the overloaded channel is turned off and restarts only when case temperature decrea ses down to tcr. in order to avoid high-peak current from the supply, when more than one channel is overloaded the tcsd restart is not simultaneous. non overloaded channels continue to operate normally. the open-drain diagnostics output indicates over-temperature conditions and open- load in off state. type v demag (1) 1. per channel r dson (1) i out (1) v cc vni2140j v cc -45 v 0.08 1 a (2) 2. current limitation 45 v powersso-12 table 1. device summary order codes package packaging vni2140j powersso-12 tube VNI2140JTR tape and reel www.st.com
contents vni2140j 2/23 doc id 15187 rev 8 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 switching waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 open load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
vni2140j block diagram doc id 15187 rev 8 3/23 1 block diagram figure 1. block diagram
pin connections vni2140j 4/23 doc id 15187 rev 8 2 pin connections figure 2. pin connections (top view) table 2. pin description n name description 1 nc not connected 2 input 1 channel 1 input 3.3 v cmos/ttl compatible 3 diag 1 channel 1 diagnostic in open-drain configuration 4 gnd device ground connection 5 diag 2 channel 2 diagnostic in open-drain configuration 6 input 2 channel 2 input 3.3 v cmos/ttl compatible 7 vcc supply voltage 8 output 2 channel 2 power stage output, internally protected 9 output 2 channel 2 power stage output, internally protected 10 output 1 channel 1 power stage output, internally protected 11 output 1 channel 1 power stage output, internally protected 12 vcc supply voltage tab tab supply voltage vcc output 1 output 1 output 2 output 2 vcc nc input 1 diag 1 gnd diag 2 input 2
vni2140j maximum ratings doc id 15187 rev 8 5/23 3 maximum ratings 3.1 thermal data table 3. absolute maximum ratings symbol parameter value unit v cc power supply voltage 45 v -v cc reverse supply voltage -0.3 v i gnd dc ground reverse current -250 ma i out output current (continuous) internally limited a i r reverse output current (per channel) -5 a i in input current (per channel) 10 ma v in input voltage +v cc v v diag diag pin voltage +v cc v i diag diag pin current 10 ma v esd electrostatic discharge (r = 1.5 k ; c = 100 pf) 2000 v e as single pulse avalanche energy per channel not simultaneously 300 mj p tot power dissipation at t c = 25 c internally limited w t j junction operating tem perature internally limited c t stg storage temperature -55 to 150 c table 4. thermal data symbol parameter value unit r th(jc) thermal resistance junction-case (1) 1. per channel max 1 c/w r th(ja) thermal resistance junction-ambient (2) 2. when mounted using minimum re commended pad size on fr-4 board max see figure 11 on page 15 c/w
electrical characteristics vni2140j 6/23 doc id 15187 rev 8 4 electrical characteristics 9 v < v cc < 36 v; -40 c < t j < 125 c ; unless otherwise specified v cc = 24 table 5. power section symbol parameter test cond itions min. typ. max. unit vcc supply voltage 9 45 v r ds(on) on-state resistance i out = 0.5 a at t j = 25 c i out = 0.5 a 0.080 0.150 v clamp clamp voltage is = 20 ma 45 52 v i s supply current all channel in off-state on-state with v in =5 v (t j = 125 c) 300 1.9 4 a ma i lgnd output current at turn-off v cc = v diag = v in = v gnd = 24 v, v out = 0 v 1ma v out(off) off-state output voltage v in = 0 v and i out = 0 a 3 v i out (off) off-state output current v in = v out = 0 v 0 5 a i out (off1) v in = 0 v; v out = 4 v -35 0 a table 6. switching symbol parameter test conditions min. typ. max. unit t d(on) turn-on delay time of output current i out = 0.5 a, resistive load input rise time < 0.1 s, t j = 25 c -20 -s t r rise time of output current i out = 0.5 a, resistive load input rise time < 0.1 s, t j = 25 c -10 -s t d(off) turn-off delay time of output current i out = 0.5 a, resistive load input rise time < 0.1 s, t j = 25 c -30 -s t f fall time of output current i out = 0.5 a, resistive load input rise time < 0.1 s, t j = 25 c -8 -s t dol delay time for open load detection - 500 - s dv/dt (on) turn on voltage slope - 3 - v/s dv/dt (off) turn off voltage slope -4 -v/s
vni2140j electrical characteristics doc id 15187 rev 8 7/23 table 7. logical input symbol parameter test conditions min. typ. max. unit v il input low level voltage 0.8 v v ih input high level voltage 2.20 v v i(hyst) input hysteresis voltage 0.15 v i in input current v in = 15 v 10 a v in = 36 v 210 table 8. protection and diagnostic symbol parameter test conditions min. typ. max. unit v diag (1) 1. diag determination > 100 ms after the switching edge. diag voltage output low i diag = 1.5 ma (fault condition) 0.6 v v usd undervoltage protection 79v v usdhys undervoltage hysteresis 0.4 0.5 v i lim dc short circuit current v cc = 24 v; r load < 10 m 12a i ldiag diag leakage current v cc = 32 v 30 a v ol open-load off-state voltage detection threshold v in = 0 v 2 3 4 v t tsd junction shutdown temperature 150 170 c t r junction reset temperature 135 155 200 c t hist junction thermal hysteresis 715 c t csd case shutdown temperature 125 130 135 c t cr case reset temperature 110 c t chyst case thermal hysteresis 715 c v demag output voltage at turn-off i out = 0.5 a; l load >= 1 mh v cc - 45 v cc - 50 v cc - 52 v
electrical characteristics vni2140j 8/23 doc id 15187 rev 8 figure 3. current and voltage conventions
vni2140j truth table doc id 15187 rev 8 9/23 5 truth table table 9. truth table inputn outputn diagn normal operation l h l h h h overtemperature l h l l h l undervoltage l h l l x x shorted load (current limitation) l h l x h h output voltage > v ol l h z (1) h 1. z = depending on the external circuit l h short to v cc l h h h l h
switching waveforms vni2140j 10/23 doc id 15187 rev 8 6 switching waveforms figure 4. switching waveforms
vni2140j switching waveforms doc id 15187 rev 8 11/23 figure 5. switching waveforms (continued) figure 6. switching parameter test conditions i out v in
switching waveforms vni2140j 12/23 doc id 15187 rev 8 figure 7. typical application circuit
vni2140j open load doc id 15187 rev 8 13/23 7 open load in order to detect the open load fault a pull-up resistor must be connected between the v cc line and the output pin. in a normal condition a current flows through the network made up of a pull-up resistor and a load. the voltage across the load is less than v olmin ; so the diag pin is kept high. this is the result in the condition: equation 1 or equation 2 when a open load event occurs the voltage on the output pin rises to a value higher than v olmax (depending on the pull-up resi stor). the diag pin will go down. this result in the condition: equation 3 figure 8. open load detection v cc r load r load r pu + ----------------------------------- - v olmin < v cc v olmin ------------------- - 1 ? ?? ?? r load ? r pu < r pu v cc v olmax ? i out off1 () min ----------------------------------------- - <
open load vni2140j 14/23 doc id 15187 rev 8 figure 9. turn on/off to open load
vni2140j package and pcb thermal data doc id 15187 rev 8 15/23 8 package and pcb thermal data figure 10. powersso-12 pc board figure 11. r thja vs pcb copper area in open box free air condition figure 12. powersso-12 thermal impedance junction ambient single pulse
package and pcb thermal data vni2140j 16/23 doc id 15187 rev 8 pulse calculation formula equation 4 z th = r th x + z thtp (1 ? ) where = t p /t figure 13. thermal fitting model of a double channel hsd in powersso-12 table 10. thermal parameter area/island (cm 2 ) footprint 2 8 r1 (c/w) 0.1 r2 (c/w) 0.2 r3 (c/w) 7 r4 (c/w) 10 10 9 r5 (c/w) 22 15 10 r6 (c/w) 26 20 15 c1 (w.s/c) 0.0001 c2 (w.s/c) 0.002 c3 (w.s/c) 0.05 c4 (w.s/c) 0.2 0.1 0.1 c5 (w.s/c) 0.27 0.8 1 c6 (w.s/c) 3 6 9
vni2140j reverse polarity protection doc id 15187 rev 8 17/23 9 reverse polarity protection this schematic can be used with any type of load. the following is an indication on how to dimension the r gnd resistor. r gnd = (-v cc ) / (-i gnd ) where -i gnd is the dc reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. power dissipation in r gnd (when v cc < 0: during reverse polarity situations) is: pd = (-v cc ) 2 /r gnd note: in normal condition (no reverse polarity) due to the diode there will be a voltage drop between gnd of the device and gnd of the system. figure 14. reverse polarity protection diag i input i gnd output i + vcc r gnd load diode diag i input i gnd output i + vcc r gnd load diode
package mechanical data vni2140j 18/23 doc id 15187 rev 8 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark.
vni2140j package mechanical data doc id 15187 rev 8 19/23 figure 15. powersso-12? package dimensions table 11. powersso-12? mechanical data symbol mm min. typ. max. a 1.250 1.620 a1 0.000 0.100 a2 1.100 1.650 b 0.230 0.410 c 0.190 0.250 d 4.800 5.000 e 3.800 4.000 e 0.800 h 5.800 6.200 h 0.250 0.500 l 0.400 1.270 k 0 8 x 1.900 2.500 y 3.600 4.200 ddd 0.100
package mechanical data vni2140j 20/23 doc id 15187 rev 8 figure 16. powersso-12? tube shipment (no suffix) figure 17. powersso-12? tape and reel shipment (suffix ?tr?)
vni2140j package mechanical data doc id 15187 rev 8 21/23 figure 18. suggested footprint
revision history vni2140j 22/23 doc id 15187 rev 8 11 revision history table 12. document revision history date revision changes 16-dec-2008 1 initial release 29-apr-2009 2 updated table 5 on page 6 03-jul-2009 3 updated features in coverpage and table 5 on page 6 27-aug-2009 4 updated section 9: reverse polarity protection 25-mar-2010 5 updated coverpage and table4 on page5 26-apr-2010 6 updated table 5 on page 6 21-jul-2010 7 updated table 8 on page 7 15-nov-2011 8 updated figure 18 on page 21
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